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From github.com:llvm/llvm-project
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   3c71e661b96c..abc4f4ceca7e  main       -> origin/main
Switched to branch 'main'
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HEAD is now at abc4f4ceca7e [NewPM][CodeGen] Port cfguard-longjmp (#234481)
INFO:2026-10-22T07:00:42Z:root:syncing...
Deleted branch merge (was fa017a697034).
Switched to a new branch 'merge'
branch 'merge' set up to track 'origin/main'.
[merge 6db8c0ee91f9] [gn build] Port ea4c43d796c4
 1 file changed, 1 insertion(+)
[gn build] Port ea4c43d796c4 -- https://github.com/llvm/llvm-project/commit/ea4c43d796c4
INFO:2026-10-22T07:00:44Z:root:building
ninja: Entering directory `out/gn'
[0/1] Regenerating ninja files
[1/1702] COPY ../../libcxxabi/include/__cxxabi_config.h include/c++/v1/__cxxabi_config.h
[2/1702] COPY ../../libcxxabi/include/cxxabi.h include/c++/v1/cxxabi.h
[3/1702] ACTION //libcxx/include:copy_headers(//llvm/utils/gn/build/toolchain:unix)
[4/1702] CXX obj/llvm/lib/Analysis/Analysis.LazyBlockFrequencyInfo.o
[5/1702] CXX obj/llvm/lib/Analysis/Analysis.CycleAnalysis.o
[6/1702] CXX obj/llvm/lib/Analysis/Analysis.Analysis.o
[7/1702] CXX obj/llvm/lib/Target/Target.Target.o
[8/1702] CXX obj/llvm/lib/Analysis/Analysis.PostDominators.o
[9/1702] CXX obj/llvm/lib/Analysis/Analysis.LazyBranchProbabilityInfo.o
[10/1702] CXX obj/llvm/lib/Analysis/Analysis.DominanceFrontier.o
[11/1702] CXX obj/llvm/lib/Analysis/Analysis.PhiValues.o
[12/1702] CXX obj/llvm/lib/Analysis/Analysis.OptimizationRemarkEmitter.o
[13/1702] CXX obj/llvm/lib/Analysis/Analysis.CallGraph.o
[14/1702] CXX obj/llvm/lib/Bitcode/Writer/Writer.BitcodeWriterPass.o
[15/1702] CXX obj/llvm/lib/Analysis/Analysis.DXILMetadataAnalysis.o
[16/1702] CXX obj/llvm/lib/Analysis/Analysis.LoopPass.o
[17/1702] CXX obj/llvm/lib/Analysis/Analysis.CallPrinter.o
[18/1702] CXX obj/llvm/lib/Analysis/Analysis.CallGraphSCCPass.o
[19/1702] CXX obj/llvm/lib/Analysis/Analysis.RuntimeLibcallInfo.o
[20/1702] CXX obj/llvm/lib/Analysis/Analysis.IVUsers.o
[21/1702] CXX obj/llvm/lib/Analysis/Analysis.DomPrinter.o
[22/1702] CXX obj/llvm/lib/Analysis/Analysis.AliasAnalysis.o
[23/1702] CXX obj/llvm/lib/Analysis/Analysis.ProfileSummaryInfo.o
[24/1702] CXX obj/llvm/lib/Analysis/Analysis.AssumptionCache.o
[25/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86MachineFunctionInfo.o
[26/1702] CXX obj/llvm/lib/Analysis/Analysis.ScopedNoAliasAA.o
[27/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86MacroFusion.o
[28/1702] CXX obj/llvm/lib/Analysis/Analysis.RegionInfo.o
[29/1702] CXX obj/llvm/lib/Analysis/Analysis.BranchProbabilityInfo.o
[30/1702] CXX obj/llvm/lib/Analysis/Analysis.BlockFrequencyInfo.o
[31/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86SelectionDAGInfo.o
[32/1702] CXX obj/llvm/lib/Analysis/Analysis.RegionPrinter.o
[33/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86WinEHUnwindV3.o
[34/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86SpeculativeExecutionSideEffectSuppression.o
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[49/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64CondBrTuning.o
[50/1702] CXX obj/llvm/lib/CodeGen/GlobalISel/GlobalISel.LegalizerInfo.o
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[58/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64CompressJumpTables.o
[59/1702] CXX obj/clang/tools/driver/clang.cc1_main.o
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[63/1702] CXX obj/llvm/lib/Analysis/Analysis.UniformityAnalysis.o
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[77/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVCodeGenPassBuilder.o
[78/1702] CXX obj/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.LegalizeTypesGeneric.o
[79/1702] CXX obj/llvm/lib/CodeGen/CodeGen.AllocationOrder.o
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[86/1702] CXX obj/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.LegalizeTypes.o
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[88/1702] CXX obj/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.FunctionLoweringInfo.o
[89/1702] CXX obj/llvm/lib/CodeGen/CodeGen.BasicBlockPathCloning.o
[90/1702] CXX obj/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.ScheduleDAGFast.o
[91/1702] CXX obj/llvm/lib/CodeGen/GlobalISel/GlobalISel.Legalizer.o
[92/1702] CXX obj/llvm/lib/CodeGen/CodeGen.CFGuardLongjmp.o
[93/1702] CXX obj/llvm/lib/CodeGen/GlobalISel/GlobalISel.Utils.o
[94/1702] CXX obj/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.SelectionDAGPrinter.o
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[97/1702] CXX obj/llvm/lib/CodeGen/CodeGen.BreakFalseDeps.o
[98/1702] CXX obj/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.LegalizeFloatTypes.o
[99/1702] CXX obj/llvm/lib/CodeGen/CodeGen.BranchRelaxation.o
[100/1702] CXX obj/llvm/lib/CodeGen/CodeGen.CFIFixup.o
[101/1702] CXX obj/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.LegalizeVectorOps.o
[102/1702] CXX obj/llvm/lib/CodeGen/CodeGen.BasicBlockSectionsProfileReader.o
[103/1702] CXX obj/llvm/lib/Target/RISCV/GISel/LLVMRISCVCodeGen.RISCVPreLegalizerCombiner.o
[104/1702] CXX obj/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.ScheduleDAGSDNodes.o
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[108/1702] CXX obj/llvm/lib/CodeGen/CodeGen.BasicBlockSections.o
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[110/1702] CXX obj/llvm/lib/CodeGen/CodeGen.EdgeBundles.o
[111/1702] CXX obj/llvm/lib/CodeGen/CodeGen.CFIInstrInserter.o
[112/1702] CXX obj/llvm/lib/CodeGen/CodeGen.Analysis.o
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[118/1702] CXX obj/llvm/lib/CodeGen/CodeGen.AtomicExpandPass.o
[119/1702] CXX obj/bolt/lib/Target/AArch64/AArch64.AArch64MCPlusBuilder.o
[120/1702] CXX obj/bolt/unittests/Passes/PassTests.LivenessAnalysis.o
[121/1702] CXX obj/bolt/unittests/Passes/PassTests.PointerAuthCFIFixup.o
[122/1702] CXX obj/llvm/lib/CodeGen/CodeGen.GCMetadata.o
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[124/1702] CXX obj/llvm/lib/CodeGen/CodeGen.CodeGenCommonISel.o
[125/1702] CXX obj/llvm/lib/CodeGen/CodeGen.ExpandPostRAPseudos.o
[126/1702] CXX obj/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.LegalizeIntegerTypes.o
[127/1702] CXX obj/llvm/lib/CodeGen/CodeGen.FuncletLayout.o
[128/1702] CXX obj/llvm/lib/CodeGen/CodeGen.ExecutionDomainFix.o
[129/1702] CXX obj/llvm/lib/CodeGen/CodeGen.EHContGuardTargets.o
[130/1702] CXX obj/llvm/lib/CodeGen/CodeGen.ExpandReductions.o
[131/1702] CXX obj/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.LegalizeDAG.o
[132/1702] CXX obj/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.StatepointLowering.o
[133/1702] CXX obj/llvm/lib/CodeGen/CodeGen.BranchFolding.o
[134/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86TargetTransformInfo.o
[135/1702] CXX obj/llvm/lib/CodeGen/CodeGen.LibcallLoweringInfo.o
[136/1702] CXX obj/bolt/unittests/Core/CoreTests.MCPlusBuilder.o
[137/1702] CXX obj/llvm/lib/CodeGen/CodeGen.IndirectBrExpandPass.o
[138/1702] CXX obj/llvm/lib/CodeGen/CodeGen.LazyMachineBlockFrequencyInfo.o
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[166/1702] CXX obj/llvm/lib/CodeGen/CodeGen.LowerEmuTLS.o
[167/1702] CXX obj/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.LegalizeVectorTypes.o
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[169/1702] CXX obj/llvm/lib/CodeGen/CodeGen.LiveRegMatrix.o
[170/1702] CXX obj/llvm/lib/CodeGen/CodeGen.LiveVariables.o
[171/1702] CXX obj/llvm/lib/CodeGen/CodeGen.MachineBranchProbabilityInfo.o
[172/1702] CXX obj/llvm/lib/CodeGen/CodeGen.LiveInterval.o
[173/1702] CXX obj/llvm/lib/CodeGen/CodeGen.MachineBlockHashInfo.o
[174/1702] CXX obj/llvm/lib/CodeGen/CodeGen.LiveRangeEdit.o
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[176/1702] CXX obj/llvm/lib/CodeGen/CodeGen.CodeGenTargetMachineImpl.o
[177/1702] CXX obj/llvm/lib/CodeGen/CodeGen.MIRVRegNamerUtils.o
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[180/1702] CXX obj/llvm/lib/CodeGen/CodeGen.IfConversion.o
[181/1702] CXX obj/llvm/lib/CodeGen/CodeGen.ComplexDeinterleavingPass.o
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[183/1702] CXX obj/llvm/lib/CodeGen/CodeGen.MachineDominanceFrontier.o
[184/1702] CXX obj/llvm/lib/CodeGen/CodeGen.MachineFunctionPrinterPass.o
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[191/1702] CXX obj/clang/lib/CodeGen/CodeGen.BackendUtil.o
[192/1702] CXX obj/llvm/lib/CodeGen/CodeGen.MachineFrameInfo.o
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[194/1702] CXX obj/llvm/lib/CodeGen/CodeGen.MachineOptimizationRemarkEmitter.o
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[264/1702] CXX obj/llvm/lib/CodeGen/CodeGen.SanitizerBinaryMetadata.o
[265/1702] CXX obj/llvm/lib/Analysis/Analysis.ScalarEvolution.o
[266/1702] CXX obj/llvm/lib/CodeGen/CodeGen.TargetSubtargetInfo.o
[267/1702] CXX obj/llvm/lib/CodeGen/CodeGen.MIRPrinter.o
[268/1702] CXX obj/llvm/lib/CodeGen/CodeGen.StackMapLivenessAnalysis.o
[269/1702] CXX obj/llvm/lib/CodeGen/CodeGen.SjLjEHPrepare.o
[270/1702] CXX obj/llvm/lib/CodeGen/CodeGen.ReplaceWithVeclib.o
[271/1702] CXX obj/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.SelectionDAGBuilder.o
[272/1702] CXX obj/llvm/lib/CodeGen/CodeGen.PreISelIntrinsicLowering.o
[273/1702] CXX obj/llvm/lib/CodeGen/CodeGen.ShadowStackGCLowering.o
[274/1702] CXX obj/llvm/lib/CodeGen/GlobalISel/GlobalISel.GlobalISel.o
[275/1702] CXX obj/llvm/lib/CodeGen/CodeGen.StaticDataAnnotator.o
[276/1702] CXX obj/llvm/lib/CodeGen/CodeGen.ScheduleDAGPrinter.o
[277/1702] CXX obj/llvm/lib/CodeGen/CodeGen.ScoreboardHazardRecognizer.o
[278/1702] CXX obj/llvm/lib/CodeGen/CodeGen.ScheduleDAG.o
[279/1702] CXX obj/llvm/lib/CodeGen/CodeGen.ModuloSchedule.o
[280/1702] CXX obj/llvm/lib/CodeGen/CodeGen.RegAllocFast.o
[281/1702] CXX obj/llvm/lib/CodeGen/CodeGen.StaticDataSplitter.o
[282/1702] CXX obj/llvm/lib/CodeGen/CodeGen.RDFGraph.o
[283/1702] CXX obj/llvm/lib/CodeGen/CodeGen.MachineSink.o
[284/1702] CXX obj/llvm/lib/CodeGen/CodeGen.PrologEpilogInserter.o
[285/1702] CXX obj/llvm/lib/CodeGen/CodeGen.TargetSchedule.o
[286/1702] CXX obj/llvm/lib/CodeGen/CodeGen.TargetFrameLoweringImpl.o
[287/1702] CXX obj/llvm/lib/CodeGen/CodeGen.TailDuplication.o
[288/1702] CXX obj/llvm/lib/CodeGen/CodeGen.StackFrameLayoutAnalysisPass.o
[289/1702] CXX obj/llvm/lib/CodeGen/CodeGen.MachineOutliner.o
[290/1702] CXX obj/llvm/lib/CodeGen/CodeGen.RegAllocPBQP.o
[291/1702] CXX obj/llvm/lib/CodeGen/CodeGen.WasmEHPrepare.o
[292/1702] CXX obj/llvm/lib/CodeGen/CodeGen.StackMaps.o
[293/1702] CXX obj/llvm/lib/CodeGen/CodeGen.MachineVerifier.o
[294/1702] CXX obj/llvm/lib/CodeGen/CodeGen.SwiftErrorValueTracking.o
[295/1702] CXX obj/llvm/lib/CodeGen/CodeGen.UnreachableBlockElim.o
[296/1702] CXX obj/llvm/lib/CodeGen/CodeGen.StackSlotColoring.o
[297/1702] CXX obj/llvm/lib/CodeGen/CodeGen.RegisterCoalescer.o
[298/1702] CXX obj/llvm/lib/CodeGen/CodeGen.ScheduleDAGInstrs.o
[299/1702] CXX obj/llvm/lib/CodeGen/CodeGen.XRayInstrumentation.o
[300/1702] CXX obj/llvm/lib/CodeGen/GlobalISel/GlobalISel.GISelChangeObserver.o
[301/1702] CXX obj/llvm/lib/CodeGen/CodeGen.Rematerializer.o
[302/1702] CXX obj/llvm/lib/CodeGen/CodeGen.RegAllocGreedy.o
[303/1702] CXX obj/llvm/lib/CodeGen/CodeGen.ShrinkWrap.o
[304/1702] CXX obj/llvm/lib/CodeGen/CodeGen.SwitchLoweringUtils.o
[305/1702] CXX obj/llvm/lib/CodeGen/CodeGen.TailDuplicator.o
[306/1702] CXX obj/llvm/lib/CodeGen/CodeGen.CodeGenPrepare.o
[307/1702] CXX obj/llvm/lib/CodeGen/CodeGen.MachineScheduler.o
[308/1702] CXX obj/llvm/lib/CodeGen/CodeGen.WindowsSecureHotPatching.o
[309/1702] CXX obj/llvm/lib/CodeGen/LiveDebugValues/CodeGen.InstrRefBasedImpl.o
[310/1702] CXX obj/llvm/lib/CodeGen/GlobalISel/GlobalISel.GIMatchTableExecutor.o
[311/1702] CXX obj/llvm/lib/CodeGen/CodeGen.TargetRegisterInfo.o
[312/1702] CXX obj/llvm/lib/CodeGen/CodeGen.StackProtector.o
[313/1702] CXX obj/llvm/lib/IR/IR.IRPrintingPasses.o
[314/1702] CXX obj/llvm/lib/CodeGen/CodeGen.TargetPassConfig.o
[315/1702] CXX obj/llvm/lib/CodeGen/CodeGen.SplitKit.o
[316/1702] CXX obj/llvm/lib/CodeGen/CodeGen.VirtRegMap.o
[317/1702] CXX obj/llvm/lib/CodeGen/CodeGen.SafeStack.o
[318/1702] CXX obj/llvm/lib/CodeGen/CodeGen.StackColoring.o
[319/1702] CXX obj/llvm/lib/CodeGen/GlobalISel/GlobalISel.CSEInfo.o
[320/1702] CXX obj/llvm/lib/CodeGen/CodeGen.VLIWMachineScheduler.o
[321/1702] CXX obj/llvm/lib/CodeGen/GlobalISel/GlobalISel.CombinerHelperCasts.o
[322/1702] CXX obj/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.DebugHandlerBase.o
[323/1702] CXX obj/llvm/lib/CodeGen/CodeGen.SelectOptimize.o
[324/1702] CXX obj/llvm/lib/CodeGen/GlobalISel/GlobalISel.CombinerHelperVectorOps.o
[325/1702] CXX obj/llvm/lib/CodeGen/CodeGen.TwoAddressInstructionPass.o
[326/1702] CXX obj/llvm/lib/CodeGen/GlobalISel/GlobalISel.CombinerHelperCompares.o
[327/1702] CXX obj/llvm/lib/CodeGen/CodeGen.WinEHPrepare.o
[328/1702] CXX obj/llvm/lib/CodeGen/GlobalISel/GlobalISel.InlineAsmLowering.o
[329/1702] CXX obj/llvm/lib/CodeGen/GlobalISel/GlobalISel.CSEMIRBuilder.o
[330/1702] CXX obj/llvm/lib/CodeGen/CodeGen.TargetLoweringBase.o
[331/1702] CXX obj/llvm/lib/CodeGen/CodeGen.TypePromotion.o
[332/1702] CXX obj/llvm/lib/LTO/LTO.UpdateCompilerUsed.o
[333/1702] CXX obj/llvm/lib/CodeGen/GlobalISel/GlobalISel.InstructionSelect.o
[334/1702] CXX obj/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.AsmPrinterInlineAsm.o
[335/1702] CXX obj/llvm/lib/CodeGen/CodeGen.TargetInstrInfo.o
[336/1702] CXX obj/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.DbgEntityHistoryCalculator.o
[337/1702] CXX obj/llvm/lib/CodeGen/CodeGen.WindowScheduler.o
[338/1702] CXX obj/llvm/lib/IR/IR.SafepointIRVerifier.o
[339/1702] CXX obj/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.WinException.o
[340/1702] CXX obj/llvm/lib/CodeGen/CodeGen.MachinePipeliner.o
[341/1702] CXX obj/llvm/lib/CodeGen/GlobalISel/GlobalISel.Combiner.o
[342/1702] CXX obj/llvm/lib/CodeGen/GlobalISel/GlobalISel.CallLowering.o
[343/1702] CXX obj/llvm/lib/CodeGen/GlobalISel/GlobalISel.GISelValueTracking.o
[344/1702] CXX obj/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.DwarfCompileUnit.o
[345/1702] CXX obj/llvm/lib/IR/IR.Core.o
[346/1702] CXX obj/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.DAGCombiner.o
[347/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64A53Fix835769.o
[348/1702] CXX obj/llvm/lib/LTO/LTO.LTOModule.o
[349/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64DeadRegisterDefinitionsPass.o
[350/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64SMEAttributes.o
[351/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64ExpandImm.o
[352/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64ConditionOptimizer.o
[353/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64AdvSIMDScalarPass.o
[354/1702] CXX obj/llvm/lib/IR/IR.Dominators.o
[355/1702] CXX obj/llvm/lib/LTO/LTO.LTOCodeGenerator.o
[356/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64CleanupLocalDynamicTLSPass.o
[357/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64CallingConvention.o
[358/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64ConditionalCompares.o
[359/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64MIPeepholeOpt.o
[360/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64RedundantCondBranchPass.o
[361/1702] CXX obj/llvm/unittests/CodeGen/CodeGenTests.MIR2VecTest.o
[362/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64BranchTargets.o
[363/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64MachineScheduler.o
[364/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64PTrueCoalescing.o
[365/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64MacroFusion.o
[366/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64A57FPLoadBalancing.o
[367/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64FalkorHWPFFix.o
[368/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64RedundantCopyElimination.o
[369/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64ExpandPseudoInsts.o
[370/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64PBQPRegAlloc.o
[371/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64LowerHomogeneousPrologEpilog.o
[372/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64MachineFunctionInfo.o
[373/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64Arm64ECCallLowering.o
[374/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64SIMDInstrOpt.o
[375/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64PredicateAsCounterLoopRewrites.o
[376/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64PromoteConstant.o
[377/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64PostCoalescerPass.o
[378/1702] CXX obj/llvm/lib/Target/AArch64/GISel/LLVMAArch64CodeGen.AArch64GlobalISelUtils.o
[379/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64PointerAuth.o
[380/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64StorePairSuppress.o
[381/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64MCInstLower.o
[382/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64SpeculationHardening.o
[383/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64SRLTDefineSuperRegs.o
[384/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64SelectionDAGInfo.o
[385/1702] CXX obj/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.CodeViewDebug.o
[386/1702] CXX obj/llvm/lib/CodeGen/GlobalISel/GlobalISel.IRTranslator.o
[387/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64StackTaggingPreRA.o
[388/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64SLSHardening.o
[389/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64LoadStoreOptimizer.o
[390/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64AsmPrinter.o
[391/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64PrologueEpilogue.o
[392/1702] CXX obj/llvm/lib/Passes/Passes.CodeGenPassBuilder.o
[393/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUArgumentUsageInfo.o
[394/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64TargetObjectFile.o
[395/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64RegisterInfo.o
[396/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64StackTagging.o
[397/1702] CXX obj/llvm/lib/CodeGen/GlobalISel/GlobalISel.CombinerHelper.o
[398/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUAsanInstrumentation.o
[399/1702] CXX obj/llvm/lib/Target/AArch64/GISel/LLVMAArch64CodeGen.AArch64CallLowering.o
[400/1702] CXX obj/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.AsmPrinter.o
[401/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64FastISel.o
[402/1702] CXX obj/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.DwarfDebug.o
[403/1702] CXX obj/llvm/lib/Target/AArch64/GISel/LLVMAArch64CodeGen.AArch64PostSelectOptimize.o
[404/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUAnnotateUniformValues.o
[405/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64FrameLowering.o
[406/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUGlobalISelUtils.o
[407/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUExportClustering.o
[408/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUBarrierLatency.o
[409/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.SMEPeepholeOpt.o
[410/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUAlwaysInlinePass.o
[411/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUCombinerHelper.o
[412/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUHazardLatency.o
[413/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUHWEvents.o
[414/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUGlobalISelDivergenceLowering.o
[415/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.SVEShuffleOpts.o
[416/1702] CXX obj/llvm/lib/IR/IR.Verifier.o
[417/1702] AR lib/libLLVMCore.a
[418/1702] CXX obj/llvm/lib/Target/AArch64/GISel/LLVMAArch64CodeGen.AArch64RegisterBankInfo.o
[419/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.MachineSMEABIPass.o
[420/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64InstrInfo.o
[421/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUAtomicOptimizer.o
[422/1702] AR lib/libLLVMAnalysis.a
[423/1702] AR lib/libLLVMTarget.a
[424/1702] LINK ./bin/llvm-objcopy
[425/1702] LINK ./bin/sanstats
[426/1702] LINK ./bin/llvm-ifs
[427/1702] ACTION //llvm/tools/llvm-objcopy:llvm-strip(//llvm/utils/gn/build/toolchain:unix)
[428/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPULowerKernelAttributes.o
[429/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUCoExecSchedStrategy.o
[430/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUMacroFusion.o
[431/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUCallLowering.o
[432/1702] CXX obj/llvm/lib/Target/AArch64/GISel/LLVMAArch64CodeGen.AArch64O0PreLegalizerCombiner.o
[433/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPULowerVGPREncoding.o
[434/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUPrintfRuntimeBinding.o
[435/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUHSAMetadataStreamer.o
[436/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUPromoteKernelArguments.o
[437/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUImageIntrinsicOptimizer.o
[438/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64ISelDAGToDAG.o
[439/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPULowerKernelArguments.o
[440/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64TargetMachine.o
[441/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUAsmPrinter.o
[442/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPULowerExecSync.o
[443/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUInsertDelayAlu.o
[444/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPULowerIntrinsics.o
[445/1702] CXX obj/llvm/lib/Target/AArch64/GISel/LLVMAArch64CodeGen.AArch64LegalizerInfo.o
[446/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUMarkLastScratchLoad.o
[447/1702] CXX obj/llvm/lib/Target/AArch64/GISel/LLVMAArch64CodeGen.AArch64PostLegalizerCombiner.o
[448/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUMCResourceInfo.o
[449/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUMIRFormatter.o
[450/1702] CXX obj/llvm/lib/Target/AArch64/GISel/LLVMAArch64CodeGen.AArch64PostLegalizerLowering.o
[451/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPURewriteUndefForPHI.o
[452/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPULateCodeGenPrepare.o
[453/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUCodeGenPrepare.o
[454/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUMCInstLower.o
[455/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUAttributor.o
[456/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUPreloadKernelArguments.o
[457/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUPreloadKernArgProlog.o
[458/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPURewriteOutArguments.o
[459/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPURemoveIncompatibleFunctions.o
[460/1702] CXX obj/llvm/lib/Target/AArch64/GISel/LLVMAArch64CodeGen.AArch64PreLegalizerCombiner.o
[461/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64TargetTransformInfo.o
[462/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUPerfHintAnalysis.o
[463/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPURegBankSelect.o
[464/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUInstCombineIntrinsic.o
[465/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUISelLowering.o
[466/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUPrepareAGPRAlloc.o
[467/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUUniformIntrinsicCombine.o
[468/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPURegBankLegalize.o
[469/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUSetWavePriority.o
[470/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUIGroupLP.o
[471/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPULowerModuleLDSPass.o
[472/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUUnifyDivergentExitNodes.o
[473/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.GCNILPSched.o
[474/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUReserveWWMRegs.o
[475/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.GCNMinRegStrategy.o
[476/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUNextUseAnalysis.o
[477/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUResourceUsageAnalysis.o
[478/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPULowerBufferFatPointers.o
[479/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUWaitcntUtils.o
[480/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPURegBankLegalizeHelper.o
[481/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUSwLowerLDS.o
[482/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUSubtarget.o
[483/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUPromoteAlloca.o
[484/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.GCNRewritePartialRegUses.o
[485/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.R600ClauseMergePass.o
[486/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.GCNDPPCombine.o
[487/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.GCNCreateVOPD.o
[488/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.R600FrameLowering.o
[489/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.R600EmitClauseMarkers.o
[490/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.GCNPreRAOptimizations.o
[491/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.R600ExpandSpecialInstrs.o
[492/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPURewriteAGPRCopyMFMA.o
[493/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUWaitSGPRHazards.o
[494/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUPreLegalizerCombiner.o
[495/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.GCNPreRAAntiHints.o
[496/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.GCNPreRALongBranchReg.o
[497/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.R600ControlFlowFinalizer.o
[498/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.GCNVOPDUtils.o
[499/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.R600AsmPrinter.o
[500/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUPostLegalizerCombiner.o
[501/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.R600MachineFunctionInfo.o
[502/1702] CXX obj/llvm/lib/Target/AArch64/AsmParser/AsmParser.AArch64AsmParser.o
[503/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPURegisterBankInfo.o
[504/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.GCNNSAReassign.o
[505/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.R600Subtarget.o
[506/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.R600MachineScheduler.o
[507/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.R600Packetizer.o
[508/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.R600OptimizeVectorRegisters.o
[509/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPURegBankCombiner.o
[510/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.R600RegisterInfo.o
[511/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.GCNIterativeScheduler.o
[512/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.R600ISelLowering.o
[513/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.R600InstrInfo.o
[514/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUISelDAGToDAG.o
[515/1702] CXX obj/llvm/lib/Target/AArch64/GISel/LLVMAArch64CodeGen.AArch64InstructionSelector.o
[516/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.R600MachineCFGStructurizer.o
[517/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.R600MCInstLower.o
[518/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPULegalizerInfo.o
[519/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIFixVGPRCopies.o
[520/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.GCNSubtarget.o
[521/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIAnnotateControlFlow.o
[522/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.GCNHazardRecognizer.o
[523/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPURegBankLegalizeRules.o
[524/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIInsertHardClauses.o
[525/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.GCNRegPressure.o
[526/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIModeRegisterDefaults.o
[527/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIFormMemoryClauses.o
[528/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIFixSGPRCopies.o
[529/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIModeRegister.o
[530/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIProgramInfo.o
[531/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIPostRA16BitMovFolding.o
[532/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SILateBranchLowering.o
[533/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUTargetTransformInfo.o
[534/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SILowerI1Copies.o
[535/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIOptimizeExecMaskingPreRA.o
[536/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIOptimizeExecMasking.o
[537/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIPostRABundler.o
[538/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SILowerControlFlow.o
[539/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMBasicBlockInfo.o
[540/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SILowerWWMCopies.o
[541/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIPeepholeSDWA.o
[542/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIShrinkInstructions.o
[543/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIPreEmitPeephole.o
[544/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SILoadStoreOptimizer.o
[545/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIFrameLowering.o
[546/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMBranchTargets.o
[547/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SILowerSGPRSpills.o
[548/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIFoldOperands.o
[549/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.R600TargetMachine.o
[550/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIMachineScheduler.o
[551/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.GCNSchedStrategy.o
[552/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIPreAllocateWWMRegs.o
[553/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.A15SDOptimizer.o
[554/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIOptimizeVGPRLiveRange.o
[555/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIMemoryLegalizer.o
[556/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMCallLowering.o
[557/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIMachineFunctionInfo.o
[558/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIWholeQuadMode.o
[559/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMFixCortexA57AES1742098Pass.o
[560/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.R600ISelDAGToDAG.o
[561/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMBlockPlacement.o
[562/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64ISelLowering.o
[563/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.R600TargetTransformInfo.o
[564/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMCallingConv.o
[565/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMHazardRecognizer.o
[566/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMOptimizeBarriersPass.o
[567/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMBaseRegisterInfo.o
[568/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMInstrInfo.o
[569/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMExpandPseudoInsts.o
[570/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIInsertWaitcnts.o
[571/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMAsmPrinter.o
[572/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMLatencyMutations.o
[573/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMLegalizerInfo.o
[574/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMConstantIslandPass.o
[575/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMMachineFunctionInfo.o
[576/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMMacroFusion.o
[577/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMRegisterBankInfo.o
[578/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIInstrInfo.o
[579/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMFrameLowering.o
[580/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMMCInstLower.o
[581/1702] CXX obj/llvm/lib/Target/AVR/LLVMAVRCodeGen.AVRFrameLowering.o
[582/1702] CXX obj/llvm/lib/Target/AVR/LLVMAVRCodeGen.AVRSubtarget.o
[583/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMFastISel.o
[584/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.MLxExpansionPass.o
[585/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMTargetObjectFile.o
[586/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.MVEVPTBlockPass.o
[587/1702] CXX obj/llvm/lib/Target/AVR/LLVMAVRCodeGen.AVRMCInstLower.o
[588/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMSLSHardening.o
[589/1702] CXX obj/llvm/lib/Target/AVR/LLVMAVRCodeGen.AVRRegisterInfo.o
[590/1702] CXX obj/llvm/lib/Target/AVR/LLVMAVRCodeGen.AVRInstrInfo.o
[591/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.Thumb1InstrInfo.o
[592/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIRegisterInfo.o
[593/1702] CXX obj/llvm/lib/Target/AVR/LLVMAVRCodeGen.AVRISelDAGToDAG.o
[594/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.MVELaneInterleavingPass.o
[595/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.Thumb2ITBlockPass.o
[596/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ThumbRegisterInfo.o
[597/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.MVEGatherScatterLowering.o
[598/1702] CXX obj/llvm/lib/Target/AVR/LLVMAVRCodeGen.AVRExpandPseudoInsts.o
[599/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.Thumb2InstrInfo.o
[600/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMSelectionDAGInfo.o
[601/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMLowOverheadLoops.o
[602/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.MVETPAndVPTOptimisationsPass.o
[603/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.Thumb2SizeReduction.o
[604/1702] CXX obj/llvm/lib/Target/AVR/LLVMAVRCodeGen.AVRAsmPrinter.o
[605/1702] CXX obj/llvm/lib/Target/AVR/LLVMAVRCodeGen.AVRTargetObjectFile.o
[606/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMParallelDSP.o
[607/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMISelDAGToDAG.o
[608/1702] CXX obj/llvm/lib/Target/AVR/LLVMAVRCodeGen.AVRISelLowering.o
[609/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMLoadStoreOptimizer.o
[610/1702] CXX obj/llvm/lib/Target/BPF/LLVMBPFCodeGen.BPFFrameLowering.o
[611/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMBaseInstrInfo.o
[612/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.Thumb1FrameLowering.o
[613/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMInstructionSelector.o
[614/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMSubtarget.o
[615/1702] CXX obj/llvm/lib/Target/BPF/LLVMBPFCodeGen.BPFMIChecking.o
[616/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.MVETailPredication.o
[617/1702] CXX obj/llvm/lib/Target/BPF/LLVMBPFCodeGen.BPFISelDAGToDAG.o
[618/1702] CXX obj/llvm/lib/Target/BPF/LLVMBPFCodeGen.BPFInstrInfo.o
[619/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonCFGOptimizer.o
[620/1702] CXX obj/llvm/lib/Target/BPF/LLVMBPFCodeGen.BPFMIPeephole.o
[621/1702] CXX obj/llvm/lib/Target/BPF/LLVMBPFCodeGen.BPFSubtarget.o
[622/1702] CXX obj/llvm/lib/Target/BPF/LLVMBPFCodeGen.BPFAsmPrinter.o
[623/1702] CXX obj/llvm/lib/Target/BPF/LLVMBPFCodeGen.BPFRegisterInfo.o
[624/1702] CXX obj/llvm/lib/Target/BPF/LLVMBPFCodeGen.BPFMCInstLower.o
[625/1702] CXX obj/llvm/lib/Target/AVR/LLVMAVRCodeGen.AVRTargetMachine.o
[626/1702] CXX obj/llvm/lib/Target/ARM/AsmParser/AsmParser.ARMAsmParser.o
[627/1702] CXX obj/llvm/lib/Target/BPF/LLVMBPFCodeGen.BPFMISimplifyPatchable.o
[628/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.BitTracker.o
[629/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonGenExtract.o
[630/1702] CXX obj/llvm/lib/Target/BPF/GISel/LLVMBPFCodeGen.BPFCallLowering.o
[631/1702] CXX obj/llvm/lib/Target/BPF/LLVMBPFCodeGen.BPFISelLowering.o
[632/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.SIISelLowering.o
[633/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonBranchRelaxation.o
[634/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMTargetMachine.o
[635/1702] CXX obj/llvm/lib/Target/AVR/LLVMAVRCodeGen.AVRTargetTransformInfo.o
[636/1702] CXX obj/llvm/lib/Target/Lanai/LLVMLanaiCodeGen.LanaiDelaySlotFiller.o
[637/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonAggressiveRDFCopy.o
[638/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonBlockRanges.o
[639/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonCommonGEP.o
[640/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonFixupHwLoops.o
[641/1702] CXX obj/llvm/lib/Target/BPF/LLVMBPFCodeGen.BPFCodeGenPassBuilder.o
[642/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMTargetTransformInfo.o
[643/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonGenMemAbsolute.o
[644/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonBitTracker.o
[645/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonCopyToCombine.o
[646/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonExpandCondsets.o
[647/1702] CXX obj/llvm/lib/Target/BPF/LLVMBPFCodeGen.BPFAbstractMemberAccess.o
[648/1702] CXX obj/llvm/lib/Target/ARM/Disassembler/Disassembler.ARMDisassembler.o
[649/1702] CXX obj/llvm/lib/Target/Lanai/LLVMLanaiCodeGen.LanaiAsmPrinter.o
[650/1702] CXX obj/llvm/lib/Target/BPF/LLVMBPFCodeGen.BPFUnwind.o
[651/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonEarlyIfConv.o
[652/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonGenMux.o
[653/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonGlobalRegion.o
[654/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonCopyHoisting.o
[655/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonHazardRecognizer.o
[656/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonGenPredicate.o
[657/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonHVXSaveRemark.o
[658/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonBitSimplify.o
[659/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonAsmPrinter.o
[660/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonConstExtenders.o
[661/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonHardwareLoops.o
[662/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonConstPropagation.o
[663/1702] CXX obj/llvm/lib/Target/AMDGPU/AsmParser/AsmParser.AMDGPUAsmParser.o
[664/1702] CXX obj/llvm/lib/Target/Lanai/LLVMLanaiCodeGen.LanaiCodeGenPassBuilder.o
[665/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonLiveVariables.o
[666/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUTargetMachine.o
[667/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonLoopAlign.o
[668/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonMask.o
[669/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonMachineScheduler.o
[670/1702] CXX obj/llvm/lib/Passes/Passes.PassBuilder.o
[671/1702] CXX obj/llvm/lib/Target/BPF/GISel/LLVMBPFCodeGen.BPFInstructionSelector.o
[672/1702] CXX obj/llvm/lib/Target/Lanai/LLVMLanaiCodeGen.LanaiMachineFunctionInfo.o
[673/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonQFPOptimizer.o
[674/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonPeephole.o
[675/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonNewValueJump.o
[676/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonLoadStoreWidening.o
[677/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonSplitConst32AndConst64.o
[678/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonGenInsert.o
[679/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonMCInstLower.o
[680/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonSelectionDAGInfo.o
[681/1702] CXX obj/llvm/lib/Target/Lanai/LLVMLanaiCodeGen.LanaiRegisterInfo.o
[682/1702] CXX obj/llvm/lib/Target/BPF/LLVMBPFCodeGen.BTFDebug.o
[683/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.RDFDeadCode.o
[684/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonISelLoweringHVX.o
[685/1702] CXX obj/llvm/lib/Target/Lanai/Disassembler/Disassembler.LanaiDisassembler.o
[686/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonOptAddrMode.o
[687/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonTfrCleanup.o
[688/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonVectorPrint.o
[689/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonRDFOpt.o
[690/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonFrameLowering.o
[691/1702] CXX obj/llvm/lib/Target/Lanai/LLVMLanaiCodeGen.LanaiSubtarget.o
[692/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonRegisterInfo.o
[693/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonISelDAGToDAG.o
[694/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonISelDAGToDAGHVX.o
[695/1702] CXX obj/llvm/lib/Target/Lanai/LLVMLanaiCodeGen.LanaiFrameLowering.o
[696/1702] CXX obj/llvm/lib/Target/Lanai/LLVMLanaiCodeGen.LanaiMemAluCombiner.o
[697/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonVExtract.o
[698/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonVectorLoopCarriedReuse.o
[699/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonGlobalScheduler.o
[700/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonSplitDouble.o
[701/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonXQFloatGenerator.o
[702/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonSubtarget.o
[703/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonVLIWPacketizer.o
[704/1702] CXX obj/llvm/lib/Target/LoongArch/LLVMLoongArchCodeGen.LoongArchDeadRegisterDefinitions.o
[705/1702] CXX obj/llvm/lib/Target/Lanai/LLVMLanaiCodeGen.LanaiInstrInfo.o
[706/1702] CXX obj/llvm/lib/Target/Lanai/LLVMLanaiCodeGen.LanaiISelDAGToDAG.o
[707/1702] CXX obj/llvm/lib/Target/Lanai/AsmParser/AsmParser.LanaiAsmParser.o
[708/1702] CXX obj/llvm/lib/Target/Lanai/LLVMLanaiCodeGen.LanaiTargetObjectFile.o
[709/1702] CXX obj/llvm/lib/Target/BPF/LLVMBPFCodeGen.BPFTargetMachine.o
[710/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonPostRAHandleQFP.o
[711/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonISelLowering.o
[712/1702] CXX obj/llvm/lib/Target/AMDGPU/LLVMAMDGPUCodeGen.AMDGPUInstructionSelector.o
[713/1702] CXX obj/llvm/lib/Target/ARM/LLVMARMCodeGen.ARMISelLowering.o
[714/1702] CXX obj/llvm/lib/Target/LoongArch/LLVMLoongArchCodeGen.LoongArchExpandAtomicPseudoInsts.o
[715/1702] CXX obj/llvm/lib/Target/LoongArch/LLVMLoongArchCodeGen.LoongArchFrameLowering.o
[716/1702] CXX obj/llvm/lib/Target/Lanai/LLVMLanaiCodeGen.LanaiISelLowering.o
[717/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonLoopIdiomRecognition.o
[718/1702] CXX obj/llvm/lib/Target/LoongArch/LLVMLoongArchCodeGen.LoongArchExpandPseudoInsts.o
[719/1702] CXX obj/llvm/lib/Target/LoongArch/LLVMLoongArchCodeGen.LoongArchMemoryBarrierOpt.o
[720/1702] CXX obj/llvm/lib/Target/LoongArch/LLVMLoongArchCodeGen.LoongArchLateBranchOpt.o
[721/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonInstrInfo.o
[722/1702] CXX obj/llvm/lib/Target/LoongArch/LLVMLoongArchCodeGen.LoongArchSubtarget.o
[723/1702] CXX obj/llvm/lib/Target/LoongArch/LLVMLoongArchCodeGen.LoongArchAsmPrinter.o
[724/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.Mips16RegisterInfo.o
[725/1702] CXX obj/llvm/lib/Target/LoongArch/LLVMLoongArchCodeGen.LoongArchRegisterInfo.o
[726/1702] CXX obj/llvm/lib/Target/AMDGPU/Disassembler/Disassembler.AMDGPUDisassembler.o
[727/1702] CXX obj/llvm/lib/Target/LoongArch/LLVMLoongArchCodeGen.LoongArchOptWInstrs.o
[728/1702] CXX obj/llvm/lib/Target/LoongArch/LLVMLoongArchCodeGen.LoongArchMergeBaseOffset.o
[729/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.Mips16InstrInfo.o
[730/1702] CXX obj/llvm/lib/Target/LoongArch/LLVMLoongArchCodeGen.LoongArchISelDAGToDAG.o
[731/1702] CXX obj/llvm/lib/Target/LoongArch/LLVMLoongArchCodeGen.LoongArchInstrInfo.o
[732/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsCCState.o
[733/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.Mips16FrameLowering.o
[734/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsCallLowering.o
[735/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MicroMipsSizeReduction.o
[736/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.Mips16ISelLowering.o
[737/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonTargetTransformInfo.o
[738/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.Mips16HardFloat.o
[739/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.Mips16ISelDAGToDAG.o
[740/1702] CXX obj/llvm/lib/Target/PowerPC/GISel/LLVMPowerPCCodeGen.PPCRegisterBankInfo.o
[741/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsBranchExpansion.o
[742/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsFrameLowering.o
[743/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsMachineFunction.o
[744/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsMulMulBugPass.o
[745/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsPreLegalizerCombiner.o
[746/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsOptimizePICCall.o
[747/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsAsmPrinter.o
[748/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsExpandPseudo.o
[749/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsOs16.o
[750/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsDelaySlotFiller.o
[751/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsMCInstLower.o
[752/1702] CXX obj/llvm/lib/Target/Lanai/LLVMLanaiCodeGen.LanaiTargetMachine.o
[753/1702] CXX obj/llvm/lib/Target/NVPTX/LLVMNVPTXCodeGen.NVPTXAddressFolder.o
[754/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsConstantIslandPass.o
[755/1702] CXX obj/llvm/lib/Target/NVPTX/LLVMNVPTXCodeGen.NVPTXForwardParams.o
[756/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsLegalizerInfo.o
[757/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsISelDAGToDAG.o
[758/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsInstrInfo.o
[759/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsRegisterInfo.o
[760/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonTargetMachine.o
[761/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsSubtarget.o
[762/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsSERegisterInfo.o
[763/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsSEFrameLowering.o
[764/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsTargetObjectFile.o
[765/1702] CXX obj/llvm/lib/Target/NVPTX/LLVMNVPTXCodeGen.NVPTXFrameLowering.o
[766/1702] CXX obj/llvm/lib/Target/LoongArch/LLVMLoongArchCodeGen.LoongArchTargetMachine.o
[767/1702] CXX obj/llvm/lib/Target/NVPTX/LLVMNVPTXCodeGen.NVPTXProxyRegErasure.o
[768/1702] CXX obj/llvm/lib/Target/NVPTX/LLVMNVPTXCodeGen.NVPTXPeephole.o
[769/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsSEInstrInfo.o
[770/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsSEISelDAGToDAG.o
[771/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCBoolRetToInt.o
[772/1702] CXX obj/llvm/lib/Target/NVPTX/LLVMNVPTXCodeGen.NVPTXInstrInfo.o
[773/1702] CXX obj/llvm/lib/Target/NVPTX/LLVMNVPTXCodeGen.NVPTXPrologEpilogPass.o
[774/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsRegisterBankInfo.o
[775/1702] CXX obj/llvm/lib/Target/NVPTX/LLVMNVPTXCodeGen.NVPTXLowerAggrCopies.o
[776/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsSEISelLowering.o
[777/1702] CXX obj/llvm/lib/Target/LoongArch/LLVMLoongArchCodeGen.LoongArchTargetTransformInfo.o
[778/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCCTRLoopsVerify.o
[779/1702] CXX obj/llvm/lib/Target/NVPTX/LLVMNVPTXCodeGen.NVPTXRegisterInfo.o
[780/1702] CXX obj/llvm/lib/Target/Hexagon/LLVMHexagonCodeGen.HexagonVectorCombine.o
[781/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCBranchCoalescing.o
[782/1702] CXX obj/llvm/lib/Target/NVPTX/LLVMNVPTXCodeGen.NVPTXSubtarget.o
[783/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsFastISel.o
[784/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCEarlyReturn.o
[785/1702] CXX obj/llvm/lib/Target/NVPTX/LLVMNVPTXCodeGen.NVPTXReplaceImageHandles.o
[786/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCExpandAtomicPseudoInsts.o
[787/1702] CXX obj/llvm/lib/Target/PowerPC/GISel/LLVMPowerPCCodeGen.PPCCallLowering.o
[788/1702] CXX obj/llvm/lib/Target/NVPTX/LLVMNVPTXCodeGen.NVPTXLowerArgs.o
[789/1702] CXX obj/llvm/lib/Target/NVPTX/LLVMNVPTXCodeGen.NVPTXDwarfDebug.o
[790/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCBranchSelector.o
[791/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsISelLowering.o
[792/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsInstructionSelector.o
[793/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCCTRLoops.o
[794/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCCallingConv.o
[795/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCMachineScheduler.o
[796/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCHazardRecognizers.o
[797/1702] CXX obj/llvm/lib/Target/PowerPC/AsmParser/AsmParser.PPCAsmParser.o
[798/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsPostLegalizerCombiner.o
[799/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCAsmPrinter.o
[800/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsTargetMachine.o
[801/1702] CXX obj/llvm/lib/Target/NVPTX/LLVMNVPTXCodeGen.NVPTXISelDAGToDAG.o
[802/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCMacroFusion.o
[803/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCTOCRegDeps.o
[804/1702] CXX obj/llvm/lib/Target/Mips/LLVMMipsCodeGen.MipsTargetTransformInfo.o
[805/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCReduceCRLogicals.o
[806/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCTLSDynamicCall.o
[807/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCPrepareIFuncsOnAIX.o
[808/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCLowerMASSVEntries.o
[809/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCMCInstLower.o
[810/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCVSXWACCCopy.o
[811/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCGenScalarMASSEntries.o
[812/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCSubtarget.o
[813/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCPreEmitPeephole.o
[814/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCVSXFMAMutate.o
[815/1702] CXX obj/llvm/lib/Target/NVPTX/LLVMNVPTXCodeGen.NVPTXCodeGenPassBuilder.o
[816/1702] CXX obj/llvm/lib/Target/LoongArch/LLVMLoongArchCodeGen.LoongArchISelLowering.o
[817/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCFastISel.o
[818/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCFrameLowering.o
[819/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCMIPeephole.o
[820/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCVSXSwapRemoval.o
[821/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCRegisterInfo.o
[822/1702] CXX obj/llvm/lib/Target/NVPTX/LLVMNVPTXCodeGen.NVPTXTargetMachine.o
[823/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVExpandPseudoBase.o
[824/1702] CXX obj/llvm/lib/Target/NVPTX/LLVMNVPTXCodeGen.NVPTXAsmPrinter.o
[825/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVExpandPseudoPostRA.o
[826/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVDeadRegisterDefinitions.o
[827/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVExpandPseudoAtomics.o
[828/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVExpandPseudoPreEmit.o
[829/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVFoldMemOffset.o
[830/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCInstrInfo.o
[831/1702] CXX obj/llvm/lib/Target/NVPTX/LLVMNVPTXCodeGen.NVPTXISelLowering.o
[832/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCLoopInstrFormPrep.o
[833/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVInsertReadWriteCSR.o
[834/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVExpandPseudoPreRA.o
[835/1702] CXX obj/llvm/lib/Target/RISCV/GISel/LLVMRISCVCodeGen.RISCVCallLowering.o
[836/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVCodeGenPrepare.o
[837/1702] CXX obj/llvm/lib/Target/NVPTX/LLVMNVPTXCodeGen.NVPTXTargetTransformInfo.o
[838/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVInsertWriteVXRM.o
[839/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVLateBranchOpt.o
[840/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVLandingPadSetup.o
[841/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVRedundantCopyElimination.o
[842/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVIndirectBranchTracking.o
[843/1702] CXX obj/llvm/lib/Target/RISCV/GISel/LLVMRISCVCodeGen.RISCVLegalizerInfo.o
[844/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVMachineScheduler.o
[845/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVMakeCompressible.o
[846/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVInsertVSETVLI.o
[847/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVLoadStoreOptimizer.o
[848/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVMachineFunctionInfo.o
[849/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVQCRelaxMarking.o
[850/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVGatherScatterLowering.o
[851/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVFrameLowering.o
[852/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVMoveMerger.o
[853/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVInterleavedAccess.o
[854/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVSelectionDAGInfo.o
[855/1702] CXX obj/llvm/lib/Target/RISCV/GISel/LLVMRISCVCodeGen.RISCVO0PreLegalizerCombiner.o
[856/1702] CXX obj/llvm/lib/Target/Sparc/LLVMSparcCodeGen.LeonPasses.o
[857/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVPushPopOptimizer.o
[858/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCTargetMachine.o
[859/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCTargetTransformInfo.o
[860/1702] CXX obj/llvm/lib/Target/Sparc/LLVMSparcCodeGen.DelaySlotFiller.o
[861/1702] CXX obj/llvm/lib/Target/RISCV/GISel/LLVMRISCVCodeGen.RISCVPostLegalizerCombiner.o
[862/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVMergeBaseOffset.o
[863/1702] CXX obj/llvm/lib/Target/PowerPC/GISel/LLVMPowerPCCodeGen.PPCInstructionSelector.o
[864/1702] CXX obj/llvm/lib/Target/Sparc/LLVMSparcCodeGen.SparcRegisterInfo.o
[865/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVVMV0Elimination.o
[866/1702] CXX obj/llvm/lib/Target/Sparc/LLVMSparcCodeGen.SparcSubtarget.o
[867/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVPromoteConstant.o
[868/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVOptWInstrs.o
[869/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCISelDAGToDAG.o
[870/1702] CXX obj/llvm/lib/Target/Sparc/LLVMSparcCodeGen.SparcInstrInfo.o
[871/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVVectorMaskDAGMutation.o
[872/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVTargetObjectFile.o
[873/1702] CXX obj/llvm/lib/Target/Sparc/LLVMSparcCodeGen.SparcFrameLowering.o
[874/1702] CXX obj/llvm/lib/Target/Sparc/LLVMSparcCodeGen.SparcISelDAGToDAG.o
[875/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZCallingConv.o
[876/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVZilsdOptimizer.o
[877/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVVSETVLIInfoAnalysis.o
[878/1702] CXX obj/llvm/lib/Target/Sparc/LLVMSparcCodeGen.SparcTargetObjectFile.o
[879/1702] CXX obj/llvm/lib/Target/Sparc/LLVMSparcCodeGen.SparcAsmPrinter.o
[880/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVRegisterInfo.o
[881/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVVectorPeephole.o
[882/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVZacasABIFix.o
[883/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVVLOptimizer.o
[884/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZHazardRecognizer.o
[885/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZCopyPhysRegs.o
[886/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVSubtarget.o
[887/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZElimCompare.o
[888/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZPostRewrite.o
[889/1702] CXX obj/llvm/lib/Target/Sparc/LLVMSparcCodeGen.SparcISelLowering.o
[890/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZLDCleanup.o
[891/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZFrameLowering.o
[892/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZSubtarget.o
[893/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZLongBranch.o
[894/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZMachineScheduler.o
[895/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZELFAsmPrinter.o
[896/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZAsmPrinter.o
[897/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZSelectionDAGInfo.o
[898/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZTDC.o
[899/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZShortenInst.o
[900/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZMCInstLower.o
[901/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZInstrInfo.o
[902/1702] CXX obj/llvm/lib/Target/Sparc/LLVMSparcCodeGen.SparcTargetMachine.o
[903/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZRegisterInfo.o
[904/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVInstrInfo.o
[905/1702] CXX obj/llvm/lib/Target/WebAssembly/GISel/LLVMWebAssemblyCodeGen.WebAssemblyRegisterBankInfo.o
[906/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyArgumentMove.o
[907/1702] CXX obj/llvm/lib/Target/PowerPC/LLVMPowerPCCodeGen.PPCISelLowering.o
[908/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZISelDAGToDAG.o
[909/1702] CXX obj/llvm/lib/Target/Sparc/LLVMSparcCodeGen.SparcTargetTransformInfo.o
[910/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyAddMissingPrototypes.o
[911/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyCleanCodeAfterTrap.o
[912/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVTargetMachine.o
[913/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyFixBrTableDefaults.o
[914/1702] CXX obj/llvm/lib/Target/WebAssembly/GISel/LLVMWebAssemblyCodeGen.WebAssemblyLegalizerInfo.o
[915/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyCFGSort.o
[916/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyExceptionInfo.o
[917/1702] CXX obj/llvm/lib/Target/WebAssembly/GISel/LLVMWebAssemblyCodeGen.WebAssemblyCallLowering.o
[918/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyDebugFixup.o
[919/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyFixFunctionBitcasts.o
[920/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZXPLINKAsmPrinter.o
[921/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyDebugValueManager.o
[922/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVISelDAGToDAG.o
[923/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyCoalesceFeaturesAndStripAtomics.o
[924/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyISelDAGToDAG.o
[925/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyFrameLowering.o
[926/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyLateEHPrepare.o
[927/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyLowerBrUnless.o
[928/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyInstrInfo.o
[929/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyNullifyDebugValueLists.o
[930/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyExplicitLocals.o
[931/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyFastISel.o
[932/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyMCLowerPrePass.o
[933/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyMCInstLower.o
[934/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVTargetTransformInfo.o
[935/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyFixIrreducibleControlFlow.o
[936/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZTargetMachine.o
[937/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyMachineFunctionInfo.o
[938/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyMemIntrinsicResults.o
[939/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyOptimizeLiveIntervals.o
[940/1702] CXX obj/llvm/lib/Target/WebAssembly/GISel/LLVMWebAssemblyCodeGen.WebAssemblyInstructionSelector.o
[941/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyAsmPrinter.o
[942/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZTargetTransformInfo.o
[943/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyReplacePhysRegs.o
[944/1702] CXX obj/llvm/lib/Target/WebAssembly/GISel/LLVMWebAssemblyCodeGen.WebAssemblyPreLegalizerCombiner.o
[945/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyOptimizeReturned.o
[946/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyRegNumbering.o
[947/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblySelectionDAGInfo.o
[948/1702] CXX obj/llvm/lib/Target/WebAssembly/GISel/LLVMWebAssemblyCodeGen.WebAssemblyPostLegalizerCombiner.o
[949/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblySortRegion.o
[950/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyRuntimeLibcallSignatures.o
[951/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblySetP2AlignOperands.o
[952/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyReduceToAnyAllTrue.o
[953/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyCFGStackify.o
[954/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyPeephole.o
[955/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblySubtarget.o
[956/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyRefTypeMem2Local.o
[957/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyRegisterInfo.o
[958/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyISelLowering.o
[959/1702] CXX obj/llvm/lib/Target/X86/GISel/LLVMX86CodeGen.X86RegisterBankInfo.o
[960/1702] CXX obj/llvm/lib/Transforms/IPO/IPO.IPO.o
[961/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyUtilities.o
[962/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyRegColoring.o
[963/1702] CXX obj/llvm/lib/Target/SystemZ/LLVMSystemZCodeGen.SystemZISelLowering.o
[964/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyRegStackify.o
[965/1702] CXX obj/llvm/lib/Transforms/IPO/IPO.BarrierNoopPass.o
[966/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyLowerEmscriptenEHSjLj.o
[967/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86AvoidTrailingCall.o
[968/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyCodeGenPassBuilder.o
[969/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86ArgumentStackSlotRebase.o
[970/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86AvoidStoreForwardingBlocks.o
[971/1702] CXX obj/llvm/lib/Target/X86/GISel/LLVMX86CodeGen.X86LegalizerInfo.o
[972/1702] CXX obj/llvm/lib/Target/X86/GISel/LLVMX86CodeGen.X86CallLowering.o
[973/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86CleanupLocalDynamicTLS.o
[974/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86CompressEVEX.o
[975/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86CallFrameOptimization.o
[976/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86FixupBWInsts.o
[977/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86FixupInstTuning.o
[978/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86InstrFMA3Info.o
[979/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86FixupSetCC.o
[980/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86DynAllocaExpander.o
[981/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86DomainReassignment.o
[982/1702] CXX obj/llvm/lib/Transforms/CFGuard/CFGuard.CFGuard.o
[983/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.FlattenCFGPass.o
[984/1702] AR lib/libLLVMCFGuard.a
[985/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86ExpandPseudo.o
[986/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86InstrFoldTables.o
[987/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.Scalar.o
[988/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86CmovConversion.o
[989/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86FixupLEAs.o
[990/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86FixupVectorConstants.o
[991/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86FastPreTileConfig.o
[992/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86FastTileConfig.o
[993/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86GlobalBaseReg.o
[994/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86FloatingPoint.o
[995/1702] CXX obj/llvm/lib/Transforms/Utils/Utils.FixIrreducible.o
[996/1702] CXX obj/llvm/lib/Transforms/Utils/Utils.EntryExitInstrumenter.o
[997/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86InsertX87Wait.o
[998/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86AsmPrinter.o
[999/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.InstSimplifyPass.o
[1000/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86CallingConv.o
[1001/1702] CXX obj/llvm/lib/Transforms/IPO/IPO.AlwaysInliner.o
[1002/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86InsertVZeroUpper.o
[1003/1702] CXX obj/llvm/lib/Transforms/Utils/Utils.CanonicalizeFreezeInLoops.o
[1004/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.DCE.o
[1005/1702] CXX obj/llvm/lib/Transforms/ObjCARC/ObjCARC.ObjCARCContract.o
[1006/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86IndirectBranchTracking.o
[1007/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86LoadValueInjectionRetHardening.o
[1008/1702] CXX obj/llvm/lib/Transforms/IPO/IPO.ExpandVariadics.o
[1009/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.LowerAtomicPass.o
[1010/1702] CXX obj/llvm/lib/Transforms/IPO/IPO.GlobalDCE.o
[1011/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86IndirectThunks.o
[1012/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86FlagsCopyLowering.o
[1013/1702] LINK ./bin/llvm-bcanalyzer
[1014/1702] CXX obj/llvm/lib/Target/X86/GISel/LLVMX86CodeGen.X86PostLegalizerCombiner.o
[1015/1702] CXX obj/llvm/lib/Target/X86/GISel/LLVMX86CodeGen.X86PreLegalizerCombiner.o
[1016/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyTargetMachine.o
[1017/1702] LINK ./bin/llvm-ctxprof-util
[1018/1702] LINK ./bin/llubi
[1019/1702] CXX obj/llvm/lib/Transforms/Utils/Utils.Utils.o
[1020/1702] LINK ./bin/llvm-cvtres
[1021/1702] CXX obj/llvm/lib/Transforms/IPO/IPO.DeadArgumentElimination.o
[1022/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86InterleavedAccess.o
[1023/1702] LINK ./bin/llvm-cov
[1024/1702] CXX obj/llvm/lib/Transforms/Vectorize/Vectorize.Vectorize.o
[1025/1702] LINK ./bin/llvm-debuginfod
[1026/1702] LINK ./bin/llvm-diff
[1027/1702] LINK ./bin/llvm-dis
[1028/1702] LINK ./bin/llvm-debuginfod-find
[1029/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.Reg2Mem.o
[1030/1702] ACTION //llvm/tools/llvm-objcopy:llvm-bitcode-strip(//llvm/utils/gn/build/toolchain:unix)
[1031/1702] ACTION //llvm/tools/llvm-objcopy:llvm-install-name-tool(//llvm/utils/gn/build/toolchain:unix)
[1032/1702] ACTION //llvm/tools/llvm-objcopy:llvm-extract-bundle-entry(//llvm/utils/gn/build/toolchain:unix)
[1033/1702] LINK ./bin/llvm-offload-binary
[1034/1702] LINK ./bin/llvm-profdata
[1035/1702] LINK ./bin/llvm-opt-report
[1036/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86LowerTileCopy.o
[1037/1702] LINK ./bin/llvm-pdbutil
[1038/1702] LINK ./bin/llvm-rc
[1039/1702] ACTION //llvm/tools/llvm-rc:llvm-windres(//llvm/utils/gn/build/toolchain:unix)
[1040/1702] CXX obj/llvm/lib/Target/WebAssembly/LLVMWebAssemblyCodeGen.WebAssemblyTargetTransformInfo.o
[1041/1702] LINK ./bin/llvm-readobj
[1042/1702] ACTION //llvm/tools/llvm-readobj:llvm-readelf(//llvm/utils/gn/build/toolchain:unix)
[1043/1702] CXX obj/llvm/lib/Transforms/Utils/Utils.LowerInvoke.o
[1044/1702] LINK ./bin/llvm-readtapi
[1045/1702] LINK ./bin/llvm-stress
[1046/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.ConstantHoisting.o
[1047/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86LowerAMXType.o
[1048/1702] LINK ./bin/llvm-strings
[1049/1702] LINK ./bin/llvm-size
[1050/1702] CXX obj/llvm/lib/Transforms/Utils/Utils.Mem2Reg.o
[1051/1702] LINK ./bin/llvm-symbolizer
[1052/1702] ACTION //llvm/tools/llvm-symbolizer:llvm-addr2line(//llvm/utils/gn/build/toolchain:unix)
[1053/1702] LINK ./bin/llvm-remarkutil
[1054/1702] LINK ./bin/llvm-tli-checker
[1055/1702] CXX obj/llvm/lib/Transforms/Utils/Utils.LowerGlobalDtors.o
[1056/1702] LINK ./bin/obj2yaml
[1057/1702] LINK ./bin/yaml2obj
[1058/1702] LINK obj/llvm/unittests/ABI/ABITests
[1059/1702] CXX obj/llvm/lib/Transforms/Utils/Utils.BreakCriticalEdges.o
[1060/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.LoopDataPrefetch.o
[1061/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.Sink.o
[1062/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.SpeculativeExecution.o
[1063/1702] CXX obj/llvm/lib/Target/X86/GISel/LLVMX86CodeGen.X86InstructionSelector.o
[1064/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.PartiallyInlineLibCalls.o
[1065/1702] LINK obj/llvm/unittests/AsmParser/AsmParserTests
[1066/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86CodeGenPassBuilder.o
[1067/1702] CXX obj/llvm/lib/Transforms/Utils/Utils.StripConvergenceIntrinsics.o
[1068/1702] CXX obj/llvm/lib/Transforms/Utils/Utils.LowerSwitch.o
[1069/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.InferAddressSpaces.o
[1070/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.PlaceSafepoints.o
[1071/1702] CXX obj/llvm/lib/Transforms/Utils/Utils.UnifyLoopExits.o
[1072/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.EarlyCSE.o
[1073/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86LowerAMXIntrinsics.o
[1074/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.LoopTermFold.o
[1075/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86LoadValueInjectionLoadHardening.o
[1076/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86FrameLowering.o
[1077/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86ISelLoweringCall.o
[1078/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.SimplifyCFGPass.o
[1079/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.NaryReassociate.o
[1080/1702] CXX obj/llvm/lib/Transforms/Utils/Utils.LCSSA.o
[1081/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.ScalarizeMaskedMemIntrin.o
[1082/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86InstCombineIntrinsic.o
[1083/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.SeparateConstOffsetFromGEP.o
[1084/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86MCInstLower.o
[1085/1702] CXX obj/llvm/lib/Transforms/Utils/Utils.LoopSimplify.o
[1086/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.TailRecursionElimination.o
[1087/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.Scalarizer.o
[1088/1702] CXX obj/llvm/tools/llvm-exegesis/lib/RISCV/RISCV.RISCVExegesisPostprocessing.o
[1089/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.LoopUnrollPass.o
[1090/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.DeadStoreElimination.o
[1091/1702] CXX obj/llvm/tools/llvm-reduce/deltas/llvm-reduce.ReduceRegisterUses.o
[1092/1702] CXX obj/llvm/tools/llvm-reduce/deltas/llvm-reduce.ReduceRegisterMasks.o
[1093/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86FastISel.o
[1094/1702] CXX obj/llvm/tools/llvm-reduce/deltas/llvm-reduce.ReduceVirtualRegisters.o
[1095/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.StraightLineStrengthReduce.o
[1096/1702] LINK obj/llvm/unittests/DebugInfo/BTF/DebugInfoBTFTests
[1097/1702] LINK obj/llvm/unittests/DebugInfo/Symbolizer/DebugInfoSymbolizerTests
[1098/1702] LINK obj/llvm/unittests/Debuginfod/DebuginfodTests
[1099/1702] CXX obj/llvm/tools/llvm-ir2vec/lib/MIRUtils/MIRUtils.MIRUtils.o
[1100/1702] LINK obj/llvm/unittests/DebugInfo/PDB/DebugInfoPDBTests
[1101/1702] CXX obj/llvm/unittests/Analysis/AnalysisTests.CFGTest.o
[1102/1702] CXX obj/llvm/tools/llvm-exegesis/lib/RISCV/RISCV.RISCVExegesisPreprocessing.o
[1103/1702] CXX obj/llvm/tools/llvm-reduce/deltas/llvm-reduce.ReduceInstructionsMIR.o
[1104/1702] LINK obj/llvm/unittests/InterfaceStub/InterfaceStubTests
[1105/1702] CXX obj/llvm/tools/llvm-reduce/deltas/llvm-reduce.ReduceRegisterDefs.o
[1106/1702] LINK obj/llvm/unittests/ObjCopy/ObjCopyTests
[1107/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.Reassociate.o
[1108/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.GVN.o
[1109/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.LICM.o
[1110/1702] LINK obj/llvm/unittests/Object/ObjectTests
[1111/1702] CXX obj/llvm/unittests/Analysis/AnalysisTests.AliasAnalysisTest.o
[1112/1702] CXX obj/llvm/tools/llvm-ir2vec/llvm-ir2vec.llvm-ir2vec.o
[1113/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.StructurizeCFG.o
[1114/1702] LINK obj/llvm/unittests/ObjectYAML/ObjectYAMLTests
[1115/1702] LINK obj/llvm/unittests/Remarks/RemarksTests
[1116/1702] CXX obj/llvm/tools/llvm-calc-occupancy/llvm-calc-occupancy.llvm-calc-occupancy.o
[1117/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86InstrInfo.o
[1118/1702] LINK obj/llvm/unittests/ProfileData/ProfileDataTests
[1119/1702] LINK obj/llvm/unittests/SandboxIR/SandboxIRTests
[1120/1702] CXX obj/llvm/tools/llc/lib/lib.llcdriver.o
[1121/1702] AR lib/libLLVMLlcDriver.a
[1122/1702] CXX obj/llvm/unittests/CodeGen/GlobalISel/GlobalISelTests.IRTranslatorBF16Test.o
[1123/1702] CXX obj/llvm/lib/Target/RISCV/LLVMRISCVCodeGen.RISCVISelLowering.o
[1124/1702] CXX obj/llvm/lib/Transforms/Utils/Utils.LoopUtils.o
[1125/1702] AR lib/libLLVMTransformUtils.a
[1126/1702] AR lib/libLLVMBitWriter.a
[1127/1702] LINK ./bin/verify-uselistorder
[1128/1702] AR lib/libLLVMObjCARCOpts.a
[1129/1702] LINK ./bin/llvm-as
[1130/1702] CXX obj/llvm/unittests/CodeGen/CodeGenTests.RegAllocBasicTest.o
[1131/1702] CXX obj/llvm/unittests/ExecutionEngine/MCJIT/MCJITTests.MCJITCAPITest.o
[1132/1702] LINK ./bin/llvm-cat
[1133/1702] CXX obj/llvm/unittests/CodeGen/CodeGenTests.TargetOptionsTest.o
[1134/1702] LINK ./bin/llvm-offload-wrapper
[1135/1702] LINK ./bin/llvm-modextract
[1136/1702] LINK obj/llvm/unittests/Bitcode/BitcodeTests
[1137/1702] LINK obj/llvm/unittests/Linker/LinkerTests
[1138/1702] CXX obj/llvm/unittests/CodeGen/GlobalISel/GlobalISelTests.GISelMITest.o
[1139/1702] CXX obj/llvm/unittests/CodeGen/GlobalISel/GlobalISelTests.InstructionSelectTest.o
[1140/1702] CXX obj/llvm/lib/Transforms/Vectorize/Vectorize.LoadStoreVectorizer.o
[1141/1702] AR lib/libLLVMVectorize.a
[1142/1702] CXX obj/llvm/tools/llvm-exegesis/lib/lib.SnippetRepetitor.o
[1143/1702] CXX obj/llvm/unittests/CodeGen/CodeGenTests.SchedBoundary.o
[1144/1702] CXX obj/llvm/unittests/CodeGen/CodeGenTests.TypeTraitsTest.o
[1145/1702] CXX obj/llvm/unittests/CodeGen/GlobalISel/GlobalISelTests.LegalizerTest.o
[1146/1702] CXX obj/llvm/unittests/CodeGen/GlobalISel/GlobalISelTests.KnownFPClassTest.o
[1147/1702] CXX obj/llvm/lib/Transforms/InstCombine/InstCombine.InstructionCombining.o
[1148/1702] AR lib/libLLVMInstCombine.a
[1149/1702] CXX obj/llvm/unittests/CodeGen/CodeGenTests.SelectionDAGAddressAnalysisTest.o
[1150/1702] CXX obj/llvm/unittests/CodeGen/GlobalISel/GlobalISelTests.MachineIRBuilderTest.o
[1151/1702] CXX obj/llvm/unittests/CodeGen/CodeGenTests.SelectionDAGCSETest.o
[1152/1702] CXX obj/llvm/unittests/CodeGen/GlobalISel/GlobalISelTests.LegalizerInfoTest.o
[1153/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86ISelDAGToDAG.o
[1154/1702] CXX obj/llvm/unittests/ExecutionEngine/MCJIT/MCJITTests.MCJITObjectCacheTest.o
[1155/1702] LINK obj/llvm/unittests/Telemetry/TelemetryTests
[1156/1702] CXX obj/llvm/unittests/IR/IRTests.LegacyPassManagerTest.o
[1157/1702] LINK obj/llvm/unittests/XRay/XRayTests
[1158/1702] LINK obj/llvm/unittests/Transforms/Vectorize/VectorizeTests
[1159/1702] CXX obj/llvm/unittests/ExecutionEngine/MCJIT/MCJITTests.MCJITMultipleModuleTest.o
[1160/1702] LINK obj/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizerTests
[1161/1702] CXX obj/llvm/tools/opt/lib.optdriver.o
[1162/1702] CXX obj/llvm/unittests/CodeGen/GlobalISel/GlobalISelTests.GISelUtilsTest.o
[1163/1702] CXX obj/llvm/tools/llvm-exegesis/lib/lib.Assembler.o
[1164/1702] CXX obj/llvm/unittests/ExecutionEngine/MCJIT/MCJITTests.MCJITTest.o
[1165/1702] CXX obj/llvm/tools/lli/lli.lli.o
[1166/1702] CXX obj/llvm/unittests/CodeGen/CodeGenTests.RegAllocScoreTest.o
[1167/1702] CXX obj/llvm/unittests/CodeGen/GlobalISel/GlobalISelTests.CSETest.o
[1168/1702] LINK obj/llvm/unittests/tools/llvm-profdata/LLVMProfdataTests
[1169/1702] CXX obj/llvm/unittests/CodeGen/CodeGenTests.RegisterPressureTest.o
[1170/1702] CXX obj/llvm/unittests/CodeGen/CodeGenTests.SelectionDAGNodeConstructionTest.o
[1171/1702] CXX obj/llvm/unittests/tools/llvm-exegesis/X86/LLVMExegesisX86Tests.RegisterAliasingTest.o
[1172/1702] CXX obj/llvm/tools/llvm-reduce/llvm-reduce.ReducerWorkItem.o
[1173/1702] CXX obj/llvm/unittests/CodeGen/CodeGenTests.MachineOperandTest.o
[1174/1702] CXX obj/llvm/unittests/CodeGen/GlobalISel/GlobalISelTests.GISelAliasTest.o
[1175/1702] CXX obj/llvm/unittests/CodeGen/GlobalISel/GlobalISelTests.ConstantFoldingTest.o
[1176/1702] CXX obj/llvm/tools/llvm-exegesis/lib/RISCV/RISCV.Target.o
[1177/1702] CXX obj/llvm/unittests/CodeGen/CodeGenTests.MachineInstrTest.o
[1178/1702] CXX obj/llvm/unittests/CodeGen/CodeGenTests.LexicalScopesTest.o
[1179/1702] CXX obj/llvm/unittests/CodeGen/GlobalISel/GlobalISelTests.KnownBitsVectorTest.o
[1180/1702] CXX obj/llvm/unittests/MI/MITests.LiveIntervalTest.o
[1181/1702] CXX obj/llvm/unittests/CodeGen/CodeGenTests.MachineBasicBlockTest.o
[1182/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.SROA.o
[1183/1702] CXX obj/llvm/lib/Target/RISCV/GISel/LLVMRISCVCodeGen.RISCVInstructionSelector.o
[1184/1702] CXX obj/llvm/lib/Transforms/Scalar/Scalar.LoopStrengthReduce.o
[1185/1702] AR lib/libLLVMScalarOpts.a
[1186/1702] CXX obj/llvm/unittests/CodeGen/CodeGenTests.X86MCInstLowerTest.o
[1187/1702] LINK ./bin/clang-apply-replacements
[1188/1702] LINK ./bin/clang-ssaf-src-edit-merge
[1189/1702] LINK obj/clang-tools-extra/unittests/clang-apply-replacements/ClangApplyReplacementsTests
[1190/1702] CXX obj/llvm/unittests/Target/AArch64/AArch64Tests.DecomposeStackOffsetTest.o
[1191/1702] LINK ./bin/clang-ssaf-linker
[1192/1702] LINK ./bin/clang-ssaf-analyzer
[1193/1702] LINK ./bin/clang-change-namespace
[1194/1702] LINK ./bin/clang-query
[1195/1702] LINK ./bin/find-all-symbols
[1196/1702] LINK ./bin/clang-include-fixer
[1197/1702] LINK obj/clang-tools-extra/include-cleaner/unittests/ClangIncludeCleanerTests
[1198/1702] LINK ./bin/clang-move
[1199/1702] LINK ./bin/modularize
[1200/1702] LINK ./bin/clang-doc
[1201/1702] LINK ./bin/clang-reorder-fields
[1202/1702] LINK ./bin/clangd-remap
[1203/1702] LINK ./bin/dexp
[1204/1702] LINK obj/clang-tools-extra/unittests/clang-change-namespace/ClangChangeNamespaceTests
[1205/1702] LINK ./bin/pp-trace
[1206/1702] LINK obj/clang-tools-extra/unittests/clang-doc/ClangDocTests
[1207/1702] LINK ./bin/clang-offload-bundler
[1208/1702] LINK ./bin/clangd
[1209/1702] LINK obj/clang-tools-extra/unittests/clang-move/ClangMoveTests
[1210/1702] LINK obj/clang-tools-extra/unittests/clang-include-fixer/find-all-symbols/FindAllSymbolsTests
[1211/1702] LINK obj/clang-tools-extra/clangd/unittests/ClangdTests
[1212/1702] LINK ./bin/clang-ssaf-format
[1213/1702] LINK obj/clang-tools-extra/unittests/clang-include-fixer/ClangIncludeFixerTests
[1214/1702] LINK ./bin/clangd-indexer
[1215/1702] LINK obj/clang/unittests/DependencyScanning/ClangDependencyScanningTests
[1216/1702] LINK obj/clang/unittests/Analysis/ClangAnalysisTests
[1217/1702] LINK obj/clang-tools-extra/unittests/clang-query/ClangQueryTests
[1218/1702] LINK ./bin/diagtool
[1219/1702] LINK obj/clang/unittests/Format/FormatTests
[1220/1702] LINK ./bin/clang-diff
[1221/1702] LINK ./bin/clang-installapi
[1222/1702] LINK ./bin/clang-refactor
[1223/1702] LINK obj/clang/unittests/InstallAPI/InstallAPITests
[1224/1702] AR lib/libLLVMipo.a
[1225/1702] AR lib/libLLVMCodeGen.a
[1226/1702] AR lib/libLLVMMIRParser.a
[1227/1702] AR lib/libLLVMAsmPrinter.a
[1228/1702] AR lib/libLLVMBOLTTargetAArch64.a
[1229/1702] LINK obj/clang/unittests/ASTMatchers/ASTMatchersTests
[1230/1702] AR lib/libLLVMSelectionDAG.a
[1231/1702] AR lib/libLLVMGlobalISel.a
[1232/1702] LINK obj/clang/unittests/ASTMatchers/Dynamic/DynamicASTMatchersTests
[1233/1702] AR lib/libLLVMPasses.a
[1234/1702] AR lib/libLLVMAArch64AsmParser.a
[1235/1702] AR lib/libLLVMLTO.a
[1236/1702] AR lib/libclangCodeGen.a
[1237/1702] LINK obj/clang-tools-extra/unittests/clang-tidy/ClangTidyTests
[1238/1702] LINK obj/clang/unittests/Index/IndexTests
[1239/1702] LINK obj/llvm/unittests/FuzzMutate/FuzzMutateTests
[1240/1702] LINK obj/clang/unittests/AST/ByteCode/InterpTests
[1241/1702] LINK obj/clang/unittests/AST/ASTTests
[1242/1702] AR lib/libLLVMAMDGPUDisassembler.a
[1243/1702] AR lib/libLLVMAMDGPUAsmParser.a
[1244/1702] AR lib/libLLVMAMDGPUCodeGen.a
[1245/1702] AR lib/libLLVMARMAsmParser.a
[1246/1702] LINK obj/clang/unittests/Analysis/FlowSensitive/ClangAnalysisFlowSensitiveTests
[1247/1702] CXX obj/llvm/unittests/MIR/MIRTests.MachineMetadata.o
[1248/1702] AR lib/libLLVMARMDisassembler.a
[1249/1702] AR lib/libLLVMARMCodeGen.a
[1250/1702] AR lib/libLLVMAVRCodeGen.a
[1251/1702] LINK ./bin/llvm-link
[1252/1702] AR lib/libLLVMBPFCodeGen.a
[1253/1702] AR lib/libLLVMLanaiCodeGen.a
[1254/1702] AR lib/libLLVMLanaiAsmParser.a
[1255/1702] LINK obj/clang/unittests/Parse/ParseTests
[1256/1702] AR lib/libLLVMHexagonCodeGen.a
[1257/1702] AR lib/libLLVMLanaiDisassembler.a
[1258/1702] CXX obj/llvm/unittests/CodeGen/GlobalISel/GlobalISelTests.LegalizerHelperTest.o
[1259/1702] LINK obj/llvm/unittests/Transforms/IPO/IPOTests
[1260/1702] AR lib/libLLVMLoongArchCodeGen.a
[1261/1702] AR lib/libLLVMMipsCodeGen.a
[1262/1702] AR lib/libLLVMNVPTXCodeGen.a
[1263/1702] AR lib/libLLVMPowerPCAsmParser.a
[1264/1702] AR lib/libLLVMPowerPCCodeGen.a
[1265/1702] CXX obj/llvm/unittests/CodeGen/CodeGenTests.RematerializerTest.o
[1266/1702] LINK obj/clang/unittests/Lex/LexTests
[1267/1702] AR lib/libLLVMRISCVCodeGen.a
[1268/1702] AR lib/libLLVMSparcCodeGen.a
[1269/1702] AR lib/libLLVMSystemZCodeGen.a
[1270/1702] AR lib/libLLVMWebAssemblyCodeGen.a
[1271/1702] CXX obj/llvm/unittests/Target/AArch64/AArch64Tests.MatrixRegisterAliasing.o
[1272/1702] CXX obj/llvm/unittests/Target/ARM/ARMTests.MachineInstrTest.o
[1273/1702] CXX obj/llvm/unittests/CodeGen/GlobalISel/GlobalISelTests.PatternMatchTest.o
[1274/1702] AR lib/libLLVMExegesisRISCV.a
[1275/1702] AR lib/libLLVMMIREmbUtils.a
[1276/1702] LINK ./bin/llvm-bat-dump
[1277/1702] AR lib/libLLVMExegesis.a
[1278/1702] LINK ./bin/llvm-cgdata
[1279/1702] LINK obj/clang/unittests/Support/ClangSupportTests
[1280/1702] LINK obj/llvm/unittests/Frontend/LLVMFrontendTests
[1281/1702] LINK obj/clang/unittests/Serialization/SerializationTests
[1282/1702] LINK obj/clang/unittests/Rewrite/RewriteTests
[1283/1702] LINK obj/clang/unittests/StaticAnalyzer/StaticAnalysisTests
[1284/1702] LINK obj/clang/unittests/Sema/SemaTests
[1285/1702] LINK obj/clang/unittests/ScalableStaticAnalysis/ClangScalableAnalysisTests
[1286/1702] CXX obj/llvm/unittests/Target/AArch64/AArch64Tests.Immediates.o
[1287/1702] LINK ./bin/clang-import-test
[1288/1702] LINK ./bin/lli-child-target
[1289/1702] CXX obj/llvm/unittests/Target/X86/X86Tests.X86SelectionDAGTest.o
[1290/1702] LINK obj/llvm/unittests/MC/SystemZ/SystemZAsmLexerTests
[1291/1702] LINK ./bin/sancov
[1292/1702] LINK ./bin/llvm-dwarfdump
[1293/1702] LINK obj/llvm/unittests/DWARFLinkerParallel/DWARFLinkerParallelTests
[1294/1702] CXX obj/llvm/unittests/CodeGen/CodeGenTests.SelectionDAGPatternMatchTest.o
[1295/1702] LINK ./bin/llvm-mca
[1296/1702] LINK ./bin/llvm-nm
[1297/1702] LINK obj/llvm/unittests/ExecutionEngine/ExecutionEngineTests
[1298/1702] LINK ./bin/llvm-cfi-verify
[1299/1702] LINK ./bin/lldb-server
[1300/1702] LINK ./bin/llvm-objdump
[1301/1702] LINK ./bin/llvm-profgen
[1302/1702] CXX obj/llvm/unittests/tools/llvm-exegesis/Mips/LLVMExegesisMipsTests.RegisterAliasingTest.o
[1303/1702] ACTION //llvm/tools/llvm-objdump:llvm-otool(//llvm/utils/gn/build/toolchain:unix)
[1304/1702] LINK obj/llvm/unittests/Target/PowerPC/PowerPCTests
[1305/1702] LINK ./bin/llvm-extract
[1306/1702] LINK ./bin/llvm-calc-occupancy
[1307/1702] LINK obj/llvm/unittests/IR/IRTests
[1308/1702] LINK obj/llvm/unittests/Analysis/AnalysisTests
[1309/1702] LINK ./bin/llvm-debuginfo-analyzer
[1310/1702] LINK obj/llvm/unittests/Transforms/Coroutines/CoroTests
[1311/1702] CXX obj/llvm/unittests/Target/RISCV/RISCVTests.RISCVSelectionDAGTest.o
[1312/1702] LINK obj/llvm/unittests/tools/llvm-exegesis/LLVMExegesisTests
[1313/1702] LINK ./bin/clang-extdef-mapping
[1314/1702] LINK obj/llvm/unittests/Transforms/Instrumentation/InstrumentationTests
[1315/1702] LINK obj/llvm/unittests/tools/llvm-cfi-verify/CFIVerifyTests
[1316/1702] LINK obj/llvm/unittests/Passes/Plugins/PluginsTests
[1317/1702] LINK obj/llvm/unittests/Transforms/Scalar/ScalarTests
[1318/1702] LINK obj/llvm/unittests/MC/AMDGPU/AMDGPUMCTests
[1319/1702] LINK obj/llvm/unittests/Transforms/Utils/UtilsTests
[1320/1702] LINK obj/clang/unittests/Frontend/FrontendTests
[1321/1702] LINK obj/clang/unittests/CodeGen/ClangCodeGenTests
[1322/1702] CXX obj/llvm/unittests/Target/AMDGPU/AMDGPUTests.PALMetadata.o
[1323/1702] CXX obj/llvm/unittests/Target/AArch64/AArch64Tests.AddressingModes.o
[1324/1702] LINK ./bin/clang-tidy
[1325/1702] CXX obj/llvm/unittests/Target/AMDGPU/AMDGPUTests.MFMACoExecRules.o
[1326/1702] CXX obj/llvm/unittests/Target/AMDGPU/AMDGPUTests.RCIUpdateReservedRegsTest.o
[1327/1702] CXX obj/llvm/unittests/Target/AMDGPU/AMDGPUTests.CSETest.o
[1328/1702] CXX obj/llvm/unittests/Target/LoongArch/LoongArchTests.InstSizes.o
[1329/1702] CXX obj/llvm/unittests/tools/llvm-exegesis/Mips/LLVMExegesisMipsTests.BenchmarkResultTest.o
[1330/1702] CXX obj/llvm/unittests/Target/AMDGPU/AMDGPUTests.AMDGPUUnitTests.o
[1331/1702] CXX obj/llvm/unittests/Target/ARM/ARMTests.ARMSelectionDAGTest.o
[1332/1702] CXX obj/llvm/unittests/Target/AMDGPU/AMDGPUTests.AMDGPUMCExprTest.o
[1333/1702] CXX obj/llvm/unittests/Target/AMDGPU/AMDGPUTests.LiveRegUnits.o
[1334/1702] LINK obj/llvm/unittests/Target/LoongArch/LoongArchTests
[1335/1702] CXX obj/llvm/unittests/CodeGen/GlobalISel/GlobalISelTests.KnownBitsTest.o
[1336/1702] CXX obj/llvm/unittests/Target/WebAssembly/WebAssemblyTests.WebAssemblyExceptionInfoTest.o
[1337/1702] CXX obj/llvm/unittests/Target/AArch64/AArch64Tests.AArch64CacheLineSizeTest.o
[1338/1702] LINK obj/llvm/unittests/Target/WebAssembly/WebAssemblyTests
[1339/1702] CXX obj/llvm/unittests/Target/AMDGPU/AMDGPUTests.UniformityAnalysisTest.o
[1340/1702] CXX obj/llvm/unittests/Target/AArch64/AArch64Tests.AArch64SVESchedPseudoTest.o
[1341/1702] CXX obj/llvm/unittests/tools/llvm-exegesis/X86/LLVMExegesisX86Tests.BenchmarkResultTest.o
[1342/1702] CXX obj/llvm/unittests/Target/AMDGPU/AMDGPUTests.ExecMayBeModifiedBeforeAnyUse.o
[1343/1702] CXX obj/llvm/unittests/Target/AArch64/AArch64Tests.AArch64RegisterInfoTest.o
[1344/1702] CXX obj/llvm/unittests/Target/AMDGPU/AMDGPUTests.DwarfRegMappings.o
[1345/1702] CXX obj/llvm/unittests/Target/AArch64/AArch64Tests.AArch64SelectionDAGTest.o
[1346/1702] CXX obj/llvm/unittests/Target/ARM/ARMTests.InstSizes.o
[1347/1702] LINK obj/llvm/unittests/Target/ARM/ARMTests
[1348/1702] CXX obj/llvm/unittests/Target/AArch64/AArch64Tests.InstSizes.o
[1349/1702] CXX obj/llvm/unittests/Target/AMDGPU/AMDGPUTests.InstSizes.o
[1350/1702] CXX obj/llvm/unittests/Target/AMDGPU/AMDGPUTests.GCNRegPressureTest.o
[1351/1702] CXX obj/llvm/unittests/Target/RISCV/RISCVTests.RISCVInstrInfoTest.o
[1352/1702] LINK obj/llvm/unittests/Target/RISCV/RISCVTests
[1353/1702] LINK obj/llvm/unittests/Target/AMDGPU/AMDGPUTests
[1354/1702] CXX obj/llvm/unittests/CodeGen/CodeGenTests.InstrRefLDVTest.o
[1355/1702] CXX obj/llvm/unittests/tools/llvm-exegesis/PowerPC/LLVMExegesisPowerPCTests.SnippetGeneratorTest.o
[1356/1702] CXX obj/llvm/unittests/tools/llvm-exegesis/Mips/LLVMExegesisMipsTests.SnippetGeneratorTest.o
[1357/1702] LINK obj/llvm/unittests/tools/llvm-exegesis/PowerPC/LLVMExegesisPowerPCTests
[1358/1702] LINK obj/llvm/unittests/tools/llvm-exegesis/Mips/LLVMExegesisMipsTests
[1359/1702] CXX obj/llvm/unittests/tools/llvm-exegesis/X86/LLVMExegesisX86Tests.SnippetRepetitorTest.o
[1360/1702] CXX obj/llvm/unittests/tools/llvm-exegesis/RISCV/LLVMExegesisRISCVTests.SnippetGeneratorTest.o
[1361/1702] LINK obj/llvm/unittests/tools/llvm-exegesis/RISCV/LLVMExegesisRISCVTests
[1362/1702] CXX obj/llvm/unittests/tools/llvm-exegesis/X86/LLVMExegesisX86Tests.SnippetFileTest.o
[1363/1702] CXX obj/llvm/unittests/tools/llvm-exegesis/X86/LLVMExegesisX86Tests.SnippetGeneratorTest.o
[1364/1702] CXX obj/llvm/lib/Target/AArch64/LLVMAArch64CodeGen.AArch64Subtarget.o
[1365/1702] AR lib/libLLVMAArch64CodeGen.a
[1366/1702] LINK obj/llvm/unittests/tools/llvm-exegesis/AArch64/LLVMExegesisAArch64Tests
[1367/1702] LINK obj/llvm/unittests/Target/AArch64/AArch64Tests
[1368/1702] CXX obj/llvm/lib/Target/X86/LLVMX86CodeGen.X86ISelLowering.o
[1369/1702] AR lib/libLLVMX86CodeGen.a
[1370/1702] AR lib/libLLVMOptDriver.a
[1371/1702] LINK obj/llvm/unittests/CGData/CodeGenDataTests
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[1373/1702] LINK obj/llvm/unittests/MC/X86/X86MCTests
[1374/1702] LINK ./bin/llvm-cxxdump
[1375/1702] LINK ./bin/llvm-libtool-darwin
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[1378/1702] LINK ./bin/llvm-mc
[1379/1702] LINK ./bin/llvm-ar
[1380/1702] LINK ./bin/llvm-xray
[1381/1702] LINK obj/llvm/unittests/MC/MCTests
[1382/1702] ACTION //llvm/tools/llvm-ar:llvm-ranlib(//llvm/utils/gn/build/toolchain:unix)
[1383/1702] LINK obj/llvm/unittests/DebugInfo/GSYM/DebugInfoGSYMTests
[1384/1702] ACTION //llvm/tools/llvm-ar:llvm-dlltool(//llvm/utils/gn/build/toolchain:unix)
[1385/1702] LINK ./bin/llvm-rtdyld
[1386/1702] ACTION //llvm/tools/llvm-ml:llvm-ml64(//llvm/utils/gn/build/toolchain:unix)
[1387/1702] ACTION //llvm/tools/llvm-ar:llvm-lib(//llvm/utils/gn/build/toolchain:unix)
[1388/1702] LINK obj/llvm/unittests/ExecutionEngine/JITLink/JITLinkTests
[1389/1702] LINK ./bin/lli
[1390/1702] LINK ./bin/llvm-bolt
[1391/1702] LINK ./bin/llvm-jitlink
[1392/1702] LINK ./bin/llvm-lipo
[1393/1702] LINK obj/bolt/unittests/Passes/PassTests
[1394/1702] LINK obj/llvm/unittests/ExecutionEngine/MCJIT/MCJITTests
[1395/1702] ACTION //bolt/tools/driver:llvm-boltdiff(//llvm/utils/gn/build/toolchain:unix)
[1396/1702] ACTION //bolt/tools/driver:perf2bolt(//llvm/utils/gn/build/toolchain:unix)
[1397/1702] LINK ./bin/llvm-bolt-heatmap
[1398/1702] LINK obj/bolt/unittests/Profile/ProfileTests
[1399/1702] LINK obj/llvm/unittests/ExecutionEngine/Orc/OrcJITTests
[1400/1702] LINK obj/bolt/unittests/Core/CoreTests
[1401/1702] LINK obj/clang/unittests/Tooling/Syntax/SyntaxTests
[1402/1702] LINK ./bin/llvm-exegesis
[1403/1702] LINK ./bin/llvm-reduce
[1404/1702] LINK obj/llvm/unittests/tools/llvm-exegesis/X86/LLVMExegesisX86Tests
[1405/1702] LINK obj/llvm/unittests/Target/X86/X86Tests
[1406/1702] LINK obj/llvm/unittests/Passes/PassBuilderBindings/PassesBindingsTests
[1407/1702] LINK ./bin/dsymutil
[1408/1702] LINK obj/llvm/unittests/tools/llvm-mca/LLVMMCATests
[1409/1702] LINK ./bin/llvm-opt-fuzzer
[1410/1702] LINK ./bin/clang-scan-deps
[1411/1702] LINK obj/clang/unittests/CrossTU/CrossTUTests
[1412/1702] LINK ./bin/llc
[1413/1702] LINK obj/llvm/unittests/CodeGen/CodeGenTests
[1414/1702] LINK ./bin/llvm-isel-fuzzer
[1415/1702] LINK obj/llvm/unittests/Target/TargetMachineCTests
[1416/1702] LINK obj/lld/unittests/AsLibELF/LLDAsLibELFTests
[1417/1702] LINK ./bin/llvm-ir2vec
[1418/1702] LINK obj/llvm/unittests/DebugInfo/DWARF/DebugInfoDWARFTests
[1419/1702] LINK ./bin/llvm-lto
[1420/1702] LINK ./bin/llvm-lto2
[1421/1702] LINK ./bin/llvm-dwarfutil
[1422/1702] LINK ./bin/clang-sycl-linker
[1423/1702] LINK obj/llvm/unittests/MIR/MIRTests
[1424/1702] LINK ./bin/clang-linker-wrapper
[1425/1702] LINK obj/llvm/unittests/MI/MITests
[1426/1702] LINK obj/llvm/unittests/CodeGen/GlobalISel/GlobalISelTests
[1427/1702] LINK ./bin/llvm-c-test
[1428/1702] LINK ./bin/clang-nvlink-wrapper
[1429/1702] LINK ./bin/llvm-gsymutil
[1430/1702] LINK ./bin/llvm-split
[1431/1702] LINK ./bin/opt
[1432/1702] SOLINK ./lib/libLTO.so
[1433/1702] LINK obj/clang/unittests/Tooling/ToolingTests
[1434/1702] LINK ./bin/lld
[1435/1702] ACTION //lld/tools/lld:ld.lld(//llvm/utils/gn/build/toolchain:unix)
[1436/1702] ACTION //lld/tools/lld:lld-link(//llvm/utils/gn/build/toolchain:unix)
[1437/1702] ACTION //lld/tools/lld:wasm-ld(//llvm/utils/gn/build/toolchain:unix)
[1438/1702] ACTION //lld/tools/lld:ld64.lld(//llvm/utils/gn/build/toolchain:unix)
[1439/1702] LINK obj/llvm/unittests/DebugInfo/LogicalView/DebugInfoLogicalViewTests
[1440/1702] LINK obj/lld/unittests/AsLibAll/LLDAsLibAllTests
[1441/1702] LINK obj/clang/unittests/Driver/ClangDriverTests
[1442/1702] LINK obj/clang/unittests/Interpreter/ClangReplInterpreterTests
[1443/1702] LINK ./bin/lldb-test
[1444/1702] LINK obj/clang/unittests/Interpreter/ExceptionTests/ClangReplInterpreterExceptionTests
[1445/1702] LINK ./bin/lldb
[1446/1702] LINK ./bin/clang-check
[1447/1702] LINK ./bin/clang-repl
[1448/1702] LINK ./bin/lldb-dap
[1449/1702] SOLINK ./lib/libclang.so
[1450/1702] LINK obj/clang/unittests/libclang/libclangTests
[1451/1702] LINK obj/clang/unittests/libclang/CrashTests/libclangCrashTests
[1452/1702] LINK ./bin/clang
[1453/1702] ACTION //clang/tools/driver:clang-cpp(//llvm/utils/gn/build/toolchain:unix)
[1454/1702] ACTION //clang/tools/driver:clang-cl(//llvm/utils/gn/build/toolchain:unix)
[1455/1702] ACTION //clang/tools/driver:clangxx(//llvm/utils/gn/build/toolchain:unix)
[1456/1702] ACTION //compiler-rt/test/asan:lit_site_cfg(//llvm/utils/gn/build/toolchain:stage2_unix)
[1457/1702] ACTION //compiler-rt/test/hwasan:lit_site_cfg(//llvm/utils/gn/build/toolchain:stage2_unix)
[1458/1702] ACTION //libcxx/src:cxx_symlink(//llvm/utils/gn/build/toolchain:stage2_unix)
[1459/1702] ACTION //compiler-rt/test:lit_common_configured(//llvm/utils/gn/build/toolchain:stage2_unix)
[1460/1702] ACTION //compiler-rt/test/lsan:asan_mode_cfg(//llvm/utils/gn/build/toolchain:stage2_unix)
[1461/1702] ACTION //compiler-rt/test/builtins:builtins_mode_cfg(//llvm/utils/gn/build/toolchain:stage2_unix)
[1462/1702] ACTION //llvm/include/llvm/Config:llvm-config(//llvm/utils/gn/build/toolchain:stage2_unix)
[1463/1658] ACTION //llvm/include/llvm/Config:TargetExegesis.def(//llvm/utils/gn/build/toolchain:stage2_unix)
[1464/1658] ACTION //llvm/include/llvm/Config:Disassemblers.def(//llvm/utils/gn/build/toolchain:stage2_unix)
[1465/1658] ACTION //llvm/include/llvm/Config:AsmPrinters.def(//llvm/utils/gn/build/toolchain:stage2_unix)
[1466/1658] ACTION //llvm/include/llvm/Config:abi-breaking(//llvm/utils/gn/build/toolchain:stage2_unix)
[1467/1514] ACTION //llvm/include/llvm/Config:AsmParsers.def(//llvm/utils/gn/build/toolchain:stage2_unix)
[1468/1514] ACTION //llvm/include/llvm/Config:TargetMCAs.def(//llvm/utils/gn/build/toolchain:stage2_unix)
[1469/1514] ACTION //llvm/include/llvm/Config:Targets.def(//llvm/utils/gn/build/toolchain:stage2_unix)
[1470/1514] ACTION //llvm/include/llvm/Support:write_extension_def(//llvm/utils/gn/build/toolchain:stage2_unix)
[1471/1514] ACTION //llvm/include/llvm/Config:Targets(//llvm/utils/gn/build/toolchain:stage2_unix)
[1472/1514] ACTION //llvm/include/llvm/Support:write_vcsrevision(//llvm/utils/gn/build/toolchain:stage2_unix)
[1473/1514] ACTION //libcxx/src:cxx_linker_script(//llvm/utils/gn/build/toolchain:stage2_unix)
[1474/1514] ACTION //llvm/include/llvm/Config:config(//llvm/utils/gn/build/toolchain:stage2_unix)
[1475/1482] ACTION //compiler-rt/lib/ubsan:ubsan_loop_detect_dynamic_list(//llvm/utils/gn/build/toolchain:stage2_unix)
[1476/1482] ACTION //compiler-rt/lib/ubsan:ubsan_static_cxx_dynamic_list(//llvm/utils/gn/build/toolchain:stage2_unix)
[1477/1482] ACTION //compiler-rt/lib/ubsan:ubsan_static_dynamic_list(//llvm/utils/gn/build/toolchain:stage2_unix)
[1478/1482] ACTION //compiler-rt/lib/ubsan:version_script(//llvm/utils/gn/build/toolchain:stage2_unix)
[1479/1482] ACTION //compiler-rt/lib/hwasan:version_script(//llvm/utils/gn/build/toolchain:stage2_unix)
[1480/1482] LINK ./bin/c-index-test
[1481/1482] SOLINK lib/clang/24/lib/linux/libclang_rt.ubsan_standalone-x86_64.so
[1482/1482] SOLINK lib/clang/24/lib/linux/libclang_rt.hwasan_aliases-x86_64.so
INFO:2026-10-22T07:04:44Z:root:analyze
skipping analyze because previous build was not green
INFO:2026-10-22T07:04:44Z:root:testing
INFO:2026-10-22T07:04:44Z:root:test check-clang
ninja: Entering directory `out/gn'
[0/1] ACTION //clang/test:check-clang(//llvm/utils/gn/build/toolchain:unix)
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using clang: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using lld-link: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/lld-link
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld64.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld64.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using wasm-ld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/wasm-ld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using lld-link: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/lld-link
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld64.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld64.lld
llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using wasm-ld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/wasm-ld
-- Testing: 27911 tests, 64 workers --
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c (1 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570cca5e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005570cca5b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005570cca5e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa476705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa47675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa476705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4766ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570cc9f3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005570cc9f3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005570cc9d8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005570cc6880b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005570cc687dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa4766eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4766ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4766ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570cc687cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c (2 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale
# | ...
# `---data was truncated (10240/14485) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e192ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555e192a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555e192ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f347dd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f347dd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f347dd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f347dced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e19240e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555e19240c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555e19225b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555e18ed50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555e18ed4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f347dceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f347dcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f347dcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e18ed4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c (3 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555ecf7d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005555ecf7a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005555ecf7d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50c3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50c3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50c3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50c3c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555ecf12e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005555ecf12c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005555ecef7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005555ecba70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005555ecba6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f50c3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50c3c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50c3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555ecba6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c (4 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwin
# | ...
# `---data was truncated (10240/10798) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055695cb1215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055695cb0f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055695cb1289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7243c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7243c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7243c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7243c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055695caa7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055695caa7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055695ca8cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055695c73c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055695c73bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7243c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7243c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7243c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055695c73bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c (5 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevw_u64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f6e58b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f6e58b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f6e58b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96a8905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96a895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96a8905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96a88ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6e584ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f6e584cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f6e5831b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f6e54e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f6e54e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f96a88eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96a88ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96a88ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6e54e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c (6 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(targe
# | ...
# `---data was truncated (10240/53734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056192398215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056192397f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056192398289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb945133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb94518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb945133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb94511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561923917e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561923917c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005619238fcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005619235ac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005619235abdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb94511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb94511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb94511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619235abcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c (7 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn1q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn1q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn1q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn1q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn1q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn1q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn1q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn1q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn1q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn1q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtrn1_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.trn1q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.trn1q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d22613915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d2261360f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d22613989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f535c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f535c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f535c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f535c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2260cee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d2260cec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d2260b3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d225d630b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d225d62dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f535c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f535c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f535c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d225d62cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c (8 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8bdd4d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c8bdd4a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c8bdd4d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2126333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f212638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2126333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f212631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8bdce2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c8bdce2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c8bdcc7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c8bd9770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c8bd976dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f212631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f212631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f212631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8bd976cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c (9 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb8e72e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bb8e72b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bb8e72e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a10f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a10f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a10f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a10f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb8e6c3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bb8e6c3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bb8e6a8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bb8e3580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bb8e357dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9a10f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a10f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a10f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb8e357cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c (10 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556212d1215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556212d0f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556212d1289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78bcd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78bcd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78bcd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78bcced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556212ca7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556212ca7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556212c8cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055621293c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055621293bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f78bcceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78bccef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78bccef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055621293bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c (11 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c40dd9c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c40dd990f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c40dd9c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5340e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5340ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5340e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5340e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c40dd31e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c40dd31c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c40dd16b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c40d9c60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c40d9c5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5340e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5340e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5340e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c40d9c5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c (12 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b96f0a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555b96f070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555b96f0a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40c3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40c318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40c3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40c311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b96e9fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555b96e9fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555b96e84b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555b96b340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555b96b33dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f40c311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40c311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40c311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b96b33cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c (13 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.smop4a.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x2_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.umop4a.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x2_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.umop4s.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.sumop4a.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4a.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x2_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.sumop4s.wide.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4s.wide.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_u8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <
# | ...
# `---data was truncated (10240/50724) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005558aabb715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005558aabb40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005558aabb789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc63f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc63f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc63f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc63f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558aab4ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005558aab4cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005558aab31b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005558aa7e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005558aa7e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbc63f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc63f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc63f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558aa7e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c (14 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649d76a415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005649d76a10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005649d76a489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1dc6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1dc62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1dc6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1dc6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649d7639e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005649d7639c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005649d761eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005649d72ce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005649d72cddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1dc6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1dc62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1dc62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649d72cdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c (15 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscal
# | ...
# `---data was truncated (10240/26704) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056117a87315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056117a8700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056117a87389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a9801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a980725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a9801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a98003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056117a808e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056117a808c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056117a7edb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056117a49d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056117a49cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1a98004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a980050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a980050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056117a49ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c (16 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5446de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f5446db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f5446de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c89d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c89d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c89d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c89d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f544673e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f544673c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f544658b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f5443080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f544307dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3c89d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c89d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c89d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f544307cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c (17 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c54845015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c54844d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c54845089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ed8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ed818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ed8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ed811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5483e5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c5483e5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c5483cab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c54807a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c548079dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3ed811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ed811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ed811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c548079cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c (18 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_u8mf8x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_u8mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vect
# | ...
# `---data was truncated (10240/32932) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055708a13915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055708a1360f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055708a13989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd78a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd78a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd78a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd78a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055708a0cee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055708a0cec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055708a0b3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557089d630b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557089d62dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd78a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd78a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd78a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557089d62cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c (19 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_s32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_u32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_f32_x2(<vscale x 4 x float> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_s32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_u32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_n_f32_x2(<vscale x 4 x float> %op1, <vscale x 8 x half> %op2, half noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca half, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store half %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load half, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x half> poison, half %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x half> %.splatinsert, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_s32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_u32_x2(<vscale x 4 x i32> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_lane_f32_x2(<vscale x 4 x float> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync no
# | ...
# `---data was truncated (10240/10512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000555aa061f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555aa061c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555aa061f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f354a705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f354a75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f354a705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f354a6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555aa05b4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555aa05b4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555aa0599b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555aa02490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555aa0248dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f354a6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f354a6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f354a6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555aa0248cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c (20 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b29ae8615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b29ae830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b29ae8689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8a5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8a5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8a5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8a5e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b29ae1be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b29ae1bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b29ae00b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b29aab00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b29aaafdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe8a5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8a5e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8a5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b29aaafcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c (21 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ...
# `---data was truncated (10240/64958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563c384f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005563c384c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005563c384f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f652ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f652ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f652ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f652ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563c37e4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005563c37e4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005563c37c9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005563c34790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005563c3478dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f652ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f652ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f652ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563c3478cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c (22 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb7207715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cb720740f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cb7207789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9432a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9432aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9432a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9432a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb7200ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cb7200cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cb71ff1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cb71ca10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cb71ca0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9432a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9432a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9432a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb71ca0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c (23 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005574eb70c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005574eb7090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005574eb70c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33db705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33db75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33db705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33db6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574eb6a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005574eb6a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005574eb686b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005574eb3360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005574eb335dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f33db6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33db6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33db6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574eb335cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c (24 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e22d32315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e22d3200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e22d32389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4eb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4eb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4eb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4eb51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e22d2b8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e22d2b8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e22d29db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e22cf4d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e22cf4cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd4eb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4eb51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4eb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e22cf4ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vaddq.c (25 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = add <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fadd <8 x half> %0, %1
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vaddq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = add <4 x i32> %0, %.splat
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_n_f16(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fadd <8 x half> %0, %.splat
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vaddq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, float noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca float, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load float, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %1, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %.splat, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_x_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @t
# | ...
# `---data was truncated (10240/11617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000560508b5d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560508b5a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560508b5d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fd8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fd878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fd8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fd871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560508af2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560508af2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560508ad7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005605087870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560508786dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9fd871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fd871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fd871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560508786cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c (26 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm
# | ...
# `---data was truncated (10240/53200) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056222281c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005622228190f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056222281c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f2a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f2a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f2a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f2a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622227b1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005622227b1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562222796b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005622224460b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562222445dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4f2a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f2a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f2a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562222445cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c (27 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function A
# | ...
# `---data was truncated (10240/30415) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576f4f3b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005576f4f380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005576f4f3b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8660e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8660ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8660e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8660e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576f4ed0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005576f4ed0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005576f4eb5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005576f4b650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005576f4b64dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8660e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8660e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8660e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576f4b64cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c (28 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0dd42215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c0dd41f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c0dd42289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4c8105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4c815c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4c8105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4c80ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0dd3b7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c0dd3b7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c0dd39cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c0dd04c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c0dd04bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd4c80eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4c80ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4c80ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0dd04bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c (29 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639c58f715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005639c58f40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005639c58f789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01d741bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01d74725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01d741ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01d7403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639c588ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005639c588cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005639c5871b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005639c55210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005639c5520dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f01d7404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01d74050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01d74050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639c5520cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c (30 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %
# | ...
# `---data was truncated (10240/29210) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f55ce2215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f55ce1f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f55ce2289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f09bb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09bb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f09bb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f09bb031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f55cdb7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f55cdb7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f55cd9cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f55ca4c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f55ca4bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f09bb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09bb0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09bb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f55ca4bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c (31 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %
# | ...
# `---data was truncated (10240/280171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e68dd615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559e68dd30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559e68dd689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6be0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6be038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6be0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6be031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e68d6be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559e68d6bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559e68d50b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559e68a000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559e689ffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6be031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6be031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6be031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e689ffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c (32 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556046ec415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556046ec10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556046ec489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9ce933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9ce98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9ce933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9ce91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556046e59e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556046e59c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556046e3eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556046aee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556046aeddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff9ce91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9ce91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9ce91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556046aedcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve/eorv.c (33 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/eorv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_sveorv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_sveorv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_sveorv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_sveorv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_sveorv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_sveorv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_sveorv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_sveorv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055bbf685815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bbf68550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bbf685889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fb3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fb398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fb3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fb391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbf67ede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bbf67edc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bbf67d2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bbf64820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bbf6481dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9fb391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fb391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fb391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbf6481cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c (34 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c29e65515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c29e6520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c29e65589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ab3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ab358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ab3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ab351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c29e5eae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c29e5eac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c29e5cfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c29e27f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c29e27edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2ab351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ab351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ab351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c29e27ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c (35 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563fdb3f615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563fdb3f30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563fdb3f689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d61f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d61f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d61f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d61f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563fdb38be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563fdb38bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563fdb370b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563fdb0200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563fdb01fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5d61f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d61f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d61f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563fdb01fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c (36 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056128e79715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056128e7940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056128e79789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b1bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b1bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b1bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b1bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056128e72ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056128e72cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056128e711b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056128e3c10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056128e3c0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1b1bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b1bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b1bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056128e3c0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c (37 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | 
# | ...
# `---data was truncated (10240/12216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9d118415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f9d11810f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f9d118489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5544533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f554458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5544533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f554451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9d1119e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f9d1119c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f9d10feb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f9d0dae0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f9d0daddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f554451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f554451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f554451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9d0dadcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c (38 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/113047) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ef930515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562ef93020f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562ef930589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad1a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad1a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad1a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad1a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ef929ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562ef929ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562ef927fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562ef8f2f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562ef8f2edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fad1a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad1a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad1a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ef8f2ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c (39 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1977a515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d1977a20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d1977a589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d45f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d45f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d45f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d45eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d19773ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d19773ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d19771fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d1973cf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d1973cedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0d45eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d45eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d45eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1973cecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c (40 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x f
# | ...
# `---data was truncated (10240/70110) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056318377015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056318376d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056318377089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47fde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47fdea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47fde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47fde31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563183705e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563183705c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005631836eab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056318339a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563183399dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f47fde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47fde330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47fde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563183399cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c (41 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16
# | ...
# `---data was truncated (10240/129182) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056539272415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005653927210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056539272489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82bfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82bfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82bfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82bfd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653926b9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005653926b9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056539269eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056539234e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056539234ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f82bfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82bfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82bfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056539234dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c (42 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/39922) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558e337e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005558e337b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005558e337e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71bf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71bf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71bf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71bf91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558e3313e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005558e3313c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005558e32f8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005558e2fa80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005558e2fa7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f71bf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71bf91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71bf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558e2fa7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c (43 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/296943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e42552115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e42551e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e42552189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc58a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc58aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc58a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc58a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4254b6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e4254b6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e42549bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e42514b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e42514add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdc58a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc58a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc58a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e42514acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c (44 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed603bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ed603ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ed603bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6fe849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6fe8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6fe849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6fe831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed60352e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ed60352c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ed60337b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ed5ffe70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ed5ffe6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc6fe832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6fe8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6fe8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed5ffe6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c (45 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055656f39815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055656f3950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055656f39889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb436533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb43658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb436533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb43651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055656f32de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055656f32dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055656f312b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055656efc20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055656efc1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb43651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb43651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb43651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055656efc1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c (46 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/98141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc24c0e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bc24c0b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bc24c0e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6930a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6930aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6930a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6930a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc24ba3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bc24ba3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bc24b88b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bc248380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bc24837dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6930a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6930a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6930a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc24837cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c (47 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_u8mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_u8m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstrid
# | ...
# `---data was truncated (10240/28111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b311a615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564b311a30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564b311a689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d76e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d76ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d76e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d76e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b3113be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564b3113bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564b31120b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564b30dd00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564b30dcfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4d76e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d76e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d76e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b30dcfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c (48 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_m(<vscale x 2 x i1
# | ...
# `---data was truncated (10240/14031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055772eecd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055772eeca0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055772eecd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12e1f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12e1f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12e1f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12e1eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055772ee62e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055772ee62c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055772ee47b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055772eaf70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055772eaf6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f12e1eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12e1eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12e1eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055772eaf6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c (49 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: noca
# | ...
# `---data was truncated (10240/100960) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1c2e6015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e1c2e5d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e1c2e6089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe776649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7766a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe776649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe776631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1c2df5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e1c2df5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e1c2ddab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e1c2a8a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e1c2a89dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe776632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7766330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7766330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1c2a89cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c (50 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @and_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %and = and <32 x i8> %0, %1
# |   store <32 x i8> %and, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @and_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %and = and <16 x i16> %0, %1
# |   store <16 x i16> %and, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @and_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %and = and <8 x i32> %0, %1
# |   store <8 x i32> %and, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @and_i64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %and = and <4 x i64> %0, %1
# |   store <4 x i64> %and, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64>, <4 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @and_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %and = and <32 x i8> %0, %1
# |   store <32 x i8> %and, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @and_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %and = and <16 x i16> %0, %1
# |   store <16 x i16> %and, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @and_u32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %and = and <8 x i32> %0, %1
# |   store <8 x i32> %and, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @and_u64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %and = and <4 x i64> %0, %1
# |   store <4 x i64> %and, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @or_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %or = or <32 x i8> %0, %1
# |   store <32 x i8> %or, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 
# | ...
# `---data was truncated (10240/30877) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055b06895015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b06894d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b06895089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d43933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d4398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d43933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d4391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0688e5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b0688e5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b0688cab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b06857a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b068579dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1d4391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d4391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d4391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b068579cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c (51 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056390038615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005639003830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056390038689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee6b705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee6b75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee6b705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee6b6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056390031be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056390031bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563900300b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005638fffb00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005638fffafdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fee6b6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee6b6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee6b6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638fffafcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c (52 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575daf6615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005575daf630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005575daf6689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c5ae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c5ae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c5ae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c5ae03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575daefbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005575daefbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005575daee0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005575dab900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005575dab8fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8c5ae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c5ae050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c5ae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575dab8fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c (53 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vremu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055940400c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005594040090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055940400c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5458533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f545858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5458533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f545851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559403fa1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559403fa1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559403f86b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559403c360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559403c35dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f545851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f545851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f545851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559403c35cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c (54 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexpa_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 
# | ...
# `---data was truncated (10240/21465) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4c5f6d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a4c5f6a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a4c5f6d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83ede49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83edea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83ede49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83ede31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4c5f02e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a4c5f02c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a4c5ee7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a4c5b970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a4c5b96dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f83ede32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83ede330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83ede330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4c5b96cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c (55 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/65582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d682f8a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d682f870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d682f8a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c64b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c64b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c64b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c64b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d682f1fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d682f1fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d682f04b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d682bb40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d682bb3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6c64b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c64b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c64b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d682bb3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c (56 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056429fdd215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056429fdcf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056429fdd289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fae305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fae35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fae305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fae2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056429fd67e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056429fd67c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056429fd4cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056429f9fc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056429f9fbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2fae2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fae2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fae2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056429f9fbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: Modules/pr93497.cppm (57 of 27911)
******************** TEST 'Clang :: Modules/pr93497.cppm' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
rm -rf /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# executed command: rm -rf /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# RUN: at line 2
mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# RUN: at line 3
split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/Modules/pr93497.cppm /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# executed command: split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/Modules/pr93497.cppm /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.cppm      -emit-module-interface -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.cppm -emit-module-interface -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm
# RUN: at line 7
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp      -fmodule-file=mod=/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm -emit-llvm      -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp -fmodule-file=mod=/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.Thing = type { i32 }
# | %struct.C = type { i32 }
# | %struct.NonConstexprDtor = type { i32 }
# | 
# | $needed = comdat any
# | 
# | @_ZNW3mod5Thing3OneE = external global %struct.Thing, align 4
# | @_ZW3mod13ConstantValue = available_externally constant %struct.C { i32 1 }, align 4
# | @_ZW3mod11ConstantPtr = external global ptr, align 8
# | @_ZW3mod16NonConstantValue = external global %struct.C, align 4
# | @_ZW3mod21NonConstexprDtorValue = external global %struct.NonConstexprDtor, align 4
# | @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @_GLOBAL__sub_I_use.cpp, ptr null }]
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z3usev() #0 {
# | entry:
# |   %t1 = alloca %struct.Thing, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %t1, ptr align 4 @_ZNW3mod5Thing3OneE, i64 4, i1 false)
# |   %raw = getelementptr inbounds nuw %struct.Thing, ptr %t1, i32 0, i32 0
# |   %0 = load i32, ptr %raw, align 4
# |   %call = call noundef i32 @_Z7consumei(i32 noundef %0)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #1
# | 
# | declare noundef i32 @_Z7consumei(i32 noundef) #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use2v() #0 {
# | entry:
# |   %agg.tmp = alloca %struct.C, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 @_ZW3mod13ConstantValue, i64 4, i1 false)
# |   %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0
# |   %0 = load i32, ptr %coerce.dive, align 4
# |   %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %0)
# |   ret i32 %call
# | }
# | 
# | declare noundef i32 @_Z8consumeCW3mod1C(i32) #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use3v() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %Ptr = alloca ptr, align 8
# |   %agg.tmp = alloca %struct.C, align 4
# |   %0 = load ptr, ptr @_ZW3mod11ConstantPtr, align 8
# |   store ptr %0, ptr %Ptr, align 8
# |   %1 = load ptr, ptr %Ptr, align 8
# |   %value = getelementptr inbounds nuw %struct.C, ptr %1, i32 0, i32 0
# |   %2 = load i32, ptr %value, align 4
# |   %tobool = icmp ne i32 %2, 0
# |   br i1 %tobool, label %if.then, label %if.end
# | 
# | if.then:                                          ; preds = %entry
# |   %3 = load ptr, ptr %Ptr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 %3, i64 4, i1 false)
# |   %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0
# |   %4 = load i32, ptr %coerce.dive, align 4
# |   %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %4)
# |   store i32 %call, ptr %retval, align 4
# |   br label %return
# | 
# | if.end:                                           ; preds = %entry
# |   %call1 = call i32 @needed()
# |   store i32 %call1, ptr %retval, align 4
# |   br label %return
# | 
# | return:                                           ; preds = %if.end, %if.then
# |   %5 = load i32, ptr %retval, align 4
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define linkonce_odr i32 @needed() #0 comdat {
# | entry:
# |   %call = call noundef i32 @_Z7consumei(i32 noundef 43)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use4v() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %Ref = alloca %struct.C, align 4
# |   %agg.tmp = alloca %struct.C, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %Ref, ptr align 4 @_ZW3mod16NonConstantValue, i64 4, i1 false)
# |   %value = getelementptr inbounds nuw %struct.C, ptr %Ref, i32 0, i32 0
# |   %0 = load i32, ptr %value, align 4
# |   %tobool = icmp ne i32 %0, 0
# |   br i1 %tobool, label %if.then, label %if.end
# | 
# | if.then:                                          ; preds = %entry
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 %Ref, i64 4, i1 false)
# |   %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0
# |   %1 = load i32, ptr %coerce.dive, align 4
# |   %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %1)
# |   store i32 %call, ptr %retval, align 4
# |   br label %return
# | 
# | if.end:                                           ; preds = %entry
# |   %call1 = call i32 @needed()
# |   store i32 %call1, ptr %retval, align 4
# |   br label %return
# | 
# | return:                                           ; preds = %if.end, %if.then
# |   %2 = load i32, ptr %retval, align 4
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z4use5v() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %V = alloca %struct.NonConstexprDtor, align 4
# |   %cleanup.dest.slot = alloca i32, align 4
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %V, ptr align 4 @_ZW3mod21NonConstexprDtorValue, i64 4, i1 false)
# |   %raw = getelementptr inbounds nuw %struct.NonConstexprDtor, ptr %V, i32 0, i32 0
# |   %0 = load i32, ptr %raw, align 4
# |   %tobool = icmp ne i32 %0, 0
# |   br i1 %tobool, label %if.then, label %if.end
# | 
# | if.then:                                          ; preds = %entry
# |   %raw1 = getelementptr inbounds nuw %struct.NonConstexprDtor, ptr %V, i32 0, i32 0
# |   %1 = load i32, ptr %raw1, align 4
# |   %call = call noundef i32 @_Z7consumei(i32 noundef %1)
# |   store i32 %call, ptr %retval, align 4
# |   store i32 1, ptr %cleanup.dest.slot, align 4
# |   br label %cleanup
# | 
# | if.end:                                           ; preds = %entry
# |   %call2 = call i32 @needed()
# |   store i32 %call2, ptr %retval, align 4
# |   store i32 1, ptr %cleanup.dest.slot, align 4
# |   br label %cleanup
# | 
# | cleanup:                                          ; preds = %if.end, %if.then
# |   call void @_ZNW3mod16NonConstexprDtorD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) %V) #5
# |   %2 = load i32, ptr %retval, align 4
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @_ZNW3mod16NonConstexprDtorD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4)) unnamed_addr #3
# | 
# | declare void @_ZGIW3mod()
# | 
# | ; Function Attrs: noinline nounwind
# | define internal void @_GLOBAL__sub_I_use.cpp() #4 section ".text.startup" {
# | entry:
# |   call void @_ZGIW3mod()
# |   ret void
# | }
# | 
# | attributes #0 = { mustprogress noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #4 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #5 = { nounwind }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg
# |  #0 0x0000557362bce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557362bcb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557362bce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafa5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafa5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafa5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafa5c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557362b63e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557362b63c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557362b48b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005573627f80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005573627f7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fafa5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafa5c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafa5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573627f7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c (58 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2_tu(target("riscv
# | ...
# `---data was truncated (10240/295533) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cdf7ce615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cdf7ce30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cdf7ce689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f9c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f9c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f9c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f9c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cdf7c7be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cdf7c7bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cdf7c60b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cdf79100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cdf790fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8f9c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f9c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f9c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cdf790fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c (59 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.mask.nxv2i8.i64.p0(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.mask.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.mask.nxv4i8.i64.p0(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.mask.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64.p0(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.mask.nxv16i8.i64.p0(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.mask.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.mask.nxv32i8.i64.p0(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 32 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.mask.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.mask.nxv64i8.i64.p0(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 64 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 64 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.mask.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   
# | ...
# `---data was truncated (10240/17236) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055909f78615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055909f7830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055909f78689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f97ad01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97ad0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f97ad01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97ad003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055909f71be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055909f71bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055909f700b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055909f3b00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055909f3afdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f97ad004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97ad0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97ad0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055909f3afcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c (60 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i
# | ...
# `---data was truncated (10240/14788) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559bb5da15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005559bb5d70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005559bb5da89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29bbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29bbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29bbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29bbb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559bb56fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005559bb56fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005559bb554b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005559bb2040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005559bb203dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f29bbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29bbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29bbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559bb203cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c (61 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/23405) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562838e6f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562838e6c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562838e6f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9290533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f929058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9290533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f929051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562838e04e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562838e04c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562838de9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562838a990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562838a98dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f929051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f929051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f929051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562838a98cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c (62 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_u32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_u32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1
# | ...
# `---data was truncated (10240/24058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618f621d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005618f621a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005618f621d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98b2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98b22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98b2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98b2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618f61b2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005618f61b2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005618f6197b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005618f5e470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005618f5e46dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f98b2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98b22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98b22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618f5e46cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c (63 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 
# | ...
# `---data was truncated (10240/28361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a63e3ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a63e3a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a63e3ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd930533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd93058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd930533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd93051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a63e340e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a63e340c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a63e325b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a63dfd50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a63dfd4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd93051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd93051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd93051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a63dfd4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c (64 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf4fb5915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bf4fb560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bf4fb5989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc8bcb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8bcb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc8bcb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc8bcb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf4faeee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bf4faeec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bf4fad3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bf4f7830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bf4f782dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc8bcb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8bcb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8bcb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf4f782cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c (65 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsl_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsl_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsl_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsl_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsl_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsl_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsl_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsl_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsl_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/53158) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d33a5f115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d33a5ee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d33a5f189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34cc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34cc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34cc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34cc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d33a586e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d33a586c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d33a56bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d33a21b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d33a21add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f34cc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34cc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34cc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d33a21acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c (66 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vaa
# | ...
# `---data was truncated (10240/99585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4d922015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b4d921d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b4d922089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57beb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57beb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57beb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57beb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4d91b5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b4d91b5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b4d919ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b4d8e4a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b4d8e49dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f57beb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57beb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57beb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4d8e49cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-neon-directed-rounding.c (67 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-directed-rounding.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57      -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c -o - |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnda_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnda_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnda_v1.i = call <2 x float> @llvm.round.v2f32(<2 x float> %vrnda_v.i)
# |   %vrnda_v2.i = bitcast <2 x float> %vrnda_v1.i to <8 x i8>
# |   store <8 x i8> %vrnda_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndaq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndaq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndaq_v1.i = call <4 x float> @llvm.round.v4f32(<4 x float> %vrndaq_v.i)
# |   %vrndaq_v2.i = bitcast <4 x float> %vrndaq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndaq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndm_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndm_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndm_v1.i = call <2 x float> @llvm.floor.v2f32(<2 x float> %vrndm_v.i)
# |   %vrndm_v2.i = bitcast <2 x float> %vrndm_v1.i to <8 x i8>
# |   store <8 x i8> %vrndm_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndmq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndmq_v1.i = call <4 x float> @llvm.floor.v4f32(<4 x float> %vrndmq_v.i)
# |   %vrndmq_v2.i = bitcast <4 x float> %vrndmq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndmq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndn_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndn_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndn_v1.i = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %vrndn_v.i)
# |   %vrndn_v2.i = bitcast <2 x float> %vrndn_v1.i to <8 x i8>
# |   store <8 x i8> %vrndn_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndnq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndnq_v1.i = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %vrndnq_v.i)
# |   %vrndnq_v2.i = bitcast <4 x float> %vrndnq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndnq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndp_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndp_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndp_v1.i = call <2 x float> @llvm.ceil.v2f32(<2 x float> %vrndp_v.i)
# |   %vrndp_v2.i = bitcast <2 x float> %vrndp_v1.i to <8 x i8>
# |   store <8 x i8> %vrndp_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndpq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndpq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndpq_v1.i = call <4 x float> @llvm.ceil.v4f32(<4 x float> %vrndpq_v.i)
# |   %vrndpq_v2.i = bitcast <4 x float> %vrndpq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndpq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndx_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndx_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndx_v1.i = call <2 x float> @llvm.rint.v2f32(<2 x float> %vrndx_v.i)
# |   %vrndx_v2.i = bitcast <2 x float> %vrndx_v1.i to <8 x i8>
# |   store <8 x i8> %vrndx_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndxq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndxq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndxq_v1.i = call <4 x float> @llvm.rint.v4f32(<4 x float> %vrndxq_v.i)
# |   %vrndxq_v2.i = bitcast <4 x float> %vrndxq_v1.i to <16 x i8>
# |   store <16 x i8> %vrndxq_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd_v1.i = call <2 x float> @llvm.trunc.v2f32(<2 x float> %vrnd_v.i)
# |   %vrnd_v2.i = bitcast <2 x float> %vrnd_v1.i to <8 x i8>
# |   store <8 x i8> %vrnd_v2.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x
# | ...
# `---data was truncated (10240/16447) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000557a4dab515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557a4dab20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557a4dab589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd58f705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd58f75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd58f705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd58f6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a4da4ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557a4da4ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557a4da2fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557a4d6df0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557a4d6dedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd58f6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd58f6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd58f6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a4d6decc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c (68 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561746ab815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561746ab50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561746ab889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb377849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3778a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb377849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb377831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561746a4de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561746a4dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561746a32b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005617466e20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005617466e1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb377832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3778330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3778330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617466e1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c (69 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fcd464115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fcd463e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fcd464189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f68af505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68af55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f68af505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68af4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fcd45d6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fcd45d6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fcd45bbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fcd426b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fcd426add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f68af4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68af4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68af4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fcd426acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c (70 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vas
# | ...
# `---data was truncated (10240/99585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c7f2ed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555c7f2ea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555c7f2ed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff212b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff212b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff212b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff212b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c7f282e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555c7f282c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555c7f267b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555c7ef170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555c7ef16dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff212b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff212b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff212b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c7ef16cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c (71 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | 
# | ...
# `---data was truncated (10240/12216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056230251715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005623025140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056230251789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7be9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7be9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7be9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7be9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623024ace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005623024acc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562302491b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005623021410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562302140dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7be9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7be9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7be9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562302140cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c (72 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e63122215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e63121f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e63122289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe56b81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe56b8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe56b81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe56b803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6311b7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e6311b7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e63119cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e630e4c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e630e4bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe56b804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe56b8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe56b8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e630e4bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c (73 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   stor
# | ...
# `---data was truncated (10240/29518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de7f7bf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055de7f7bc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055de7f7bf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f65afd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65afd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f65afd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f65afd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de7f754e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055de7f754c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055de7f739b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055de7f3e90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055de7f3e8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f65afd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65afd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65afd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de7f3e8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c (74 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4_tu(<vscale x 16 x h
# | ...
# `---data was truncated (10240/619135) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563533b9115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563533b8e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563533b9189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe80de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe80dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe80de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe80de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563533b26e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563533b26c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563533b0bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005635337bb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005635337badd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe80de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe80de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe80de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635337bacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c (75 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056029e4e215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056029e4df0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056029e4e289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe8cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe8cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe8cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe8cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056029e477e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056029e477c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056029e45cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056029e10c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056029e10bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efe8cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe8cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe8cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056029e10bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/aapcs-bitfield.c (76 of 27911)
******************** TEST 'Clang :: CodeGen/aapcs-bitfield.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-eabi -fno-aapcs-bitfield-width -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-eabi -fno-aapcs-bitfield-width -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-none-linux-eabi"
# | 
# | %struct.st6 = type { i16, i8, i8 }
# | %struct.st7b = type { i8, [3 x i8], %struct.st7a }
# | %struct.st7a = type { i8, i8, [2 x i8] }
# | %struct.st11 = type <{ i8, i16, i8 }>
# | %struct.st13 = type <{ i8, i32 }>
# | %struct.st16 = type { i32, i16, i32, i16 }
# | %struct.st17 = type <{ i32, i8 }>
# | %struct.zero_bitfield = type { i8, i8, [2 x i8] }
# | %struct.zero_bitfield_ok = type { i16, i32 }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st0_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i8, ptr %0, align 2
# |   %bf.shl = shl i8 %bf.load, 1
# |   %bf.ashr = ashr i8 %bf.shl, 1
# |   %bf.cast = sext i8 %bf.ashr to i16
# |   %conv = sext i16 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st0_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i8, ptr %0, align 2
# |   %bf.clear = and i8 %bf.load, -128
# |   %bf.set = or i8 %bf.clear, 1
# |   store i8 %bf.set, ptr %0, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st1_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.ashr = ashr i16 %bf.load, 10
# |   %conv = sext i16 %bf.ashr to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st1_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, 1023
# |   %bf.set = or i16 %bf.clear, 1024
# |   store i16 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st2_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i32, ptr %0, align 4
# |   %bf.shl = shl i32 %bf.load, 9
# |   %bf.ashr = ashr i32 %bf.shl, 25
# |   %bf.cast = trunc i32 %bf.ashr to i16
# |   %conv = sext i16 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st2_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i32, ptr %0, align 4
# |   %bf.clear = and i32 %bf.load, -8323073
# |   %bf.set = or i32 %bf.clear, 65536
# |   store i32 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st3_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i8, ptr %0, align 2
# |   %bf.shl = shl i8 %bf.load, 1
# |   %bf.ashr = ashr i8 %bf.shl, 1
# |   %bf.cast = sext i8 %bf.ashr to i16
# |   %conv = sext i16 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st3_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i8, ptr %0, align 2
# |   %bf.clear = and i8 %bf.load, -128
# |   %bf.set = or i8 %bf.clear, 1
# |   store volatile i8 %bf.set, ptr %0, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st4_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i16, ptr %0, align 4
# |   %bf.shl = shl i16 %bf.load, 2
# |   %bf.ashr = ashr i16 %bf.shl, 11
# |   %bf.cast = trunc i16 %bf.ashr to i8
# |   %conv = sext i8 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st4_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, -15873
# |   %bf.set = or i16 %bf.clear, 512
# |   store volatile i16 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st4_check_nonv_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, -512
# |   %bf.set = or i16 %bf.clear, 1
# |   store i16 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st5_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i32, ptr %0, align 4
# |   %bf.shl = shl i32 %bf.load, 11
# |   %bf.ashr = ashr i32 %bf.shl, 27
# |   %bf.cast = trunc i32 %bf.ashr to i8
# |   %conv = sext i8 %bf.cast to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st5_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i32, ptr %0, align 4
# |   %bf.clear = and i32 %bf.load, -2031617
# |   %bf.set = or i32 %bf.clear, 65536
# |   store volatile i32 %bf.set, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st6_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   %x = alloca i32, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i16, ptr %0, align 4
# |   %bf.shl = shl i16 %bf.load, 4
# |   %bf.ashr = ashr i16 %bf.shl, 4
# |   %bf.cast = sext i16 %bf.ashr to i32
# |   store i32 %bf.cast, ptr %x, align 4
# |   %1 = load ptr, ptr %m.addr, align 4
# |   %b = getelementptr inbounds nuw %struct.st6, ptr %1, i32 0, i32 1
# |   %2 = load volatile i8, ptr %b, align 2
# |   %conv = sext i8 %2 to i32
# |   %3 = load i32, ptr %x, align 4
# |   %add = add nsw i32 %3, %conv
# |   store i32 %add, ptr %x, align 4
# |   %4 = load ptr, ptr %m.addr, align 4
# |   %c = getelementptr inbounds nuw %struct.st6, ptr %4, i32 0, i32 2
# |   %bf.load1 = load volatile i8, ptr %c, align 1
# |   %bf.shl2 = shl i8 %bf.load1, 3
# |   %bf.ashr3 = ashr i8 %bf.shl2, 3
# |   %bf.cast4 = sext i8 %bf.ashr3 to i32
# |   %5 = load i32, ptr %x, align 4
# |   %add5 = add nsw i32 %5, %bf.cast4
# |   store i32 %add5, ptr %x, align 4
# |   %6 = load i32, ptr %x, align 4
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st6_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load i16, ptr %0, align 4
# |   %bf.clear = and i16 %bf.load, -4096
# |   %bf.set = or i16 %bf.clear, 1
# |   store i16 %bf.set, ptr %0, align 4
# |   %1 = load ptr, ptr %m.addr, align 4
# |   %b = getelementptr inbounds nuw %struct.st6, ptr %1, i32 0, i32 1
# |   store i8 2, ptr %b, align 2
# |   %2 = load ptr, ptr %m.addr, align 4
# |   %c = getelementptr inbounds nuw %struct.st6, ptr %2, i32 0, i32 2
# |   %bf.load1 = load i8, ptr %c, align 1
# |   %bf.clear2 = and i8 %bf.load1, -32
# |   %bf.set3 = or i8 %bf.clear2, 3
# |   store i8 %bf.set3, ptr %c, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st7_check_load(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   %r = alloca i32, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %x = getelementptr inbounds nuw %struct.st7b, ptr %0, i32 0, i32 0
# |   %1 = load i8, ptr %x, align 4
# |   %conv = sext i8 %1 to i32
# |   store i32 %conv, ptr %r, align 4
# |   %2 = load ptr, ptr %m.addr, align 4
# |   %y = getelementptr inbounds nuw %struct.st7b, ptr %2, i32 0, i32 2
# |   %a = getelementptr inbounds nuw %struct.st7a, ptr %y, i32 0, i32 0
# |   %3 = load volatile i8, ptr %a, align 4
# |   %conv1 = sext i8 %3 to i32
# |   %4 = load i32, ptr %r, align 4
# |   %add = add nsw i32 %4, %conv1
# |   store i32 %add, ptr %r, align 4
# |   %5 = load ptr, ptr %m.addr, align 4
# |   %y2 = getelementptr inbounds nuw %struct.st7b, ptr %5, i32 0, i32 2
# |   %b = getelementptr inbounds nuw %struct.st7a, ptr %y2, i32 0, i32 1
# |   %bf.load = load volatile i8, ptr %b, align 1
# |   %bf.shl = shl i8 %bf.load, 3
# |   %bf.ashr = ashr i8 %bf.shl, 3
# |   %bf.cast = sext i8 %bf.ashr to i32
# |   %6 = load i32, ptr %r, align 4
# |   %add3 = add nsw i32 %6, %bf.cast
# |   store i32 %add3, ptr %r, align 4
# |   %7 = load i32, ptr %r, align 4
# |   ret i32 %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @st7_check_store(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %x = getelementptr inbounds nuw %struct.st7b, ptr %0, i32 0, i32 0
# |   store i8 1, ptr %x, align 4
# |   %1 = load ptr, ptr %m.addr, align 4
# |   %y = getelementptr inbounds nuw %struct.st7b, ptr %1, i32 0, i32 2
# |   %a = getelementptr inbounds nuw %struct.st7a, ptr %y, i32 0, i32 0
# |   store volatile i8 2, ptr %a, align 4
# |   %2 = load ptr, ptr %m.addr, align 4
# |   %y1 = getelementptr inbounds nuw %struct.st7b, ptr %2, i32 0, i32 2
# |   %b = getelementptr inbounds nuw %struct.st7a, ptr %y1, i32 0, i32 1
# |   %bf.load = load volatile i8, ptr %b, align 1
# |   %bf.clear = and i8 %bf.load, -32
# |   %bf.set = or i8 %bf.clear, 3
# |   store volatile i8 %bf.set, ptr %b, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @st8_check_assignment(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   store i16 -1, ptr %0, align 4
# |   ret i32 65535
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @read_st9(ptr noundef %m) #0 {
# | entry:
# |   %m.addr = alloca ptr, align 4
# |   store ptr %m, ptr %m.addr, align 4
# |   %0 = load ptr, ptr %m.addr, align 4
# |   %bf.load = load volatile i8, ptr %0, align 4
# |   %bf.cast = sext i8 %bf.load to i32
# |   r
# | ...
# `---data was truncated (10240/24998) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da73dce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055da73dcb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055da73dce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50ab249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50ab2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50ab249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50ab231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da73d63e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055da73d63c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055da73d48b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055da739f80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055da739f7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f50ab232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50ab2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50ab2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da739f7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c (77 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056434485315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005643448500f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056434485389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f259a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f259a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f259a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f259a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643447e8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005643447e8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005643447cdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056434447d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056434447cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f259a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f259a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f259a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056434447ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c (78 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sw_gather_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/18766) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000560e6247f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560e6247c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560e6247f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84e2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84e2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84e2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84e2c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e62414e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560e62414c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560e623f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560e620a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560e620a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f84e2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84e2c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84e2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e620a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c (79 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a555d015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562a555cd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562a555d089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ae5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ae5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ae5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ae5e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a55565e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562a55565c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562a5554ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562a551fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562a551f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5ae5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ae5e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ae5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a551f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c (80 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_add_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.add = call i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.add
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_and_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.and = call i32 @llvm.vector.reduce.and.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.and
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.and.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_or_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.or = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.or
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_xor_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.xor = call i32 @llvm.vector.reduce.xor.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.xor
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.xor.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_smax_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.smax.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.smax.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_smin_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.smin.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.smin.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_umax_u32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.umax.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.umax.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_umin_u32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.min = call i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fmax_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.min = call float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fmin_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.min = call float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.min
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fmaximum_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.maximum = call float @llvm.vector.reduce.fmaximum.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.maximum
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fmaximum.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @reduce_fminimum_f32(<vscale x 2 x float> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %a.addr, align 4
# |   %rdx.minimum = call float @llvm.vector.reduce.fminimum.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %rdx.minimum
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.vector.reduce.fminimum.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_add_i32_m8(<vscale x 16 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i32>, align 4
# |   store <vscale x 16 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 16 x i32>, ptr %a.addr, align 4
# |   %rdx.add = call i32 @llvm.vector.reduce.add.nxv16i32(<vscale x 16 x i32> %0)
# |   ret i32 %rdx.add
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.add.nxv16i32(<vscale x 16 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @reduce_add_i64(<vscale x 1 x i64> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 1 x i64>, align 8
# |   store <vscale x 1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %a.addr, align 8
# |   %rdx.add = call i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64> %0)
# |   ret i64 %rdx.add
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @reduce_mul_i32(<vscale x 2 x i32> %a) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i32>, align 4
# |   store <vscale x 2 x i32> %a, ptr %a.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %a.addr, align 4
# |   %rdx.mul = call i32 @llvm.vector.reduce.mul.nxv2i32(<vscale x 2 x i32> %0)
# |   ret i32 %rdx.mul
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.vector.reduce.mul.nxv2i32(<vscale x 2 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000056414c86615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056414c8630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056414c86689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d38733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d3878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d38733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d3871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056414c7fbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056414c7fbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056414c7e0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056414c4900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056414c48fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5d3871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d3871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d3871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056414c48fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c (81 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559202c2015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559202c1d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559202c2089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06b2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06b28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06b2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06b2831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559202bb5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559202bb5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559202b9ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055920284a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559202849dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f06b2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06b28330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06b28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559202849cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c (82 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind 
# | ...
# `---data was truncated (10240/77062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f696ed415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f696ed10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f696ed489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1356a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1356a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1356a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1356a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f696e69e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f696e69c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f696e4eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f696afe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f696afddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1356a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1356a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1356a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f696afdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c (83 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg)
# | ...
# `---data was truncated (10240/32178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644cf76415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005644cf7610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005644cf76489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa636333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa63638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa636333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa63631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644cf6f9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005644cf6f9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005644cf6deb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005644cf38e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005644cf38ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa63631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa63631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa63631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644cf38dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c (84 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564516c3715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564516c340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564516c3789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e85133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e8518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e85133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e8511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564516bcce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564516bccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564516bb1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005645168610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564516860dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3e8511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e8511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e8511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564516860cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c (85 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be3204115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055be3203e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055be3204189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e58249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e582a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e58249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e58231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be31fd6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055be31fd6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055be31fbbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055be31c6b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055be31c6add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3e58232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e582330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e582330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be31c6acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c (86 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619a0eb815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005619a0eb50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005619a0eb889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b59133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b5918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b59133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b5911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619a0e4de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005619a0e4dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005619a0e32b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005619a0ae20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005619a0ae1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5b5911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b5911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b5911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619a0ae1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c (87 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4a646f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b4a646c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b4a646f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa879d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa879d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa879d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa879ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4a6404e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b4a6404c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b4a63e9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b4a60990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b4a6098dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa879ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa879cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa879cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4a6098cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c (88 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056409cb2115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056409cb1e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056409cb2189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67d1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67d16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67d1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67d1631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056409cab6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056409cab6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056409ca9bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056409c74b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056409c74add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f67d1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67d16330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67d16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056409c74acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c (89 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056306673915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005630667360f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056306673989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9882733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f988278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9882733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f988271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630666cee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005630666cec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005630666b3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005630663630b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563066362dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f988271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f988271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f988271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563066362cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c (90 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e169f415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562e169f10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562e169f489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f971b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f971b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f971b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f971b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e16989e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562e16989c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562e1696eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562e1661e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562e1661ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f971b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f971b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f971b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e1661dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c (91 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.a
# | ...
# `---data was truncated (10240/36974) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000555b9b70615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555b9b7030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555b9b70689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5392f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5392f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5392f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5392f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b9b69be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555b9b69bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555b9b680b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555b9b3300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555b9b32fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5392f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5392f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5392f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b9b32fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c (92 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ee0ed415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557ee0ed10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557ee0ed489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02f3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02f3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02f3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02f3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ee0e69e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557ee0e69c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557ee0e4eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557ee0afe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557ee0afddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f02f3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02f3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02f3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ee0afdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c (93 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056442cd3415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056442cd310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056442cd3489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdadfa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdadfaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdadfa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdadfa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056442ccc9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056442ccc9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056442ccaeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056442c95e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056442c95ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdadfa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdadfa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdadfa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056442c95dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c (94 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsmul_vv_i8
# | ...
# `---data was truncated (10240/99577) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056152bc2d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056152bc2a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056152bc2d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2335d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2335d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2335d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2335d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056152bbc2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056152bbc2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056152bba7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056152b8570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056152b856dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2335d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2335d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2335d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056152b856cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c (95 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba1c86c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ba1c8690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ba1c86c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe33e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe33e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe33e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe33e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba1c801e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ba1c801c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ba1c7e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ba1c4960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ba1c495dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe33e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe33e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe33e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba1c495cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c (96 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale
# | ...
# `---data was truncated (10240/10790) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb127f515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cb127f20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cb127f589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8c5c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8c5c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8c5c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8c5c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb1278ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cb1278ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cb1276fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cb1241f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cb1241edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd8c5c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8c5c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8c5c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb1241ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c (97 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %b
# | ...
# `---data was truncated (10240/38307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d848cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563d848c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563d848cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc98ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc98baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc98ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc98ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d84860e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563d84860c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563d84845b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563d844f50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563d844f4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc98ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc98ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc98ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d844f4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c (98 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vsc
# | ...
# `---data was truncated (10240/59603) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563ba8e415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005563ba8e10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005563ba8e489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f436f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f436f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f436f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f436f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563ba879e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005563ba879c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005563ba85eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005563ba50e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005563ba50ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f436f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f436f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f436f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563ba50dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c (99 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 
# | ...
# `---data was truncated (10240/255538) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ee319a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564ee31970f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564ee319a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c0a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c0a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c0a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c0a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ee312fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564ee312fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564ee3114b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564ee2dc40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564ee2dc3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8c0a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c0a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c0a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ee2dc3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c (100 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f  -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f  -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone  -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w2_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 %4, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 immarg, <vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f32m8(<vscale x 16 x float> %vs2, <vscale x 16 x float> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 16 x float>, align 4
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, <vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 immarg, <vscale x 16 x float>, <vscale x 16 x float>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f64m8(<vscale x 8 x double> %vs2, <vscale x 8 x double> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vs1.addr = alloca <vscale x 8 x double>, align 8
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x double> %vs1, ptr %vs1.addr, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, <vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 immarg, <vscale x 8 x double>, <vscale x 8 x double>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfmm32a16f,+xsfmm32a32f,+xsfmm64a64f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl32b1p0_zvl64b1p0_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm64a64f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556e145615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005556e14530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005556e145689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8064533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f806458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8064533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f806451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556e13ebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005556e13ebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005556e13d0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005556e10800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005556e107fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f806451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f806451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f806451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556e107fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c (101 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8_tu(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   
# | ...
# `---data was truncated (10240/92362) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e44bae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560e44bab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560e44bae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5990049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59900a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5990049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5990031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e44b43e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560e44b43c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560e44b28b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560e447d80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560e447d7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5990032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59900330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59900330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e447d7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c (102 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/78328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e89b53215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e89b52f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e89b53289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87deb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87deb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87deb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87deb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e89b4c7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e89b4c7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e89b4acb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e89b15c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e89b15bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f87deb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87deb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87deb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e89b15bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c (103 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8f1e0615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d8f1e030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d8f1e0689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff799733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff79978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff799733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff79971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8f1d9be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d8f1d9bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d8f1d80b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d8f1a300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d8f1a2fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff79971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff79971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff79971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8f1a2fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c (104 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627a18cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005627a18c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005627a18cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5d1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5d10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5d1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5d1031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627a1860e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005627a1860c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005627a1845b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005627a14f50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005627a14f4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff5d1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5d10330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5d10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627a14f4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c (105 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | de
# | ...
# `---data was truncated (10240/70971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055638a5e515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055638a5e20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055638a5e589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4de1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4de158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4de1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4de151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055638a57ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055638a57ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055638a55fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055638a20f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055638a20edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4de151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4de151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4de151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055638a20ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c (106 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c4866f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564c4866c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564c4866f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facf5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facf5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facf5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facf5e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c48604e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564c48604c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564c485e9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564c482990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564c48298dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007facf5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facf5e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facf5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c48298cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c (107 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559be708115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559be707e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559be708189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb586a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb586aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb586a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb586a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559be7016e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559be7016c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559be6ffbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559be6cab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559be6caadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb586a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb586a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb586a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559be6caacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c (108 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_cvt_f16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcvt.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_cvt_bf16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvt.x2(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvt.x2(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svcvt_f32_u32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svcvt_f32_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcvt_u32_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcvt_s32_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svcvt_f32_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, p
# | ...
# `---data was truncated (10240/39207) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000559dabace15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559dabacb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559dabace89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0474249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04742a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0474249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0474231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559daba63e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559daba63c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559daba48b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559dab6f80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559dab6f7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0474232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04742330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04742330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559dab6f7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c (109 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinta_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinta_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinta_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinta_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinta_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinta_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinta_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinta.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinta_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinta_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinta.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055fdbf09f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fdbf09c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fdbf09f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8737849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87378a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8737849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8737831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fdbf034e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fdbf034c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fdbf019b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fdbecc90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fdbecc8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8737832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87378330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87378330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fdbecc8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c (110 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqincb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 5, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %0, i32 6, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincb_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincb.n32(i32 %0, i32 7, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincb_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincb.n64(i64 %0, i32 8, i32 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c480d2f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c480d2c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c480d2f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8253d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8253d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8253d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8253d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c480cc4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c480cc4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c480ca9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c4809590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c480958dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8253d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8253d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8253d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c480958cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c (111 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ecc9fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558ecc9fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558ecc9fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efffb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efffb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efffb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efffb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ecc992e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558ecc992c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558ecc977b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558ecc6270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558ecc626dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efffb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efffb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efffb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ecc626cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c (112 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_s16_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x4.nxv8i16(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x4.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_u16_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x4.nxv8i16(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x4.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_s32_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x4.nxv4i32(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x4.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_u32_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x4.nxv4i32(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x4.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_s64_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x4.nxv2i64(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x4.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_u64_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x4.nxv2i64(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x4.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d7c483915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d7c48360f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d7c483989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5534049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55340a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5534049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5534031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7c47cee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d7c47cec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d7c47b3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d7c44630b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d7c4462dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5534032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55340330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55340330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7c4462cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c (113 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561638e6d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561638e6a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561638e6d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8fa505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8fa55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8fa505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8fa4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561638e02e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561638e02c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561638de7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561638a970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561638a96dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd8fa4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8fa4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8fa4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561638a96cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c (114 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_u8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.
# | ...
# `---data was truncated (10240/13557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9097eb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d9097e80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d9097eb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd57e705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd57e75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd57e705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd57e6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d909780e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d909780c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d909765b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d9094150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d909414dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd57e6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd57e6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd57e6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d909414cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c (115 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cdfc42115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cdfc41e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cdfc42189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed0b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed0b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed0b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed0b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cdfc3b6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cdfc3b6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cdfc39bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cdfc04b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cdfc04add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fed0b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed0b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed0b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cdfc04acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c (116 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind
# | ...
# `---data was truncated (10240/365431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555cb611c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555cb61190f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555cb611c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa615249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6152a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa615249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa615231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555cb60b1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555cb60b1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555cb6096b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555cb5d460b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555cb5d45dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa615232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6152330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6152330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555cb5d45cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c (117 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa13a4515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aa13a420f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aa13a4589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba78c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba78ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba78c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba78c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa139dae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aa139dac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aa139bfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aa1366f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aa1366edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fba78c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba78c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba78c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa1366ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c (118 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16
# | ...
# `---data was truncated (10240/69305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056007a72b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056007a7280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056007a72b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe697733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe69778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe697733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe69771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056007a6c0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056007a6c0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056007a6a5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056007a3550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056007a354dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe69771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe69771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe69771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056007a354cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c (119 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df0299a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055df029970f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055df0299a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75eb333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75eb38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75eb333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75eb31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df0292fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055df0292fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055df02914b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055df025c40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055df025c3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f75eb31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75eb31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75eb31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df025c3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp (120 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme    -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | %class.anon = type { i8 }
# | 
# | $_Z15template_functyIiET_S0_ = comdat any
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @streaming_caller() #0 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | declare i32 @normal_callee() #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @streaming_callee() #0 {
# | entry:
# |   %call = call i32 @streaming_decl() #15
# |   ret i32 %call
# | }
# | 
# | declare i32 @streaming_decl() #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @streaming_compatible_caller() #3 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @streaming_compatible_callee() #3 {
# | entry:
# |   %call = call i32 @streaming_compatible_decl() #16
# |   ret i32 %call
# | }
# | 
# | declare i32 @streaming_compatible_decl() #4
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @locally_streaming_caller() #5 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local i32 @locally_streaming_callee() #5 {
# | entry:
# |   %call = call i32 @locally_streaming_caller() #17
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @shared_za_caller() #6 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @shared_za_callee() #6 {
# | entry:
# |   %call = call i32 @shared_za_decl() #18
# |   ret i32 %call
# | }
# | 
# | declare i32 @shared_za_decl() #7
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @preserves_za_caller() #8 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @preserves_za_callee() #8 {
# | entry:
# |   %call = call i32 @preserves_za_decl() #19
# |   ret i32 %call
# | }
# | 
# | declare i32 @preserves_za_decl() #9
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @new_za_caller() #10 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @new_za_callee() #10 {
# | entry:
# |   %call = call i32 @private_za_decl()
# |   ret i32 %call
# | }
# | 
# | declare i32 @private_za_decl() #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @agnostic_za_caller() #11 {
# | entry:
# |   %call = call i32 @normal_callee()
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @agnostic_za_callee() #12 {
# | entry:
# |   %call = call i32 @agnostic_za_decl() #20
# |   ret i32 %call
# | }
# | 
# | declare i32 @agnostic_za_decl() #13
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local i32 @agnostic_za_callee_live_za() #6 {
# | entry:
# |   %call = call i32 @agnostic_za_decl() #20
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_streaming_ptrty(ptr noundef %f, i32 noundef %x, i32 noundef %y) #12 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #15
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_streaming_compatible_ptrty(ptr noundef %f, i32 noundef %x, i32 noundef %y) #12 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #16
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_shared_za(ptr noundef %f, i32 noundef %x, i32 noundef %y) #6 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #18
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_preserved_za(ptr noundef %f, i32 noundef %x, i32 noundef %y) #6 {
# | entry:
# |   %f.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %f, ptr %f.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %f.addr, align 8
# |   %1 = load i32, ptr %x.addr, align 4
# |   %2 = load i32, ptr %y.addr, align 4
# |   call void %0(i32 noundef %1, i32 noundef %2) #19
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @test_indirect_streaming_ptrty(ptr noundef %fptr, i32 noundef %x, i32 noundef %y) #12 {
# | entry:
# |   %fptr.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store ptr %fptr, ptr %fptr.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load ptr, ptr %fptr.addr, align 8
# |   %1 = load ptr, ptr %0, align 8
# |   %2 = load ptr, ptr %1, align 8
# |   %3 = load i32, ptr %x.addr, align 4
# |   %4 = load i32, ptr %y.addr, align 4
# |   call void %2(i32 noundef %3, i32 noundef %4) #15
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @_Z24test_same_type_streamingv() #12 {
# | entry:
# |   call void @_Z10streaming1v() #15
# |   call void @_Z10streaming2v() #15
# |   call void @_Z20same_type_streaming1v() #15
# |   call void @_Z20same_type_streaming2v() #15
# |   ret void
# | }
# | 
# | declare void @_Z10streaming1v() #2
# | 
# | declare void @_Z10streaming2v() #2
# | 
# | declare void @_Z20same_type_streaming1v() #2
# | 
# | declare void @_Z20same_type_streaming2v() #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local noundef i32 @_Z12overloadedfni(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef float @_Z12overloadedfnf(float noundef %x) #12 {
# | entry:
# |   %x.addr = alloca float, align 4
# |   store float %x, ptr %x.addr, align 4
# |   %0 = load float, ptr %x.addr, align 4
# |   ret float %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z13test_overloadi(i32 noundef %x) #12 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @_Z12overloadedfni(i32 noundef %0) #15
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef float @_Z13test_overloadf(float noundef %x) #12 {
# | entry:
# |   %x.addr = alloca float, align 4
# |   store float %x, ptr %x.addr, align 4
# |   %0 = load float, ptr %x.addr, align 4
# |   %call = call noundef float @_Z12overloadedfnf(float noundef %0)
# |   ret float %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z11test_lambdai(i32 noundef %x) #12 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %F = alloca %class.anon, align 1
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @"_ZZ11test_lambdaiENK3$_0clEi"(ptr noundef nonnull align 1 dereferenceable(1) %F, i32 noundef %0) #15
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define internal noundef i32 @"_ZZ11test_lambdaiENK3$_0clEi"(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load i32, ptr %x.addr, align 4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z27test_template_instantiationv() #12 {
# | entry:
# |   %call = call noundef i32 @_Z15template_functyIiET_S0_(i32 noundef 12) #15
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define linkonce_odr noundef i32 @_Z15template_functyIiET_S0_(i32 noundef %x) #0 comdat {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local void @_Z25locally_streaming_inheritv() #5 {
# | entry:
# |   %call = call i32 @streaming_decl() #15
# |   ret void
# | }
# | 
# | ; Function Attrs: alwaysinline mustprogress nounwind
# | define dso_local noundef i32 @_Z4callv() #14 {
# | entry:
# |   ret i32 0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local noundef i32 @_Z22test_variadic_templatev() #6 {
# | entry:
# |   %f.addr.i16 = alloca ptr, align 8
# |   %f.addr.i12 = alloca ptr, align 8
# |   %other.addr.i13 = alloca ptr, align 8
# |   %f.addr.i7 = alloca ptr, align 8
# |   %other.addr.i8 = alloca ptr, align 8
# |   %other.addr2.i9 = alloca ptr, align 8
# |   %f.addr.i1 = alloca ptr, align 8
# |   %other.addr.i2 = alloca ptr, align 8
# |   %other.addr2.i3 = alloca ptr, align 8
# |   %other.addr4.i4 = alloca ptr, align 8
# |   %f.addr.i = alloca ptr, align 8
# |   %other.addr.i = alloca ptr, align 8
# |   %other.addr2.i = alloca ptr, align 8
# |   %other.addr4.i = alloca ptr, align 8
# |   %other.addr6.i = alloca ptr, align 8
# |   store ptr @normal_callee, ptr %f.addr.i, align 8
# |   store ptr @streaming_decl, ptr %other.addr.i, align 8
# |   store ptr @streaming_compatible_decl
# | ...
# `---data was truncated (10240/15241) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d727ffa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d727ff70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d727ffa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9b6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9b6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9b6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9b6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d727f8fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d727f8fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d727f74b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d727c240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d727c23dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd9b6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9b6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9b6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d727c23cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# |  #0 0x000055da7b82f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055da7b82c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055da7b82f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b4eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b4eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b4eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b4eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da7b7c4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055da7b7c4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055da7b7a9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055da7b4590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055da7b458dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0b4eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b4eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b4eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da7b458cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c (121 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedo
# | ...
# `---data was truncated (10240/30751) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628389db15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005628389d80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005628389db89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2291d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2291d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2291d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2291ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562838970e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562838970c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562838955b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005628386050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562838604dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2291ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2291cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2291cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562838604cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c (122 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.bf16.nxv
# | ...
# `---data was truncated (10240/51702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc4d51815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dc4d5150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dc4d51889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56e1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56e1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56e1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56e1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc4d4ade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dc4d4adc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dc4d492b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dc4d1420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dc4d141dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f56e1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56e1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56e1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc4d141cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c (123 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store
# | ...
# `---data was truncated (10240/79497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ef513115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562ef512e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562ef513189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9b4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9b478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9b4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9b471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ef50c6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562ef50c6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562ef50abb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562ef4d5b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562ef4d5add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa9b471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9b471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9b471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ef4d5acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c (124 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de8fa1515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055de8fa120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055de8fa1589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8775505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f877555c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8775505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87754ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de8f9aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055de8f9aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055de8f98fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055de8f63f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055de8f63edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f87754eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87754ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87754ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de8f63ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c (125 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055656f1ba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055656f1b70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055656f1ba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f85ca249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85ca2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f85ca249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f85ca231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055656f14fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055656f14fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055656f134b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055656ede40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055656ede3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f85ca232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85ca2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85ca2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055656ede3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c (126 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, fl
# | ...
# `---data was truncated (10240/25099) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aeed2a615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aeed2a30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aeed2a689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb90649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb906a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb90649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb90631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aeed23be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aeed23bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aeed220b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aeeced00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aeececfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdb90632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb906330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb906330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aeececfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/memcmp-inline-builtin-to-asm.c (127 of 27911)
******************** TEST 'Clang :: CodeGen/memcmp-inline-builtin-to-asm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64"
# | 
# | @con_unify_unimap_p1 = global ptr null, align 8
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @con_unify_unimap_q1() #0 {
# | entry:
# |   %p.addr.i = alloca ptr, align 8
# |   %q.addr.i = alloca ptr, align 8
# |   %size.addr.i = alloca i64, align 8
# |   %0 = load ptr, ptr @con_unify_unimap_p1, align 8
# |   store ptr %0, ptr %p.addr.i, align 8
# |   store ptr @con_unify_unimap_q1, ptr %q.addr.i, align 8
# |   store i64 4, ptr %size.addr.i, align 8
# |   %1 = load ptr, ptr %p.addr.i, align 8
# |   %2 = load ptr, ptr %q.addr.i, align 8
# |   %3 = load i64, ptr %size.addr.i, align 8
# |   %call.i = call i32 @memcmp(ptr noundef %1, ptr noundef %2, i64 noundef %3) #2
# |   ret i32 %call.i
# | }
# | 
# | ; Function Attrs: alwaysinline nobuiltin nounwind
# | declare i32 @memcmp(ptr noundef, ptr noundef, i64 noundef) #1
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { alwaysinline nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #2 = { nounwind }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify
# |  #0 0x0000559b725b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559b725b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559b725b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb53ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb53ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb53ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb53ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b7254be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559b7254bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559b72530b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559b721e00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559b721dfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb53ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb53ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb53ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b721dfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c (128 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055565f2f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055565f2f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055565f2f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ff3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ff30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ff3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ff3031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055565f28de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055565f28dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055565f272b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055565ef220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055565ef21dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7ff3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ff30330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ff30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055565ef21cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c (129 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale 
# | ...
# `---data was truncated (10240/215486) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559401eb615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559401eb30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559401eb689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e54e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e54ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e54e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e54e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559401e4be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559401e4bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559401e30b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559401ae00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559401adfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5e54e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e54e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e54e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559401adfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c (130 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055717c64315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055717c6400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055717c64389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd978b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd978b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd978b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd978b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055717c5d8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055717c5d8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055717c5bdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055717c26d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055717c26cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd978b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd978b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd978b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055717c26ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c (131 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055752bb3515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055752bb320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055752bb3589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f692ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f692aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f692ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f692ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055752bacae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055752bacac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055752baafb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055752b75f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055752b75edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f692ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f692ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f692ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055752b75ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c (132 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da5405b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055da540580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055da5405b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb469305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb46935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb469305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4692ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da53ff0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055da53ff0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055da53fd5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055da53c850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055da53c84dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb4692eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4692ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4692ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da53c84cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c (133 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005616c88fe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005616c88fb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005616c88fe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5c1e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5c1e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5c1e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5c1e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616c8893e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005616c8893c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005616c8878b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005616c85280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005616c8527dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe5c1e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5c1e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5c1e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616c8527cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c (134 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573d3f8b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005573d3f880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005573d3f8b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa1b1f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1b1f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa1b1f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa1b1eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573d3f20e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005573d3f20c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005573d3f05b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005573d3bb50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005573d3bb4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa1b1eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1b1eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1b1eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573d3bb4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-vls-arith-ops.c (135 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-arith-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @add_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %add = add <64 x i8> %0, %1
# |   store <64 x i8> %add, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @add_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %add = add <32 x i16> %0, %1
# |   store <32 x i16> %add, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @add_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %add = add <16 x i32> %0, %1
# |   store <16 x i32> %add, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @add_i64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %add = add <8 x i64> %0, %1
# |   store <8 x i64> %add, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64>, <8 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @add_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %add = add <64 x i8> %0, %1
# |   store <64 x i8> %add, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @add_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %add = add <32 x i16> %0, %1
# |   store <32 x i16> %add, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @add_u32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %add = add <16 x i32> %0, %1
# |   store <16 x i32> %add, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @add_u64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %add = add <8 x i64> %0, %1
# |   store <8 x i64> %add, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x half> @add_f16(<vscale x 8 x half> noundef %a.coerce, <vscale x 8 x half> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x half>, align 16
# |   %a.addr = alloca <32 x half>, align 16
# |   %b.addr = alloca <32 x half>, align 16
# |   %a = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> %a.coerce, i64 0)
# |   %b = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> %b.coerce, i64 0)
# |   store <32 x half> %a, ptr %a.addr, align 16
# |   store <32 x half> %b, ptr %b.addr, align 16
# |   %0 = load <32 x ha
# | ...
# `---data was truncated (10240/161192) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055896003415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005589600310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055896003489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee49449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee494a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee49449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee49431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055895ffc9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055895ffc9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055895ffaeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055895fc5e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055895fc5ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fee49432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee494330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee494330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055895fc5dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c (136 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, p
# | ...
# `---data was truncated (10240/14521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a333b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555a333b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555a333b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46e7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46e76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46e7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46e7631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a3334be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555a3334bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555a33330b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555a32fe00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555a32fdfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f46e7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46e76330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46e76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a32fdfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vld24.c (137 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vld24.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc %struct.float16x8x2_t @test_vld2q_f16(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0(ptr %0)
# |   %2 = extractvalue { <8 x half>, <8 x half> } %1, 0
# |   %3 = insertvalue %struct.float16x8x2_t poison, <8 x half> %2, 0, 0
# |   %4 = extractvalue { <8 x half>, <8 x half> } %1, 1
# |   %5 = insertvalue %struct.float16x8x2_t %3, <8 x half> %4, 0, 1
# |   ret %struct.float16x8x2_t %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc %struct.uint8x16x4_t @test_vld4q_u8(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0(ptr %0)
# |   %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 0
# |   %3 = insertvalue %struct.uint8x16x4_t poison, <16 x i8> %2, 0, 0
# |   %4 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 1
# |   %5 = insertvalue %struct.uint8x16x4_t %3, <16 x i8> %4, 0, 1
# |   %6 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2
# |   %7 = insertvalue %struct.uint8x16x4_t %5, <16 x i8> %6, 0, 2
# |   %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3
# |   %9 = insertvalue %struct.uint8x16x4_t %7, <16 x i8> %8, 0, 3
# |   ret %struct.uint8x16x4_t %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @test_vst2q_u32(ptr noundef %addr, %struct.uint32x4x2_t %value.coerce) #0 {
# | entry:
# |   %value = alloca %struct.uint32x4x2_t, align 8
# |   %addr.addr = alloca ptr, align 4
# |   %tmp = alloca %struct.uint32x4x2_t, align 8
# |   %0 = getelementptr inbounds nuw %struct.uint32x4x2_t, ptr %value, i32 0, i32 0
# |   %1 = extractvalue %struct.uint32x4x2_t %value.coerce, 0
# |   store [2 x <4 x i32>] %1, ptr %0, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 32, i1 false)
# |   %3 = load %struct.uint32x4x2_t, ptr %tmp, align 8
# |   %4 = extractvalue %struct.uint32x4x2_t %3, 0, 0
# |   %5 = extractvalue %struct.uint32x4x2_t %3, 0, 1
# |   call void @llvm.arm.mve.vst2q.p0.v4i32(ptr %2, <4 x i32> %4, <4 x i32> %5, i32 0)
# |   call void @llvm.arm.mve.vst2q.p0.v4i32(ptr %2, <4 x i32> %4, <4 x i32> %5, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i32(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i32, i1 immarg) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.mve.vst2q.p0.v4i32(ptr, <4 x i32>, <4 x i32>, i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @test_vst4q_s8(ptr noundef %addr, %struct.int8x16x4_t %value.coerce) #0 {
# | entry:
# |   %value = alloca %struct.int8x16x4_t, align 8
# |   %addr.addr = alloca ptr, align 4
# |   %tmp = alloca %struct.int8x16x4_t, align 8
# |   %0 = getelementptr inbounds nuw %struct.int8x16x4_t, ptr %value, i32 0, i32 0
# |   %1 = extractvalue %struct.int8x16x4_t %value.coerce, 0
# |   store [4 x <16 x i8>] %1, ptr %0, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 64, i1 false)
# |   %3 = load %struct.int8x16x4_t, ptr %tmp, align 8
# |   %4 = extractvalue %struct.int8x16x4_t %3, 0, 0
# |   %5 = extractvalue %struct.int8x16x4_t %3, 0, 1
# |   %6 = extractvalue %struct.int8x16x4_t %3, 0, 2
# |   %7 = extractvalue %struct.int8x16x4_t %3, 0, 3
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 0)
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 1)
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 2)
# |   call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.mve.vst4q.p0.v16i8(ptr, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @test_vst2q_f16(ptr noundef %addr, %struct.float16x8x2_t %value.coerce) #0 {
# | entry:
# |   %value = alloca %struct.float16x8x2_t, align 8
# |   %addr.addr = alloca ptr, align 4
# |   %tmp = alloca %struct.float16x8x2_t, align 8
# |   %0 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %value, i32 0, i32 0
# |   %1 = extractvalue %struct.float16x8x2_t %value.coerce, 0
# |   store [2 x <8 x half>] %1, ptr %0, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 32, i1 false)
# |   %3 = load %struct.float16x8x2_t, ptr %tmp, align 8
# |   %4 = extractvalue %struct.float16x8x2_t %3, 0, 0
# |   %5 = extractvalue %struct.float16x8x2_t %3, 0, 1
# |   call void @llvm.arm.mve.vst2q.p0.v8f16(ptr %2, <8 x half> %4, <8 x half> %5, i32 0)
# |   call void @llvm.arm.mve.vst2q.p0.v8f16(ptr %2, <8 x half> %4, <8 x half> %5, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.mve.vst2q.p0.v8f16(ptr, <8 x half>, <8 x half>, i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @load_into_variable(ptr noundef %addr, ptr noundef %values) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %values.addr = alloca ptr, align 4
# |   %v = alloca %struct.uint16x8x2_t, align 8
# |   %tmp = alloca %struct.uint16x8x2_t, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store ptr %values, ptr %values.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr %0)
# |   %2 = extractvalue { <8 x i16>, <8 x i16> } %1, 0
# |   %3 = insertvalue %struct.uint16x8x2_t poison, <8 x i16> %2, 0, 0
# |   %4 = extractvalue { <8 x i16>, <8 x i16> } %1, 1
# |   %5 = insertvalue %struct.uint16x8x2_t %3, <8 x i16> %4, 0, 1
# |   store %struct.uint16x8x2_t %5, ptr %tmp, align 8
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %v, ptr align 8 %tmp, i32 32, i1 false)
# |   %val = getelementptr inbounds nuw %struct.uint16x8x2_t, ptr %v, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <8 x i16>], ptr %val, i32 0, i32 0
# |   %6 = load <8 x i16>, ptr %arrayidx, align 8
# |   %7 = load ptr, ptr %values.addr, align 4
# |   %arrayidx1 = getelementptr inbounds <8 x i16>, ptr %7, i32 0
# |   store <8 x i16> %6, ptr %arrayidx1, align 8
# |   %val2 = getelementptr inbounds nuw %struct.uint16x8x2_t, ptr %v, i32 0, i32 0
# |   %arrayidx3 = getelementptr inbounds [2 x <8 x i16>], ptr %val2, i32 0, i32 1
# |   %8 = load <8 x i16>, ptr %arrayidx3, align 8
# |   %9 = load ptr, ptr %values.addr, align 4
# |   %arrayidx4 = getelementptr inbounds <8 x i16>, ptr %9, i32 1
# |   store <8 x i16> %8, ptr %arrayidx4, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @extract_one_vector(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %ref.tmp = alloca %struct.int32x4x2_t, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.p0(ptr %0)
# |   %2 = extractvalue { <4 x i32>, <4 x i32> } %1, 0
# |   %3 = insertvalue %struct.int32x4x2_t poison, <4 x i32> %2, 0, 0
# |   %4 = extractvalue { <4 x i32>, <4 x i32> } %1, 1
# |   %5 = insertvalue %struct.int32x4x2_t %3, <4 x i32> %4, 0, 1
# |   store %struct.int32x4x2_t %5, ptr %ref.tmp, align 8
# |   %val = getelementptr inbounds nuw %struct.int32x4x2_t, ptr %ref.tmp, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <4 x i32>], ptr %val, i32 0, i32 0
# |   %6 = load <4 x i32>, ptr %arrayidx, align 8
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.p0(ptr) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x000055a35b7bc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a35b7b90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a35b7bc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02e9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02e978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02e9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02e971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a35b751e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a35b751c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a35b736b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a35b3e60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a35b3e5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f02e971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02e971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02e971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a35b3e5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c (138 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x fl
# | ...
# `---data was truncated (10240/90693) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c4deb615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555c4deb30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555c4deb689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d5ca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d5ca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d5ca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d5ca03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c4de4be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555c4de4bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555c4de30b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555c4dae00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555c4dadfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2d5ca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d5ca050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d5ca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c4dadfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c (139 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b47075f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b47075c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b47075f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70c1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70c1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70c1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70c1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4706f4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b4706f4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b4706d9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b4703890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b470388dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f70c1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70c1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70c1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b470388cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c (140 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056219da8715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056219da840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056219da8789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad2af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad2af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad2af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad2af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056219da1ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056219da1cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056219da01b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056219d6b10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056219d6b0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fad2af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad2af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad2af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056219d6b0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c (141 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <v
# | ...
# `---data was truncated (10240/65080) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585fd50d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005585fd50a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005585fd50d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc31e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc31e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc31e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc31e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005585fd4a2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005585fd4a2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005585fd487b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005585fd1370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005585fd136dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc31e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc31e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc31e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005585fd136cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c (142 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646de52d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005646de52a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005646de52d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3949b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3949b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3949b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3949b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646de4c2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005646de4c2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005646de4a7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005646de1570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005646de156dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3949b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3949b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3949b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646de156cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c (143 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp1q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp1q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp1q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp1q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp1q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp1q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp1q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp1q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp1q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp1q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzp1_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp1q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp1q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b26612715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b2661240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b26612789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c55733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c5578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c55733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c5571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2660bce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b2660bcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b2660a1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b265d510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b265d50dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5c5571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c5571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c5571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b265d50cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c (144 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640608c115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005640608be0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005640608c189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f438a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f438a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f438a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f438a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564060856e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564060856c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056406083bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005640604eb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005640604eadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f438a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f438a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f438a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640604eacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c (145 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %o
# | ...
# `---data was truncated (10240/223855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055abc839a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055abc83970f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055abc839a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f650ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f650caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f650ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f650ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055abc832fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055abc832fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055abc8314b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055abc7fc40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055abc7fc3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f650ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f650ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f650ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055abc7fc3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c (146 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056401187b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005640118780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056401187b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f212d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f212d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f212d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f212d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564011810e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564011810c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005640117f5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005640114a50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005640114a4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f212d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f212d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f212d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640114a4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c (147 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f64097815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f6409750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f64097889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82eeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82eeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82eeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82eeb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f64090de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f64090dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f6408f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f6405a20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f6405a1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f82eeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82eeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82eeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6405a1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c (148 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale
# | ...
# `---data was truncated (10240/410383) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a047ebf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a047ebc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a047ebf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe284f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe284f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe284f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe284f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a047e54e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a047e54c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a047e39b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a047ae90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a047ae8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe284f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe284f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe284f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a047ae8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c (149 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacgt_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005635c8da615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005635c8da30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005635c8da689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba7ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba7ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba7ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba7ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635c8d3be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005635c8d3bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005635c8d20b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005635c89d00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005635c89cfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fba7ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba7ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba7ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635c89cfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c (150 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561af005315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561af00500f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561af005389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d7ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d7baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d7ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d7ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561aeffe8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561aeffe8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561aeffcdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561aefc7d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561aefc7cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5d7ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d7ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d7ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561aefc7ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c (151 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056431eb5415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056431eb510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056431eb5489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f309d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f309d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f309d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f309d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056431eae9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056431eae9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056431eaceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056431e77e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056431e77ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f309d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f309d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f309d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056431e77dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGenCoroutines/coro-gro4.cpp (152 of 27911)
******************** TEST 'Clang :: CodeGenCoroutines/coro-gro4.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O2 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes='default<O0>,default<O2>' -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O2 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.wrapper = type { %struct.task }
# | %struct.task = type { %"struct.std::coroutine_handle" }
# | %"struct.std::coroutine_handle" = type { %"struct.std::coroutine_handle.0" }
# | %"struct.std::coroutine_handle.0" = type { ptr }
# | %"struct.task::promise_type" = type { i8 }
# | %"struct.std::suspend_always" = type { i8 }
# | 
# | $_ZN4task12promise_type17get_return_objectEv = comdat any
# | 
# | $_ZN4task12promise_type15initial_suspendEv = comdat any
# | 
# | $_ZNSt14suspend_always11await_readyEv = comdat any
# | 
# | $_ZNSt14suspend_always13await_suspendESt16coroutine_handleIvE = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEE12from_addressEPv = comdat any
# | 
# | $_ZNSt14suspend_always12await_resumeEv = comdat any
# | 
# | $_ZN4task12promise_type11return_voidEv = comdat any
# | 
# | $_ZN4task12promise_type13final_suspendEv = comdat any
# | 
# | $_ZN7wrapperC1EO4task = comdat any
# | 
# | $_ZN4taskD1Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEE12from_promiseERS1_ = comdat any
# | 
# | $_ZN4taskC1ESt16coroutine_handleINS_12promise_typeEE = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEEC1Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIN4task12promise_typeEEC2Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIvEC2Ev = comdat any
# | 
# | $_ZN4taskC2ESt16coroutine_handleINS_12promise_typeEE = comdat any
# | 
# | $_ZN7wrapperC2EO4task = comdat any
# | 
# | $_ZN4taskC1EOS_ = comdat any
# | 
# | $_ZN4taskC2EOS_ = comdat any
# | 
# | $_ZNSt16coroutine_handleIvEaSEDn = comdat any
# | 
# | $_ZN4taskD2Ev = comdat any
# | 
# | $_ZNKSt16coroutine_handleIvEcvbEv = comdat any
# | 
# | $_ZNKSt16coroutine_handleIvE7destroyEv = comdat any
# | 
# | ; Function Attrs: mustprogress nounwind presplitcoroutine
# | define dso_local void @_Z2fnv(ptr dead_on_unwind noalias writable sret(%struct.wrapper) align 8 %agg.result) #0 {
# | entry:
# |   %result.ptr = alloca ptr, align 8
# |   %gro.active = alloca i1, align 1
# |   %__promise = alloca %"struct.task::promise_type", align 1
# |   %__coro_gro = alloca %struct.task, align 8, !coro.outside.frame !6
# |   %ref.tmp = alloca %"struct.std::suspend_always", align 1
# |   %undef.agg.tmp = alloca %"struct.std::suspend_always", align 1
# |   %ref.tmp2 = alloca %"struct.std::suspend_always", align 1
# |   %undef.agg.tmp3 = alloca %"struct.std::suspend_always", align 1
# |   store ptr %agg.result, ptr %result.ptr, align 8
# |   %0 = call token @llvm.coro.id(i32 16, ptr %__promise, ptr null, ptr null)
# |   %1 = call i1 @llvm.coro.alloc(token %0)
# |   br i1 %1, label %coro.alloc, label %coro.init
# | 
# | coro.alloc:                                       ; preds = %entry
# |   %2 = call i64 @llvm.coro.size.i64()
# |   %call = call noalias noundef nonnull ptr @_Znwm(i64 noundef %2) #14
# |   br label %coro.init
# | 
# | coro.init:                                        ; preds = %coro.alloc, %entry
# |   %3 = phi ptr [ null, %entry ], [ %call, %coro.alloc ]
# |   %4 = call ptr @llvm.coro.begin(token %0, ptr %3)
# |   store i1 false, ptr %gro.active, align 1
# |   call void @llvm.lifetime.start.p0(ptr %__promise) #9
# |   call void @llvm.lifetime.start.p0(ptr %__coro_gro) #9
# |   call void @_ZN4task12promise_type17get_return_objectEv(ptr dead_on_unwind writable sret(%struct.task) align 8 %__coro_gro, ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   store i1 true, ptr %gro.active, align 1
# |   call void @llvm.lifetime.start.p0(ptr %ref.tmp) #9
# |   call void @_ZN4task12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   %call1 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp) #9
# |   br i1 %call1, label %init.ready, label %init.suspend
# | 
# | init.suspend:                                     ; preds = %coro.init
# |   %5 = call token @llvm.coro.save(ptr null)
# |   call void @llvm.coro.await.suspend.void(ptr %ref.tmp, ptr %4, ptr @_Z2fnv.__await_suspend_wrapper__init) #9
# |   %6 = call i8 @llvm.coro.suspend(token %5, i1 false)
# |   switch i8 %6, label %pre.gvo.conv [
# |     i8 0, label %init.ready
# |     i8 1, label %init.cleanup
# |   ]
# | 
# | init.cleanup:                                     ; preds = %init.suspend
# |   br label %cleanup
# | 
# | init.ready:                                       ; preds = %init.suspend, %coro.init
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp) #9
# |   br label %cleanup
# | 
# | cleanup:                                          ; preds = %init.ready, %init.cleanup
# |   %cleanup.dest.slot.0 = phi i32 [ 0, %init.ready ], [ 2, %init.cleanup ]
# |   call void @llvm.lifetime.end.p0(ptr %ref.tmp) #9
# |   switch i32 %cleanup.dest.slot.0, label %unreachable [
# |     i32 0, label %cleanup.cont
# |     i32 2, label %coro.cleanup
# |   ]
# | 
# | cleanup.cont:                                     ; preds = %cleanup
# |   call void @_ZN4task12promise_type11return_voidEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   br label %coro.final
# | 
# | coro.final:                                       ; preds = %cleanup.cont
# |   call void @llvm.lifetime.start.p0(ptr %ref.tmp2) #9
# |   call void @_ZN4task12promise_type13final_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9
# |   %call4 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp2) #9
# |   br i1 %call4, label %final.ready, label %final.suspend
# | 
# | final.suspend:                                    ; preds = %coro.final
# |   %7 = call token @llvm.coro.save(ptr null)
# |   call void @llvm.coro.await.suspend.void(ptr %ref.tmp2, ptr %4, ptr @_Z2fnv.__await_suspend_wrapper__final) #9
# |   %8 = call i8 @llvm.coro.suspend(token %7, i1 true)
# |   switch i8 %8, label %pre.gvo.conv [
# |     i8 0, label %final.ready
# |     i8 1, label %final.cleanup
# |   ]
# | 
# | final.cleanup:                                    ; preds = %final.suspend
# |   br label %cleanup5
# | 
# | final.ready:                                      ; preds = %final.suspend, %coro.final
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp2) #9
# |   br label %cleanup5
# | 
# | cleanup5:                                         ; preds = %final.ready, %final.cleanup
# |   %cleanup.dest.slot.1 = phi i32 [ 0, %final.ready ], [ 2, %final.cleanup ]
# |   call void @llvm.lifetime.end.p0(ptr %ref.tmp2) #9
# |   switch i32 %cleanup.dest.slot.1, label %unreachable [
# |     i32 0, label %pre.gvo.conv
# |     i32 2, label %coro.cleanup
# |   ]
# | 
# | pre.gvo.conv:                                     ; preds = %cleanup5, %final.suspend, %init.suspend
# |   %9 = phi i1 [ true, %cleanup5 ], [ false, %final.suspend ], [ false, %init.suspend ]
# |   %InRamp = call i1 @llvm.coro.is_in_ramp()
# |   br i1 %InRamp, label %gro.conv, label %after.gro.conv
# | 
# | gro.conv:                                         ; preds = %pre.gvo.conv
# |   call void @_ZN7wrapperC1EO4task(ptr noundef nonnull align 8 dereferenceable(8) %agg.result, ptr noundef nonnull align 8 dereferenceable(8) %__coro_gro) #9
# |   %cleanup.is_active = load i1, ptr %gro.active, align 1
# |   br i1 %cleanup.is_active, label %cleanup.action, label %cleanup.done
# | 
# | cleanup.action:                                   ; preds = %gro.conv
# |   call void @_ZN4taskD1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) %__coro_gro) #9
# |   br label %cleanup.done
# | 
# | cleanup.done:                                     ; preds = %cleanup.action, %gro.conv
# |   br label %after.gro.conv
# | 
# | after.gro.conv:                                   ; preds = %cleanup.done, %pre.gvo.conv
# |   br i1 %9, label %cleanup.cont7, label %coro.ret
# | 
# | cleanup.cont7:                                    ; preds = %after.gro.conv
# |   br label %coro.cleanup
# | 
# | coro.cleanup:                                     ; preds = %cleanup.cont7, %cleanup5, %cleanup
# |   call void @llvm.lifetime.end.p0(ptr %__coro_gro) #9
# |   call void @llvm.lifetime.end.p0(ptr %__promise) #9
# |   %10 = call ptr @llvm.coro.free(token %0, ptr %4)
# |   %11 = icmp ne ptr %10, null
# |   br i1 %11, label %coro.free, label %after.coro.free
# | 
# | coro.free:                                        ; preds = %coro.cleanup
# |   %12 = call i64 @llvm.coro.size.i64()
# |   call void @_ZdlPvm(ptr noundef %10, i64 noundef %12) #9
# |   br label %after.coro.free
# | 
# | after.coro.free:                                  ; preds = %coro.cleanup, %coro.free
# |   call void @llvm.coro.dead(ptr %4)
# |   br label %coro.ret
# | 
# | coro.ret:                                         ; preds = %after.coro.free, %after.gro.conv
# |   call void @llvm.coro.end(ptr null, i1 false, token none)
# |   ret void
# | 
# | unreachable:                                      ; preds = %cleanup5, %cleanup
# |   unreachable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare token @llvm.coro.id(i32, ptr readnone, ptr readonly captures(none), ptr) #1
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare i1 @llvm.coro.alloc(token) #2
# | 
# | ; Function Attrs: nobuiltin allocsize(0)
# | declare noundef nonnull ptr @_Znwm(i64 noundef) #3
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare i64 @llvm.coro.size.i64() #2
# | 
# | ; Function Attrs: nounwind memory(argmem: readwrite)
# | declare ptr @llvm.coro.begin(token, ptr writeonly) #4
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.lifetime.start.p0(ptr captures(none)) #5
# | 
# | ; Function Attrs: mustprogress nounwind
# | define linkonce_odr void @_ZN4task12promise_type17get_return_objectEv(ptr dead_on_unwind noalias writable sret(%struct.task) align 8 %agg.result, ptr noundef nonnull align 1 dereferenceable(1) %this) #6 comdat align 2 {
# | entry:
# |   %result.ptr = alloca ptr, align 8
# |   %this.addr = alloca ptr, align 8
# |   %agg.tmp = alloca %"struct.std::coroutine_handle", align 8
# |   store ptr %agg.result, ptr %result.ptr, align 8
# |   store ptr %this, ptr %this.addr, align 8, !tbaa !7
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %call = call ptr @_ZNSt16coroutine_handleIN4task12promise_typeEE12from_promiseERS1_(ptr noundef nonnull align 1 dereferenceable(1) %this1)
# |   %coerce.dive = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %agg.tmp, i32 0, i32 0
# |   %coerce.dive2 = getelementptr inbounds nuw %"s
# | ...
# `---data was truncated (10240/31146) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt '-passes=default<O0>,default<O2>' -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=default<O0>,default<O2> -S
# |  #0 0x0000558f0cf0715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558f0cf040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558f0cf0789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9af2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9af278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9af2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9af271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f0ce9ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558f0ce9cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558f0ce81b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558f0cb310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558f0cb30dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9af271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9af271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9af271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f0cb30cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c (153 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7c458c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c7c45890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c7c458c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3714533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f371458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3714533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f371451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7c4521e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c7c4521c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c7c4506b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c7c41b60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c7c41b5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f371451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f371451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f371451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7c41b5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c (154 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function 
# | ...
# `---data was truncated (10240/22115) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c24f6de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c24f6db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c24f6de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4d641bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4d64725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4d641ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4d6403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c24f673e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c24f673c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c24f658b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c24f3080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c24f307dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe4d6404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4d64050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4d64050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c24f307cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c (155 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/427575) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005623bf11215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005623bf10f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005623bf11289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4111e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4111ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4111e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4111e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623bf0a7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005623bf0a7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005623bf08cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005623bed3c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005623bed3bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4111e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4111e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4111e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623bed3bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c (156 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605eea3115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005605eea2e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005605eea3189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee7d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee7d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee7d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee7d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605ee9c6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005605ee9c6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005605ee9abb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005605ee65b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005605ee65add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fee7d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee7d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee7d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605ee65acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c (157 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555682dc315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555682dc00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555682dc389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4955105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f495515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4955105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f49550ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555682d58e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555682d58c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555682d3db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005556829ed0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005556829ecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f49550eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49550ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49550ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556829eccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-vector-arith-ops.c (158 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-arith-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %add = add <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %add = add <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %add = add <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @add_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %add = add <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %add = add <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %add = add <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %add = add <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @add_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %add = add <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @add_f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %add = fadd <vscale x 8 x half> %0, %1
# |   ret <vscale x 8 x half> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @add_f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %b.addr, align 16
# |   %add = fadd <vscale x 4 x float> %0, %1
# |   ret <vscale x 4 x float> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @add_f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x double>, align 16
# |   %b.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %b.addr, align 16
# |   %add = fadd <vscale x 2 x double> %0, %1
# |   ret <vscale x 2 x double> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_inplace_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %add = add <vscale x 16 x i8> %1, %0
# |   store <vscale x 16 x i8> %add, ptr %a.addr, align 16
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_inplace_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %add = add <vscale x 8 x i16> %1, %0
# |   store <vscale x 8 x i16> %add, ptr %a.addr, align 16
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_inplace_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %add = add <vscale x 4 x i32> %1, %0
# |   store <vscale x 4 x i32> %add, ptr %a.addr, align 16
# |   ret <vscale x 4 x i32> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @add_inplace_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %add = add <vscale x 2 x i64> %1, %0
# |   store <vscale x 2 x i64> %add, ptr %a.addr, align 16
# |   ret <vscale x 2 x i64> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @add_inplace_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %add = add <vscale x 16 x i8> %1, %0
# |   store <vscale x 16 x i8> %add, ptr %a.addr, align 16
# |   ret <vscale x 16 x i8> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @add_inplace_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %add = add <vscale x 8 x i16> %1, %0
# |   store <vscale x 8 x i16> %add, ptr %a.addr, align 16
# |   ret <vscale x 8 x i16> %add
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @add_inplace_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <
# | ...
# `---data was truncated (10240/107144) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000563109dfc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563109df90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563109dfc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc679a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc679aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc679a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc679a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563109d91e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563109d91c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563109d76b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563109a260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563109a25dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc679a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc679a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc679a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563109a25cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c (159 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgeu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2fb42f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e2fb42c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e2fb42f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feaf8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feaf8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feaf8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feaf8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2fb3c4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e2fb3c4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e2fb3a9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e2fb0590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e2fb058dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feaf8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feaf8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feaf8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2fb058cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c (160 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16
# | ...
# `---data was truncated (10240/93458) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561fe87ee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561fe87eb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561fe87ee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa26a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa26a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa26a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa26a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561fe8783e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561fe8783c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561fe8768b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561fe84180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561fe8417dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa26a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa26a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa26a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561fe8417cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c (161 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_u32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_vnum_u32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i32>, ptr %1, i64 1
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_s32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_vnum_s32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x i32> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i32>, ptr %1, i64 1
# |   call void @llvm.aarch64.sve.st1wq.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_f32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x float> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1wq.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1wq.nxv4f32.p0(<vscale x 4 x float>, <vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1wq_vnum_f32(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 4 x float> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x float>, ptr %1, i64 1
# |   call void @llvm.aarch64.sve.st1wq.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_u64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_vnum_u64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i64>, ptr %1, i64 -8
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_s64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_vnum_s64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x i64> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %zt, ptr %zt.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %zt.addr, align 16
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 1 x i64>, ptr %1, i64 -8
# |   call void @llvm.aarch64.sve.st1dq.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 1 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1dq_f64(<vscale x 16 x i1> %pred, ptr noundef %base, <vscale x 2 x double> %zt) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x double> %zt, ptr %zt.addr
# | ...
# `---data was truncated (10240/12466) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005616df85115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005616df84e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005616df85189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d99133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d9918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d99133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d9911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616df7e6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005616df7e6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005616df7cbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005616df47b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005616df47add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6d9911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d9911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d9911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616df47acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c (162 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055682ec5c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055682ec590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055682ec5c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc058933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc05898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc058933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc05891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055682ebf1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055682ebf1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055682ebd6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055682e8860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055682e885dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc05891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc05891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc05891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055682e885cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c (163 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmsb_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.msb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.msb.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmsb_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.msb.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.msb.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmsb_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmsb_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.msb.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.msb.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmsb_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.msb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmsb_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.msb.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmsb_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/86847) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056150102515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005615010220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056150102589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b12e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b12ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b12e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b12e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561500fbae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561500fbac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561500f9fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561500c4f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561500c4edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4b12e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b12e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b12e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561500c4ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c (164 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d676b915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564d676b60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564d676b989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8fd2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8fd298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8fd2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8fd291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d6764ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564d6764ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564d67633b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564d672e30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564d672e2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8fd291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8fd291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8fd291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d672e2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c (165 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqadd_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqadd_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqadd_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqadd_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqadd_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqadd_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqadd_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqadd_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqadd_n_s8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqadd_n_s16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqadd_n_s32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %.splatinsert = insertelement <vscale x 4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <vscale x 4 x i32> %.splatinsert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %.splat)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqadd_n_s64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %.splatinsert = insertelement <vscale x 2 x i64> poison, i64 %1, i64 0
# |   %.splat = shufflevector <vscale x 2 x i64> %.splatinsert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %.splat)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_l
# | ...
# `---data was truncated (10240/13780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055eb774ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eb774a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eb774ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe49733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe4978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe49733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe4971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb77440e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eb77440c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eb77425b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eb770d50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eb770d4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efe4971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe4971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe4971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb770d4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c (166 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | decl
# | ...
# `---data was truncated (10240/20497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d9ab0a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556d9ab070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556d9ab0a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd62041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6204725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd62041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd620403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d9aa9fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556d9aa9fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556d9aa84b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556d9a7340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556d9a733dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd620404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6204050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6204050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d9a733cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c (167 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f3
# | ...
# `---data was truncated (10240/179503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056039339815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005603933950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056039339889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f17b7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17b76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f17b7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17b7631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056039332de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056039332dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560393312b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560392fc20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560392fc1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f17b7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17b76330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17b76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560392fc1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c (168 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-b16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-b16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_bf16(<vscale x 8 x bfloat> %acc, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %a.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %b.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %acc, ptr %acc.addr, align 16
# |   store <vscale x 8 x bfloat> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x bfloat> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %a.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %b.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmmla.nxv8bf16.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmmla.nxv8bf16.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16mm" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563691d5415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563691d510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563691d5489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00c4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00c4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00c4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00c4d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563691ce9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563691ce9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563691cceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056369197e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056369197ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f00c4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00c4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00c4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056369197dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c (169 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align
# | ...
# `---data was truncated (10240/39586) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eaa361115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eaa360e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eaa361189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08edd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08edd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08edd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08edd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eaa35a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eaa35a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eaa358bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eaa323b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eaa323add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f08edd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08edd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08edd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eaa323acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c (170 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabs_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabs_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabs_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabs_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabs_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabs_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabs_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabs_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabs_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabs_s16_x(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabs_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1
# | ...
# `---data was truncated (10240/20016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005636c23ee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005636c23eb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005636c23ee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f083ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f083caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f083ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f083ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636c2383e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005636c2383c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005636c2368b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005636c20180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005636c2017dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f083ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f083ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f083ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636c2017cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c (171 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055960dddf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055960dddc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055960dddf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff09733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff0978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff09733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff0971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055960dd74e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055960dd74c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055960dd59b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055960da090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055960da08dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007eff0971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff0971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff0971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055960da08cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c (172 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget2_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, 0
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget2_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, 1
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005636cb0e115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005636cb0de0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005636cb0e189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27ea449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27ea4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27ea449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27ea431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636cb076e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005636cb076c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005636cb05bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005636cad0b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005636cad0add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f27ea432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27ea4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27ea4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636cad0acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c (173 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslb(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslb_lane(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb.lane(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb.lane(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslt(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlslt_lane(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt.lane(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt.lane(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055cacd4fe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cacd4fb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cacd4fe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8c1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8c1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8c1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8c1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cacd493e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cacd493c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cacd478b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cacd1280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cacd127dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe8c1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8c1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8c1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cacd127cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c (174 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/306627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc1aa8315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bc1aa800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bc1aa8389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ac2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ac2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ac2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ac2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc1aa18e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bc1aa18c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bc1a9fdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bc1a6ad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bc1a6acdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8ac2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ac2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ac2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc1a6accc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c (175 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x 
# | ...
# `---data was truncated (10240/70013) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056055729f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056055729c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056055729f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb1dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb1dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb1dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb1dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560557234e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560557234c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560557219b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560556ec90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560556ec8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbb1dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb1dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb1dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560556ec8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c (176 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c52c0d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560c52c0a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560c52c0d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2570c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2570c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2570c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2570c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c52ba2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560c52ba2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560c52b87b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560c528370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560c52836dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2570c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2570c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2570c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c52836cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c (177 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dba368a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dba36870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dba368a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf9d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf9d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf9d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf9d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dba361fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dba361fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dba3604b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dba32b40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dba32b3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdf9d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf9d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf9d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dba32b3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c (178 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aecbd9b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aecbd980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aecbd9b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd773649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7736a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd773649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd773631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aecbd30e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aecbd30c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aecbd15b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aecb9c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aecb9c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd773632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7736330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7736330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aecb9c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c (179 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdot_f16(<4 x half> noundef %vd, <8 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <4 x half>, align 8
# |   %vd.addr = alloca <4 x half>, align 8
# |   %vn.addr = alloca <8 x i8>, align 8
# |   %vm.addr = alloca <8 x i8>, align 8
# |   %fpmr.addr = alloca i64, align 8
# |   store <4 x half> %vd, ptr %vd.addr, align 8
# |   store <8 x i8> %vn, ptr %vn.addr, align 8
# |   store <8 x i8> %vm, ptr %vm.addr, align 8
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <4 x half>, ptr %vd.addr, align 8
# |   %1 = load <8 x i8>, ptr %vn.addr, align 8
# |   %2 = load <8 x i8>, ptr %vm.addr, align 8
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %6 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2.i = bitcast <8 x i8> %4 to <4 x half>
# |   %fdot21.i = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.v4f16.v8i8(<4 x half> %fdot2.i, <8 x i8> %5, <8 x i8> %6)
# |   store <4 x half> %fdot21.i, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %8, ptr %__ret.i, align 8
# |   %9 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdotq_f16(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fdot21.i = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.v8f16.v16i8(<8 x half> %fdot2.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %fdot21.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdot_lane_f16(<4 x half> noundef %vd, <8 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %vd.addr = alloca <4 x half>, align 8
# |   %vn.addr = alloca <8 x i8>, align 8
# |   %vm.addr = alloca <8 x i8>, align 8
# |   %fpmr.addr = alloca i64, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %__s2 = alloca <8 x i8>, align 8
# |   %__s4 = alloca i64, align 8
# |   %ref.tmp = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %vd, ptr %vd.addr, align 8
# |   store <8 x i8> %vn, ptr %vn.addr, align 8
# |   store <8 x i8> %vm, ptr %vm.addr, align 8
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <4 x half>, ptr %vd.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %vn.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %vm.addr, align 8
# |   store <8 x i8> %2, ptr %__s2, align 8
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store i64 %3, ptr %__s4, align 8
# |   %4 = load <8 x i8>, ptr %__s0, align 8
# |   %5 = load <8 x i8>, ptr %__s1, align 8
# |   %6 = load <8 x i8>, ptr %__s2, align 8
# |   %7 = load i64, ptr %__s4, align 8
# |   %8 = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> %6, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2_lane = bitcast <8 x i8> %4 to <4 x half>
# |   %fdot2_lane1 = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> %fdot2_lane, <8 x i8> %5, <16 x i8> %8, i32 3)
# |   store <4 x half> %fdot2_lane1, ptr %ref.tmp, align 8
# |   %9 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %9, ptr %__ret, align 8
# |   %10 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %10, ptr %tmp, align 8
# |   %11 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8>, <8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half>, <8 x i8>, <16 x i8>, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdot_laneq_f16(<4 x half> noundef %vd, <8 x i8> %vn, <16 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %vd.addr = alloca <4 x half>, align 8
# |   %vn.addr = alloca <8 x i8>, align 8
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %__s2 = alloca <16 x i8>, align 16
# |   %__s4 = alloca i64, align 8
# |   %ref.tmp = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %vd, ptr %vd.addr, align 8
# |   store <8 x i8> %vn, ptr %vn.addr, align 8
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <4 x half>, ptr %vd.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %vn.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   store <16 x i8> %2, ptr %__s2, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store i64 %3, ptr %__s4, align 8
# |   %4 = load <8 x i8>, ptr %__s0, align 8
# |   %5 = load <8 x i8>, ptr %__s1, align 8
# |   %6 = load <16 x i8>, ptr %__s2, align 16
# |   %7 = load i64, ptr %__s4, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2_lane = bitcast <8 x i8> %4 to <4 x half>
# |   %fdot2_lane1 = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> %fdot2_lane, <8 x i8> %5, <16 x i8> %6, i32 7)
# |   store <4 x half> %fdot2_lane1, ptr %ref.tmp, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %8, ptr %__ret, align 8
# |   %9 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %9, ptr %tmp, align 8
# |   %10 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdotq_lane_f16(<8 x half> noundef %vd, <16 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 {
# | entry:
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <8 x i8>, align 8
# |   %fpmr.addr = alloca i64, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <16 x i8>, align 16
# |   %__s2 = alloca <8 x i8>, align 8
# |   %__s4 = alloca i64, align 8
# |   %ref.tmp = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <8 x i8> %vm, ptr %vm.addr, align 8
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   store <16 x i8> %1, ptr %__s1, align 16
# |   %2 = load <8 x i8>, ptr %vm.addr, align 8
# |   store <8 x i8> %2, ptr %__s2, align 8
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   store i64 %3, ptr %__s4, align 8
# |   %4 = load <16 x i8>, ptr %__s0, align 16
# |   %5 = load <16 x i8>, ptr %__s1, align 16
# |   %6 = load <8 x i8>, ptr %__s2, align 8
# |   %7 = load i64, ptr %__s4, align 8
# |   %8 = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> %6, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fdot2_lane = bitcast <16 x i8> %4 to <8 x half>
# |   %fdot2_lane1 = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half> %fdot2_lane, <16 x i8> %5, <16 x i8> %8, i32 3)
# |   store <8 x half> %fdot2_lane1, ptr %ref.tmp, align 16
# |   %9 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %9, ptr %__ret, align 16
# |   %10 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %10, ptr %tmp, align 16
# |   %11 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half>, <16 x i8>, <16 x i8>, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdotq_laneq_f16(<8 x half> noundef %vd, <16 x i8> %vn, <
# | ...
# `---data was truncated (10240/24508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x000055c48b6f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c48b6f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c48b6f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffaa9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffaa9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffaa9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffaa9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c48b68de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c48b68dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c48b672b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c48b3220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c48b321dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ffaa9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffaa9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffaa9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c48b321cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c (180 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, float noun
# | ...
# `---data was truncated (10240/25091) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559756c0015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559756bfd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559756c0089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f650f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f650f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f650f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f650f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559756b95e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559756b95c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559756b7ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055975682a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559756829dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f650f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f650f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f650f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559756829cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c (181 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za16_vg2x1(i32 noundef %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za16_vg2x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 15)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za16_vg2x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %4 = load i32, ptr %slice.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %11 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %11)
# |   call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 7)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za32_vg4x1(i32 noundef %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za32_vg4x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 15)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_lane_za32_vg4x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0
# | ...
# `---data was truncated (10240/39820) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055896176115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055896175e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055896176189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc506533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc50658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc506533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc50651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589616f6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005589616f6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005589616dbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055896138b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055896138add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc50651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc50651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc50651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055896138acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c (182 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055945bcd815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055945bcd50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055945bcd889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d9b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d9b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d9b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d9b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055945bc6de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055945bc6dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055945bc52b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055945b9020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055945b901dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4d9b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d9b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d9b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055945b901cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c (183 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlastb_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.lastb.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlastb_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lastb.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.lastb.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlastb_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lastb.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.lastb.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastb_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lastb.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastb.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlastb_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlastb_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lastb.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlastb_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lastb.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastb_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lastb.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svlastb_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.lastb.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare half @llvm.aarch64.sve.lastb.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svlastb_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.lastb.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.aarch64.sve.lastb.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svlastb_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.lastb.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare double @llvm.aarch64.sve.lastb.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local bfloat @test_svlastb_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call bfloat @llvm.aarch64.sve.lastb.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret bfloat %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willretur
# | ...
# `---data was truncated (10240/10821) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005611707b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005611707ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005611707b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ac5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ac5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ac5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ac5a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561170746e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561170746c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056117072bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005611703db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005611703dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7ac5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ac5a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ac5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611703dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c (184 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget4_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, 0
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget4_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, 1
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svget4_b_3(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, 3
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005555898e815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005555898e50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005555898e889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f714b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f714b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f714b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f714b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055558987de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055558987dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555589862b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005555895120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555589511dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f714b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f714b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f714b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555589511cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrev.c (185 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev32q_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev32q_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev32q_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x half> %0, <8 x half> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev64q_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev64q_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev64q_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev64q_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev64q_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x half> %0, <8 x half> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrev64q_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrev64q_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrev64q_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %0, i32 16, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %0, i32 16, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev32q_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vrev.predicated.v8f16.v8i1(<8 x half> %0, i32 32, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vrev.predicated.v8f16.v8i1(<8 x half>, i32, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |  
# | ...
# `---data was truncated (10240/29535) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dcb219d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dcb219a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dcb219d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c3a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c3a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c3a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c3a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dcb2132e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dcb2132c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dcb2117b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dcb1dc70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dcb1dc6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8c3a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c3a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c3a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dcb1dc6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c (186 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_s64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single2_u64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single4_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 1
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 2
# |   %9 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 3
# |   %10 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32 %4, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i32> %9, <vscale x 4 x i32> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svadd_write_single4_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i
# | ...
# `---data was truncated (10240/67892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000559e0fd6f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559e0fd6c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559e0fd6f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc8b9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8b9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc8b9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc8b9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e0fd04e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559e0fd04c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559e0fce9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559e0f9990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559e0f998dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc8b9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8b9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8b9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e0f998cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c (187 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0d8ff115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d0d8fee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d0d8ff189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7151d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7151d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7151d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7151d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0d8f86e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d0d8f86c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d0d8f6bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d0d8c1b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d0d8c1add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7151d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7151d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7151d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0d8c1acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c (188 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   %6 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %2, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_s64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single2_u64(i32 noundef %slice_base, <vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 1
# |   %6 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %2, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single4_s32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 1
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 2
# |   %9 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 3
# |   %10 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32 %4, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i32> %9, <vscale x 4 x i32> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsub_write_single4_u32(i32 noundef %slice_base, <vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i
# | ...
# `---data was truncated (10240/67892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055bee478e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bee478b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bee478e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f680aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f680aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f680aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f680aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bee4723e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bee4723c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bee4708b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bee43b80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bee43b7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f680aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f680aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f680aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bee43b7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c (189 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmls_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmls.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmls_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmls.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmls.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmls_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmls.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmls.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmls_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmls_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmls.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmls_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmls.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmls_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563f111c315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563f111c00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563f111c389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1869049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18690a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1869049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1869031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f11158e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563f11158c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563f1113db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563f10ded0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563f10decdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1869032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18690330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18690330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f10deccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c (190 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555db690215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555db68ff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555db690289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62daa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62daa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62daa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62daa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555db6897e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555db6897c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555db687cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555db652c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555db652bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f62daa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62daa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62daa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555db652bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c (191 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_sveor_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.eor.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.eor.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_sveor_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.eor.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.eor.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_sveor_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_sveor_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.eor.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.eor.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_sveor_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.eor.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_sveor_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.eor.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_sveor_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_sveor_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.eor.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_sveor_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055935a13115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055935a12e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055935a13189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1efcf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1efcf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1efcf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1efcf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055935a0c6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055935a0c6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055935a0abb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559359d5b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559359d5add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1efcf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1efcf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1efcf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559359d5acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c (192 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d     -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpaire_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 =
# | ...
# `---data was truncated (10240/125488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f0eb6a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557f0eb670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557f0eb6a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4153249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41532a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4153249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4153231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f0eaffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557f0eaffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557f0eae4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557f0e7940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557f0e793dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4153232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41532330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41532330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f0e793cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c (193 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 
# | ...
# `---data was truncated (10240/199596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b08686a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b0868670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b08686a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37a8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37a84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37a8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37a8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0867ffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b0867ffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b0867e4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b0864940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b086493dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f37a8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37a84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37a84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b086493cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c (194 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabd_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.sabd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sabd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabd_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sabd.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sabd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabd_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sabd.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sabd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabd_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sabd.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sabd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svabd_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.uabd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uabd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svabd_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uabd.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uabd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svabd_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.uabd.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uabd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svabd_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale
# | ...
# `---data was truncated (10240/74195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056520a43615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056520a4330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056520a43689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ee6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ee64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ee6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ee6431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056520a3cbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056520a3cbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056520a3b0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056520a0600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056520a05fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8ee6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ee64330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ee64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056520a05fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c (195 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# | 
# | ...
# `---data was truncated (10240/54488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560fcb83115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560fcb82e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560fcb83189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2132333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f213238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2132333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f213231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560fcb7c6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560fcb7c6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560fcb7abb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560fcb45b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560fcb45add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f213231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f213231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f213231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560fcb45acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c (196 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055588bb1415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055588bb110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055588bb1489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0dc3505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0dc355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0dc3505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0dc34ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055588baa9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055588baa9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055588ba8eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055588b73e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055588b73ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0dc34eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0dc34ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0dc34ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055588b73dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c (197 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c9a99315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562c9a9900f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562c9a99389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75be133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75be18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75be133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75be11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c9a928e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562c9a928c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562c9a90db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562c9a5bd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562c9a5bcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f75be11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75be11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75be11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c9a5bccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c (198 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_svzero_zt() #0 {
# | entry:
# |   call void @llvm.aarch64.sme.zero.zt(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.zero.zt(i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "aarch64_out_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055db3e7a215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055db3e79f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055db3e7a289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faccd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faccd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faccd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faccd231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db3e737e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055db3e737c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055db3e71cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055db3e3cc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055db3e3cbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faccd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faccd2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faccd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db3e3cbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c (199 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff
# | ...
# `---data was truncated (10240/18920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a0ae68c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a0ae6890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a0ae68c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7493649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74936a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7493649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7493631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0ae621e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a0ae621c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a0ae606b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a0ae2b60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a0ae2b5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7493632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74936330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74936330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0ae2b5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c (200 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.st1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.st1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_f16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv8f16.p0(<vscale x 8 x half> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv8f16.p0(<vscale x 8 x half>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1_f32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x float> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4f32.p0(<vscale x 4 x float>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind
# | ...
# `---data was truncated (10240/75656) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000559e1c74015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559e1c73d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559e1c74089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c8e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c8e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c8e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c8e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e1c6d5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559e1c6d5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559e1c6bab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559e1c36a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559e1c369dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7c8e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c8e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c8e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e1c369cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c (201 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintm_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintm_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintm_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintm_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintm_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintm_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintm_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintm.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintm_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintm_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintm.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056125238115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056125237e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056125238189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b3cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b3cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b3cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b3cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561252316e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561252316c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005612522fbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561251fab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561251faadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1b3cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b3cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b3cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561251faacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c (202 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556133f3f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556133f3c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556133f3f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c3e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c3e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c3e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c3e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556133ed4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556133ed4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556133eb9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556133b690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556133b68dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1c3e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c3e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c3e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556133b68cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c (203 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055877823e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055877823b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055877823e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0554b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0554b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0554b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0554b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587781d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005587781d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005587781b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558777e680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558777e67dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0554b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0554b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0554b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558777e67cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c (204 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_v
# | ...
# `---data was truncated (10240/253156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cb823a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557cb82370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557cb823a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d74133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d7418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d74133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d7411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cb81cfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557cb81cfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557cb81b4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557cb7e640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557cb7e63dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3d7411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d7411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d7411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cb7e63cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c (205 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/99851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055862882415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005586288210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055862882489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6ea705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6ea75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6ea705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6ea6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005586287b9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005586287b9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055862879eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055862844e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055862844ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc6ea6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6ea6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6ea6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055862844dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c (206 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @subscript_int16(<vscale x 8 x i16> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 8 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @subscript_uint16(<vscale x 8 x i16> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 8 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @subscript_int32(<vscale x 4 x i32> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 4 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @subscript_uint32(<vscale x 4 x i32> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 4 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @subscript_int64(<vscale x 2 x i64> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 2 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @subscript_uint64(<vscale x 2 x i64> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 2 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @subscript_float16(<vscale x 8 x half> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 8 x half> %0, i64 %1
# |   ret half %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @subscript_float32(<vscale x 4 x float> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 4 x float> %0, i64 %1
# |   ret float %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @subscript_float64(<vscale x 2 x double> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x double>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <vscale x 2 x double> %0, i64 %1
# |   ret double %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @subscript_write_float32(<vscale x 4 x float> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %b.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %vecins = insertelement <vscale x 4 x float> %1, float 1.000000e+00, i64 %0
# |   store <vscale x 4 x float> %vecins, ptr %a.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @subscript_read_write_float32(<vscale x 4 x float> %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %b.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %vecext = extractelement <vscale x 4 x float> %1, i64 %0
# |   %add = fadd float %vecext, 1.000000e+00
# |   %2 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %vecins = insertelement <vscale x 4 x float> %2, float %add, i64 %0
# |   store <vscale x 4 x float> %vecins, ptr %a.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055cd27f5715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cd27f540f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cd27f5789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8ad133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8ad18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8ad133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8ad11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd27eece2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cd27eecc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cd27ed1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cd27b810b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cd27b80dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd8ad11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8ad11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8ad11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd27b80cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c (207 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale 
# | ...
# `---data was truncated (10240/20131) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f8d0a9815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f8d0a950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f8d0a9889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f346db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f346db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f346db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f346db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f8d0a2de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f8d0a2dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f8d0a12b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f8d06c20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f8d06c1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f346db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f346db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f346db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8d06c1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c (208 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vget_v_u64m4x2_u64m4(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %src) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %src, ptr %src.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %src.addr, align 8
# |   %1 = call <vscale x 4 x i64> @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, i32 1)
# |   ret <vscale x 4 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vset_v_u64m4_u64m4x2(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %dest, <vscale x 4 x i64> %val) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %val.addr = alloca <vscale x 4 x i64>, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %dest, ptr %dest.addr, align 8
# |   store <vscale x 4 x i64> %val, ptr %val.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %dest.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %val.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, <vscale x 4 x i64> %1, i32 1)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), <vscale x 4 x i64>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7afcce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f7afccb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f7afcce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a27c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a27ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a27c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a27c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7afc63e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f7afc63c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f7afc48b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f7af8f80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f7af8f7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7a27c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a27c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a27c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7af8f7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c (209 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tu(<vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tu(<vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tu(<vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tum(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tum(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tum(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tumu(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align
# | ...
# `---data was truncated (10240/18311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a1a9d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558a1a9d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558a1a9d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83d4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83d4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83d4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83d4c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a1a969e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558a1a969c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558a1a94eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558a1a5fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558a1a5fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f83d4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83d4c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83d4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a1a5fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c (210 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056442979b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005644297980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056442979b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f121e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f121e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f121e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f121e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564429730e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564429730c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564429715b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005644293c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005644293c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f121e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f121e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f121e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644293c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c (211 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c070e215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563c070df0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563c070e289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4110333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f411038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4110333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f411031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c07077e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563c07077c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563c0705cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563c06d0c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563c06d0bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f411031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f411031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f411031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c06d0bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c (212 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1(<vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2(<vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4(<vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8(<vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_m(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_m(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_m(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_m(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfvfexpa,+xsfvfexpa64e,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexpa0p2_xsfvfexpa64e0p2"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604ca31015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005604ca30d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005604ca31089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f806ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f806aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f806ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f806ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604ca2a5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005604ca2a5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005604ca28ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005604c9f3a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005604c9f39dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f806ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f806ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f806ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604c9f39cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c (213 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svminnm_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fminnm.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fminnm.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svminnm_single_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svminnm_single_f32_x2(<vscale x 4 x float> %zdn.coerce0, <vscale x 4 x float> %zdn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zdn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %5)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svminnm_single_f64_x2(<vscale x 2 x double> %zdn.coerce0, <vscale x 2 x double> %zdn.coerce1, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %zdn.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 1
# |   %5 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64(<vscale x 2 x double> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %5)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svminnm_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fminnm.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/50311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055763b1f415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055763b1f10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055763b1f489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f062f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f062f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f062f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f062f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055763b189e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055763b189c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055763b16eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055763ae1e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055763ae1ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f062f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f062f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f062f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055763ae1dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c (214 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f8e55915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562f8e5560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562f8e55989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1f4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1f438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1f4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1f431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f8e4eee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562f8e4eec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562f8e4d3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562f8e1830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562f8e182dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff1f431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1f431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1f431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f8e182cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c (215 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a97c06815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a97c0650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a97c06889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6583533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f658358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6583533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f658351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a97bffde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a97bffdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a97bfe2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a97bc920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a97bc91dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f658351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f658351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f658351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a97bc91cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c (216 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextb_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextb_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.uxtb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uxtb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextb_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextb_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uxtb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.sxtb.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextb_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextb_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextb_u16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.ad
# | ...
# `---data was truncated (10240/17434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a2e76aa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a2e76a70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a2e76aa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9ba333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9ba38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9ba333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9ba31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2e763fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a2e763fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a2e7624b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a2e72d40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a2e72d3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd9ba31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9ba31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9ba31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2e72d3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c (217 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrdffr() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr()
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrdffr_z(<vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005650bd97815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005650bd9750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005650bd97889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5703e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5703e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5703e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5703e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650bd90de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005650bd90dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005650bd8f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005650bd5a20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005650bd5a1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5703e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5703e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5703e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650bd5a1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c (218 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmax_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564017a6e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564017a6b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564017a6e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f4b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f4b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f4b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f4b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564017a03e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564017a03c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005640179e8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005640176980b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564017697dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8f4b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f4b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f4b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564017697cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing: 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c (219 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.smop4a.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x2_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.smop4s.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.umop4a.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x2_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   call void @llvm.aarch64.sme.umop4s.wide.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %
# | ...
# `---data was truncated (10240/74176) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557107ec215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557107ebf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557107ec289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29faf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29faf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29faf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29faf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557107e57e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557107e57c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557107e3cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557107aec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557107aebdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f29faf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29faf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29faf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557107aebcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c (220 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmla_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mla.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mla.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmla_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mla.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mla.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmla_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmla_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.mla.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mla.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmla_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mla.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmla_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mla.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmla_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/92910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557f4264b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557f426480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557f4264b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbfae105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbfae15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbfae105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbfae0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f425e0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557f425e0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557f425c5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557f422750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557f42274dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbfae0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbfae0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbfae0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f42274cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c (221 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svmov_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005651ecb6915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005651ecb660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005651ecb6989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33edf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33edf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33edf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33edeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651ecafee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005651ecafec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005651ecae3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005651ec7930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005651ec792dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f33edeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33edeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33edeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651ec792cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c (222 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x2_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.udot.za32.vg1x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.udot.za32.vg1x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x4_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zn.coerce2, <vscale x 8 x i16> %zn.coerce3, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1, <vscale x 8 x i16> %zm.coerce2, <vscale x 8 x i16> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zn.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %zm.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 0
# |   %11 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 1
# |   %12 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 2
# |   %13 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9, 3
# |   %14 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 0
# |   %16 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 1
# |   %17 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 2
# |   %18 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %14, 3
# |   call void @llvm.aarch64.sme.udot.za32.vg1x4.nxv8i16(i32 %8, <vscale x 8 x i16> %10, <vscale x 8 x i16> %11, <vscale x 8 x i16> %12, <vscale x 8 x i16> %13, <vscale x 8 x i16> %15, <vscale x 8 x i16> %16, <vscale x 8 x i16> %17, <vscale x 8 x i16> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.udot.za32.vg1x4.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x2_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   call void @llvm.aarch64.sme.udot.za32.vg1x2.nxv16i8(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.udot.za32.vg1x2.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x4_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, <vscale x 16 x i8> %zm.coerce2, <vscale x 16 x i8> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align
# | ...
# `---data was truncated (10240/127452) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005603c962915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005603c96260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005603c962989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7224449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72244a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7224449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7224431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603c95bee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005603c95bec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005603c95a3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005603c92530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005603c9252dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7224432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72244330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72244330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603c9252cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c (223 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntd(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntd_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntd(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055dc16eab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dc16ea80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dc16eab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0c3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0c378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0c3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0c371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc16e40e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dc16e40c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dc16e25b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dc16ad50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dc16ad4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd0c371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0c371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0c371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc16ad4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c (224 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 1
# |   %8 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 1
# |   call void @llvm.aarch64.sme.fmlal.vg2x2.nxv8f16(i32 %4, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %9, <vscale x 8 x half> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlal.vg2x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_bf16(i32 noundef %slice_base, <vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 1
# |   %8 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 1
# |   call void @llvm.aarch64.sme.fmlal.vg2x2.nxv8bf16(i32 %4, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %9, <vscale x 8 x bfloat> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlal.vg2x2.nxv8bf16(i32, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.umlal.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umlal.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.smlal.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smlal.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla4
# | ...
# `---data was truncated (10240/73614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b2a66cc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b2a66c90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b2a66cc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf02b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf02b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf02b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf02b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2a6661e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b2a6661c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b2a6646b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b2a62f60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b2a62f5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdf02b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf02b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf02b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2a62f5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/minv.c (225 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/minv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svminv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.sminv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.sminv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svminv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.sminv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.sminv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svminv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.sminv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sminv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svminv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.sminv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sminv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svminv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svminv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svminv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svminv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svminv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fminv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fminv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svminv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fminv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fminv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svminv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fminv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fminv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attribute
# | ...
# `---data was truncated (10240/10818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x00005613a3f2d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005613a3f2a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005613a3f2d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f777d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f777d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f777d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f777d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613a3ec2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005613a3ec2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005613a3ea7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005613a3b570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005613a3b56dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f777d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f777d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f777d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613a3b56cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c (226 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4a.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x1_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4s.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4a.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x1_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4s.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4a.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4a.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_2x1_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4s.wide.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4s.wide.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za32_u8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <
# | ...
# `---data was truncated (10240/50499) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000558947bbf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558947bbc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558947bbf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc04fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc04fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc04fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc04fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558947b54e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558947b54c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558947b39b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005589477e90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005589477e8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc04fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc04fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc04fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589477e8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c (227 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9eb38a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f9eb3870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f9eb38a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b06a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b06aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b06a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b06a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9eb31fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f9eb31fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f9eb304b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f9eafb40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f9eafb3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2b06a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b06a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b06a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9eafb3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c (228 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e30dceb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e30dce80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e30dceb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9575e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9575ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9575e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9575e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e30dc80e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e30dc80c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e30dc65b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e30d9150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e30d914dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9575e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9575e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9575e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e30d914cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c (229 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558a837315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005558a83700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005558a837389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c5781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c578725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c5781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c57803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558a8308e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005558a8308c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005558a82edb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005558a7f9d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005558a7f9cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4c57804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c578050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c578050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558a7f9ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c (230 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056365864615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005636586430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056365864689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e7661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e766725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e7661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e76603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636585dbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005636585dbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005636585c0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005636582700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056365826fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6e76604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e766050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e766050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056365826fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c (231 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2, i32 90)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_z_1(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2, i32 270)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcadd_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fcadd.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2, i32 90)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fcadd.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcadd_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fcadd.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2, i32 90)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fcadd.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 90)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcadd_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fcadd.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i32 90)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcadd_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fcadd.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2, i32 90)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcadd_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fcadd.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 90)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcadd_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.ad
# | ...
# `---data was truncated (10240/12234) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562abbbcc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562abbbc90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562abbbcc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5b4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5b4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5b4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5b4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562abbb61e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562abbb61c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562abbb46b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562abb7f60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562abb7f5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd5b4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5b4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5b4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562abb7f5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c (232 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2q_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2q_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2q_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2q_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2q_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2q_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2q_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2q_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svld2q_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2q.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2q.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svld2q_bf16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld2q.sret.nxv8bf16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld2q.sret.nxv8bf16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svld2q_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld2q.sret.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | d
# | ...
# `---data was truncated (10240/75038) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000561b5533e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561b5533b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561b5533e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4004933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f400498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4004933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f400491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b552d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561b552d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561b552b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561b54f680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561b54f67dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f400491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f400491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f400491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b54f67cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c (233 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566a734e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005566a734b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005566a734e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce26133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce2618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce26133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce2611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566a72e3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005566a72e3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005566a72c8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005566a6f780b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005566a6f77dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fce2611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce2611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce2611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566a6f77cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c (234 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055781515f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055781515c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055781515f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b87449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b874a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b87449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b87431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578150f4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005578150f4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005578150d9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557814d890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557814d88dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0b87432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b874330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b874330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557814d88cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c (235 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dcd01f715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dcd01f40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dcd01f789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d68c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d68ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d68c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d68c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dcd018ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dcd018cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dcd0171b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dccfe210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dccfe20dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5d68c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d68c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d68c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dccfe20cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c (236 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e30eea715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e30eea40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e30eea789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c87049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c870a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c87049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c87031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e30ee3ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e30ee3cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e30ee21b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e30ead10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e30ead0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7c87032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c870330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c870330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e30ead0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c (237 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtsmul_f16(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftsmul.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ftsmul.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtsmul_f32(<vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.ftsmul.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ftsmul.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtsmul_f64(<vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.ftsmul.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ftsmul.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b4dd00a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b4dd0070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b4dd00a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3c9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3c958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3c9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3c951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4dcf9fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b4dcf9fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b4dcf84b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b4dcc340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b4dcc33dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa3c951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3c951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3c951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4dcc33cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c (238 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vle.mask.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.mask.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.mask.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.mask.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vle.mask.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.mask.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>,
# | ...
# `---data was truncated (10240/11969) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a11c06d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a11c06a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a11c06d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c84133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c8418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c84133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c8411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a11c002e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a11c002c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a11bfe7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a11bc970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a11bc96dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7c8411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c8411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c8411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a11bc96cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c (239 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -O0    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=O0
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=O0
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @foo() #0 {
# | entry:
# |   %v_tuple = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @bar() #0 {
# | entry:
# |   %v_tuple = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple, align 4
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @baz(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple) #0 {
# | entry:
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @qux(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple) #0 {
# | entry:
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @quux(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple) #0 {
# | entry:
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %call = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @qux(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %call
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zicsr,+zve32x,+zvl32b" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055956cae115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055956cade0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055956cae189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd48d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd48d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd48d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd48d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055956ca76e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055956ca76c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055956ca5bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055956c70b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055956c70add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd48d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd48d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd48d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055956c70acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c (240 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret 
# | ...
# `---data was truncated (10240/50516) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e83bc8115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e83bc7e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e83bc8189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f946641bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94664725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f946641ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9466403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e83bc16e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e83bc16c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e83bbfbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e83b8ab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e83b8aadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9466404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94664050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94664050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e83b8aacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c (241 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget4_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget4_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %tuple.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 2
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget4_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale x 4 x i32> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %tuple.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget4_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2, <vscale x 2 x i64> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %tuple.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 3
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget4_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget4_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %tuple.coerce3) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %tuple.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.a
# | ...
# `---data was truncated (10240/28771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055dde15eb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dde15e80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dde15eb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd32505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd3255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd32505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd324ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dde1580e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dde1580c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dde1565b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dde12150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dde1214dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efd324eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd324ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd324ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dde1214cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c (242 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558dcbbce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558dcbbcb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558dcbbce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb12449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb124a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb12449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb12431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558dcbb63e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558dcbb63c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558dcbb48b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558dcb7f80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558dcb7f7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbb12432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb124330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb124330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558dcb7f7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c (243 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfneg_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfneg_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, al
# | ...
# `---data was truncated (10240/30861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c6cf5215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560c6cf4f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560c6cf5289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b58b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b58b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b58b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b58aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c6cee7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560c6cee7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560c6ceccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560c6cb7c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560c6cb7bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8b58aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b58aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b58aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c6cb7bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c (244 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store tar
# | ...
# `---data was truncated (10240/30818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056011afc515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056011afc20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056011afc589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c9c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c9c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c9c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c9c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056011af5ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056011af5ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056011af3fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056011abef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056011abeedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8c9c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c9c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c9c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056011abeecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm-neon-shifts.c (245 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-shifts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin    -disable-O0-optnone    -target-cpu cortex-a8    -ffreestanding    -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -disable-O0-optnone -target-cpu cortex-a8 -ffreestanding -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c"
# | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "thumbv7-apple-darwin"
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vshr(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = lshr <8 x i8> %1, splat (i8 5)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vshr_smax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = ashr <8 x i8> %1, splat (i8 7)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vshr_umax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   store <8 x i8> zeroinitializer, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vsra(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = lshr <8 x i8> %3, splat (i8 5)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vsra_smax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = ashr <8 x i8> %3, splat (i8 7)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_shift_vsra_umax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = add <8 x i8> %2, zeroinitializer
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a8" "target-features"="+armv7-a,+d32,+dsp,+fp64,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp" }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"apcs-gnu"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7f420e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e7f420b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e7f420e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb66e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb66ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb66e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb66e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7f41a3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e7f41a3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e7f4188b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e7f3e380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e7f3e37dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbb66e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb66e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb66e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7f3e37cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c (246 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %2, <vscale x 2 x i64> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmplt_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c723b3815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c723b350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c723b3889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f717a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f717a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f717a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f717a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c723acde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c723acdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c723ab2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c7237620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c723761dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f717a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f717a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f717a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c723761cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c (247 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/40852) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d70b6315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557d70b600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557d70b6389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e34b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e34b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e34b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e34b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d70af8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557d70af8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557d70addb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557d7078d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557d7078cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4e34b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e34b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e34b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d7078ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c (248 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf4_bf16(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf2_bf16(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m1_bf16(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m2_bf16(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m4_bf16(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv16bf16(<vscale x 16 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv16bf16(<vscale x 16 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m8_bf16(<vscale x 32 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv32bf16(<vscale x 32 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv32bf16(<vscale x 32 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad2cead15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ad2ceaa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ad2cead89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc4e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc4e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc4e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc4e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad2ce42e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ad2ce42c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ad2ce27b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ad2cad70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ad2cad6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbc4e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc4e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc4e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad2cad6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c (249 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055772c8fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055772c8f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055772c8fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7476b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7476b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7476b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7476b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055772c891e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055772c891c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055772c876b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055772c5260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055772c525dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7476b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7476b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7476b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055772c525cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c (250 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vscale x 2 
# | ...
# `---data was truncated (10240/59595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c959ca415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c959ca10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c959ca489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33e7d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33e7d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33e7d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33e7ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c959c39e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c959c39c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c959c1eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c9598ce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c9598cddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f33e7ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33e7cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33e7cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9598cdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/store.c (251 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/store.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float64x1x2_t = type { [2 x <1 x double>] }
# | %struct.float64x1x3_t = type { [3 x <1 x double>] }
# | %struct.float64x1x4_t = type { [4 x <1 x double>] }
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.poly64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.poly64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.float64x2x2_t = type { [2 x <2 x double>] }
# | %struct.float64x2x3_t = type { [3 x <2 x double>] }
# | %struct.float64x2x4_t = type { [4 x <2 x double>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.poly64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.poly64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16(ptr noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x half>
# |   store <4 x half> %3, ptr %1, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f32(ptr noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %__s1 = alloca <2 x float>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <2 x float>
# |   store <2 x float> %3, ptr %1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f64(ptr noundef %a, <1 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   %0 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x double>
# |   store <1 x double> %3, ptr %1, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_mf8(ptr noundef %a, <8 x i8> %val) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %val.addr = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <8 x i8> %val, ptr %val.addr, align 8
# |   %0 = load <8 x i8>, ptr %val.addr, align 8
# |   store <8 x i8> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   store <8 x i8> %2, ptr %1, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_p16(ptr noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %__s1 = alloca <4 x i16>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x i16>
# |   store <4 x i16> %3, ptr %1, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_p64(ptr noundef %ptr, <1 x i64> noundef %val) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store <1 x i64> %val, ptr %val.addr, align 8
# |   %0 = load <1 x i64>, ptr %val.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %ptr.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   store <1 x i64> %3, ptr %1, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_p8(ptr noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   store <8 x i8> %2, ptr %1, align 1
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1q_f16(ptr noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x half>
# |   store <8 x half> %3, ptr %1, align 2
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1q_f32(ptr noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <4 x float>, align 16
# |   %__s1 = alloca <4 x float>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <4 x float>
# |   store <4 x float> %3, ptr %1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1q_f64(ptr noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x double>, align 16
# |   %__s1 = alloca <2 x double>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr
# | ...
# `---data was truncated (10240/446007) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x00005572a153b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005572a15380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005572a153b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e25f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e25f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e25f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e25f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572a14d0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005572a14d0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005572a14b5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005572a11650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005572a1164dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4e25f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e25f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e25f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572a1164cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c (252 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmaxnm_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svmaxnm_single_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svmaxnm_single_f32_x2(<vscale x 4 x float> %zdn.coerce0, <vscale x 4 x float> %zdn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zdn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %5)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svmaxnm_single_f64_x2(<vscale x 2 x double> %zdn.coerce0, <vscale x 2 x double> %zdn.coerce1, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %zdn.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 1
# |   %5 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64(<vscale x 2 x double> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %5)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmaxnm_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmaxnm.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/50311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005627e907b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005627e90780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005627e907b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6408733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f640878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6408733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f640871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627e9010e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005627e9010c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005627e8ff5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005627e8ca50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005627e8ca4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f640871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f640871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f640871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627e8ca4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vector-shift-ops.c (253 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-shift-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @rshift_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @rshift_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @lshift_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @rshift_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @lshift_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @rshift_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @lshift_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @rshift_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @lshift_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @rshift_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @lshift_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @rshift_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shr = ashr <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @lshift_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shl = shl <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @rshift_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %shr = lshr <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %shr
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_i8_rsplat(<vscale x 16 x i8> %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load i8, ptr %b.addr, align 1
# |   %splat.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %1, i64 0
# |   %splat.splat = shufflevector <vscale x 16 x i8> %splat.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %shl = shl <vscale x 16 x i8> %0, %splat.splat
# |   ret <vscale x 16 x i8> %shl
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @lshift_i8_lsplat(<vscale x 16 x i8> %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i8, ptr %b.addr, align 1
# |   %splat.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %0, i64 0
# |   %splat.splat
# | ...
# `---data was truncated (10240/32491) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000056276e94615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056276e9430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056276e94689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c80f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c80f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c80f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c80eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056276e8dbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056276e8dbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056276e8c0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056276e5700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056276e56fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2c80eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c80eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c80eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056276e56fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c (254 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b3096c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556b309690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556b3096c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5cb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5cb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5cb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5cb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b30901e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556b30901c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556b308e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556b305960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556b30595dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc5cb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5cb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5cb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b30595cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c (255 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_n_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdot_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdot_n_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdot_lane_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdot_lane_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8dot2,+fp8dot4,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a1abbc815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a1abbc50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a1abbc889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3914933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f391498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3914933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f391491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1abb5de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a1abb5dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a1abb42b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a1ab7f20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a1ab7f1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f391491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f391491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f391491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1ab7f1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c (256 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624b7f8a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005624b7f870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005624b7f8a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0957333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f095738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0957333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f095731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624b7f1fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005624b7f1fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005624b7f04b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005624b7bb40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005624b7bb3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f095731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f095731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f095731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624b7bb3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c (257 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea176b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ea176b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ea176b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa81c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa81c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa81c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa81c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea1764be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ea1764bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ea17630b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ea172e00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ea172dfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa81c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa81c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa81c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea172dfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c (258 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/52599) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa7173215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fa7172f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fa7173289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88f9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88f998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88f9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88f991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa716c7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fa716c7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fa716acb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fa7135c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fa7135bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f88f991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88f991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88f991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa7135bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c (259 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.hsub.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.hsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8> %0, <16 x i8> %.splat, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 x i
# | ...
# `---data was truncated (10240/14644) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b0767715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557b076740f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557b0767789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4172a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4172aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4172a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4172a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b0760ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557b0760cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557b075f1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557b072a10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557b072a0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4172a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4172a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4172a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b072a0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c (260 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i16 @subscript_int16(<vscale x 8 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i16 @subscript_uint16(<vscale x 8 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i32 @subscript_int32(<vscale x 4 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i32 @subscript_uint32(<vscale x 4 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_int64(<vscale x 2 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_uint64(<vscale x 2 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local half @subscript_float16(<vscale x 8 x half> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x half>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> %a.coerce, i64 0)
# |   store <32 x half> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x half>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x half> %0, i64 %1
# |   ret half %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local float @subscript_float32(<vscale x 4 x float> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x float>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> %a.coerce, i64 0)
# |   store <16 x float> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x float>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x float> %0, i64 %1
# |   ret float %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local double @subscript_float64(<vscale x 2 x double> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x double>, align 16
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> %a.coerce, i64 0)
# |   store <8 x double> %a, ptr %a.addr, align 16
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x double>, ptr %a.addr, align 16
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x double> %0, i64 %1
# |   ret double %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double>, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,4) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055a7139d715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a7139d40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a7139d789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7fdb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7fdb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7fdb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7fdb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a71396ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a71396cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a713951b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a7136010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a713600dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd7fdb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7fdb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7fdb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a713600cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c (261 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b8() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b16() #0 {
# | entry:
# |   %0 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b32() #0 {
# | entry:
# |   %0 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_b64() #0 {
# | entry:
# |   %0 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 0)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_1() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 1)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_2() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 2)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_3() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 3)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_4() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 4)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_5() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 5)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_6() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 6)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_7() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 7)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_8() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 8)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_9() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 9)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_10() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 10)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_11() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_12() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 12)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_13() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 13)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_14() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 29)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_15() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 30)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b8_16() #0 {
# | entry:
# |   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
# |   ret <vscale x 16 x i1> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b16() #0 {
# | entry:
# |   %0 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 0)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b32() #0 {
# | entry:
# |   %0 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 1)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svptrue_pat_b64() #0 {
# | entry:
# |   %0 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 2)
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005555bfc1f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005555bfc1c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005555bfc1f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0262b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0262b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0262b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0262b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555bfbb4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005555bfbb4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005555bfb99b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005555bf8490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005555bf848dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0262b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0262b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0262b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555bf848cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/2005-09-24-AsmUserPrefix.c (262 of 27911)
******************** TEST 'Clang :: CodeGen/2005-09-24-AsmUserPrefix.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 | llc |     not grep _foo2
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @bar() #0 {
# | entry:
# |   call void @foo2()
# |   ret void
# | }
# | 
# | declare void @foo2() #1
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3
# |  #0 0x00005595f7cd715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005595f7cd40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005595f7cd789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3bb7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3bb7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3bb7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3bb7b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595f7c6ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005595f7c6cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005595f7c51b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005595f79010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005595f7900dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3bb7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3bb7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3bb7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595f7900cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: llc
# executed command: not grep _foo2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c (263 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdech.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdech.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdech.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdech.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdech.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 10, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdech.n64(i64 %0, i32 11, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdech_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %0, i32 12, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdech_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %0, i32 13, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_pat_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16> %0, i32 29, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqdech_pat_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %0, i32 30, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005606c4a8415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005606c4a810f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005606c4a8489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e19533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e1958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e19533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e1951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606c4a19e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005606c4a19c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005606c49feb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005606c46ae0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005606c46addd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3e1951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e1951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e1951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606c46adcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c (264 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, al
# | ...
# `---data was truncated (10240/12389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055945eabd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055945eaba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055945eabd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1943f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1943f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1943f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1943f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055945ea52e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055945ea52c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055945ea37b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055945e6e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055945e6e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1943f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1943f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1943f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055945e6e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/recps.c (265 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/recps.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecps_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.frecps.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frecps.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecps_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.frecps.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frecps.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecps_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.frecps.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frecps.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055e38fbfc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e38fbf90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e38fbfc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff374333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff37438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff374333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff37431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e38fb91e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e38fb91c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e38fb76b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e38f8260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e38f825dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff37431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff37431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff37431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e38f825cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c (266 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/12235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607930ad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005607930aa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005607930ad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdfe8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdfe8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdfe8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdfe8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560793042e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560793042c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560793027b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560792cd70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560792cd6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdfe8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdfe8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdfe8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560792cd6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c (267 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #
# | ...
# `---data was truncated (10240/12075) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9f08bc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a9f08b90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a9f08bc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5cb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5cb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5cb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5cb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9f0851e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a9f0851c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a9f0836b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a9f04e60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a9f04e5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa5cb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5cb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5cb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9f04e5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c (268 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmax_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smax.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smax.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmax_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smax.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smax.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svmax_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smax.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smax.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svmax_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smax.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smax.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmax_single_u8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umax.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umax.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmax_single_u16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umax.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umax.single.x
# | ...
# `---data was truncated (10240/142195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055cc23f1f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cc23f1c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cc23f1f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0873333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f087338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0873333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f087331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc23eb4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cc23eb4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cc23e99b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cc23b490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cc23b48dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f087331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f087331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f087331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc23b48cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c (269 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_u8_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x half> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_bf16(<vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x float> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_mf8_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x double> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_u16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_u32_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svreinterpret_s64_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svreinterpret_u64_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svreinterpret_f16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svreinterpret_bf16_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svreinterpret_f32_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x float>
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svreinterpret_f64_mf8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 t
# | ...
# `---data was truncated (10240/168193) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# |  #0 0x0000556cc8f4215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556cc8f3f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556cc8f4289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45aed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45aed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45aed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45aed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556cc8ed7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556cc8ed7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556cc8ebcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556cc8b6c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556cc8b6bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f45aed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45aed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45aed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556cc8b6bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c (270 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti4_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti4_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti4_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000559ef2fe215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559ef2fdf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559ef2fe289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa7f7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7f78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa7f7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa7f7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ef2f77e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559ef2f77c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559ef2f5cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559ef2c0c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559ef2c0bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa7f7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7f78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7f78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ef2c0bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c (271 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_i16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.
# | ...
# `---data was truncated (10240/16654) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb4c12d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eb4c12a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eb4c12d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9abe449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9abe4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9abe449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9abe431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb4c0c2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eb4c0c2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eb4c0a7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eb4bd570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eb4bd56dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9abe432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9abe4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9abe4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb4bd56cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c (272 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevb_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevb_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevb_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrevb_u16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevb_u32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |  
# | ...
# `---data was truncated (10240/16804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e05888615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e0588830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e05888689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4dbec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4dbeca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4dbec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4dbec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e05881be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e05881bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e058800b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e0584b00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e0584afdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4dbec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4dbec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4dbec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0584afcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll (273 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 8
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll >/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/supports-hot-cold-new.ll.tmp.o
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll
# |  #0 0x000055f02cea115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f02ce9e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f02cea189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f346b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f346b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f346b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f346b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f02ce36e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f02ce36c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f02ce1bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f02cacb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f02cacadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f346b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f346b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f346b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f02cacacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c (274 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628e9d2315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005628e9d200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005628e9d2389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4aa121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4aa12725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4aa121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4aa1203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628e9cb8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005628e9cb8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005628e9c9db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005628e994d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005628e994cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4aa1204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4aa12050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4aa12050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628e994ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c (275 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +faminmax -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +faminmax -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svamax_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 1
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famax.x2.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famax.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svamax_f32_x2(<vscale x 4 x float> %zdn.coerce0, <vscale x 4 x float> %zdn.coerce1, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zdn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %7, 0
# |   %9 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %7, 1
# |   %10 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.famax.x2.nxv4f32(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %8, <vscale x 4 x float> %9)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.famax.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svamax_f64_x2(<vscale x 2 x double> %zdn.coerce0, <vscale x 2 x double> %zdn.coerce1, <vscale x 2 x double> %zm.coerce0, <vscale x 2 x double> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %zm.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %zdn.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, <vscale x 2 x double> %zm.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zm, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %4, 1
# |   %7 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %7, 0
# |   %9 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %7, 1
# |   %10 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.famax.x2.nxv2f64(<vscale x 2 x double> %5, <vscale x 2 x double> %6, <vscale x 2 x double> %8, <vscale x 2 x double> %9)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.famax.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svamin_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 1
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famin.x2.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famin.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8
# | ...
# `---data was truncated (10240/45703) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005626b5c7615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005626b5c730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005626b5c7689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe957733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe95778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe957733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe95771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626b5c0be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005626b5c0bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005626b5bf0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005626b58a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005626b589fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe95771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe95771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe95771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626b589fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c (276 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrh_u32base_s32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrh_u64base_s64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrh_u32base_u32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrh_u64base_u64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b38783515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b3878320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b38783589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb73933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb7398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb73933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb7391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3877cae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b3877cac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b3877afb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b38745f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b38745edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ffb7391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb7391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb7391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b38745ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c (277 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f4c6bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555f4c6ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555f4c6bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9791049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97910a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9791049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9791031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f4c652e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555f4c652c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555f4c637b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555f4c2e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555f4c2e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9791032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97910330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97910330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f4c2e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c (278 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_ver_za8_u8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 immarg, i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_ver_za8_s8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_ver_za8_mf8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_u8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 immarg, i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_s8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_mf8_vg2(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %2 = load i32, ptr %base.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrite_hor_za8_u8_vg4(i32 noundef %base, <vscale x 16 x i8> %val.coerce0, <vscale x 16 x i8> %val.coerce1, <vscale x 16 x i8> %val.coerce2, <vscale x 16 x i8> %val.coerce3) #0 {
# | entry:
# |   %val = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %base.addr = alloca i32, align 4
# |   %val.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %val.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %val.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %val.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %val.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %val, align 16
# |   %val1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val, align 16
# |   store i32 %base, ptr %base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %val1, ptr %val.addr, align 16
# |   %4 = load i32, ptr %base.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %val.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale
# | ...
# `---data was truncated (10240/150970) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000563606bfe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563606bfb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563606bfe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01a9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01a9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01a9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01a9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563606b93e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563606b93c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563606b78b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005636068280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563606827dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f01a9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01a9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01a9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563606827cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c (279 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsleu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587c8a8e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005587c8a8b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005587c8a8e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6590049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65900a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6590049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6590031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587c8a23e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005587c8a23c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005587c8a08b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005587c86b80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005587c86b7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6590032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65900330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65900330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587c86b7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c (280 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_s16_x2(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x2.nxv8i16(<vscale x 16 x i8> %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sunpk.x2.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svunpk_u16_x2(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x2.nxv8i16(<vscale x 16 x i8> %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uunpk.x2.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_s32_x2(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x2.nxv4i32(<vscale x 8 x i16> %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sunpk.x2.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svunpk_u32_x2(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x2.nxv4i32(<vscale x 8 x i16> %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uunpk.x2.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_s64_x2(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x2.nxv2i64(<vscale x 4 x i32> %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sunpk.x2.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svunpk_u64_x2(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x2.nxv2i64(<vscale x 4 x i32> %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uunpk.x2.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055fec499615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fec49930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fec499689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f68c2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68c26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f68c2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68c2631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fec492be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fec492bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fec4910b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fec45c00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fec45bfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f68c2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68c26330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68c26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fec45bfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c (281 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_s8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_u8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.sumop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sumop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_u8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmop4a.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.usmop4a.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_u8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmop4s.wide.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.usmop4s.wide.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_s16_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4a.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_s16_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_u16_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4a.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4s_1x1_za32_u16_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv8i16(i32 1, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umop4s.wide.1x1.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_f16_f16(
# | ...
# `---data was truncated (10240/27272) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000563a7142115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563a7141e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563a7142189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75b6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75b678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75b6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75b671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a713b6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563a713b6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563a7139bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563a7104b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563a7104add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f75b671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75b671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75b671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a7104acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm-mve-intrinsics/absneg.c (282 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/absneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vabsq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabsq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = icmp slt <16 x i8> %0, zeroinitializer
# |   %2 = sub <16 x i8> zeroinitializer, %0
# |   %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabsq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = icmp slt <8 x i16> %0, zeroinitializer
# |   %2 = sub <8 x i16> zeroinitializer, %0
# |   %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabsq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = icmp slt <4 x i32> %0, zeroinitializer
# |   %2 = sub <4 x i32> zeroinitializer, %0
# |   %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = xor <16 x i8> %0, splat (i8 -1)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = xor <8 x i16> %0, splat (i16 -1)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = xor <4 x i32> %0, splat (i32 -1)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = xor <16 x i8> %0, splat (i8 -1)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = xor <8 x i16> %0, splat (i16 -1)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = xor <4 x i32> %0, splat (i32 -1)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_x_s8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = al
# | ...
# `---data was truncated (10240/40137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581d6aa215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005581d6a9f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005581d6aa289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f09d0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09d0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f09d0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f09d0e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581d6a37e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005581d6a37c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005581d6a1cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005581d66cc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005581d66cbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f09d0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09d0e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09d0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581d66cbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c (283 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0533e015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a0533dd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a0533e089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ba8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ba8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ba8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ba8f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a053375e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a053375c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a05335ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a05300a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a053009dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6ba8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ba8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ba8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a053009cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c (284 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_s32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64 %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b16(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64 %0, <vscale x 8 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b32(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64 %0, <vscale x 4 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_s64_b64(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64 %0, <vscale x 2 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincp_n_u32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincp_n_u64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/19010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ac6368015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ac6367d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ac6368089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23d2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23d2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23d2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23d2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac63615e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ac63615c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ac635fab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ac632aa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ac632a9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f23d2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23d2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23d2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac632a9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c (285 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmla_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmla.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmla_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmla.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmla.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmla_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmla.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmla.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmla_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmla_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmla.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmla_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmla.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmla_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005587aedd515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005587aedd20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005587aedd589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f664be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f664bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f664be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f664be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587aed6ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005587aed6ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005587aed4fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005587ae9ff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005587ae9fedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f664be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f664be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f664be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587ae9fecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c (286 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a1e76c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556a1e7690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556a1e76c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f566f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f566f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f566f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f566f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a1e701e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556a1e701c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556a1e6e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556a1e3960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556a1e395dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f566f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f566f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f566f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a1e395cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c (287 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bcb36715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559bcb3640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559bcb36789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6746849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67468a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6746849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6746831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bcb2fce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559bcb2fcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559bcb2e1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559bcaf910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559bcaf90dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6746832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67468330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67468330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bcaf90cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c (288 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtmad_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftmad.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ftmad.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtmad_f16_1(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftmad.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 7)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtmad_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.ftmad.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 0)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ftmad.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtmad_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.ftmad.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 0)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ftmad.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564ca2ba015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564ca2b9d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564ca2ba089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc25b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc25b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc25b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc25b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ca2b35e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564ca2b35c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564ca2b1ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564ca27ca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564ca27c9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc25b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc25b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc25b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ca27c9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c (289 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp2_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp2.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.uzp2.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp2_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp2.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005576ef8a515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005576ef8a20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005576ef8a589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb93321bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9332725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb93321ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb933203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576ef83ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005576ef83ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005576ef81fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005576ef4cf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005576ef4cedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb933204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9332050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9332050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576ef4cecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c (290 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnot_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnot_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnot_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnot_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnot_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnot_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnot_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnot_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnot_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnot_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnot_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x
# | ...
# `---data was truncated (10240/21349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000565497af315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000565497af00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000565497af389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4768f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4768f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4768f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4768f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565497a88e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565497a88c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565497a6db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056549771d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056549771cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4768f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4768f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4768f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056549771ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm_neon_intrinsics.c (291 of 27911)
******************** TEST 'Clang :: CodeGen/arm_neon_intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7s-apple-darwin -target-abi apcs-gnu  -target-cpu swift   -target-feature +fullfp16 -ffreestanding   -flax-vector-conversions=none   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7s-apple-darwin -target-abi apcs-gnu -target-cpu swift -target-feature +fullfp16 -ffreestanding -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c"
# | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "thumbv7s-apple-darwin"
# | 
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_vaba_s8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x i8>, align 8
# |   %__p1.addr.i2 = alloca <8 x i8>, align 8
# |   %__ret.i3 = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p0.addr.i1, align 8
# |   store <8 x i8> %5, ptr %__p1.addr.i2, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %vabd_v.i = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %6, <8 x i8> %7)
# |   store <8 x i8> %vabd_v.i, ptr %ref.tmp.i, align 8
# |   %8 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %8, ptr %__ret.i3, align 8
# |   %9 = load <8 x i8>, ptr %__ret.i3, align 8
# |   %add.i = add <8 x i8> %3, %9
# |   store <8 x i8> %add.i, ptr %__ret.i, align 8
# |   %10 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @test_vaba_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <4 x i16>, align 8
# |   %__p1.addr.i2 = alloca <4 x i16>, align 8
# |   %__ret.i3 = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %c.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   %2 = load <4 x i16>, ptr %c.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %5 = load <4 x i16>, ptr %__p2.addr.i, align 8
# |   store <4 x i16> %4, ptr %__p0.addr.i1, align 8
# |   store <4 x i16> %5, ptr %__p1.addr.i2, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %vabd_v.i = bitcast <8 x i8> %6 to <4 x i16>
# |   %vabd_v1.i = bitcast <8 x i8> %7 to <4 x i16>
# |   %vabd_v2.i = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %vabd_v.i, <4 x i16> %vabd_v1.i)
# |   %vabd_v3.i = bitcast <4 x i16> %vabd_v2.i to <8 x i8>
# |   store <8 x i8> %vabd_v3.i, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %8, ptr %__ret.i3, align 8
# |   %9 = load <4 x i16>, ptr %__ret.i3, align 8
# |   %add.i = add <4 x i16> %3, %9
# |   store <4 x i16> %add.i, ptr %__ret.i, align 8
# |   %10 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x i32> @test_vaba_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <2 x i32>, align 8
# |   %__p1.addr.i2 = alloca <2 x i32>, align 8
# |   %__ret.i3 = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %c.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <2 x i32> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   %2 = load <2 x i32>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   store <2 x i32> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %5 = load <2 x i32>, ptr %__p2.addr.i, align 8
# |   store <2 x i32> %4, ptr %__p0.addr.i1, align 8
# |   store <2 x i32> %5, ptr %__p1.addr.i2, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %vabd_v.i = bitcast <8 x i8> %6 to <2 x i32>
# |   %vabd_v1.i = bitcast <8 x i8> %7 to <2 x i32>
# |   %vabd_v2.i = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %vabd_v.i, <2 x i32> %vabd_v1.i)
# |   %vabd_v3.i = bitcast <2 x i32> %vabd_v2.i to <8 x i8>
# |   store <8 x i8> %vabd_v3.i, ptr %ref.tmp.i, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %8, ptr %__ret.i3, align 8
# |   %9 = load <2 x i32>, ptr %__ret.i3, align 8
# |   %add.i = add <2 x i32> %3, %9
# |   store <2 x i32> %add.i, ptr %__ret.i, align 8
# |   %10 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @test_vaba_u8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x i8>, align 8
# |   %__p1.addr.i2 = alloca <8 x i8>, align 8
# |   %__ret.i3 = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   store <8 x i8> %4, pt
# | ...
# `---data was truncated (10240/2159854) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055759284215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055759283f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055759284289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efcc7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efcc70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efcc7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efcc7031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575927d7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005575927d7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005575927bcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055759246c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055759246bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efcc7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efcc70330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efcc70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055759246bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp (292 of 27911)
******************** TEST 'Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @_Z9cond_boolu10__SVBool_tS_(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %cmp = icmp ult <vscale x 16 x i1> %0, %1
# |   %2 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %vector_select = select <vscale x 16 x i1> %cmp, <vscale x 16 x i1> %2, <vscale x 16 x i1> %3
# |   ret <vscale x 16 x i1> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @_Z7cond_i8u10__SVInt8_tS_(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   %2 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 16 x i8> %sext, zeroinitializer
# |   %vector_select = select <vscale x 16 x i1> %vector_cond, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3
# |   ret <vscale x 16 x i8> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @_Z7cond_u8u11__SVUint8_tS_(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   %2 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 16 x i8> %sext, zeroinitializer
# |   %vector_select = select <vscale x 16 x i1> %vector_cond, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3
# |   ret <vscale x 16 x i8> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @_Z8cond_i16u11__SVInt16_tS_(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   %2 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 8 x i16> %sext, zeroinitializer
# |   %vector_select = select <vscale x 8 x i1> %vector_cond, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3
# |   ret <vscale x 8 x i16> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @_Z8cond_u16u12__SVUint16_tS_(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   %2 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 8 x i16> %sext, zeroinitializer
# |   %vector_select = select <vscale x 8 x i1> %vector_cond, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3
# |   ret <vscale x 8 x i16> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @_Z8cond_i32u11__SVInt32_tS_(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   %2 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 4 x i32> %sext, zeroinitializer
# |   %vector_select = select <vscale x 4 x i1> %vector_cond, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3
# |   ret <vscale x 4 x i32> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @_Z8cond_u32u12__SVUint32_tS_(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   %2 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 4 x i32> %sext, zeroinitializer
# |   %vector_select = select <vscale x 4 x i1> %vector_cond, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3
# |   ret <vscale x 4 x i32> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @_Z8cond_i64u11__SVInt64_tS_(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp slt <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   %2 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 2 x i64> %sext, zeroinitializer
# |   %vector_select = select <vscale x 2 x i1> %vector_cond, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3
# |   ret <vscale x 2 x i64> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @_Z8cond_u64u12__SVUint64_tS_(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp ult <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   %2 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 2 x i64> %sext, zeroinitializer
# |   %vector_select = select <vscale x 2 x i1> %vector_cond, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3
# |   ret <vscale x 2 x i64> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @_Z8cond_f16u13__SVFloat16_tS_(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %cmp = fcmp olt <vscale x 8 x half> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   %2 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %vector_cond = icmp ne <vscale x 8 x i16> %sext, zeroinitializer
# |   %vector_select = select <vscale x 8 x i1> %vector_cond, <vscale x 8 x half> %2, <vscale x 8 x half> %3
# |   ret <vscale x 8 x half> %vector_select
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @_Z8cond_f32u13__SVFloat32_tS_(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %b.addr, align 16
# |   %cmp = fcmp olt <vscale x 4 x float> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   %2 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %3 = load <vs
# | ...
# `---data was truncated (10240/16444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005603fdeb915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005603fdeb60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005603fdeb989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89d1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89d16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89d1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89d1631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603fde4ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005603fde4ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005603fde33b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005603fdae30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005603fdae2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f89d1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89d16330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89d16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603fdae2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c (293 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/53678) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f0571b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556f057180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556f0571b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11ef333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11ef38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11ef333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11ef31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f056b0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556f056b0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556f05695b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556f053450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556f05344dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f11ef31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11ef31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11ef31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f05344cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c (294 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_s8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_u8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_mf8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svuzp_s16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svuzp_u16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svuzp_f16_x2(<vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.uzp.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.uzp.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svuzp_bf16_x2(<vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.uzp.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.uzp.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svuzp_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.c
# | ...
# `---data was truncated (10240/35785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557d7813f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557d7813c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557d7813f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3140649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31406a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3140649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3140631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d780d4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557d780d4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557d780b9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557d77d690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557d77d68dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3140632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31406330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31406330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d77d68cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c (295 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-tmop -target-feature +sme-f16f16 -target-feature +sme-f8f32 -target-feature +sme-b16b16 -target-feature +sme-f8f16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-tmop -target-feature +sme-f16f16 -target-feature +sme-f8f32 -target-feature +sme-b16b16 -target-feature +sme-f8f16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_s8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.stmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.stmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_u8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.utmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.utmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_s8_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.sutmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.sutmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_u8_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.ustmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.ustmopa.za32.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_s16_s16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %zk.addr, align 16
# |   call void @llvm.aarch64.sme.stmopa.za32.nxv8i16(i32 1, <vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.stmopa.za32.nxv8i16(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svtmopa_lane_za32_u16_u16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm, <vscale x 16 x i8> %zk) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %zk.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   store <vscale x 16 x i8> %zk, ptr %zk.addr, align 16
# |   %2 = load { <v
# | ...
# `---data was truncated (10240/25017) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055baadc2f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055baadc2c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055baadc2f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc2e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc2e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc2e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc2e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055baadbc4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055baadbc4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055baadba9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055baad8590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055baad858dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efc2e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc2e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc2e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055baad858cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c (296 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1uh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1uh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg,
# | ...
# `---data was truncated (10240/37388) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005652ae06315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005652ae0600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005652ae06389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a05705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a0575c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a05705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a056ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652adff8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005652adff8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005652adfddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005652adc8d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005652adc8cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7a056eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a056ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a056ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652adc8ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c (297 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnt_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnt_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnt_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnt_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcnt_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnt_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnt_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnt_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcnt_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcnt_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4f32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4f32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcnt_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2f64(<vscale x 2 x i64> zeroi
# | ...
# `---data was truncated (10240/32102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559c2a18115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559c2a17e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559c2a18189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6330249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63302a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6330249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6330231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c2a116e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559c2a116c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559c2a0fbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559c29dab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559c29daadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6330232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63302330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63302330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c29daacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c (298 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b16_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b32_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b64_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b16_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b32_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b64_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilelt_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/13340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e85428815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e8542850f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e85428889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5084505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f508455c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5084505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50844ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e85421de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e85421dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e854202b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e853eb20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e853eb1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f50844eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50844ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50844ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e853eb1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c (299 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005573fe2e415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005573fe2e10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005573fe2e489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa215d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa215d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa215d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa215ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573fe279e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005573fe279c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005573fe25eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005573fdf0e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005573fdf0ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa215ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa215cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa215cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573fdf0dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c (300 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svnot_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svnot_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svnot_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svnot_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svnot_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svnot_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svnot_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svnot_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.not.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svnot_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.not.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svnot_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.not.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svnot_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscal
# | ...
# `---data was truncated (10240/22149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562e2fef915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562e2fef60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562e2fef989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce6e705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce6e75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce6e705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce6e6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e2fe8ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562e2fe8ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562e2fe73b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562e2fb230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562e2fb22dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fce6e6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce6e6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce6e6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e2fb22cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c (301 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i1> @and_bool(<vscale x 16 x i1> noundef %0, <vscale x 16 x i1> noundef %1) #0 {
# | entry:
# |   %retval = alloca <8 x i8>, align 2
# |   %a.addr = alloca <8 x i8>, align 2
# |   %b.addr = alloca <8 x i8>, align 2
# |   %a.coerce = bitcast <vscale x 16 x i1> %0 to <vscale x 2 x i8>
# |   %a = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %a.coerce, i64 0)
# |   %b.coerce = bitcast <vscale x 16 x i1> %1 to <vscale x 2 x i8>
# |   %b = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %b.coerce, i64 0)
# |   store <8 x i8> %a, ptr %a.addr, align 2
# |   store <8 x i8> %b, ptr %b.addr, align 2
# |   %2 = load <8 x i8>, ptr %a.addr, align 2
# |   %3 = load <8 x i8>, ptr %b.addr, align 2
# |   %and = and <8 x i8> %2, %3
# |   store <8 x i8> %and, ptr %retval, align 2
# |   %4 = load <8 x i8>, ptr %retval, align 2
# |   %cast.scalable = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> poison, <8 x i8> %4, i64 0)
# |   %5 = bitcast <vscale x 2 x i8> %cast.scalable to <vscale x 16 x i1>
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8>, <8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @and_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %and = and <64 x i8> %0, %1
# |   store <64 x i8> %and, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @and_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %and = and <32 x i16> %0, %1
# |   store <32 x i16> %and, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @and_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %and = and <16 x i32> %0, %1
# |   store <16 x i32> %and, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @and_i64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %and = and <8 x i64> %0, %1
# |   store <8 x i64> %and, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64>, <8 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @and_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %and = and <64 x i8> %0, %1
# |   store <64 x i8> %and, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @and_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %and = and <32 x i16> %0, %1
# |   store <32 x i16> %and, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @and_u32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %and = and <16 x i32> %0, %1
# |   store <16 x i32> %and, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @and_u64(<vscale x
# | ...
# `---data was truncated (10240/35910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000564a1056f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564a1056c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564a1056f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16a3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16a38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16a3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16a3831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a10504e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564a10504c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564a104e9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564a101990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564a10198dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f16a3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16a38330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16a38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a10198cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c (302 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclamp_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.uclamp.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uclamp.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclamp_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.uclamp.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uclamp.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclamp_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.uclamp.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uclamp.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclamp_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uclamp.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uclamp.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055f641d5615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f641d530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f641d5689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0df0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0df078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0df0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0df071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f641cebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f641cebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f641cd0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f6419800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f64197fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0df071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0df071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0df071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f64197fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c (303 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbl_s8(<vscale x 16 x i8> %data, <vscale x 16 x i8> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %indices.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store <vscale x 16 x i8> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbl.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.tbl.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbl_s16(<vscale x 8 x i16> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbl.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.tbl.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbl_s32(<vscale x 4 x i32> %data, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbl.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.tbl.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbl_s64(<vscale x 2 x i64> %data, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbl.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.tbl.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbl_u8(<vscale x 16 x i8> %data, <vscale x 16 x i8> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %indices.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store <vscale x 16 x i8> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbl.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbl_u16(<vscale x 8 x i16> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbl.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbl_u32(<vscale x 4 x i32> %data, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbl.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbl_u64(<vscale x 2 x i64> %data, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbl.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtbl_f16(<vscale x 8 x half> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.tbl.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.tbl.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtbl_f32(<vscale x 4 x float> %data, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.tbl.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.tbl.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtbl_f64(<vscale x 2 x double> %data, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x double>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %data, ptr %data.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %data.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.tbl.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.tbl.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtbl_bf16(<vscale x 8 x bfloat> %data, <vscale x 8 x i16> %indices) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %indices.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x bfloat> %data, ptr %data.addr, align 16
# |   store <vscale x 8 x i16> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %data.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.tbl.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.tbl.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptra
# | ...
# `---data was truncated (10240/10361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d3f65bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d3f65ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d3f65bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6feef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6feef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6feef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6feef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3f6552e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d3f6552c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d3f6537b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d3f61e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d3f61e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6feef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6feef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6feef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3f61e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c (304 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.
# | ...
# `---data was truncated (10240/288058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d3a78115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563d3a77e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563d3a78189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5087b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5087b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5087b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5087b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d3a716e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563d3a716c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563d3a6fbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563d3a3ab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563d3a3aadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5087b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5087b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5087b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d3a3aacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c (305 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055984c34015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055984c33d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055984c34089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e79933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e7998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e79933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e7991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055984c2d5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055984c2d5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055984c2bab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055984bf6a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055984bf69dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0e7991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e7991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e7991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055984bf69cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/X86/avx-shuffle-builtins.c (306 of 27911)
******************** TEST 'Clang :: CodeGen/X86/avx-shuffle-builtins.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @x(<8 x float> noundef %a, <8 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   %b.addr = alloca <8 x float>, align 32
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   store <8 x float> %b, ptr %b.addr, align 32
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %1 = load <8 x float>, ptr %b.addr, align 32
# |   %shufp = shufflevector <8 x float> %0, <8 x float> %1, <8 x i32> <i32 3, i32 2, i32 8, i32 11, i32 7, i32 6, i32 12, i32 15>
# |   ret <8 x float> %shufp
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_mm_permute_pd(<2 x double> noundef %a) #1 {
# | entry:
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %permil = shufflevector <2 x double> %0, <2 x double> poison, <2 x i32> <i32 1, i32 0>
# |   ret <2 x double> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_permute_pd(<4 x double> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 32
# |   store <4 x double> %a, ptr %a.addr, align 32
# |   %0 = load <4 x double>, ptr %a.addr, align 32
# |   %permil = shufflevector <4 x double> %0, <4 x double> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
# |   ret <4 x double> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_mm_permute_ps(<4 x float> noundef %a) #1 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %permil = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
# |   ret <4 x float> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_mm_permute_ps2(<4 x float> noundef %a) #1 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %permil = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> <i32 2, i32 1, i32 2, i32 3>
# |   ret <4 x float> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_permute_ps(<8 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %permil = shufflevector <8 x float> %0, <8 x float> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
# |   ret <8 x float> %permil
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_permute2f128_pd(<4 x double> noundef %a, <4 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 32
# |   %b.addr = alloca <4 x double>, align 32
# |   store <4 x double> %a, ptr %a.addr, align 32
# |   store <4 x double> %b, ptr %b.addr, align 32
# |   %0 = load <4 x double>, ptr %a.addr, align 32
# |   %1 = load <4 x double>, ptr %b.addr, align 32
# |   %vperm = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
# |   ret <4 x double> %vperm
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_permute2f128_ps(<8 x float> noundef %a, <8 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   %b.addr = alloca <8 x float>, align 32
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   store <8 x float> %b, ptr %b.addr, align 32
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %1 = load <8 x float>, ptr %b.addr, align 32
# |   %vperm = shufflevector <8 x float> %1, <8 x float> %0, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>
# |   ret <8 x float> %vperm
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i64> @test_mm256_permute2f128_si256(<4 x i64> noundef %a, <4 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 32
# |   %b.addr = alloca <4 x i64>, align 32
# |   store <4 x i64> %a, ptr %a.addr, align 32
# |   store <4 x i64> %b, ptr %b.addr, align 32
# |   %0 = load <4 x i64>, ptr %a.addr, align 32
# |   %1 = bitcast <4 x i64> %0 to <8 x i32>
# |   %2 = load <4 x i64>, ptr %b.addr, align 32
# |   %3 = bitcast <4 x i64> %2 to <8 x i32>
# |   %vperm = shufflevector <8 x i32> %1, <8 x i32> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
# |   %4 = bitcast <8 x i32> %vperm to <4 x i64>
# |   ret <4 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_mm_broadcast_ss(ptr noundef %__a) #1 {
# | entry:
# |   %__a.addr.i = alloca ptr, align 8
# |   %__f.i = alloca float, align 4
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %__a.addr = alloca ptr, align 8
# |   store ptr %__a, ptr %__a.addr, align 8
# |   %0 = load ptr, ptr %__a.addr, align 8
# |   store ptr %0, ptr %__a.addr.i, align 8
# |   %1 = load ptr, ptr %__a.addr.i, align 8
# |   %2 = load float, ptr %1, align 1
# |   store float %2, ptr %__f.i, align 4
# |   %3 = load float, ptr %__f.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %3, i32 0
# |   %4 = load float, ptr %__f.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit.i, float %4, i32 1
# |   %5 = load float, ptr %__f.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %5, i32 2
# |   %6 = load float, ptr %__f.i, align 4
# |   %vecinit4.i = insertelement <4 x float> %vecinit3.i, float %6, i32 3
# |   store <4 x float> %vecinit4.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_broadcast_sd(ptr noundef %__a) #0 {
# | entry:
# |   %__a.addr.i = alloca ptr, align 8
# |   %__d.i = alloca double, align 8
# |   %.compoundliteral.i = alloca <4 x double>, align 32
# |   %__a.addr = alloca ptr, align 8
# |   store ptr %__a, ptr %__a.addr, align 8
# |   %0 = load ptr, ptr %__a.addr, align 8
# |   store ptr %0, ptr %__a.addr.i, align 8
# |   %1 = load ptr, ptr %__a.addr.i, align 8
# |   %2 = load double, ptr %1, align 1
# |   store double %2, ptr %__d.i, align 8
# |   %3 = load double, ptr %__d.i, align 8
# |   %vecinit.i = insertelement <4 x double> poison, double %3, i32 0
# |   %4 = load double, ptr %__d.i, align 8
# |   %vecinit2.i = insertelement <4 x double> %vecinit.i, double %4, i32 1
# |   %5 = load double, ptr %__d.i, align 8
# |   %vecinit3.i = insertelement <4 x double> %vecinit2.i, double %5, i32 2
# |   %6 = load double, ptr %__d.i, align 8
# |   %vecinit4.i = insertelement <4 x double> %vecinit3.i, double %6, i32 3
# |   store <4 x double> %vecinit4.i, ptr %.compoundliteral.i, align 32
# |   %7 = load <4 x double>, ptr %.compoundliteral.i, align 32
# |   ret <4 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_broadcast_ss(ptr noundef %__a) #0 {
# | entry:
# |   %__a.addr.i = alloca ptr, align 8
# |   %__f.i = alloca float, align 4
# |   %.compoundliteral.i = alloca <8 x float>, align 32
# |   %__a.addr = alloca ptr, align 8
# |   store ptr %__a, ptr %__a.addr, align 8
# |   %0 = load ptr, ptr %__a.addr, align 8
# |   store ptr %0, ptr %__a.addr.i, align 8
# |   %1 = load ptr, ptr %__a.addr.i, align 8
# |   %2 = load float, ptr %1, align 1
# |   store float %2, ptr %__f.i, align 4
# |   %3 = load float, ptr %__f.i, align 4
# |   %vecinit.i = insertelement <8 x float> poison, float %3, i32 0
# |   %4 = load float, ptr %__f.i, align 4
# |   %vecinit2.i = insertelement <8 x float> %vecinit.i, float %4, i32 1
# |   %5 = load float, ptr %__f.i, align 4
# |   %vecinit3.i = insertelement <8 x float> %vecinit2.i, float %5, i32 2
# |   %6 = load float, ptr %__f.i, align 4
# |   %vecinit4.i = insertelement <8 x float> %vecinit3.i, float %6, i32 3
# |   %7 = load float, ptr %__f.i, align 4
# |   %vecinit5.i = insertelement <8 x float> %vecinit4.i, float %7, i32 4
# |   %8 = load float, ptr %__f.i, align 4
# |   %vecinit6.i = insertelement <8 x float> %vecinit5.i, float %8, i32 5
# |   %9 = load float, ptr %__f.i, align 4
# |   %vecinit7.i = insertelement <8 x float> %vecinit6.i, float %9, i32 6
# |   %10 = load float, ptr %__f.i, align 4
# |   %vecinit8.i = insertelement <8 x float> %vecinit7.i, float %10, i32 7
# |   store <8 x float> %vecinit8.i, ptr %.compoundliteral.i, align 32
# |   %11 = load <8 x float>, ptr %.compoundliteral.i, align 32
# |   ret <8 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x float> @test_mm256_insertf128_ps_0(<8 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 32
# |   %b.addr = alloca <4 x float>, align 16
# |   store <8 x float> %a, ptr %a.addr, align 32
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <8 x float>, ptr %a.addr, align 32
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %widen = shufflevector <4 x float> %1, <4 x float> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   %insert = shufflevector <8 x float> %0, <8 x float> %widen, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
# |   ret <8 x float> %insert
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x double> @test_mm256_insertf128_pd_0(<4 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 32
# |   %b.addr = alloca <2 x double>, align 16
# |   store <4 x double> %a, ptr %a.addr, align 32
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <4 x double>, ptr %a.addr, align 32
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   %widen = shufflevector <2 x double> %1, <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   %insert = shufflevector <4 x double> %0, <4 x double> %widen, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
# |   ret <4 x double> %insert
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i64> @test_mm256_insertf128_si256_0(<4 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 32
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <4 x i64> %a, ptr %a.addr, align 32
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i64>, ptr %a.addr, align 32
# |   %1 = bitcast <4 x i64> %0 to <8 x i32>
# |   %2 = load <2 x i64>, ptr
# | ...
# `---data was truncated (10240/21933) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585f410d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005585f410a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005585f410d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc38133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc3818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc38133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc3811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005585f40a2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005585f40a2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005585f4087b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005585f3d370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005585f3d36dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbc3811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc3811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc3811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005585f3d36cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c (307 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcompact_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.compact.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.compact.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcompact_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.compact.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.compact.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcompact_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.compact.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcompact_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.compact.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcompact_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.compact.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.compact.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcompact_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.compact.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.compact.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055da63ad915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055da63ad60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055da63ad989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb23eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb23eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb23eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb23eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da63a6ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055da63a6ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055da63a53b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055da637030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055da63702dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb23eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb23eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb23eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da63702cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c (308 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005557cd64615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005557cd6430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005557cd64689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3bd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3bd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3bd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3bd11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557cd5dbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005557cd5dbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005557cd5c0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005557cd2700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005557cd26fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe3bd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3bd11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3bd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557cd26fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c (309 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svwrffr(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   call void @llvm.aarch64.sve.wrffr(<vscale x 16 x i1> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.sve.wrffr(<vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e6dbb8d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e6dbb8a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e6dbb8d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81a7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81a70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81a7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81a7031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6dbb22e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e6dbb22c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e6dbb07b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e6db7b70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e6db7b6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f81a7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81a70330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81a70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6db7b6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c (310 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkn_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005650b739015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005650b738d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005650b739089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f058f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f058f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f058f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f058f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650b7325e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005650b7325c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005650b730ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005650b6fba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005650b6fb9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f058f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f058f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f058f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650b6fb9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c (311 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrev_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.vector.reverse.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.reverse.nxv16i8(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrev_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.vector.reverse.nxv8i16(<vscale x 8 x i16> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.reverse.nxv8i16(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrev_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrev_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.vector.reverse.nxv2i64(<vscale x 2 x i64> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.reverse.nxv2i64(<vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrev_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.vector.reverse.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrev_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.vector.reverse.nxv8i16(<vscale x 8 x i16> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrev_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrev_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.vector.reverse.nxv2i64(<vscale x 2 x i64> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrev_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.vector.reverse.nxv8f16(<vscale x 8 x half> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.reverse.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrev_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrev_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.vector.reverse.nxv2f64(<vscale x 2 x double> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.vector.reverse.nxv2f64(<vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b8(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.vector.reverse.nxv16i1(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.vector.reverse.nxv16i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b16(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rev.b16(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rev.b16(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b32(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rev.b32(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rev.b32(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svrev_b64(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.rev.b64(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.rev.b64(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svrev_bf16(<vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.reverse.nxv8bf16(<vscale x 8 x bfloat> %0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.reverse.nxv8bf16(<vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005606477ed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005606477ea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005606477ed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f378d21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f378d2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f378d21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f378d203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560647782e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560647782c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560647767b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005606474170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560647416dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f378d204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f378d2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f378d2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560647416cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c (312 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpge_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560dfa5b815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560dfa5b50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560dfa5b889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3264449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32644a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3264449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3264431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560dfa54de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560dfa54dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560dfa532b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560dfa1e20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560dfa1e1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3264432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32644330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32644330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560dfa1e1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c (313 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, i64 noundef %offset, i64 no
# | ...
# `---data was truncated (10240/287205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fefccf615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fefccf30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fefccf689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ea5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ea5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ea5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ea5c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fefcc8be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fefcc8bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fefcc70b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fefc9200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fefc91fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5ea5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ea5c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ea5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fefc91fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/pfalse.c (314 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/pfalse.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o -        /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpfalse_b() #0 {
# | entry:
# |   ret <vscale x 16 x i1> zeroinitializer
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x00005644e141d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005644e141a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005644e141d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0959b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0959b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0959b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0959b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644e13b2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005644e13b2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005644e1397b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005644e10470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005644e1046dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0959b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0959b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0959b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644e1046cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c (315 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmad_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmad_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmad_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmad_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmad_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmad_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmad_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/86847) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561db2e7315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561db2e700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561db2e7389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa01901bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0190725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa01901ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa019003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561db2e08e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561db2e08c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561db2dedb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561db2a9d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561db2a9cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa019004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0190050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0190050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561db2a9ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c (316 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset3_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %4, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset3_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %4, 2
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset3_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, <vscale x 4 x i32> %4, 0
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset3_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, <vscale x 2 x i64> %4, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset3_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %4, 2
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset3_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %4, 0
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset3_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale
# | ...
# `---data was truncated (10240/25462) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e53b0a115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e53b09e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e53b0a189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8795249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87952a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8795249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8795231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e53b036e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e53b036c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e53b01bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e53accb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e53accadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8795232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87952330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87952330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e53accacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c (317 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_s16_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_s16_f16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_s16_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_u16_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_u16_f16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcvt_u16_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcvt_s32_f16_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 8 x half
# | ...
# `---data was truncated (10240/88476) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557a01ff115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557a01fee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557a01ff189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb688d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb688d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb688d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb688d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a01f86e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557a01f86c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557a01f6bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557a01c1b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557a01c1add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb688d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb688d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb688d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a01c1acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c (318 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8
# | ...
# `---data was truncated (10240/215036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561abc3c415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561abc3c10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561abc3c489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7237049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72370a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7237049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7237031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561abc359e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561abc359c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561abc33eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561abbfee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561abbfeddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7237032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72370330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72370330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561abbfedcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c (319 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmopa_u32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmopa_s32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmops_u32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svbmops_s32(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 3, <vscale x 4 x i1> %4, <vscale x 4 x i1> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d9e034d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d9e034a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d9e034d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1491505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f149155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1491505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14914ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9e02e2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d9e02e2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d9e02c7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d9dff770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d9dff76dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f14914eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14914ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14914ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9dff76cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c (320 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %binde
# | ...
# `---data was truncated (10240/110121) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056220dbdd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056220dbda0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056220dbdd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1164733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f116478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1164733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f116471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056220db72e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056220db72c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056220db57b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056220d8070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056220d806dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f116471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f116471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f116471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056220d806cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c (321 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_n_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_n_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_n_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000556ce46bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556ce46ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556ce46bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2fdf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2fdf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2fdf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2fdeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ce4652e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556ce4652c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556ce4637b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556ce42e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556ce42e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc2fdeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2fdeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2fdeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ce42e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c (322 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_s16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.smopa.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smopa.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_u16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.umopa.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umopa.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmops_s16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.smops.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smops.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmops_u16(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   call void @llvm.aarch64.sme.umops.za32.nxv8i16(i32 3, <vscale x 8 x i1> %4, <vscale x 8 x i1> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umops.za32.nxv8i16(i32 immarg, <vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005558b6d8615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005558b6d830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005558b6d8689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efff6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efff6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efff6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efff6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558b6d1be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005558b6d1bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005558b6d00b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005558b69b00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005558b69afdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efff6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efff6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efff6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558b69afcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c (323 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync
# | ...
# `---data was truncated (10240/183423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560ceba115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005560ceb9e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005560ceba189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa459449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4594a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa459449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa459431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560ceb36e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005560ceb36c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005560ceb1bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005560ce7cb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005560ce7cadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa459432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4594330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4594330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560ce7cacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c (324 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtn_f8_bf16(<vscale x 8 x bfloat> %zn_zm.coerce0, <vscale x 8 x bfloat> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn_zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn_zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn_zm, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn_zm.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtn_f8_f16(<vscale x 8 x half> %zn_zm.coerce0, <vscale x 8 x half> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn_zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn_zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn_zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn_zm.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtnb_f8_f32(<vscale x 4 x float> %zn_zm.coerce0, <vscale x 4 x float> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn_zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn_zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnb.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnb.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcvtnt_f8_f32(<vscale x 16 x i8> %zd, <vscale x 4 x float> %zn_zm.coerce0, <vscale x 4 x float> %zn_zm.coerce1, i64 noundef %fpm) #0 {
# | entry:
# |   %zn_zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zd.addr = alloca <vscale x 16 x i8>, align 16
# |   %zn_zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpm.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn_zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn_zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn_zm, align 16
# |   %zn_zm1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm, align 16
# |   store <vscale x 16 x i8> %zd, ptr %zd.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn_zm1, ptr %zn_zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %zd.addr, align 16
# |   %3 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn_zm.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 1
# |   %6 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   %7 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnt.nxv4f32(<vscale x 16 x i8> %2, <vscale x 4 x float> %4, <vscale x 4 x float> %5)
# |   ret <vscale x 16 x i8> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnt.nxv4f32(<vscale x 16 x i8>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000561ee610f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561ee610c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561ee610f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4453c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4453ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4453c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4453c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ee60a4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561ee60a4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561ee6089b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561ee5d390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561ee5d38dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4453c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4453c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4453c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ee5d38cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c (325 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16mf2_bf16mf4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf2(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf4(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf4(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m4(<
# | ...
# `---data was truncated (10240/11404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056300c87e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056300c87b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056300c87e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36c5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36c5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36c5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36c5a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056300c813e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056300c813c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056300c7f8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056300c4a80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056300c4a7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f36c5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36c5a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36c5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056300c4a7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c (326 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_n_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_n_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %6 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_n_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, bfloat noundef %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store bfloat %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = load bfloat, ptr %op3.addr, align 2
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %3, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.u.nxv8bf16(<vscale x 8 x i1> %4, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055e9f3d6e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e9f3d6b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e9f3d6e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9e5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9e558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9e5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9e551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9f3d03e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e9f3d03c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e9f3ce8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e9f39980b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e9f3997dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff9e551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9e551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9e551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9f3997cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c (327 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp1_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.uzp1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svuzp1_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.uzp1.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563cf0ab315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563cf0ab00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563cf0ab389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4566849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45668a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4566849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4566831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563cf0a48e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563cf0a48c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563cf0a2db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563cf06dd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563cf06dcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4566832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45668330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45668330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563cf06dccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c (328 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #
# | ...
# `---data was truncated (10240/12075) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a11e48b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a11e4880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a11e48b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc09d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc09d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc09d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc09d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a11e420e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a11e420c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a11e405b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a11e0b50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a11e0b4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcc09d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc09d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc09d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a11e0b4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm64_vcreate.c (329 of 27911)
******************** TEST 'Clang :: CodeGen/arm64_vcreate.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define <2 x float> @test_vcreate_f32(i64 noundef %a1) #0 {
# | entry:
# |   %a1.addr = alloca i64, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__promote = alloca i64, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store i64 %a1, ptr %a1.addr, align 8
# |   %0 = load i64, ptr %a1.addr, align 8
# |   store i64 %0, ptr %__promote, align 8
# |   %1 = load <2 x float>, ptr %__promote, align 8
# |   store <2 x float> %1, ptr %__ret, align 8
# |   %2 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %2, ptr %tmp, align 8
# |   %3 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ee8d9515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563ee8d920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563ee8d9589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58aca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58acaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58aca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58aca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ee8d2ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563ee8d2ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563ee8d0fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563ee89bf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563ee89bedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f58aca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58aca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58aca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ee89becc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c (330 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single_x1_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smla.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single_x1_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smla.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smla.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlal_single_x1_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umla.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlal_single_x1_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umla.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umla.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single_x1_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smls.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smls.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single_x1_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.smls.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smls.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlsl_single_x1_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umls.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umls.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_uvmlsl_single_x1_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.umls.za64.single.vg4x1.nxv8i16(i32 %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umls.za64.single.vg4x1.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_sumlall_single_x1_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_usmlall_single_x1_u8(i32 noundef %slice_base, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load i32, ptr %slice_base.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32 %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single_x2_s8(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | 
# | ...
# `---data was truncated (10240/178306) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000559a1412915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559a141260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559a1412989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94c6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94c64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94c6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94c6431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a140bee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559a140bec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559a140a3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559a13d530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559a13d52dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f94c6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94c64330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94c64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a13d52cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c (331 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclastb_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.clastb.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclastb_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clastb.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.clastb.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclastb_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clastb.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.clastb.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclastb_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clastb.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.clastb.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclastb_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clastb.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclastb_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clastb.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclastb_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clastb.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclastb_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clastb.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svclastb_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %fallback, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x half>, align 16
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.clastb.nxv8f16(<vscale x 8 x i
# | ...
# `---data was truncated (10240/26390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000563a9a31b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563a9a3180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563a9a31b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f829d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f829d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f829d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f829d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a9a2b0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563a9a2b0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563a9a295b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563a99f450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563a99f44dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f829d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f829d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f829d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a99f44cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon-misc.c (332 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-misc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vcgez_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = icmp sge <8 x i8> %1, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %2 to <8 x i8>
# |   store <8 x i8> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %3 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %3, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgez_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x i16>
# |   %3 = icmp sge <4 x i16> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcgez_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x i32>
# |   %3 = icmp sge <2 x i32> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i32>
# |   store <2 x i32> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vcgez_s64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <1 x i64>
# |   %3 = icmp sge <1 x i64> %2, zeroinitializer
# |   %vcgez.i = sext <1 x i1> %3 to <1 x i64>
# |   store <1 x i64> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %4, ptr %__ret.i, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vcgezq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = icmp sge <16 x i8> %1, zeroinitializer
# |   %vcgez.i = sext <16 x i1> %2 to <16 x i8>
# |   store <16 x i8> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %3 = load <16 x i8>, ptr %ref.tmp.i, align 16
# |   store <16 x i8> %3, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgezq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x i16>
# |   %3 = icmp sge <8 x i16> %2, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcgezq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x i32>
# |   %3 = icmp sge <4 x i32> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i32>
# |   store <4 x i32> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %4, ptr %__ret.i, align 16
# |   %5 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcgezq_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <2 x i64>
# |   %3 = icmp sge <2 x i64> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i64>
# |   store <2 x i64> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %4, ptr %__ret.i, align 16
# |   %5 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcgez_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x float>
# |   %3 = fcmp oge <2 x float> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i32>
# |   store <2 x i32> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vcgez_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <1 x double>
# |   %3 = fcmp oge <1 x double> %2, zeroinitializer
# |   %vcgez.i = sext <1 x i1> %3 to <1 x i64>
# |   store <1 x i64> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %4, ptr %__ret.i, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcgezq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fcmp oge <4 x float> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i32>
# |   store <4 x i32> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %4, ptr %__ret.i, align 16
# |   %5 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcgezq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <2 x double>
# |   %3 = fcmp oge <2 x double> %2, zeroinitializer
# |   %vcgez.i = sext <2 x i1> %3 to <2 x i64>
# |   store <2 x i64> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %4, ptr %__ret.i, align 16
# |   %5 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vclez_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, ali
# | ...
# `---data was truncated (10240/217310) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055ec005d915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ec005d60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ec005d989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f39f9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39f9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f39f9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f39f9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec0056ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ec0056ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ec00553b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ec002030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ec00202dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f39f9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39f9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39f9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec00202cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c (333 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b89641e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b89641b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b89641e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1984933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f198498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1984933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f198491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8963b3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b8963b3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b896398b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b8960480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b896047dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f198491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f198491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f198491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b896047cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c (334 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_s32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_s64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_u32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_u64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_s32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_n_s64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_n_u32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdot_n_u64(<vscale x 2 x i64> %op1, <vscale x 8 x i16> %op2, i16 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca i16, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store i16 %op3, ptr %op3.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load i16, ptr %op3.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.udot.nxv2i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_s32(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdot_lane_s32_1(<vscale x 4 x i32> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 =
# | ...
# `---data was truncated (10240/15126) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556bd04f415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556bd04f10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556bd04f489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3994d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3994d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3994d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3994ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bd0489e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556bd0489c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556bd046eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556bd011e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556bd011ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3994ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3994cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3994cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bd011dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c (335 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclamp_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.sclamp.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sclamp.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclamp_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sclamp.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sclamp.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclamp_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sclamp.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sclamp.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclamp_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sclamp.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sclamp.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000560201efb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560201ef80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560201efb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6b4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6b4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6b4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6b4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560201e90e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560201e90c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560201e75b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560201b250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560201b24dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc6b4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6b4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6b4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560201b24cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c (336 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmls_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mls.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mls.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmls_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mls.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mls.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmls_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mls.nxv4i32(<vscale x 4 x i1> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3)
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mls.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmls_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %6 = call <vscale x 2 x i64> @llvm.aarch64.sve.mls.nxv2i64(<vscale x 2 x i1> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3)
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mls.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmls_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %4 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %5 = call <vscale x 16 x i8> @llvm.aarch64.sve.mls.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %4, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmls_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %6 = call <vscale x 8 x i16> @llvm.aarch64.sve.mls.nxv8i16(<vscale x 8 x i1> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3)
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmls_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %6 = call <vscale x 4 x i32> @llvm.aarch64.sve.mls.nxv4i32(<vscale x 4 x i1> %4, <vs
# | ...
# `---data was truncated (10240/92910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005638243c615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005638243c30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005638243c689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f358d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f358d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f358d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f358d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056382435be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056382435bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563824340b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563823ff00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563823fefdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f358d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f358d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f358d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563823fefcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c (337 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget3_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget3_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 2
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget3_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 1
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget3_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, 0
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget3_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 2
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget3_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 1
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget3_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %3 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, 0
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget3_u64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue 
# | ...
# `---data was truncated (10240/21007) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056088026e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056088026b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056088026e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c53e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c53ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c53e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c53e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560880203e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560880203c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005608801e8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056087fe980b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056087fe97dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5c53e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c53e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c53e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056087fe97cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c (338 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sdivr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.udivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.udivr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_s64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_u32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdivr_u64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.udivr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdivr_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 1
# | ...
# `---data was truncated (10240/48782) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e6f887815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e6f88750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e6f887889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34b0705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34b075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34b0705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34b06ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6f880de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e6f880dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e6f87f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e6f84a20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e6f84a1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f34b06eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34b06ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34b06ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6f84a1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c (339 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svadd_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svadd_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadd_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadd_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svadd_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svadd_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadd_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadd_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svadd_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/72449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056098da2715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056098da240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056098da2789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb016249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0162a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb016249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb016231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056098d9bce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056098d9bcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056098d9a1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056098d6510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056098d650dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb016232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0162330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0162330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056098d650cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c (340 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlasta_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.lasta.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlasta_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lasta.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.lasta.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlasta_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lasta.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.lasta.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlasta_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lasta.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lasta.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svlasta_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.lasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svlasta_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.lasta.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svlasta_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.lasta.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlasta_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.lasta.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svlasta_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.lasta.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare half @llvm.aarch64.sve.lasta.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svlasta_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.lasta.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.aarch64.sve.lasta.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svlasta_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.lasta.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare double @llvm.aarch64.sve.lasta.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local bfloat @test_svlasta_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call bfloat @llvm.aarch64.sve.lasta.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret bfloat %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willretur
# | ...
# `---data was truncated (10240/10821) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000555dd8a5e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555dd8a5b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555dd8a5e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc9d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc9d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc9d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc9d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555dd89f3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555dd89f3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555dd89d8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555dd86880b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555dd8687dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdc9d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc9d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc9d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555dd8687cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c (341 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055598393515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005559839320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055598393589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c7e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c7e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c7e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c7e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559838cae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005559838cac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005559838afb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055598355f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055598355edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5c7e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c7e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c7e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055598355ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c (342 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svqdmulh_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svqdmulh_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svqdmulh_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svqdmulh_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svqdmulh_single_s8_x4(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zdn.coerce2, <vscale x 16 x i8> %zdn.coerce3, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zdn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svqdmulh_single_s16_x4(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zdn.coerce2, <vscale x 8
# | ...
# `---data was truncated (10240/47111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055ced543215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ced542f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ced543289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1519c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1519ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1519c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1519c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ced53c7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ced53c7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ced53acb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ced505c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ced505bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1519c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1519c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1519c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ced505bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c (343 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svext_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svext_s8_1(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 255)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svext_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 0)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svext_s16_1(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 127)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svext_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 0)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svext_s32_1(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 63)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svext_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 0)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svext_s64_1(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 31)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svext_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 255)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svext_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 127)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svext_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 63)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svext_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 31)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svext_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ext.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 127)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ext.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svext_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr 
# | ...
# `---data was truncated (10240/12880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e93d5c615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e93d5c30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e93d5c689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f865be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f865bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f865be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f865be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e93d55be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e93d55bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e93d540b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e93d1f00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e93d1efdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f865be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f865be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f865be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e93d1efcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c (344 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svminnm_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000564134e8615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564134e830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564134e8689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f890df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f890df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f890df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f890df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564134e1be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564134e1bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564134e00b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564134ab00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564134aafdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f890df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f890df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f890df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564134aafcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c (345 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmad_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmad_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmad_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmad_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmad_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmad_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmad_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmla.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005561bab7c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005561bab790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005561bab7c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7731133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f773118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7731133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f773111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561bab11e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005561bab11c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005561baaf6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005561ba7a60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005561ba7a5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f773111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f773111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f773111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561ba7a5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c (346 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svbfmlalb_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalb_lane_0_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 0)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb.lane.v2(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalb_lane_7_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalb_n_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, bfloat noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca bfloat, align 2
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store bfloat %z, ptr %z.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load bfloat, ptr %z.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005565c821715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005565c82140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005565c821789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f885af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f885af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f885af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f885af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565c81ace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005565c81acc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005565c8191b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005565c7e410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005565c7e40dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f885af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f885af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f885af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565c7e40cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c (347 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintp_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintp_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintp_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintp_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintp_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintp_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintp_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintp.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintp_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintp_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintp.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005605daae415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005605daae10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005605daae489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa398d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa398d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa398d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa398d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605daa79e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005605daa79c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005605daa5eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005605da70e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005605da70ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa398d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa398d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa398d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605da70dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c (348 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   s
# | ...
# `---data was truncated (10240/12680) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593ecba215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005593ecb9f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005593ecba289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9982b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9982b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9982b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9982aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593ecb37e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005593ecb37c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005593ecb1cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005593ec7cc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005593ec7cbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9982aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9982aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9982aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593ec7cbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vshlc.c (349 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vshlc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_s8(<16 x i8> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %2, i32 %1, i32 18)
# |   %4 = extractvalue { i32, <16 x i8> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <16 x i8> } %3, 1
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_s16(<8 x i16> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %2, i32 %1, i32 16)
# |   %4 = extractvalue { i32, <8 x i16> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <8 x i16> } %3, 1
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_s32(<4 x i32> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <4 x i32>, ptr %a.addr, align 8
# |   %3 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %2, i32 %1, i32 4)
# |   %4 = extractvalue { i32, <4 x i32> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <4 x i32> } %3, 1
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_u8(<16 x i8> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %2, i32 %1, i32 17)
# |   %4 = extractvalue { i32, <16 x i8> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <16 x i8> } %3, 1
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_u16(<8 x i16> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %2, i32 %1, i32 17)
# |   %4 = extractvalue { i32, <8 x i16> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <8 x i16> } %3, 1
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_u32(<4 x i32> noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <4 x i32>, ptr %a.addr, align 8
# |   %3 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %2, i32 %1, i32 20)
# |   %4 = extractvalue { i32, <4 x i32> } %3, 0
# |   store i32 %4, ptr %0, align 4
# |   %5 = extractvalue { i32, <4 x i32> } %3, 1
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_s8(<16 x i8> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %2, i32 %1, i32 29, <16 x i1> %5)
# |   %7 = extractvalue { i32, <16 x i8> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <16 x i8> } %6, 1
# |   ret <16 x i8> %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8>, i32, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_s16(<8 x i16> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %2, i32 %1, i32 17, <8 x i1> %5)
# |   %7 = extractvalue { i32, <8 x i16> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <8 x i16> } %6, 1
# |   ret <8 x i16> %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_s32(<4 x i32> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <4 x i32>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32> %2, i32 %1, i32 9, <4 x i1> %5)
# |   %7 = extractvalue { i32, <4 x i32> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <4 x i32> } %6, 1
# |   ret <4 x i32> %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32>, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_u8(<16 x i8> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <16 x i8>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %2, i32 %1, i32 21, <16 x i1> %5)
# |   %7 = extractvalue { i32, <16 x i8> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <16 x i8> } %6, 1
# |   ret <16 x i8> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_u16(<8 x i16> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %b.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = load <8 x i16>, ptr %a.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %2, i32 %1, i32 24, <8 x i1> %5)
# |   %7 = extractvalue { i32, <8 x i16> } %6, 0
# |   store i32 %7, ptr %0, align 4
# |   %8 = extractvalue { i32, <8 x i16> } %6, 1
# |   ret <8 x i16> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_u32(<4 x i32> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# | 
# | ...
# `---data was truncated (10240/11454) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b5859f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559b5859c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559b5859f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f09dd21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09dd2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f09dd21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f09dd203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b58534e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559b58534c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559b58519b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559b581c90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559b581c8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f09dd204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09dd2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09dd2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b581c8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c (350 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_i16m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_i16m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_u16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | ent
# | ...
# `---data was truncated (10240/31706) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559cc561815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559cc56150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559cc561889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faba1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faba12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faba1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faba1231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559cc55ade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559cc55adc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559cc5592b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559cc52420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559cc5241dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faba1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faba12330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faba12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cc5241cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c (351 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vsc
# | ...
# `---data was truncated (10240/88436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562fb4d5215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562fb4d4f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562fb4d5289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc616133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc61618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc616133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc61611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fb4ce7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562fb4ce7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562fb4cccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562fb497c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562fb497bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc61611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc61611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc61611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fb497bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c (352 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x
# | ...
# `---data was truncated (10240/68062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559dd739015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559dd738d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559dd739089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb86733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb8678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb86733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb8671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559dd7325e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559dd7325c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559dd730ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559dd6fba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559dd6fb9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feb8671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb8671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb8671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559dd6fb9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c (353 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt1_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt1.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt1.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt2_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt2.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt2.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtlt1_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtlt2_bf16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvt1_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt1.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt1.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvt2_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt2.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt2.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvtlt1_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcvtlt2_f16_mf8(<vscale x 16 x i8> %zn, i64 noundef %fpm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005566ec88015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005566ec87d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005566ec88089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42f7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42f76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42f7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42f7631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566ec815e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005566ec815c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005566ec7fab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005566ec4aa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005566ec4a9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f42f7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42f76330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42f76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566ec4a9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/load.c (354 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/load.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.float64x2x2_t = type { [2 x <2 x double>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.float64x1x2_t = type { [2 x <1 x double>] }
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.float64x2x3_t = type { [3 x <2 x double>] }
# | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.float64x1x3_t = type { [3 x <1 x double>] }
# | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.float64x2x4_t = type { [4 x <2 x double>] }
# | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.float64x1x4_t = type { [4 x <1 x double>] }
# | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vld1q_f16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %0, align 2
# |   store <8 x half> %1, ptr %ref.tmp, align 16
# |   %2 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %2, ptr %__ret, align 16
# |   %3 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %3, ptr %tmp, align 16
# |   %4 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vld1q_f32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <4 x float>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %0, align 4
# |   store <4 x float> %1, ptr %ref.tmp, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp, align 16
# |   store <4 x float> %2, ptr %__ret, align 16
# |   %3 = load <4 x float>, ptr %__ret, align 16
# |   store <4 x float> %3, ptr %tmp, align 16
# |   %4 = load <4 x float>, ptr %tmp, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vld1q_f64(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <2 x double>, ptr %0, align 8
# |   store <2 x double> %1, ptr %ref.tmp, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %2, ptr %__ret, align 16
# |   %3 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %3, ptr %tmp, align 16
# |   %4 = load <2 x double>, ptr %tmp, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vld1q_mf8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <16 x i8>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   store <16 x i8> %1, ptr %ref.tmp, align 16
# |   %2 = load <16 x i8>, ptr %ref.tmp, align 16
# |   store <16 x i8> %2, ptr %__ret, align 16
# |   %3 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %3, ptr %tmp, align 16
# |   %4 = load <16 x i8>, ptr %tmp, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vld1q_p16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   store <8 x i16> %1, ptr %ref.tmp, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %2, ptr %__ret, align 16
# |   %3 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %3, ptr %tmp, align 16
# |   %4 = load <8 x i16>, ptr %tmp, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vld1q_p64(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %__ret = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load <2 x i64>, ptr %0, align 8
# |   store <2 x i64> %1, ptr %ref.tmp, align 16
# |   %2 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %2, ptr %__ret, align 16
# |   %3 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %3, ptr %tmp, align 16
# |   %4 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vld1q_p8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <16 x i8>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   store <16 x i8> %1, ptr %ref.tmp, align 16
# |   %2 = load <16 x i8>, ptr %ref.tmp, align 16
# |   store <16 x i8> %2, ptr %__ret, align 16
# |   %3 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %3, ptr %tmp, align 16
# |   %4 = load <16 x i8>, ptr %tmp, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vld1q_s16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   store <8 x i16> %1, ptr %ref.tmp, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %2, ptr %__ret, align 16
# |   %3 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %3, ptr %tmp, align 16
# |   %4 = load <8 x i16>, ptr %tmp, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vld1q_s32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   store ptr %a
# | ...
# `---data was truncated (10240/415795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# |  #0 0x000055f53518c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f5351890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f53518c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fecc3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fecc36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fecc3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fecc3631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f535121e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f535121c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f535106b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f534db60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f534db5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fecc3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fecc36330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fecc36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f534db5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c (355 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sb_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sb_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sb_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1sb_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sb_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/28299) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559dc187715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559dc18740f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559dc187789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9321249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93212a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9321249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9321231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559dc180ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559dc180cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559dc17f1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559dc14a10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559dc14a0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9321232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93212330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93212330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559dc14a0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c (356 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_lane_bf16_idx1(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_lane_bf16_idx3(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 3)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmul_lane_bf16_idx7(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 7)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a89df1915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a89df160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a89df1989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb161133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb16118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb161133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb16111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a89deaee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a89deaec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a89de93b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a89db430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a89db42dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb16111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb16111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb16111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a89db42cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c (357 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnt1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnt1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnt1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnt1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnt1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnt1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svldnt1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svldnt1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svldnt1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnt1_vnum_s8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %b
# | ...
# `---data was truncated (10240/22231) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557bf393015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557bf392d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557bf393089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6509d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6509d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6509d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6509d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557bf38c5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557bf38c5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557bf38aab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557bf355a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557bf3559dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6509d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6509d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6509d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557bf3559cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c (358 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqinch.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqinch.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqinch.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqinch.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqinch.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqinch.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 30, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqinch_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqinch.n32(i32 %0, i32 0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqinch_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqinch.n64(i64 %0, i32 1, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqinch.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqinch.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqinch.nxv8i16(<vscale x 8 x i16> %0, i32 31, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqinch.nxv8i16(<vscale x 8 x i16>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_pat_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqinch.nxv8i16(<vscale x 8 x i16> %0, i32 2, i32 16)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqinch_pat_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqinch.nxv8i16(<vscale x 8 x i16> %0, i32 3, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563ddbf5a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563ddbf570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563ddbf5a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c94449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c944a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c94449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c94431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ddbeefe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563ddbeefc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563ddbed4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563ddbb840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563ddbb83dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4c94432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c944330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c944330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ddbb83cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c (359 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %2)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x1_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 1, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_2x2_za16_mf8_mf8_fpm(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 0
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %7, 1
# |   %10 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %10)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 1, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x1_za32_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %2)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 1, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmop4a_1x2_za32_mf8_mf8_fpm(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zm, align 16
# |   %zm1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm1, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %6)
# |   call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vsc
# | ...
# `---data was truncated (10240/15164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055af8ab0c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055af8ab090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055af8ab0c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87d2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87d298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87d2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87d291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af8aaa1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055af8aaa1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055af8aa86b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055af8a7360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055af8a735dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f87d291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87d291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87d291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af8a735cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c (360 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecb.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdecb.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecb.n64(i64 %0, i32 1, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecb_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %0, i32 2, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecb_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %0, i32 3, i32 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563f90b5d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563f90b5a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563f90b5d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcdd3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcdd36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcdd3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcdd3631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f90af2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563f90af2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563f90ad7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563f907870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563f90786dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcdd3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcdd36330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcdd36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f90786cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c (361 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpklo_s16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sunpklo.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sunpklo.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpklo_s32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sunpklo.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sunpklo.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpklo_s64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sunpklo.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sunpklo.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpklo_u16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uunpklo.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uunpklo.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpklo_u32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uunpklo.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uunpklo.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpklo_u64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uunpklo.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uunpklo.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svunpklo_b(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.punpklo.nxv16i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.punpklo.nxv16i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055565320815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005556532050f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055565320889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69d9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69d9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69d9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69d9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055565319de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055565319dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555653182b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555652e320b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555652e31dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f69d9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69d9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69d9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555652e31cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c (362 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_u32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxth.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexth_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxth.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexth_u32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg,
# | ...
# `---data was truncated (10240/11908) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005600b092215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005600b091f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005600b092289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5e3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5e34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5e3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5e3431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600b08b7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005600b08b7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005600b089cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005600b054c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005600b054bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb5e3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5e34330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5e34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600b054bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c (363 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmaxnm_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000562a414f215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562a414ef0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562a414f289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa78c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa78c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa78c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa78c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a41487e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562a41487c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562a4146cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562a4111c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562a4111bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa78c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa78c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa78c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a4111bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c (364 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmuls_lane_f32(float noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <2 x float>, align 8
# |   %__ret_571 = alloca float, align 4
# |   %__s0_571 = alloca float, align 4
# |   %__s1_571 = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_571, align 4
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1_571, align 8
# |   %2 = load float, ptr %__s0_571, align 4
# |   %3 = load <2 x float>, ptr %__s1_571, align 8
# |   store <2 x float> %3, ptr %__s0, align 8
# |   %4 = load <2 x float>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x float> %4, i32 1
# |   store float %vget_lane, ptr %ref.tmp, align 4
# |   %5 = load float, ptr %ref.tmp, align 4
# |   store float %5, ptr %__ret, align 4
# |   %6 = load float, ptr %__ret, align 4
# |   store float %6, ptr %tmp, align 4
# |   %7 = load float, ptr %tmp, align 4
# |   %mul = fmul float %2, %7
# |   store float %mul, ptr %__ret_571, align 4
# |   %8 = load float, ptr %__ret_571, align 4
# |   store float %8, ptr %tmp1, align 4
# |   %9 = load float, ptr %tmp1, align 4
# |   ret float %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vmuld_lane_f64(double noundef %a, <1 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %__ret_570 = alloca double, align 8
# |   %__s0_570 = alloca double, align 8
# |   %__s1_570 = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   %tmp1 = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0_570, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1_570, align 8
# |   %2 = load double, ptr %__s0_570, align 8
# |   %3 = load <1 x double>, ptr %__s1_570, align 8
# |   store <1 x double> %3, ptr %__s0, align 8
# |   %4 = load <1 x double>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x double> %4, i32 0
# |   store double %vget_lane, ptr %ref.tmp, align 8
# |   %5 = load double, ptr %ref.tmp, align 8
# |   store double %5, ptr %__ret, align 8
# |   %6 = load double, ptr %__ret, align 8
# |   store double %6, ptr %tmp, align 8
# |   %7 = load double, ptr %tmp, align 8
# |   %mul = fmul double %2, %7
# |   store double %mul, ptr %__ret_570, align 8
# |   %8 = load double, ptr %__ret_570, align 8
# |   store double %8, ptr %tmp1, align 8
# |   %9 = load double, ptr %tmp1, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmuls_laneq_f32(float noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <4 x float>, align 16
# |   %__ret_577 = alloca float, align 4
# |   %__s0_577 = alloca float, align 4
# |   %__s1_577 = alloca <4 x float>, align 16
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <4 x float>, align 16
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_577, align 4
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %1, ptr %__s1_577, align 16
# |   %2 = load float, ptr %__s0_577, align 4
# |   %3 = load <4 x float>, ptr %__s1_577, align 16
# |   store <4 x float> %3, ptr %__s0, align 16
# |   %4 = load <4 x float>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <4 x float> %4, i32 3
# |   store float %vgetq_lane, ptr %ref.tmp, align 4
# |   %5 = load float, ptr %ref.tmp, align 4
# |   store float %5, ptr %__ret, align 4
# |   %6 = load float, ptr %__ret, align 4
# |   store float %6, ptr %tmp, align 4
# |   %7 = load float, ptr %tmp, align 4
# |   %mul = fmul float %2, %7
# |   store float %mul, ptr %__ret_577, align 4
# |   %8 = load float, ptr %__ret_577, align 4
# |   store float %8, ptr %tmp1, align 4
# |   %9 = load float, ptr %tmp1, align 4
# |   ret float %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vmuld_laneq_f64(double noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca <2 x double>, align 16
# |   %__ret_575 = alloca double, align 8
# |   %__s0_575 = alloca double, align 8
# |   %__s1_575 = alloca <2 x double>, align 16
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   %tmp1 = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0_575, align 8
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %1, ptr %__s1_575, align 16
# |   %2 = load double, ptr %__s0_575, align 8
# |   %3 = load <2 x double>, ptr %__s1_575, align 16
# |   store <2 x double> %3, ptr %__s0, align 16
# |   %4 = load <2 x double>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <2 x double> %4, i32 1
# |   store double %vgetq_lane, ptr %ref.tmp, align 8
# |   %5 = load double, ptr %ref.tmp, align 8
# |   store double %5, ptr %__ret, align 8
# |   %6 = load double, ptr %__ret, align 8
# |   store double %6, ptr %tmp, align 8
# |   %7 = load double, ptr %tmp, align 8
# |   %mul = fmul double %2, %7
# |   store double %mul, ptr %__ret_575, align 8
# |   %8 = load double, ptr %__ret_575, align 8
# |   store double %8, ptr %tmp1, align 8
# |   %9 = load double, ptr %tmp1, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vmul_n_f64(<1 x double> noundef %a, double noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__p1.addr.i = alloca double, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <1 x double>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca double, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   %1 = load double, ptr %b.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   store double %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x double>, ptr %__p0.addr.i, align 8
# |   %3 = load double, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <1 x double> %2 to double
# |   %5 = fmul double %4, %3
# |   store double %5, ptr %ref.tmp.i, align 8
# |   %6 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %6, ptr %__ret.i, align 8
# |   %7 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmulxs_lane_f32(float noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__p1.addr.i = alloca float, align 4
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <2 x float>, align 8
# |   %__ret_626 = alloca float, align 4
# |   %__s0_626 = alloca float, align 4
# |   %__s1_626 = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_626, align 4
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1_626, align 8
# |   %2 = load float, ptr %__s0_626, align 4
# |   %3 = load <2 x float>, ptr %__s1_626, align 8
# |   store <2 x float> %3, ptr %__s0, align 8
# |   %4 = load <2 x float>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x float> %4, i32 1
# |   store float %vget_lane, ptr %ref.tmp, align 4
# |   %5 = load float, ptr %ref.tmp, align 4
# |   store float %5, ptr %__ret, align 4
# |   %6 = load float, ptr %__ret, align 4
# |   store float %6, ptr %tmp, align 4
# |   %7 = load float, ptr %tmp, align 4
# |   store float %2, ptr %__p0.addr.i, align 4
# |   store float %7, ptr %__p1.addr.i, align 4
# |   %8 = load float, ptr %__p0.addr.i, align 4
# |   %9 = load float, ptr %__p1.addr.i, align 4
# |   %vmulxs_f32.i = call float @llvm.aarch64.neon.fmulx.f32(float %8, float %9)
# |   store float %vmulxs_f32.i, ptr %ref.tmp.i, align 4
# |   %10 = load float, ptr %ref.tmp.i, align 4
# |   store float %10, ptr %__ret.i, align 4
# |   %11 = load float, ptr %__ret.i, align 4
# |   store float %11, ptr %__ret_626, align 4
# |   %12 = load float, ptr %__ret_626, align 4
# |   store float %12, ptr %tmp1, align 4
# |   %13 = load float, ptr %tmp1, align 4
# |   ret float %13
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmulxs_laneq_f32(float noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__p1.addr.i = alloca float, align 4
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <4 x float>, align 16
# |   %__ret_636 = alloca float, align 4
# |   %__s0_636 = alloca float, align 4
# |   %__s1_636 = alloca <4 x float>, align 16
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <4 x float>, align 16
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_636, align 4
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %1, ptr %__s1_636, align 16
# |   %2 = load float, ptr %__s0_636, align 4
# |   %3 = load <4 x float>, ptr %__s1_636, align 16
# |   store <4 x float> %3, ptr %
# | ...
# `---data was truncated (10240/74804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055db961cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055db961cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055db961cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2907f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2907f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2907f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2907f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db96164e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055db96164c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055db96149b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055db95df90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055db95df8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2907f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2907f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2907f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db95df8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c (365 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip1q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip1q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip1q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip1q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip1q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip1q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip1q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip1q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip1q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip1q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzip1_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zip1q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zip1q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557911f9e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557911f9b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557911f9e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f690dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f690dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f690dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f690dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557911f33e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557911f33c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557911f18b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557911bc80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557911bc7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f690dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f690dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f690dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557911bc7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c (366 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_cvtn_f16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fcvtn.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcvtn.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_cvtn_bf16_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvtn.x2(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvtn.x2(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_qcvtn_u8_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqcvtn.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqcvtn.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_u16_u64_x4(<vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zn.coerce2, <vscale x 2 x i64> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %zn.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 1
# |   %7 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 2
# |   %8 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 3
# |   %9 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x4.nxv2i64(<vscale x 2 x i64> %5, <vscale x 2 x i64> %6, <vscale x 2 x i64> %7, <vscale x 2 x i64> %8)
# |   ret <vscale x 8 x i16> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_qcvtn_s8_s32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtn.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtn.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_loc
# | ...
# `---data was truncated (10240/17734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000556d1580d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556d1580a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556d1580d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5580133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f558018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5580133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f558011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d157a2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556d157a2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556d15787b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556d154370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556d15436dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f558011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f558011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f558011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d15436cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon-2velem.c (367 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-2velem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmla_lane_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %v.addr = alloca <4 x i16>, align 8
# |   %__ret_72 = alloca <4 x i16>, align 8
# |   %__s0_72 = alloca <4 x i16>, align 8
# |   %__s1_72 = alloca <4 x i16>, align 8
# |   %__s2_72 = alloca <4 x i16>, align 8
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %v, ptr %v.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_72, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_72, align 8
# |   %2 = load <4 x i16>, ptr %v.addr, align 8
# |   store <4 x i16> %2, ptr %__s2_72, align 8
# |   %3 = load <4 x i16>, ptr %__s0_72, align 8
# |   %4 = load <4 x i16>, ptr %__s1_72, align 8
# |   %5 = load <4 x i16>, ptr %__s2_72, align 8
# |   store <4 x i16> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   %mul = mul <4 x i16> %4, %10
# |   %add = add <4 x i16> %3, %mul
# |   store <4 x i16> %add, ptr %__ret_72, align 8
# |   %11 = load <4 x i16>, ptr %__ret_72, align 8
# |   store <4 x i16> %11, ptr %tmp1, align 8
# |   %12 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmlaq_lane_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <4 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %v.addr = alloca <4 x i16>, align 8
# |   %__ret_62 = alloca <8 x i16>, align 16
# |   %__s0_62 = alloca <8 x i16>, align 16
# |   %__s1_62 = alloca <8 x i16>, align 16
# |   %__s2_62 = alloca <4 x i16>, align 8
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   %tmp1 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   store <4 x i16> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_62, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %1, ptr %__s1_62, align 16
# |   %2 = load <4 x i16>, ptr %v.addr, align 8
# |   store <4 x i16> %2, ptr %__s2_62, align 8
# |   %3 = load <8 x i16>, ptr %__s0_62, align 16
# |   %4 = load <8 x i16>, ptr %__s1_62, align 16
# |   %5 = load <4 x i16>, ptr %__s2_62, align 8
# |   store <4 x i16> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   store <8 x i16> %lane, ptr %ref.tmp, align 16
# |   %8 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %8, ptr %__ret, align 16
# |   %9 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %9, ptr %tmp, align 16
# |   %10 = load <8 x i16>, ptr %tmp, align 16
# |   %mul = mul <8 x i16> %4, %10
# |   %add = add <8 x i16> %3, %mul
# |   store <8 x i16> %add, ptr %__ret_62, align 16
# |   %11 = load <8 x i16>, ptr %__ret_62, align 16
# |   store <8 x i16> %11, ptr %tmp1, align 16
# |   %12 = load <8 x i16>, ptr %tmp1, align 16
# |   ret <8 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vmla_lane_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %v.addr = alloca <2 x i32>, align 8
# |   %__ret_70 = alloca <2 x i32>, align 8
# |   %__s0_70 = alloca <2 x i32>, align 8
# |   %__s1_70 = alloca <2 x i32>, align 8
# |   %__s2_70 = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp1 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <2 x i32> %v, ptr %v.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_70, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %1, ptr %__s1_70, align 8
# |   %2 = load <2 x i32>, ptr %v.addr, align 8
# |   store <2 x i32> %2, ptr %__s2_70, align 8
# |   %3 = load <2 x i32>, ptr %__s0_70, align 8
# |   %4 = load <2 x i32>, ptr %__s1_70, align 8
# |   %5 = load <2 x i32>, ptr %__s2_70, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> <i32 1, i32 1>
# |   store <2 x i32> %lane, ptr %ref.tmp, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   %mul = mul <2 x i32> %4, %10
# |   %add = add <2 x i32> %3, %mul
# |   store <2 x i32> %add, ptr %__ret_70, align 8
# |   %11 = load <2 x i32>, ptr %__ret_70, align 8
# |   store <2 x i32> %11, ptr %tmp1, align 8
# |   %12 = load <2 x i32>, ptr %tmp1, align 8
# |   ret <2 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmlaq_lane_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <2 x i32> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %v.addr = alloca <2 x i32>, align 8
# |   %__ret_60 = alloca <4 x i32>, align 16
# |   %__s0_60 = alloca <4 x i32>, align 16
# |   %__s1_60 = alloca <4 x i32>, align 16
# |   %__s2_60 = alloca <2 x i32>, align 8
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   %tmp1 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   store <2 x i32> %v, ptr %v.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0_60, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %1, ptr %__s1_60, align 16
# |   %2 = load <2 x i32>, ptr %v.addr, align 8
# |   store <2 x i32> %2, ptr %__s2_60, align 8
# |   %3 = load <4 x i32>, ptr %__s0_60, align 16
# |   %4 = load <4 x i32>, ptr %__s1_60, align 16
# |   %5 = load <2 x i32>, ptr %__s2_60, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
# |   store <4 x i32> %lane, ptr %ref.tmp, align 16
# |   %8 = load <4 x i32>, ptr %ref.tmp, align 16
# |   store <4 x i32> %8, ptr %__ret, align 16
# |   %9 = load <4 x i32>, ptr %__ret, align 16
# |   store <4 x i32> %9, ptr %tmp, align 16
# |   %10 = load <4 x i32>, ptr %tmp, align 16
# |   %mul = mul <4 x i32> %4, %10
# |   %add = add <4 x i32> %3, %mul
# |   store <4 x i32> %add, ptr %__ret_60, align 16
# |   %11 = load <4 x i32>, ptr %__ret_60, align 16
# |   store <4 x i32> %11, ptr %tmp1, align 16
# |   %12 = load <4 x i32>, ptr %tmp1, align 16
# |   ret <4 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmla_laneq_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_482 = alloca <4 x i16>, align 8
# |   %__s0_482 = alloca <4 x i16>, align 8
# |   %__s1_482 = alloca <4 x i16>, align 8
# |   %__s2_482 = alloca <8 x i16>, align 16
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_482, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_482, align 8
# |   %2 = load <8 x i16>, ptr %v.addr, align 16
# |   store <8 x i16> %2, ptr %__s2_482, align 16
# |   %3 = load <4 x i16>, ptr %__s0_482, align 8
# |   %4 = load <4 x i16>, ptr %__s1_482, align 8
# |   %5 = load <8 x i16>, ptr %__s2_482, align 16
# |   store <8 x i16> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <8 x i16>
# |   %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   %mul = mul <4 x i16> %4, %10
# |   %add = add <4 x i16> %3, %mul
# |   store <4 x i16> %add, ptr %__ret_482, align 8
# |   %11 = load <4 x i16>, ptr %__ret_482, align 8
# |   store <4 x i16> %11, ptr %tmp1, align 8
# |   %12 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmlaq_laneq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_472 = alloca <8 x i16>, align 16
# |   %__s0_472 = alloca <8 x i16>, align 16
# |   %__s1_472 = alloca <8
# | ...
# `---data was truncated (10240/857511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055af153bb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055af153b80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055af153bb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cc4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cc42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cc4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cc4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af15350e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055af15350c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055af15335b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055af14fe50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055af14fe4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4cc4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cc42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cc42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af14fe4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c (368 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpne_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_r
# | ...
# `---data was truncated (10240/34127) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d367ef015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d367eed0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d367ef089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00e9d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00e9d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00e9d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00e9ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d367e85e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d367e85c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d367e6ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d367b1a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d367b19dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f00e9ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00e9cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00e9cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d367b19cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c (369 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556271fe815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556271fe50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556271fe889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe201c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe201ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe201c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe201c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556271f7de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556271f7dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556271f62b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556271c120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556271c11dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe201c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe201c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe201c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556271c11cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c (370 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld2_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld2_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld2_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld2_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svld2_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld2.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svld2_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld2.sret.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld2.sret.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svld2_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.ld2.sret.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm
# | ...
# `---data was truncated (10240/24404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f295c3f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f295c3c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f295c3f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff621849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6218a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff621849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff621831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f295bd4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f295bd4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f295bb9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f2958690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f295868dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff621832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6218330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6218330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f295868cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/orv.c (371 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/orv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svorv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.orv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.orv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svorv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.orv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.orv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svorv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svorv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.orv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.orv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svorv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.orv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svorv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.orv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svorv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svorv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.orv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055d9163c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d9163c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d9163c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3810533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f381058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3810533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f381051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d91635ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d91635ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d91633fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d915fef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d915feedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f381051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f381051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f381051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d915feecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c (372 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p3 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p3 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_s16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sdot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sdot.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_u16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.udot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.udot.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_n_s16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sdot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_n_u16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, i8 noundef %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca i8, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store i8 %op3, ptr %op3.addr, align 1
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load i8, ptr %op3.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.udot.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_lane_s16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sdot.lane.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sdot.lane.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdot_lane_u16_x2(<vscale x 8 x i16> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.udot.lane.x2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.udot.lane.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p3" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005609d5dce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005609d5dcb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005609d5dce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0513333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f051338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0513333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f051331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609d5d63e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005609d5d63c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005609d5d48b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005609d59f80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005609d59f7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f051331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f051331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f051331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609d59f7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/intrinsics.c (373 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmaxnmv_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %vmaxnmv_f32.i = call float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float> %1)
# |   store float %vmaxnmv_f32.i, ptr %ref.tmp.i, align 4
# |   %2 = load float, ptr %ref.tmp.i, align 4
# |   store float %2, ptr %__ret.i, align 4
# |   %3 = load float, ptr %__ret.i, align 4
# |   ret float %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vmaxnmvq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %vmaxnmvq_f32.i = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> %1)
# |   store float %vmaxnmvq_f32.i, ptr %ref.tmp.i, align 4
# |   %2 = load float, ptr %ref.tmp.i, align 4
# |   store float %2, ptr %__ret.i, align 4
# |   %3 = load float, ptr %__ret.i, align 4
# |   ret float %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vmaxnmvq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca double, align 8
# |   %ref.tmp.i = alloca double, align 8
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %vmaxnmvq_f64.i = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> %1)
# |   store double %vmaxnmvq_f64.i, ptr %ref.tmp.i, align 8
# |   %2 = load double, ptr %ref.tmp.i, align 8
# |   store double %2, ptr %__ret.i, align 8
# |   %3 = load double, ptr %__ret.i, align 8
# |   ret double %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vqrshrunh_n_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %vqrshrunh_n_s16 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %2, i32 8)
# |   %3 = extractelement <8 x i8> %vqrshrunh_n_s16, i64 0
# |   store i8 %3, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret, align 1
# |   %5 = load i8, ptr %__ret, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vqrshruns_n_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %vqrshruns_n_s32 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %2, i32 16)
# |   %3 = extractelement <4 x i16> %vqrshruns_n_s32, i64 0
# |   store i16 %3, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret, align 2
# |   %5 = load i16, ptr %__ret, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vqrshrnh_n_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %vqrshrnh_n_s16 = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %2, i32 8)
# |   %3 = extractelement <8 x i8> %vqrshrnh_n_s16, i64 0
# |   store i8 %3, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret, align 1
# |   %5 = load i8, ptr %__ret, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vqrshrns_n_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %vqrshrns_n_s32 = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %2, i32 16)
# |   %3 = extractelement <4 x i16> %vqrshrns_n_s32, i64 0
# |   store i16 %3, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret, align 2
# |   %5 = load i16, ptr %__ret, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vqrshrnh_n_u16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %vqrshrnh_n_u16 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %2, i32 8)
# |   %3 = extractelement <8 x i8> %vqrshrnh_n_u16, i64 0
# |   store i8 %3, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret, align 1
# |   %5 = load i8, ptr %__ret, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vqrshrns_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %vqrshrns_n_u32 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %2, i32 16)
# |   %3 = extractelement <4 x i16> %vqrshrns_n_u32, i64 0
# |   store i16 %3, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret, align 2
# |   %5 = load i16, ptr %__ret, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqrshrun_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %__s0, align 16
# |   %vqrshrun_n = bitcast <16 x i8> %1 to <8 x i16>
# |   %vqrshrun_n1 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %vqrshrun_n, i32 3)
# |   store <8 x i8> %vqrshrun_n1, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrshrun_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %__s0, align 16
# |   %vqrshrun_n = bitcast <16 x i8> %1 to <4 x i32>
# |   %vqrshrun_n1 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %vqrshrun_n, i32 9)
# |   store <4 x i16> %vqrshrun_n1, ptr %ref.tmp, align 8
# |   %2 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %2, ptr %__ret, align 8
# |   %3 = load <4 x i16>, p
# | ...
# `---data was truncated (10240/770739) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055d87777315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d8777700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d87777389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93c3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93c398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93c3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93c391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d877708e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d877708c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d8776edb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d87739d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d87739cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f93c391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93c391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93c391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d87739ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c (374 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrinta_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrinta_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x4.nxv4f32(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrintam_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrintm_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x4.nxv4f32(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svfrintn_f32_x2(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintn.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn me
# | ...
# `---data was truncated (10240/17932) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000562a5080415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562a508010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562a5080489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cdda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cddaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cdda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cdda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a50799e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562a50799c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562a5077eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562a5042e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562a5042ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4cdda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cdda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cdda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a5042dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c (375 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt_bf16_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt_bf16_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvt_bf16_f32_m(<vscale x 8 x bfloat> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 8 x bfloat> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556fb385715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556fb38540f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556fb385789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1dd701bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1dd70725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1dd701ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1dd7003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556fb37ece2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556fb37ecc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556fb37d1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556fb34810b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556fb3480dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1dd7004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1dd70050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1dd70050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556fb3480cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c (376 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 1
# |   %8 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 0
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 1
# |   call void @llvm.aarch64.sme.fmls.vg1x2.nxv4f32(i32 %4, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %9, <vscale x 4 x float> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmls.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1, <vscale x 4 x float> %zm.coerce2, <vscale x 4 x float> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, <vscale x 4 x float> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %5, <vscale x 4 x float> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, <vscale x 4 x float> %zm.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 0
# |   %11 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 1
# |   %12 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 2
# |   %13 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 3
# |   %14 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 0
# |   %16 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 1
# |   %17 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 2
# |   %18 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 3
# |   call void @llvm.aarch64.sme.fmls.vg1x4.nxv4f32(i32 %8, <vscale x 4 x float> %10, <vscale x 4 x float> %11, <vscale x 4 x float> %12, <vscale x 4 x float> %13, <vscale x 4 x float> %15, <vscale x 4 x float> %16, <vscale x 4 x float> %17, <vscale x 4 x float> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmls.vg1x4.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 1
# |   %6 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv4f32(i32 %2, <vscale x 4 x float> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmls.single.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls_single4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x flo
# | ...
# `---data was truncated (10240/34546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000555f6e9b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555f6e9ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555f6e9b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02d6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02d6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02d6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02d6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f6e946e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555f6e946c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555f6e92bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555f6e5db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555f6e5dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f02d6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02d6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02d6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f6e5dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c (377 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg1x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg1x2(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg1x2(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg1x4(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg1x4(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg1x4(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg2x1(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg2x1(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg2x1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg2x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg2x2(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg2x2(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg2x4(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg2x4(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg2x4(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg4x1(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg4x1(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg4x1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg4x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg4x2(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg4x2(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svzero_za64_vg4x4(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   call void @llvm.aarch64.sme.zero.za64.vg4x4(i32 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write)
# | declare void @llvm.aarch64.sme.zero.za64.vg4x4(i32) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sme2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055ba24c0a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ba24c070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ba24c0a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1625e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1625e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1625e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1625e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba24b9fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ba24b9fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ba24b84b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ba248340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ba24833dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1625e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1625e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1625e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba24833cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c (378 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function
# | ...
# `---data was truncated (10240/100281) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8c84e115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b8c84de0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b8c84e189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b70933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b7098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b70933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b7091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8c8476e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b8c8476c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b8c845bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b8c810b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b8c810add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8b7091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b7091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b7091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8c810acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c (379 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd
# | ...
# `---data was truncated (10240/110070) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ed046815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563ed04650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563ed046889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d55f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d55f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d55f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d55eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ed03fde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563ed03fdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563ed03e2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563ed00920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563ed0091dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1d55eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d55eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d55eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ed0091cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c (380 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svorr_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svorr_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svorr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svorr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svorr_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svorr_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svorr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svorr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svorr_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557fc41d715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557fc41d40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557fc41d789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4feee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4feeea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4feee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4feee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fc416ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557fc416cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557fc4151b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557fc3e010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557fc3e00dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4feee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4feee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4feee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fc3e00cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c (381 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 1
# |   %8 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 1
# |   call void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8f16(i32 %4, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %9, <vscale x 8 x half> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_bf16(i32 noundef %slice_base, <vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, 1
# |   %8 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %8, 1
# |   call void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8bf16(i32 %4, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %9, <vscale x 8 x bfloat> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8bf16(i32, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_u16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.umlsl.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.umlsl.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls2_s16(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   call void @llvm.aarch64.sme.smlsl.vg2x2.nxv8i16(i32 %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.smlsl.vg2x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmls4
# | ...
# `---data was truncated (10240/73614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055aec9b4a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aec9b470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aec9b4a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5c6705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5c675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5c6705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5c66ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aec9adfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aec9adfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aec9ac4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aec97740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aec9773dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa5c66eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5c66ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5c66ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aec9773cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c (382 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ff093815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561ff09350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561ff093889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd563d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd563d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd563d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd563d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ff08cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561ff08cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561ff08b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561ff05620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561ff0561dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd563d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd563d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd563d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ff0561cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c (383 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmin_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smin.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smin.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmin_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smin.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smin.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svmin_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smin.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smin.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svmin_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smin.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smin.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svmin_single_u8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umin.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umin.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svmin_single_u16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umin.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umin.single.x
# | ...
# `---data was truncated (10240/142195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a34711d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a34711a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a34711d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ca9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ca96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ca9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ca9631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3470b2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a3470b2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a347097b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a346d470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a346d46dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7ca9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ca96330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ca96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a346d46cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c (384 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bf
# | ...
# `---data was truncated (10240/65202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555711cd615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555711cd30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555711cd689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc402e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc402ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc402e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc402e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555711c6be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555711c6bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555711c50b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005557119000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005557118ffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc402e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc402e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc402e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557118ffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c (385 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrb_u32base_s32offset(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %offsets.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrb_u64base_s64offset(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrb_u32base_u32offset(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %offsets.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrb.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrb_u64base_u64offset(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrb.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560c13bae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560c13bab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560c13bae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d98049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d980a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d98049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d98031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c13b43e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560c13b43c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560c13b28b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560c137d80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560c137d7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3d98032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d980330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d980330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c137d7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c (386 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale 
# | ...
# `---data was truncated (10240/30627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b82ca315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561b82ca00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561b82ca389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe969a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe969a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe969a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe969a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b82c38e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561b82c38c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561b82c1db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561b828cd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561b828ccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe969a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe969a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe969a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b828cccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c (387 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svld1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ld1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ld1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1_vnum_s8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = 
# | ...
# `---data was truncated (10240/63749) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000564625aa715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564625aa40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564625aa789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7314133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f731418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7314133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f731411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564625a3ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564625a3cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564625a21b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005646256d10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005646256d0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f731411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f731411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f731411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646256d0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/maxv.c (388 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/maxv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svmaxv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.smaxv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.smaxv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svmaxv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.smaxv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.smaxv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svmaxv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.smaxv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.smaxv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svmaxv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.smaxv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.smaxv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svmaxv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.umaxv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.umaxv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svmaxv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.umaxv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.umaxv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svmaxv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.umaxv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.umaxv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svmaxv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.umaxv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.umaxv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svmaxv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fmaxv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fmaxv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svmaxv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fmaxv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fmaxv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svmaxv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fmaxv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fmaxv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attribute
# | ...
# `---data was truncated (10240/10818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000558ace43115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558ace42e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558ace43189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82bed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82bed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82bed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82bed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ace3c6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558ace3c6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558ace3abb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558ace05b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558ace05add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f82bed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82bed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82bed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ace05acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c (389 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget2_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget2_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget2_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget2_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svget2_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svget2_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svget2_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svget2_u64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svget2_f16(<vscale x 8 x half> %tuple.coerce0, <vscale x 8 x half> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %tuple.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %tuple, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svget2_f32(<vscale x 4 x float> %tuple.coerce0, <vscale x 4 x float> %tuple.coerce1) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %tuple.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %tuple, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %tuple1, ptr %tuple.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %tuple.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | d
# | ...
# `---data was truncated (10240/14679) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d0f62d915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d0f62d60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d0f62d989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b87733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b8778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b87733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b8771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0f626ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d0f626ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d0f6253b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d0f5f030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d0f5f02dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9b8771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b8771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b8771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0f5f02cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c (390 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-f16f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-f16f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_f32f16(<vscale x 4 x float> %acc, <vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 4 x float>, align 16
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 4 x float> %acc, ptr %acc.addr, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16(<vscale x 4 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-f16f32mm" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005617903d615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005617903d30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005617903d689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35faf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35faf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35faf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35faeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056179036be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056179036bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561790350b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005617900000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056178ffffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f35faeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35faeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35faeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056178ffffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c (391 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svadda_f16(<vscale x 16 x i1> %pg, half noundef %initial, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %initial.addr = alloca half, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store half %initial, ptr %initial.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load half, ptr %initial.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call half @llvm.aarch64.sve.fadda.nxv8f16(<vscale x 8 x i1> %3, half %1, <vscale x 8 x half> %2)
# |   ret half %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fadda.nxv8f16(<vscale x 8 x i1>, half, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svadda_f32(<vscale x 16 x i1> %pg, float noundef %initial, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %initial.addr = alloca float, align 4
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store float %initial, ptr %initial.addr, align 4
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load float, ptr %initial.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call float @llvm.aarch64.sve.fadda.nxv4f32(<vscale x 4 x i1> %3, float %1, <vscale x 4 x float> %2)
# |   ret float %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fadda.nxv4f32(<vscale x 4 x i1>, float, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svadda_f64(<vscale x 16 x i1> %pg, double noundef %initial, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %initial.addr = alloca double, align 8
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store double %initial, ptr %initial.addr, align 8
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load double, ptr %initial.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call double @llvm.aarch64.sve.fadda.nxv2f64(<vscale x 2 x i1> %3, double %1, <vscale x 2 x double> %2)
# |   ret double %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fadda.nxv2f64(<vscale x 2 x i1>, double, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055aa147b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aa147ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aa147b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a93f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a93f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a93f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a93f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa14746e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aa14746c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aa1472bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aa143db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aa143dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0a93f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a93f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a93f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa143dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c (392 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facgt.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %2, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %2, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facgt.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %.splat, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svaclt_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facgt.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %.splat, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f86e01f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f86e01c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f86e01f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad30105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad3015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad30105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad300ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f86dfb4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f86dfb4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f86df99b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f86dc490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f86dc48dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fad300eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad300ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad300ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f86dc48cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c (393 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpfirst_b(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563ecb4f715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563ecb4f40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563ecb4f789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5936249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59362a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5936249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5936231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ecb48ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563ecb48cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563ecb471b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563ecb1210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563ecb120dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5936232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59362330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59362330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ecb120cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c (394 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x flo
# | ...
# `---data was truncated (10240/78024) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609b94d715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005609b94d40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005609b94d789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd84533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd8458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd84533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd8451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609b946ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005609b946cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005609b9451b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005609b91010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005609b9100dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcd8451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd8451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd8451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609b9100cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c (395 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2.nxv8i16.p0(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data.coerce0, <vscale x 4 x i32> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %data.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2.nxv4i32.p0(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data.coerce0, <vscale x 2 x i64> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %data.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 1
# |   %7 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2.nxv2i64.p0(<vscale x 2 x i64> %5, <vscale x 2 x i64> %6, <vscale x 2 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> }
# | ...
# `---data was truncated (10240/45653) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e2de2f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e2de2f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e2de2f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47f3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47f32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47f3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47f3231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2de28de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e2de28dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e2de272b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e2ddf220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e2ddf21dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f47f3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47f32330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47f32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2ddf21cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c (396 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsr_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsr_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsr_u8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svlsr_u16_m(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svlsr_u32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svlsr_u64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svlsr_u8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.u.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# | 
# | ...
# `---data was truncated (10240/33353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005644694bc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005644694b90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005644694bc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5bdf733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5bdf78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5bdf733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5bdf71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564469451e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564469451c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564469436b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005644690e60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005644690e5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5bdf71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5bdf71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5bdf71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644690e5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c (397 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr
# | ...
# `---data was truncated (10240/424049) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d0587d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558d0587a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558d0587d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1818b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1818b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1818b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1818b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d05812e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558d05812c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558d057f7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558d054a70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558d054a6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1818b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1818b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1818b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d054a6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c (398 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti4_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti4_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti4_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti4_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti4_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svluti4_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svluti4_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti4_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti4_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svluti4_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055651127415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005565112710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055651127489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8631c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8631ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8631c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8631c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556511209e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556511209c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005565111eeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556510e9e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556510e9ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8631c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8631c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8631c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556510e9dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vorrq.c (399 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vorrq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = or <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = or <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = or <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vorrq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = or <4 x i32> %1, %3
# |   %5 = bitcast <4 x i32> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vorrq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vorrq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5)
# |   %7 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32
# | ...
# `---data was truncated (10240/10897) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9f8bfd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e9f8bfa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e9f8bfd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd89705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd8975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd89705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd896ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9f8b92e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e9f8b92c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e9f8b77b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e9f88270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e9f8826dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efd896eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd896ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd896ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9f8826cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c (400 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinti_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinti_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinti_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinti_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinti_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinti_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrinti_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frinti.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrinti_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrinti_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frinti.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005562bf9e515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005562bf9e20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005562bf9e589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc012705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc01275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc012705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0126ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562bf97ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005562bf97ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005562bf95fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005562bf60f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005562bf60edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc0126eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0126ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0126ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562bf60ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c (401 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti4_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti4_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti4_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti4_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti4_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti4_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti4_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti4_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000564faadda15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564faadd70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564faadda89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2484649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24846a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2484649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2484631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564faad6fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564faad6fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564faad54b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564faaa040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564faaa03dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2484632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24846330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24846330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564faaa03cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c (402 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_s8_x4(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn1.coerce0, <vscale x 16 x i8> %zn1.coerce1, <vscale x 16 x i8> %zn1.coerce2, <vscale x 16 x i8> %zn1.coerce3, <vscale x 16 x i8> %zn2.coerce0, <vscale x 16 x i8> %zn2.coerce1, <vscale x 16 x i8> %zn2.coerce2, <vscale x 16 x i8> %zn2.coerce3) #0 {
# | entry:
# |   %zn1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn1.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn1.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn1.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn1.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn1, align 16
# |   %zn11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn2.coerce0, 0
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %zn2.coerce1, 1
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, <vscale x 16 x i8> %zn2.coerce2, 2
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %zn2.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7, ptr %zn2, align 16
# |   %zn22 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn11, ptr %zn1.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn22, ptr %zn2.addr, align 16
# |   %8 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %9 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1.addr, align 16
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 0
# |   %11 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 1
# |   %12 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 2
# |   %13 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, 3
# |   %14 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2.addr, align 16
# |   %15 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 0
# |   %16 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 1
# |   %17 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 2
# |   %18 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %14, 3
# |   %19 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount") %8, <vscale x 16 x i8> %10, <vscale x 16 x i8> %11, <vscale x 16 x i8> %12, <vscale x 16 x i8> %13, <vscale x 16 x i8> %15, <vscale x 16 x i8> %16, <vscale x 16 x i8> %17, <vscale x 16 x i8> %18)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %19
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount"), <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_u8_x4(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn1.coerce0, <vscale x 16 x i8> %zn1.coerce1, <vscale x 16 x i8> %zn1.coerce2, <vscale x 16 x i8> %zn1.coerce3, <vscale x 16 x i8> %zn2.coerce0, <vscale x 16 x i8> %zn2.coerce1, <vscale x 16 x i8> %zn2.coerce2, <vscale x 16 x i8> %zn2.coerce3, ptr nofreeobj noundef align 16 dead_on_return %0, ptr nofreeobj noundef align 16 dead_on_return %1) #0 {
# | entry:
# |   %zn1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn2.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn3.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn4.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn1.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn1.coerce1, 1
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %zn1.coerce2, 2
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %zn1.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, ptr %zn1, align 16
# |   %zn11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1, align 16
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn2.coerce0, 0
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %zn2.coerce1, 1
# |   %8 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7, <vscale x 16 x i8> %zn2.coerce2, 2
# |   %9 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %8, <vscale x 16 x i8> %zn2.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9, ptr %zn2, align 16
# |   %zn22 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2, align 16
# |   %zn3 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %0, align 16
# |   %zn4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %1, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn11, ptr %zn1.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn22, ptr %zn2.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn3, ptr %zn3.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn4, ptr %zn4.addr, align 16
# |   %10 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn1.addr, align 16
# |   %12 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 0
# |   %13 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 1
# |   %14 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 2
# |   %15 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %11, 3
# |   %16 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn2.addr, align 16
# |   %17 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 0
# |   %18 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 1
# |   %19 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 2
# |   %20 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %16, 3
# |   %21 = call { <vscale x 16 x i8>, <vscale x 16 
# | ...
# `---data was truncated (10240/73319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# |  #0 0x00005622a15c815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005622a15c50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005622a15c889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b7d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b7d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b7d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b7d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622a155de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005622a155dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005622a1542b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005622a11f20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005622a11f1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3b7d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b7d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b7d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622a11f1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c (403 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq1_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq1_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zipq1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq1_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zipq1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq1_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zipq1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq1_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq1_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq1_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq1_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzipq1_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zipq1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zipq1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzipq1_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zipq1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zipq1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzipq1_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zipq1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zipq1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzipq1_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq1.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq1.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq1_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055be9359915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055be935960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055be9359989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87ad533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87ad58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87ad533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87ad51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be9352ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055be9352ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055be93513b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055be931c30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055be931c2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f87ad51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87ad51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87ad51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be931c2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c (404 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef2_s8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef2_s16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef2_s32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef2_s64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef2_u8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef2_u16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef2_u32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef2_u64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svundef2_f16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svundef2_f32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svundef2_f64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef2_mf8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svundef2_bf16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a0d06cc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a0d06c90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a0d06cc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c1a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c1a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c1a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c1a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0d0661e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a0d0661c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a0d0646b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a0d02f60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a0d02f5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4c1a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c1a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c1a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0d02f5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c (405 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %
# | ...
# `---data was truncated (10240/280171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f0e30a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562f0e3070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562f0e30a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd29cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd29cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd29cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd29cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f0e29fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562f0e29fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562f0e284b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562f0df340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562f0df33dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd29cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd29cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd29cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f0df33cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c (406 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_bf16_vg1x2(i32 noundef %slice_base, <vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, 1
# |   %6 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8bf16(i32 %2, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8bf16(i32, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_f16_vg1x2(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 1
# |   %6 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8f16(i32 %2, <vscale x 8 x half> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_s16_vg1x2(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 1
# |   %6 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.svdot.lane.za32.vg1x2.nxv8i16(i32 %2, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.svdot.lane.za32.vg1x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_u16_vg1x2(i32 noundef %slice_base, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, 1
# |   %6 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.uvdot.lane.za32.vg1x2.nxv8i16(i32 %2, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.uvdot.lane.za32.vg1x2.nxv8i16(i32, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za32_s8_vg1x4(i32 noundef %slice_base, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.svdot.lane.za32.vg1x4.nxv16i8(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.svdot.lane.za32.vg1x4.nxv16i8(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | ...
# `---data was truncated (10240/24605) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557431f2e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557431f2b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557431f2e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd033e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd033ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd033e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd033e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557431ec3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557431ec3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557431ea8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557431b580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557431b57dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd033e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd033e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd033e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557431b57cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c (407 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq2_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq2_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zipq2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq2_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zipq2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq2_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zipq2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq2_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzipq2_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zipq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzipq2_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zipq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzipq2_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zipq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzipq2_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zipq2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zipq2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzipq2_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zipq2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zipq2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzipq2_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zipq2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zipq2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzipq2_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq2.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zipq2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzipq2_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zipq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005589887f715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005589887f40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005589887f789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83fd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83fd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83fd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83fd231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055898878ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055898878cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558988771b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005589884210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558988420dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f83fd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83fd2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83fd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558988420cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c (408 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclz_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclz_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclz_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclz_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclz_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclz_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclz_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclz_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclz_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclz_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclz_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscal
# | ...
# `---data was truncated (10240/21295) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559542cd915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559542cd60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559542cd989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e3cf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e3cf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e3cf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e3ceed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559542c6ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559542c6ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559542c53b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005595429030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559542902dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1e3ceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e3ceef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e3ceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559542902cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c (409 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldff1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ldff1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldff1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldff1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldff1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svldff1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ldff1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ldff1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svldff1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ldff1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ldff1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svldff1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ldff1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ldff1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldff1_vnum_mf8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# | 
# | ...
# `---data was truncated (10240/64727) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a3305d115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a3305ce0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a3305d189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf78e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf78ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf78e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf78e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a330566e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a330566c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a33054bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a3301fb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a3301fadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdf78e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf78e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf78e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3301facc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c (410 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sb_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sb_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sb_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1sb_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1sb_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/11944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005586841f615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005586841f30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005586841f689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4ec61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4ec6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4ec61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4ec603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055868418be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055868418bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558684170b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558683e200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558683e1fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd4ec604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4ec6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4ec6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558683e1fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c (411 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1ub_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1ub_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1ub_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1ub_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1ub_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/11944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056052cf2215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056052cf1f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056052cf2289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61b0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61b08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61b0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61b0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056052ceb7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056052ceb7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056052ce9cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056052cb4c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056052cb4bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f61b0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61b08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61b08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056052cb4bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c (412 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vset_v_f16m1_f16m2(<vscale x 8 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m1_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m2_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m1_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m2_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m4_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 16 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> %0, <vscale x 16 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half>, <vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vset_v_f32m1_f32m2(<vscale x 4 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m1_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m2_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 4 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> %0, <vscale x 4 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float>, <vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vset_v_f32m1_f32m8(<vscale x 16 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 16 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 16 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x float
# | ...
# `---data was truncated (10240/338684) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ddfd1a515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ddfd1a20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ddfd1a589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23b6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23b6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23b6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23b6c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddfd13ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ddfd13ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ddfd11fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ddfcdcf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ddfcdcedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f23b6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23b6c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23b6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddfcdcecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c (413 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_n_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, i8 noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store i8 %z, ptr %z.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load i8, ptr %z.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_0(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_1(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_2(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusdot_lane_s32_3(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005636c09c315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005636c09c00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005636c09c389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea2bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea2bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea2bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea2bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636c0958e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005636c0958c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005636c093db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005636c05ed0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005636c05ecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fea2bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea2bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea2bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636c05eccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c (414 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_laneq_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8> %0, i32 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_laneq_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_laneq_s16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.laneq.nxv8i16(<vscale x 8 x i16> %0, i32 1)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.dup.laneq.nxv8i16(<vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_laneq_u16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.laneq.nxv8i16(<vscale x 8 x i16> %0, i32 7)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_laneq_s32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.laneq.nxv4i32(<vscale x 4 x i32> %0, i32 2)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.laneq.nxv4i32(<vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_laneq_u32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.laneq.nxv4i32(<vscale x 4 x i32> %0, i32 3)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_laneq_s64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.laneq.nxv2i64(<vscale x 2 x i64> %0, i32 0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.laneq.nxv2i64(<vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_laneq_u64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.laneq.nxv2i64(<vscale x 2 x i64> %0, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdup_laneq_f16(<vscale x 8 x half> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.dup.laneq.nxv8f16(<vscale x 8 x half> %0, i32 4)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.dup.laneq.nxv8f16(<vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdup_laneq_f32(<vscale x 4 x float> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.dup.laneq.nxv4f32(<vscale x 4 x float> %0, i32 1)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.dup.laneq.nxv4f32(<vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svdup_laneq_f64(<vscale x 2 x double> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.dup.laneq.nxv2f64(<vscale x 2 x double> %0, i32 1)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.dup.laneq.nxv2f64(<vscale x 2 x double>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svdup_laneq_bf16(<vscale x 8 x bfloat> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.laneq.nxv8bf16(<vscale x 8 x bfloat> %0, i32 3)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.laneq.nxv8bf16(<vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_laneq_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8> %0, i32 1)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005567a26fe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005567a26fb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005567a26fe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3117049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31170a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3117049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3117031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567a2693e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005567a2693c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005567a2678b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005567a23280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005567a2327dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3117032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31170330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31170330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567a2327cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c (415 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsra_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/98351) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c1162915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557c116260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557c1162989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbcb5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbcb58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbcb5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbcb5831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c115bee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557c115bec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557c115a3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557c112530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557c11252dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbcb5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbcb58330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbcb58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c11252cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c (416 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn1_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.trn1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn1_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn1.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ce431db15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ce431d80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ce431db89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff472105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff47215c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff472105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4720ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce43170e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ce43170c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ce43155b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ce42e050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ce42e04dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff4720eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4720ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4720ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce42e04cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c (417 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/116957) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055588fe8415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055588fe810f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055588fe8489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa859f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa859f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa859f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa859f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055588fe19e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055588fe19c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055588fdfeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055588faae0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055588faaddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa859f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa859f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa859f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055588faadcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c (418 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpeq_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpeq.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_r
# | ...
# `---data was truncated (10240/34127) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005609779db15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005609779d80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005609779db89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc34c105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc34c15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc34c105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc34c0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560977970e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560977970c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560977955b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005609776050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560977604dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc34c0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc34c0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc34c0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560977604cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c (419 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1>, ptr, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = getelementptr <vscale x 16 x i8>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv16i1.p0(<vscale x 16 x i1> %0, ptr %3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfb_gather_s32offset(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, ali
# | ...
# `---data was truncated (10240/16554) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055dce7ae215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dce7adf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dce7ae289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5511333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f551138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5511333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f551131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dce7a77e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dce7a77c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dce7a5cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dce770c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dce770bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f551131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f551131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f551131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dce770bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c (420 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32
# | ...
# `---data was truncated (10240/123655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae2d70415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ae2d7010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ae2d70489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff78533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff7858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff78533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff7851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae2d699e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ae2d699c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ae2d67eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ae2d32e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ae2d32ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007eff7851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff7851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff7851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae2d32dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c (421 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/12235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5cd84f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c5cd84c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c5cd84f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff81ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff81aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff81ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff81ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5cd7e4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c5cd7e4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c5cd7c9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c5cd4790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c5cd478dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff81ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff81ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff81ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5cd478cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c (422 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %
# | ...
# `---data was truncated (10240/215941) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7b15d115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f7b15ce0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f7b15d189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9801333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f980138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9801333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f980131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7b1566e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f7b1566c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f7b154bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f7b11fb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f7b11fadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f980131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f980131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f980131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7b11facc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c (423 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4247bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f4247ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f4247bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc28ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc28eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc28ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc28ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f424752e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f424752c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f424737b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f4243e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f4243e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc28ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc28ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc28ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4243e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c (424 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/205813) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ad7b5d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564ad7b5a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564ad7b5d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f869cb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f869cb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f869cb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f869caed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ad7af2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564ad7af2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564ad7ad7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564ad77870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564ad7786dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f869caeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f869caef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f869caef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ad7786cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c (425 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmmv_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmmv_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmmv_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmmv_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmmv_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmmv_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmmv_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ad6df615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563ad6df30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563ad6df689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b8e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b8e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b8e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b8e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ad6d8be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563ad6d8bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563ad6d70b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563ad6a200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563ad6a1fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2b8e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b8e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b8e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ad6a1fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c (426 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef3_s8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef3_s16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef3_s32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef3_s64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef3_u8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef3_u16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef3_u32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef3_u64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svundef3_f16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svundef3_f32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @test_svundef3_f64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef3_mf8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svundef3_bf16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a3e191215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a3e190f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a3e191289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f785b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f785b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f785b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f785b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3e18a7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a3e18a7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a3e188cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a3e153c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a3e153bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f785b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f785b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f785b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3e153bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/maxnmv.c (427 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/maxnmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svmaxnmv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fmaxnmv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fmaxnmv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svmaxnmv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fmaxnmv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fmaxnmv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svmaxnmv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fmaxnmv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fmaxnmv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055ce41bc615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ce41bc30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ce41bc689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c93733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c9378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c93733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c9371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce41b5be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ce41b5bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ce41b40b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ce417f00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ce417efdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1c9371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c9371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c9371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce417efcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c (428 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmulh_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.smulh.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.smulh.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmulh_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.smulh.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.smulh.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmulh_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.smulh.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smulh.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmulh_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.smulh.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.smulh.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmulh_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.umulh.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.umulh.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmulh_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.umulh.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.umulh.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmulh_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.umulh.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.umulh.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmulh_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vsca
# | ...
# `---data was truncated (10240/53696) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005560ff1c015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005560ff1bd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005560ff1c089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4461f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4461f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4461f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4461f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560ff155e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005560ff155c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005560ff13ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005560fedea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005560fede9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4461f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4461f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4461f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560fede9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c (429 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn2_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn2.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.trn2.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svtrn2_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.trn2.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055956966615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005595696630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055956966689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff4a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff4a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff4a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff4a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595695fbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005595695fbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005595695e0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005595692900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055956928fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007eff4a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff4a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff4a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055956928fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c (430 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti2_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti2_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti2_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 3)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000564b8467a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564b846770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564b8467a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fece6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fece6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fece6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fece6e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b8460fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564b8460fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564b845f4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564b842a40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564b842a3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fece6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fece6e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fece6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b842a3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c (431 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1>, ptr, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %2, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i16>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv8i1.p0(<vscale x 8 x i1> %3, ptr %4, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfh_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64
# | ...
# `---data was truncated (10240/18010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557656b2d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557656b2a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557656b2d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fedd3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fedd358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fedd3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fedd351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557656ac2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557656ac2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557656aa7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005576567570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557656756dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fedd351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fedd351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fedd351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557656756cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c (432 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 0)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z_1(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 90)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z_2(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 180)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_z_3(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 270)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svcmla_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 0)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fcmla.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svcmla_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fcmla.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 90)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fcmla.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcmla_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale
# | ...
# `---data was truncated (10240/21122) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e2beff415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e2beff10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e2beff489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad54733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad5478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad54733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad5471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2bef89e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e2bef89c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e2bef6eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e2bec1e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e2bec1ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fad5471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad5471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad5471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2bec1dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c (433 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_single_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_single_f16_x4(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zdn.coerce2, <vscale x 8 x half> %zdn.coerce3, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zdn.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 3
# |   %9 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x4.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.single.x4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_f16_x2(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %7, 1
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.x2.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %8, <vscale x 8 x half> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmul.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svmul_f16_x4(<vscale x 8 x half> %zdn.coerce0, <vscale x 8 x half> %zdn.coerce1, <vscale x 8 x half> %zdn.coerce2, <vscale x 8 x half> %zdn.coerce3, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1, <vscale x 8 x half> %zm.coerce2, <vscale x 8 x half> %zm.coerce3) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zdn.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zdn, align 16
# |   %4 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, <vscale x 8 x half> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %5, <vscale x 8 x half> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %6, <vscale x 8 x half> %zm.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x
# | ...
# `---data was truncated (10240/37760) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055be5812315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055be581200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055be5812389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0341249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03412a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0341249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0341231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be580b8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055be580b8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055be5809db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055be57d4d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055be57d4cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0341232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03412330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03412330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be57d4ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c (434 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1q_gather_u64base_offset_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1q_gather_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1q_gather_u64base_offset_u32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1q_gather_u64base_offset_s32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1q_gather_u64base_offset_u16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1q_gather_u64base_offset_s16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1q_gather_u64base_offset_u8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1q_gather_u64base_offset_s8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1q_gather_u64base_offset_f64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64(<vscale x 1 x i1> %3, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1q_gather_u64base_offset_f32(<vscale x 16 x i1> %pg, <vscale x 2 x
# | ...
# `---data was truncated (10240/58824) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000559fb319915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559fb31960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559fb319989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cd8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cd80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cd8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cd8031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fb312ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559fb312ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559fb3113b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559fb2dc30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559fb2dc2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1cd8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cd80330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cd80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fb2dc2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c (435 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565211e8e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000565211e8b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000565211e8e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f85d4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85d458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f85d4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f85d451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565211e23e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565211e23c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565211e08b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000565211ab80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000565211ab7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f85d451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85d451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85d451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565211ab7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/nor.c (436 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/nor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svnor_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.nor.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.nor.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055ac145c415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ac145c10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ac145c489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe76c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe76c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe76c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe76c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac14559e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ac14559c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ac1453eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ac141ee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ac141eddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe76c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe76c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe76c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac141edcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c (437 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/113019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559df087d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559df087a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559df087d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb63ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb63ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb63ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb63ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559df0812e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559df0812c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559df07f7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559df04a70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559df04a6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb63ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb63ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb63ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559df04a6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c (438 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_f16mf8(<vscale x 8 x half> %acc, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i64 noundef %fpmr) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 8 x half>, align 16
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %acc, ptr %acc.addr, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmmla.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmmla.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f8f16mm,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560a4281515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560a428120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560a4281589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbfcd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbfcd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbfcd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbfcd631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a427aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560a427aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560a4278fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560a4243f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560a4243edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbfcd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbfcd6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbfcd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a4243ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c (439 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalb_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalb_n_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalt_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalt_n_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %4, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalb_lane_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmlalt_lane_f16_mf8(<vscale x 8 x half> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16(<vscale x 8 x half> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 7)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16(<vscale x 8 x half>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmlallbb_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmlallbb_n_f32_mf8(<vscale x 4 x float> %zda, <vscale x 16 x i8> %zn, <1 x i8> %zm, i64 noundef %fpm) #0 {
# | entry:
# |   %zda.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <1 x i8>, align 1
# |   %fpm.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %zda, ptr %zda.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <1 x i8> %zm, ptr %zm.addr, align 1
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %zda.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <1 x i8>, ptr %zm.addr, align 1
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = extractelement <1 x i8> %2, i64 0
# |   %.splat
# | ...
# `---data was truncated (10240/24132) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056528c1f915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056528c1f60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056528c1f989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0228333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f022838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0228333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f022831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056528c18ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056528c18ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056528c173b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056528be230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056528be22dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f022831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f022831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f022831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056528be22cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c (440 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkb_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkb_b_m(<vscale x 16 x i1> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i1>, align 2
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %inactive, ptr %inactive.addr, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %inactive.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564bf8a5b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564bf8a580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564bf8a5b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6003c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6003ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6003c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6003c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564bf89f0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564bf89f0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564bf89d5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564bf86850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564bf8684dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6003c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6003c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6003c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564bf8684cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c (441 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vect
# | ...
# `---data was truncated (10240/31946) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cdd3fcf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cdd3fcc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cdd3fcf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f263f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f263f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f263f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f263f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cdd3f64e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cdd3f64c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cdd3f49b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cdd3bf90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cdd3bf8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f263f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f263f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f263f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cdd3bf8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c (442 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %2, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %2, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %.splat, <vscale x 4 x float> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacle_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %.splat, <vscale x 2 x double> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564fecdcc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564fecdc90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564fecdcc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3058b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3058b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3058b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3058aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564fecd61e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564fecd61c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564fecd46b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564fec9f60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564fec9f5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3058aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3058aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3058aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564fec9f5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c (443 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdecd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 4, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecd.n64(i64 %0, i32 5, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecd_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %0, i32 6, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecd_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %0, i32 7, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdecd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_pat_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 8, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqdecd_pat_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64> %0, i32 9, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055755974b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005575597480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055755974b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb74bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb74bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb74bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb74bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575596e0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005575596e0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005575596c5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005575593750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557559374dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb74bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb74bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb74bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557559374cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c (444 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d6fe4815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556d6fe450f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556d6fe4889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed09d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed09d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed09d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed09d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d6fddde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556d6fdddc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556d6fdc2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556d6fa720b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556d6fa71dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fed09d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed09d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed09d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d6fa71cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c (445 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = ca
# | ...
# `---data was truncated (10240/67474) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564fe60c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564fe60c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564fe60c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad33c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad33c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad33c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad33c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564fe605ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564fe605ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564fe603fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564fe5cef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564fe5ceedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fad33c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad33c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad33c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564fe5ceecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c (446 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate2_s8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %1, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate2_s16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %1, 1
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate2_s32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %1, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate2_s64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %1, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate2_u8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %1, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate2_u16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %1, 1
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate2_u32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %1, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate2_u64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %1, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svcreate2_f16(<vscale x 8 x half> %x0, <vscale x 8 x half> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x half>, align 16
# |   %x1.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x half> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %1, 1
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svcreate2_f32(<vscale x 4 x float> %x0, <vscale x 4 x float> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x float>, align 16
# |   %x1.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x float> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %1, 1
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svcreate2_f64(<vscale x 2 x double> %x0, <vscale x 2 x double> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x double>, align 16
# |   %x1.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x double> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %0, 0
# |   %3 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, <vscale x 2 x double> %1, 1
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate2_mf8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %1, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svcreate2_bf16(<vscale x 8 x bfloat> %x0, <vscale x 8 x bfloat> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %x1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x bfloat> %x1, ptr %x1.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %x1.addr, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vsc
# | ...
# `---data was truncated (10240/10734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055afee90315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055afee9000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055afee90389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2bde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2bdea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2bde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2bde31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afee898e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055afee898c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055afee87db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055afee52d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055afee52cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa2bde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2bde330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2bde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afee52ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c (447 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = sext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff
# | ...
# `---data was truncated (10240/18920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055939095b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005593909580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055939095b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9cc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9cc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9cc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9cc91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593908f0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005593908f0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005593908d5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005593905850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559390584dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff9cc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9cc91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9cc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559390584cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c (448 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svscale_single_f16_x2(<vscale x 8 x half> %op1.coerce0, <vscale x 8 x half> %op1.coerce1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op1.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %op1.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %6 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svscale_single_f32_x2(<vscale x 4 x float> %op1.coerce0, <vscale x 4 x float> %op1.coerce1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op1.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %op1.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %op1, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %6 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv4f32(<vscale x 4 x float> %3, <vscale x 4 x float> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svscale_single_f64_x2(<vscale x 2 x double> %op1.coerce0, <vscale x 2 x double> %op1.coerce1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %op1.addr = alloca { <vscale x 2 x double>, <vscale x 2 x double> }, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } poison, <vscale x 2 x double> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %0, <vscale x 2 x double> %op1.coerce1, 1
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %op1, align 16
# |   store { <vscale x 2 x double>, <vscale x 2 x double> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %2 = load { <vscale x 2 x double>, <vscale x 2 x double> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %6 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv2f64(<vscale x 2 x double> %3, <vscale x 2 x double> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.fp8.scale.single.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svscale_single_f16_x4(<vscale x 8 x half> %op1.coerce0, <vscale x 8 x half> %op1.coerce1, <vscale x 8 x half> %op1.coerce2, <vscale x 8 x half> %op1.coerce3, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op1.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %op1.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %op1.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %op1.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %op1, align 16
# |   %op11 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %4 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %op1.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, 3
# |   %9 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %10 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x4.nxv8f16(<vscale x 8 x half> %5, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %8, <vscale x 8 x i16> %9)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.fp8.scale.single.x4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svscale_single_f32_x4(<vscale x 4 x float> %op1.coerce0, <vscale x 4 x float> %op1.coerce1, <vscale x 4 x float> %op1.coerce2, <vscale x 4 x float> %op1.coerce3, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op1.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %op1.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %op1.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %op1.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %op1, align 16
# |   %op11 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %op1, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %op11, ptr 
# | ...
# `---data was truncated (10240/37349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e0f8ce815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e0f8ce50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e0f8ce889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe2a0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2a0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe2a0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2a0b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0f8c7de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e0f8c7dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e0f8c62b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e0f89120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e0f8911dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe2a0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2a0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2a0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0f8911cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c (449 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_n_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, i8 noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca i8, align 1
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store i8 %z, ptr %z.addr, align 1
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load i8, ptr %z.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %2, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %.splat, <vscale x 16 x i8> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_0(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 0)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_1(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_2(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsudot_lane_s32_3(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.sudot.lane.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559d27d4f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559d27d4c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559d27d4f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab2981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab298725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab2981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab29803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d27ce4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559d27ce4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559d27cc9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559d279790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559d27978dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fab29804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab298050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab298050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d27978cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/recpe.c (450 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/recpe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpe_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpe.x.nxv8f16(<vscale x 8 x half> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frecpe.x.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpe_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpe.x.nxv4f32(<vscale x 4 x float> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frecpe.x.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpe_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpe.x.nxv2f64(<vscale x 2 x double> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frecpe.x.nxv2f64(<vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000565283d0215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000565283cff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000565283d0289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1603333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f160338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1603333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f160331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565283c97e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565283c97c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565283c7cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056528392c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056528392bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f160331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f160331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f160331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056528392bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c (451 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt1_bf16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v8i8(<8 x i8> %2)
# |   store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt1_low_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v8i8(<8 x i8> %4)
# |   store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt2_bf16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v8i8(<8 x i8> %2)
# |   store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt2_low_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v8i8(<8 x i8> %4)
# |   store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt1_high_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v16i8(<16 x i8> %2)
# |   store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvt2_high_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <8 x bfloat>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v16i8(<16 x i8> %2)
# |   store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt1_f16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl1.v8f16.v8i8(<8 x i8> %2)
# |   store <8 x half> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt1_low_f16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %op.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <16 x i8> %op, ptr %op.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <16 x i8>, ptr %op.addr, align 16
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0)
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt1.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl1.v8f16.v8i8(<8 x i8> %4)
# |   store <8 x half> %vbfcvt1.i, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt2_f16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %op.addr = alloca <8 x i8>, align 8
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x i8> %op, ptr %op.addr, align 8
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x i8>, ptr %op.addr, align 8
# |   %1 = load i64, ptr %fpm.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %vbfcvt2.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl2.v8f16.v8i8(<8 x i8> %2)
# |   store <8 x half> %vbfcvt2.i, ptr %ref.tmp.i
# | ...
# `---data was truncated (10240/23350) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x000055ded193715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ded19340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ded193789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f97e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f97ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f97e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f97e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ded18cce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ded18ccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ded18b1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ded15610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ded1560dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9f97e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f97e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f97e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ded1560cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c (452 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_svldr_zt(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sme.ldr.zt.p0(i32 0, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.ldr.zt.p0(i32, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_svstr_zt(ptr noundef %base) #2 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   call void @llvm.aarch64.sme.str.zt.p0(i32 0, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write, target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.str.zt.p0(i32, ptr) #3
# | 
# | attributes #0 = { noinline nounwind "aarch64_out_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, target_mem0: readwrite) }
# | attributes #2 = { noinline nounwind "aarch64_in_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write, target_mem0: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000555639f5015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555639f4d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555639f5089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba40733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba4078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba40733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba4071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555639ee5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555639ee5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555639ecab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555639b7a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555639b79dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fba4071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba4071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba4071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555639b79cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c (453 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vsc
# | ...
# `---data was truncated (10240/53446) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b60035915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b6003560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b60035989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdf5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdf598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdf5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdf591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6002eee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b6002eec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b6002d3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b5fff830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b5fff82dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efdf591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdf591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdf591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5fff82cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c (454 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqdecw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqdecw.n64(i64 %0, i32 0, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecw_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %0, i32 1, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecw_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %0, i32 2, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdecw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_pat_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 3, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqdecw_pat_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32> %0, i32 4, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005566c372615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005566c37230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005566c372689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f131f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f131f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f131f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f131f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566c36bbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005566c36bbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005566c36a0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005566c33500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005566c334fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f131f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f131f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f131f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566c334fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c (455 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svadd_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055f92ec4915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f92ec460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f92ec4989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa17d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa17d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa17d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa17d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f92ebdee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f92ebdec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f92ebc3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f92e8730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f92e872dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa17d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa17d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa17d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f92e872cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c (456 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclasta_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.clasta.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclasta_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clasta.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.clasta.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclasta_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clasta.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.clasta.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclasta_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clasta.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.clasta.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svclasta_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %fallback, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 16 x i8>, align 16
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.clasta.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svclasta_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %fallback, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x i16>, align 16
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.clasta.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svclasta_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %fallback, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.clasta.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svclasta_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %fallback, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.clasta.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svclasta_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %fallback, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %fallback.addr = alloca <vscale x 8 x half>, align 16
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %fallback, ptr %fallback.addr, align 16
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %fallback.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.clasta.nxv8f16(<vscale x 8 x i
# | ...
# `---data was truncated (10240/26390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055f31812515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f3181220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f31812589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0f1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0f1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0f1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0f1a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3180bae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f3180bac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f31809fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f317d4f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f317d4edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc0f1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0f1a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0f1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f317d4ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c (457 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("r
# | ...
# `---data was truncated (10240/36023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055770a5fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055770a5f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055770a5fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb61b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb61b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb61b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb61b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055770a591e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055770a591c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055770a576b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055770a2260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055770a225dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb61b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb61b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb61b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055770a225cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c (458 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zm.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %5, 1
# |   %8 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 0
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %8, 1
# |   call void @llvm.aarch64.sme.fmla.vg1x2.nxv4f32(i32 %4, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %9, <vscale x 4 x float> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmla.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm.coerce0, <vscale x 4 x float> %zm.coerce1, <vscale x 4 x float> %zm.coerce2, <vscale x 4 x float> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, <vscale x 4 x float> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %5, <vscale x 4 x float> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, <vscale x 4 x float> %zm.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 0
# |   %11 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 1
# |   %12 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 2
# |   %13 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %9, 3
# |   %14 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 0
# |   %16 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 1
# |   %17 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 2
# |   %18 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %14, 3
# |   call void @llvm.aarch64.sme.fmla.vg1x4.nxv4f32(i32 %8, <vscale x 4 x float> %10, <vscale x 4 x float> %11, <vscale x 4 x float> %12, <vscale x 4 x float> %13, <vscale x 4 x float> %15, <vscale x 4 x float> %16, <vscale x 4 x float> %17, <vscale x 4 x float> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmla.vg1x4.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single2_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %3, 1
# |   %6 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv4f32(i32 %2, <vscale x 4 x float> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fmla.single.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmla_single4_f32(i32 noundef %slice_base, <vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x flo
# | ...
# `---data was truncated (10240/34546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055d1f057915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d1f05760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d1f057989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b6a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b6a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b6a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b6a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1f050ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d1f050ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d1f04f3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d1f01a30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d1f01a2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3b6a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b6a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b6a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1f01a2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c (459 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svadd_vector_single2_s8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svadd_vector_single2_u8(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svadd_vector_single2_s16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svadd_vector_single2_u16(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svadd_vector_single2_s32(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svadd_vector_single2_u32(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svadd_vector_single2_s64(<vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   store { <vscale x
# | ...
# `---data was truncated (10240/34761) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055728ac8b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055728ac880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055728ac8b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89fdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89fdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89fdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89fdd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055728ac20e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055728ac20c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055728ac05b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055728a8b50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055728a8b4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f89fdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89fdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89fdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055728a8b4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c (460 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zm.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %4 = load i32, ptr %slice_base.addr, align 4
# |   %5 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %5, 1
# |   %8 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %8, 1
# |   call void @llvm.aarch64.sme.fdot.za32.vg1x2.nxv8f16(i32 %4, <vscale x 8 x half> %6, <vscale x 8 x half> %7, <vscale x 8 x half> %9, <vscale x 8 x half> %10)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fdot.za32.vg1x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_multi_za32_vg1x4_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zn.coerce2, <vscale x 8 x half> %zn.coerce3, <vscale x 8 x half> %zm.coerce0, <vscale x 8 x half> %zm.coerce1, <vscale x 8 x half> %zm.coerce2, <vscale x 8 x half> %zm.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %1, <vscale x 8 x half> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %2, <vscale x 8 x half> %zn.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   %4 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %4, <vscale x 8 x half> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %5, <vscale x 8 x half> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %6, <vscale x 8 x half> %zm.coerce3, 3
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %7, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %zm2, ptr %zm.addr, align 16
# |   %8 = load i32, ptr %slice_base.addr, align 4
# |   %9 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %10 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 0
# |   %11 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 1
# |   %12 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 2
# |   %13 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %9, 3
# |   %14 = load { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zm.addr, align 16
# |   %15 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 0
# |   %16 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 1
# |   %17 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 2
# |   %18 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %14, 3
# |   call void @llvm.aarch64.sme.fdot.za32.vg1x4.nxv8f16(i32 %8, <vscale x 8 x half> %10, <vscale x 8 x half> %11, <vscale x 8 x half> %12, <vscale x 8 x half> %13, <vscale x 8 x half> %15, <vscale x 8 x half> %16, <vscale x 8 x half> %17, <vscale x 8 x half> %18)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fdot.za32.vg1x4.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_single_za32_vg1x2_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store i32 %slice_base, ptr %slice_base.addr, align 4
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %2 = load i32, ptr %slice_base.addr, align 4
# |   %3 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 0
# |   %5 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %3, 1
# |   %6 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   call void @llvm.aarch64.sme.fdot.single.za32.vg1x2.nxv8f16(i32 %2, <vscale x 8 x half> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fdot.single.za32.vg1x2.nxv8f16(i32, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_single_za32_vg1x4_f16(i32 noundef %slice_base, <vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, <vscale x 8 x half> %zn.coerce2, <vscale x 8 x half> %zn.coerce3, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %slice_base.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x half>, <vscale x 8 x 
# | ...
# `---data was truncated (10240/34400) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055bb8563115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bb8562e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bb8563189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21ecb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21ecb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21ecb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21ecaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb855c6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bb855c6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bb855abb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bb8525b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bb8525add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f21ecaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21ecaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21ecaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb8525acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c (461 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.6a -target-feature +i8mm  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.6a -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x i32>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %r, ptr %r.addr, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %r.addr, align 16
# |   %1 = load <16 x i8>, ptr %a.addr, align 16
# |   %2 = load <16 x i8>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.aarch64.neon.smmla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_u32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x i32>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %r, ptr %r.addr, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %r.addr, align 16
# |   %1 = load <16 x i8>, ptr %a.addr, align 16
# |   %2 = load <16 x i8>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.aarch64.neon.ummla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vusmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x i32>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %r, ptr %r.addr, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %r.addr, align 16
# |   %1 = load <16 x i8>, ptr %a.addr, align 16
# |   %2 = load <16 x i8>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vusmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vusmmla1.i = call <4 x i32> @llvm.aarch64.neon.usmmla.v4i32.v16i8(<4 x i32> %vusmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vusmmla1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_845 = alloca <2 x i32>, align 8
# |   %__s0_845 = alloca <2 x i32>, align 8
# |   %__s1_845 = alloca <8 x i8>, align 8
# |   %__s2_845 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_845, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_845, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_845, align 8
# |   %3 = load <2 x i32>, ptr %__s0_845, align 8
# |   %4 = load <8 x i8>, ptr %__s1_845, align 8
# |   %5 = load <2 x i32>, ptr %__s2_845, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> zeroinitializer
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_845, align 8
# |   %17 = load <2 x i32>, ptr %__ret_845, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsudot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_841 = alloca <2 x i32>, align 8
# |   %__s0_841 = alloca <2 x i32>, align 8
# |   %__s1_841 = alloca <8 x i8>, align 8
# |   %__s2_841 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_841, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_841, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_841, align 8
# |   %3 = load <2 x i32>, ptr %__s0_841, align 8
# |   %4 = load <2 x i32>, ptr %__s2_841, align 8
# |   store <2 x i32> %4, ptr %__s0, align 8
# | 
# | ...
# `---data was truncated (10240/31781) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000564059e5e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564059e5b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564059e5e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7716249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77162a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7716249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7716231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564059df3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564059df3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564059dd8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564059a880b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564059a87dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7716232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77162330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77162330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564059a87cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c (462 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_lane_bf16_idx1(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_lane_bf16_idx3(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmla_lane_bf16_idx7(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005585f12e715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005585f12e40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005585f12e789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f56e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f56e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f56e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f56e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005585f127ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005585f127cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005585f1261b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005585f0f110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005585f0f10dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0f56e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f56e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f56e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005585f0f10cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c (463 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svexpa_f16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svexpa_f32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.fexpa.x.nxv4f32(<vscale x 4 x i32> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fexpa.x.nxv4f32(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svexpa_f64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055af1ad8015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055af1ad7d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055af1ad8089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ca9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ca9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ca9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ca9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af1ad15e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055af1ad15c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055af1acfab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055af1a9aa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055af1a9a9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3ca9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ca9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ca9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af1a9a9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c (464 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/153813) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2b4ddc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f2b4dd90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f2b4ddc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb75a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb75a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb75a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb75a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2b4d71e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f2b4d71c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f2b4d56b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f2b4a060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f2b4a05dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb75a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb75a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb75a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2b4a05cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c (465 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 0, i64 %2)
# | ...
# `---data was truncated (10240/69831) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc0107d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fc0107a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fc0107d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d1d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d1d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d1d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d1d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc01012e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fc01012c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fc00ff7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fc00ca70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fc00ca6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7d1d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d1d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d1d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc00ca6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c (466 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   
# | ...
# `---data was truncated (10240/132462) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7623a115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d76239e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d7623a189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f163ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f163cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f163ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f163ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d762336e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d762336c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d76231bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d761fcb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d761fcadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f163ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f163ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f163ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d761fcacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c (467 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svextq_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.extq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.extq.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svextq_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.extq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 4)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextq_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.extq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.extq.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svextq_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.extq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 5)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextq_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.extq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 2)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.extq.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svextq_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.extq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 3)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextq_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.extq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.extq.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextq_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.extq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 0)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svextq_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.extq.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 7)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.extq.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svextq_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.extq.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 2)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.extq.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svextq_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.extq.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 0)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.extq.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svextq_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.extq.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i32 6)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.extq.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svextq_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr,
# | ...
# `---data was truncated (10240/11061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055924913f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055924913c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055924913f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6de1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6de1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6de1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6de1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592490d4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005592490d4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005592490b9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559248d690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559248d68dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6de1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6de1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6de1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559248d68cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c (468 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055790f03215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055790f02f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055790f03289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe152849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1528a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe152849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe152831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055790efc7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055790efc7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055790efacb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055790ec5c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055790ec5bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe152832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1528330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1528330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055790ec5bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c (469 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1, <vscale x 16 x i8> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %data.coerce2, 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   call void @llvm.aarch64.sve.st3.nxv16i8.p0(<vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i1> %3, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1, <vscale x 8 x i16> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %data.coerce2, 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 2
# |   %9 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %3)
# |   call void @llvm.aarch64.sve.st3.nxv8i16.p0(<vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %8, <vscale x 8 x i1> %9, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data.coerce0, <vscale x 4 x i32> %data.coerce1, <vscale x 4 x i32> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %data.coerce2, 2
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 0
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 1
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, 2
# |   %9 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %3)
# |   call void @llvm.aarch64.sve.st3.nxv4i32.p0(<vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i1> %9, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data.coerce0, <vscale x 2 x i64> %data.coerce1, <vscale x 2 x i64> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %data.coerce2, 2
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, ptr %data, align 16
# |   %data1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %data1, ptr %data.addr, align 16
# |   %3 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %4 = load ptr, ptr %base.addr, align 8
# |   %5 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %data.addr, align 16
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, 0
# |   %7 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, 1
# |   %8 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, 2
# |   %9 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %3)
# |   call void @llvm.aarch64.sve.st3.nxv2i64.p0(<vscale x 2 x i64> %6, <vscale x 2 x i64> %7, <vscale x 2 x i64> %8, <vscale x 2 x i1> %9, ptr %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st3.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst3_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1, <vscale x 16 x i8> %data.coerce2) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = al
# | ...
# `---data was truncated (10240/58378) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055863be3815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055863be350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055863be3889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44ab333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44ab38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44ab333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44ab31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055863bdcde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055863bdcdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055863bdb2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055863ba620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055863ba61dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f44ab31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44ab31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44ab31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055863ba61cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c (470 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |  
# | ...
# `---data was truncated (10240/67482) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8b56ec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b8b56e90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b8b56ec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2cdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2cdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2cdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2cdd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8b5681e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b8b5681c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b8b5666b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b8b53160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b8b5315dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc2cdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2cdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2cdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8b5315cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c (471 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_u32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_vnum_u32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i32>, ptr %1, i64 -8
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_s32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uwq_vnum_s32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i32>, ptr %1, i64 7
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1uwq_f32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1uwq.nxv4f32.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1uwq.nxv4f32.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1uwq_vnum_f32(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x float>, ptr %1, i64 -8
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1uwq.nxv4f32.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_u64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_vnum_u64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i64>, ptr %1, i64 7
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_s64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1udq_vnum_s64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x i64>, ptr %1, i64 -8
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1udq_f64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1udq.nxv2f64.p0(<vscale x 1 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1udq.nxv2f64.p0(<vscale x 1 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1udq_vnum_f64(<vscale x 16 x i1> %pred, ptr noundef %base) #0 {
# | entry:
# |   %pred.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pred, ptr %pred.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pred.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   %3 = getelementptr <vscale x 1 x double>, ptr %1, i64 7
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1udq.nxv2f64.p0(<vscale x 1 x i1> %2, ptr %3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"
# | ...
# `---data was truncated (10240/10573) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055e48e72115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e48e71e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e48e72189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88e521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88e52725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88e521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88e5203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e48e6b6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e48e6b6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e48e69bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e48e34b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e48e34add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f88e5204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88e52050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88e52050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e48e34acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c (472 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrka_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrka_b_m(<vscale x 16 x i1> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i1>, align 2
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %inactive, ptr %inactive.addr, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %inactive.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c02fc2815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c02fc250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c02fc2889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b51a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b51aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b51a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b51a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c02fbbde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c02fbbdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c02fba2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c02f8520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c02f851dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4b51a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b51a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b51a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c02f851cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c (473 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float>, ha
# | ...
# `---data was truncated (10240/90685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556cb26615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005556cb2630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005556cb26689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe05849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe058a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe05849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe05831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556cb1fbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005556cb1fbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005556cb1e0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005556cae900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005556cae8fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbe05832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe058330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe058330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556cae8fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c (474 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmax_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056534b49b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056534b4980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056534b49b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f228b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f228b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f228b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f228b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056534b430e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056534b430c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056534b415b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056534b0c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056534b0c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f228b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f228b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f228b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056534b0c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c (475 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip2_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip2.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.zip2.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip2_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip2.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f98353715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f9835340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f98353789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5771e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5771ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5771e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5771e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9834cce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f9834ccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f9834b1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f9831610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f983160dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5771e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5771e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5771e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f983160cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c (476 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmmla_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8bf16(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv8bf16(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558667b5815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558667b550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558667b5889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6304105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f630415c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6304105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63040ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558667aede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558667aedc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558667ad2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005586677820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558667781dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f63040eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63040ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63040ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558667781cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c (477 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme2  -target-feature +sme  -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme2 -target-feature +sme -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u8_1(<vscale x 16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s8_2(<vscale x 16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u16_3(<vscale x 8 x i16> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 immarg, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s16_1(<vscale x 8 x i16> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u32_2(<vscale x 4 x i32> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 immarg, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s32_3(<vscale x 4 x i32> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_u64_0(<vscale x 2 x i64> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, <vscale x 2 x i64> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 immarg, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_s64_1(<vscale x 2 x i64> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, <vscale x 2 x i64> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_f16_2(<vscale x 8 x half> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8f16(i32 0, <vscale x 8 x half> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv8f16(i32 immarg, <vscale x 8 x half>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_bf16_3(<vscale x 8 x bfloat> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv8bf16(i32 0, <vscale x 8 x bfloat> %0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv8bf16(i32 immarg, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_f32_0(<vscale x 4 x float> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 0, <vscale x 4 x float> %0, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 immarg, <vscale x 4 x float>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_lane_zt_f64_1(<vscale x 2 x double> %v) #0 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.lane.zt.nxv2f64(i32 0, <vscale x 2 x double> %0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite)
# | declare void @llvm.aarch64.sme.write.lane.zt.nxv2f64(i32 immarg, <vscale x 2 x double>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u8(<vscale x 16 x i8> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s8(<vscale x 16 x i8> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u16(<vscale x 8 x i16> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv8i16(i32 immarg, <vscale x 8 x i16>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s16(<vscale x 8 x i16> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv8i16(i32 0, <vscale x 8 x i16> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u32(<vscale x 4 x i32> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv4i32(i32 immarg, <vscale x 4 x i32>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s32(<vscale x 4 x i32> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv4i32(i32 0, <vscale x 4 x i32> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_u64(<vscale x 2 x i64> %v) #2 {
# | entry:
# |   %v.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %v, ptr %v.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %v.addr, align 16
# |   call void @llvm.aarch64.sme.write.zt.nxv2i64(i32 0, <vscale x 2 x i64> %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write)
# | declare void @llvm.aarch64.sme.write.zt.nxv2i64(i32 immarg, <vscale x 2 x i64>) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_write_zt_s64(<vscale x 2 x i64> %v) #2 {
# | entry:
# |   %
# | ...
# `---data was truncated (10240/13584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005580e15ff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005580e15fc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005580e15ff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30dad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30dad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30dad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30dad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580e1594e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005580e1594c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005580e1579b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005580e12290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005580e1228dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f30dad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30dad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30dad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580e1228cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c (478 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i1 @test_svptest_any(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i1 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i1 @test_svptest_first(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i1 @llvm.aarch64.sve.ptest.first.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i1 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i1 @llvm.aarch64.sve.ptest.first.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i1 @test_svptest_last(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i1 @llvm.aarch64.sve.ptest.last.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i1 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i1 @llvm.aarch64.sve.ptest.last.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558bc70e215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558bc70df0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558bc70e289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78b9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78b998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78b9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78b991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bc7077e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558bc7077c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558bc705cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558bc6d0c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558bc6d0bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f78b991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78b991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78b991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bc6d0bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c (479 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti2_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti2_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti2_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svluti2_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svluti2_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svluti2_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svluti2_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti2_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svluti2_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svluti2_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 15)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557a29c2e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557a29c2b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557a29c2e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67b3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67b3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67b3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67b3a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a29bc3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557a29bc3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557a29ba8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557a298580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557a29857dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f67b3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67b3a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67b3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a29857cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c (480 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntw(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntw_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntw(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005613e98cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005613e98c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005613e98cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ec6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ec618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ec6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ec611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613e9860e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005613e9860c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005613e9845b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005613e94f50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005613e94f4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6ec611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ec611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ec611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613e94f4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c (481 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/18873) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f7410e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561f7410b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561f7410e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7581249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75812a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7581249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7581231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f740a3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561f740a3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561f74088b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561f73d380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561f73d37dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7581232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75812330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75812330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f73d37cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c (482 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincd.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqincd.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 9, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %0, i32 10, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincd_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %0, i32 11, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincd_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %0, i32 12, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqincd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqincd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqincd.nxv2i64(<vscale x 2 x i64> %0, i32 31, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqincd.nxv2i64(<vscale x 2 x i64>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_pat_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqincd.nxv2i64(<vscale x 2 x i64> %0, i32 13, i32 16)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqincd_pat_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqincd.nxv2i64(<vscale x 2 x i64> %0, i32 29, i32 1)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055751fd0715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055751fd040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055751fd0789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11f7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11f798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11f7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11f791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055751fc9ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055751fc9cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055751fc81b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055751f9310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055751f930dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f11f791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11f791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11f791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055751f930cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/X86/avx-cmp-builtins.c (483 of 27911)
******************** TEST 'Clang :: CodeGen/X86/avx-cmp-builtins.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -flax-vector-conversions=none -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -flax-vector-conversions=none -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmp_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   %2 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %0, <2 x double> %1, i8 13)
# |   ret <2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmp_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %0, <4 x float> %1, i8 13)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpgt_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 1)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpge_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 2)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpngt_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 5)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_cmpnge_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <4 x float>, align 16
# |   %__b.addr.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__a.addr.i, align 16
# |   store <4 x float> %1, ptr %__b.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__b.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__a.addr.i, align 16
# |   %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 6)
# |   %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
# |   ret <4 x float> %shuffle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpgt_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__a.addr.i, align 16
# |   store <2 x double> %1, ptr %__b.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__b.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 1)
# |   store <2 x double> %4, ptr %__c.i, align 16
# |   %5 = load <2 x double>, ptr %__c.i, align 16
# |   %vecext.i = extractelement <2 x double> %5, i32 0
# |   %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0
# |   %6 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %vecext1.i = extractelement <2 x double> %6, i32 1
# |   %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1
# |   store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpge_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__a.addr.i, align 16
# |   store <2 x double> %1, ptr %__b.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__b.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 2)
# |   store <2 x double> %4, ptr %__c.i, align 16
# |   %5 = load <2 x double>, ptr %__c.i, align 16
# |   %vecext.i = extractelement <2 x double> %5, i32 0
# |   %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0
# |   %6 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %vecext1.i = extractelement <2 x double> %6, i32 1
# |   %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1
# |   store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpngt_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__a.addr.i, align 16
# |   store <2 x double> %1, ptr %__b.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__b.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 5)
# |   store <2 x double> %4, ptr %__c.i, align 16
# |   %5 = load <2 x double>, ptr %__c.i, align 16
# |   %vecext.i = extractelement <2 x double> %5, i32 0
# |   %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0
# |   %6 = load <2 x double>, ptr %__a.addr.i, align 16
# |   %vecext1.i = extractelement <2 x double> %6, i32 1
# |   %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1
# |   store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16
# |   %7 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_cmpnge_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca <2 x double>, align 16
# |   %__b.addr.i = alloca <2 x double>, align 16
# |   %__c.i = alloca <2 x double>, align 16
# |   %.compoundlit
# | ...
# `---data was truncated (10240/11780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601d05ed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005601d05ea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005601d05ed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff441249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4412a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff441249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff441231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601d0582e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005601d0582c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005601d0567b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005601d02170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005601d0216dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff441232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4412330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4412330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601d0216cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c (484 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1sw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556e5daed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556e5daea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556e5daed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95e0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95e058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95e0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95e051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e5da82e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556e5da82c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556e5da67b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556e5d7170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556e5d716dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f95e051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95e051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95e051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e5d716cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c (485 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svscale_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svscale_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svscale_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fscale.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fscale.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svscale_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svscale_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svscale_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fscale.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svscale_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fscale.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svscale_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fscale.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svscale_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbo
# | ...
# `---data was truncated (10240/21216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056043e58615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056043e5830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056043e58689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93f1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93f12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93f1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93f1231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056043e51be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056043e51bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056043e500b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056043e1b00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056043e1afdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f93f1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93f12330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93f12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056043e1afcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c (486 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564eac82815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564eac8250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564eac82889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fadd7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fadd70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fadd7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fadd7031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564eac7bde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564eac7bdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564eac7a2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564eac4520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564eac451dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fadd7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fadd70330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fadd70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564eac451cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vls-shift-ops.c (487 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-shift-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @lshift_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shl = shl <64 x i8> %0, %1
# |   store <64 x i8> %shl, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @rshift_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shr = ashr <64 x i8> %0, %1
# |   store <64 x i8> %shr, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @lshift_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shl = shl <64 x i8> %0, %1
# |   store <64 x i8> %shl, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @rshift_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %shr = lshr <64 x i8> %0, %1
# |   store <64 x i8> %shr, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @lshift_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shl = shl <32 x i16> %0, %1
# |   store <32 x i16> %shl, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @rshift_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shr = ashr <32 x i16> %0, %1
# |   store <32 x i16> %shr, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @lshift_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shl = shl <32 x i16> %0, %1
# |   store <32 x i16> %shl, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @rshift_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %shr = lshr <32 x i16> %0, %1
# |   store <32 x i16> %shr, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @lshift_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %shl = shl <16 x i32> %0, %1
# |   store <16 x i32> %shl, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 imma
# | ...
# `---data was truncated (10240/51475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055d41fac115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d41fabe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d41fac189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf03a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf03aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf03a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf03a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d41fa56e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d41fa56c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d41fa3bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d41f6eb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d41f6eadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbf03a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf03a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf03a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d41f6eacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c (488 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.
# | ...
# `---data was truncated (10240/128424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb25be915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eb25be60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eb25be989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64d4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64d4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64d4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64d4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb25b7ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eb25b7ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eb25b63b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eb258130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eb25812dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f64d4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64d4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64d4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb25812cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c (489 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x h
# | ...
# `---data was truncated (10240/69487) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb2da8515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cb2da820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cb2da8589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5eb1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5eb158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5eb1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5eb151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb2da1ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cb2da1ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cb2d9ffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cb2d6af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cb2d6aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5eb151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5eb151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5eb151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb2d6aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c (490 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svminnm_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svminnm_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svminnm_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svminnm_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svminnm_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svminnm_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svminnm_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.u.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fminnm.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svminnm_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.u.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fminnm.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svminnm_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.ad
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005605ef48a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005605ef4870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005605ef48a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d11649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d116a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d11649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d11631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605ef41fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005605ef41fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005605ef404b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005605ef0b40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005605ef0b3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7d11632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d116330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d116330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605ef0b3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon-fma.c (491 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-fma.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmla_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <2 x float>, align 8
# |   %.compoundliteral.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %c.addr, align 4
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <2 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1
# |   store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8
# |   %7 = load <2 x float>, ptr %.compoundliteral.i, align 8
# |   %mul.i = fmul <2 x float> %4, %7
# |   %add.i = fadd <2 x float> %3, %mul.i
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %8 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 16
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = load float, ptr %c.addr, align 4
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1
# |   %7 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2
# |   %8 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16
# |   %9 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   %mul.i = fmul <4 x float> %4, %9
# |   %add.i = fadd <4 x float> %3, %mul.i
# |   store <4 x float> %add.i, ptr %__ret.i, align 16
# |   %10 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlsq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 16
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = load float, ptr %c.addr, align 4
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1
# |   %7 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2
# |   %8 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16
# |   %9 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   %mul.i = fmul <4 x float> %4, %9
# |   %sub.i = fsub <4 x float> %3, %mul.i
# |   store <4 x float> %sub.i, ptr %__ret.i, align 16
# |   %10 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmls_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <2 x float>, align 8
# |   %.compoundliteral.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %c.addr, align 4
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <2 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1
# |   store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8
# |   %7 = load <2 x float>, ptr %.compoundliteral.i, align 8
# |   %mul.i = fmul <2 x float> %4, %7
# |   %sub.i = fsub <2 x float> %3, %mul.i
# |   store <2 x float> %sub.i, ptr %__ret.i, align 8
# |   %8 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmla_lane_f32_0(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %v.addr = alloca <2 x float>, align 8
# |   %__ret_68 = alloca <2 x float>, align 8
# |   %__s0_68 = alloca <2 x float>, align 8
# |   %__s1_68 = alloca <2 x float>, align 8
# |   %__s2_68 = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   %tmp1 = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store <2 x float> %v, ptr %v.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__s0_68, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1_68, align 8
# |   %2 = load <2 x float>, ptr %v.addr, align 8
# |   store <2 x float> %2, ptr %__s2_68, align 8
# |   %3 = load <2 x float>, ptr %__s0_68, align 8
# |   %4 = load <2 x float>, ptr %__s1_68, align 8
# |   %5 = load <2 x float>, ptr %__s2_68, align 8
# |   store <2 x float> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x float>
# |   %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer
# |   store <2 x float> %lane, ptr %ref.tmp, align 8
# |   %8 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %8, ptr %__ret, align 8
# |   %9 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %9, ptr %tmp, align 8
# |   %10 = load <2 x float>, ptr %tmp, align 8
# |   %mul = fmul <2 x float> %4, %10
# |   %add = fadd <2 x float> %3, %mul
# |   store <2 x float> %add, ptr %__ret_68, align 8
# |   %11 = load <2 x float>, ptr %__ret_68, align 8
# |   store <2 x float> %11, ptr %tmp1, align 8
# |   %12 = load <2 x float>, ptr %tmp1, align 8
# |   ret <2 x float> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlaq_lane_f32_0(<4 x float> noundef %a, <4 x float> noundef %b, <2 x float> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %v.addr = alloca <2 x float>, align 8
# |   %__ret_58 = alloca <4 x float>, align 16
# |   %__s0_58 = alloca <4 x float>, align 16
# |   %__s1_58 = alloca <4 x float>, align 16
# |   %__s2_58 = alloca <2 x float>, align 8
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   %tmp1 = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store <2 x float> %v, ptr %v.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__s0_58, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x float> %1, ptr %__s1_58, align 16
# |   %2 = load <2 x float>, ptr %v.addr, align 8
# |   store <2 x float> %2, ptr %__s2_58, align 8
# |   %3 = load <4 x float>, ptr %__s0_58, align 16
# |   %4 = load <4 x float>, ptr %__s1_58, align 16
# |   %5 = load <2 x float>, ptr %__s2_58, align 8
# |   store <2 x f
# | ...
# `---data was truncated (10240/44730) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000561941c6715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561941c640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561941c6789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef08e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef08e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef08e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef08e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561941bfce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561941bfcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561941be1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005619418910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561941890dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fef08e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef08e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef08e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561941890cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c (492 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svundef_s8() #0 {
# | entry:
# |   ret <vscale x 16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svundef_s16() #0 {
# | entry:
# |   ret <vscale x 8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svundef_s32() #0 {
# | entry:
# |   ret <vscale x 4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svundef_s64() #0 {
# | entry:
# |   ret <vscale x 2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svundef_u8() #0 {
# | entry:
# |   ret <vscale x 16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svundef_u16() #0 {
# | entry:
# |   ret <vscale x 8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svundef_u32() #0 {
# | entry:
# |   ret <vscale x 4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svundef_u64() #0 {
# | entry:
# |   ret <vscale x 2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svundef_f16() #0 {
# | entry:
# |   ret <vscale x 8 x half> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svundef_f32() #0 {
# | entry:
# |   ret <vscale x 4 x float> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svundef_f64() #0 {
# | entry:
# |   ret <vscale x 2 x double> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svundef_mf8() #0 {
# | entry:
# |   ret <vscale x 16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svundef_bf16() #0 {
# | entry:
# |   ret <vscale x 8 x bfloat> undef
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000555ebd6eb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555ebd6e80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555ebd6eb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c95933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c9598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c95933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c9591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ebd680e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555ebd680c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555ebd665b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555ebd3150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555ebd314dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8c9591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c9591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c9591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ebd314cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-vls-compare-ops.c (493 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-compare-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone -mvscale-min=4 -mvscale-max=4   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i1> @eq_bool(<vscale x 16 x i1> noundef %0, <vscale x 16 x i1> noundef %1) #0 {
# | entry:
# |   %retval = alloca <8 x i8>, align 2
# |   %a.addr = alloca <8 x i8>, align 2
# |   %b.addr = alloca <8 x i8>, align 2
# |   %a.coerce = bitcast <vscale x 16 x i1> %0 to <vscale x 2 x i8>
# |   %a = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %a.coerce, i64 0)
# |   %b.coerce = bitcast <vscale x 16 x i1> %1 to <vscale x 2 x i8>
# |   %b = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> %b.coerce, i64 0)
# |   store <8 x i8> %a, ptr %a.addr, align 2
# |   store <8 x i8> %b, ptr %b.addr, align 2
# |   %2 = load <8 x i8>, ptr %a.addr, align 2
# |   %3 = load <8 x i8>, ptr %b.addr, align 2
# |   %cmp = icmp eq <8 x i8> %2, %3
# |   %sext = sext <8 x i1> %cmp to <8 x i8>
# |   store <8 x i8> %sext, ptr %retval, align 2
# |   %4 = load <8 x i8>, ptr %retval, align 2
# |   %cast.scalable = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> poison, <8 x i8> %4, i64 0)
# |   %5 = bitcast <vscale x 2 x i8> %cast.scalable to <vscale x 16 x i1>
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8>, <8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @eq_i8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <64 x i8> %0, %1
# |   %sext = sext <64 x i1> %cmp to <64 x i8>
# |   store <64 x i8> %sext, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8>, <64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @eq_i16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <32 x i16> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i16>
# |   store <32 x i16> %sext, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16>, <32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @eq_i32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <16 x i32> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x i32>
# |   store <16 x i32> %sext, ptr %retval, align 16
# |   %2 = load <16 x i32>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> %2, i64 0)
# |   ret <vscale x 4 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32>, <16 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i64> @eq_i64(<vscale x 2 x i64> noundef %a.coerce, <vscale x 2 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i64>, align 16
# |   %a.addr = alloca <8 x i64>, align 16
# |   %b.addr = alloca <8 x i64>, align 16
# |   %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %a.coerce, i64 0)
# |   %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> %b.coerce, i64 0)
# |   store <8 x i64> %a, ptr %a.addr, align 16
# |   store <8 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i64>, ptr %a.addr, align 16
# |   %1 = load <8 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp eq <8 x i64> %0, %1
# |   %sext = sext <8 x i1> %cmp to <8 x i64>
# |   store <8 x i64> %sext, ptr %retval, align 16
# |   %2 = load <8 x i64>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> poison, <8 x i64> %2, i64 0)
# |   ret <vscale x 2 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64>, <8 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 16 x i8> @eq_u8(<vscale x 16 x i8> noundef %a.coerce, <vscale x 16 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <64 x i8>, align 16
# |   %a.addr = alloca <64 x i8>, align 16
# |   %b.addr = alloca <64 x i8>, align 16
# |   %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %a.coerce, i64 0)
# |   %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> %b.coerce, i64 0)
# |   store <64 x i8> %a, ptr %a.addr, align 16
# |   store <64 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <64 x i8>, ptr %a.addr, align 16
# |   %1 = load <64 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <64 x i8> %0, %1
# |   %sext = sext <64 x i1> %cmp to <64 x i8>
# |   store <64 x i8> %sext, ptr %retval, align 16
# |   %2 = load <64 x i8>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> poison, <64 x i8> %2, i64 0)
# |   ret <vscale x 16 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i16> @eq_u16(<vscale x 8 x i16> noundef %a.coerce, <vscale x 8 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i16>, align 16
# |   %a.addr = alloca <32 x i16>, align 16
# |   %b.addr = alloca <32 x i16>, align 16
# |   %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %a.coerce, i64 0)
# |   %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> %b.coerce, i64 0)
# |   store <32 x i16> %a, ptr %a.addr, align 16
# |   store <32 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <32 x i16>, ptr %a.addr, align 16
# |   %1 = load <32 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <32 x i16> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i16>
# |   store <32 x i16> %sext, ptr %retval, align 16
# |   %2 = load <32 x i16>, ptr %retval, align 16
# |   %cast.scalable = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> poison, <32 x i16> %2, i64 0)
# |   ret <vscale x 8 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i32> @eq_u32(<vscale x 4 x i32> noundef %a.coerce, <vscale x 4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i32>, align 16
# |   %a.addr = alloca <16 x i32>, align 16
# |   %b.addr = alloca <16 x i32>, align 16
# |   %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %a.coerce, i64 0)
# |   %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %b.coerce, i64 0)
# |   store <16 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <16 x i32> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x 
# | ...
# `---data was truncated (10240/78785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055c59094c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c5909490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c59094c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb06133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb0618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb06133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb0611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5908e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c5908e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c5908c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c5905760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c590575dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feb0611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb0611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb0611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c590575cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c (494 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilege.x2.nxv16i1(i64 %0, i64 %1)
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilege.x2.nxv16i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv16i1(i64 %0, i64 %1)
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i1>, <vscale x 16 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv16i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilege.x2.nxv8i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilege.x2.nxv8i1(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b16_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv8i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 8 x i1>, <vscale x 8 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i1>, <vscale x 8 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv8i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilege.x2.nxv4i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilege.x2.nxv4i1(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b32_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv4i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 4 x i1>, <vscale x 4 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i1>, <vscale x 4 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv4i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilege.x2.nxv2i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilege.x2.nxv2i1(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilege_b64_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv2i1(i64 %0, i64 %1)
# |   %3 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 0
# |   %4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %3)
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %4, 0
# |   %6 = extractvalue { <vscale x 2 x i1>, <vscale x 2 x i1> } %2, 1
# |   %7 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %6)
# |   %8 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %7, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i1>, <vscale x 2 x i1> } @llvm.aarch64.sve.whilehs.x2.nxv2i1(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svwhilegt_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1
# | ...
# `---data was truncated (10240/37926) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055816539c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005581653990f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055816539c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8bec933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8bec98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8bec933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8bec91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558165331e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558165331c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558165316b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558164fc60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558164fc5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8bec91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8bec91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8bec91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558164fc5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c (495 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdupq_lane_s8(<vscale x 16 x i8> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdupq_lane_s16(<vscale x 8 x i16> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdupq_lane_s32(<vscale x 4 x i32> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdupq_lane_s64(<vscale x 2 x i64> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdupq_lane_u8(<vscale x 16 x i8> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdupq_lane_u16(<vscale x 8 x i16> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdupq_lane_u32(<vscale x 4 x i32> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdupq_lane_u64(<vscale x 2 x i64> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdupq_lane_f16(<vscale x 8 x half> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdupq_lane_f32(<vscale x 4 x float> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svdupq_lane_f64(<vscale x 2 x double> %data, i64 noundef %index) #0 {
# | entry:
# |   %data.addr = alloca <vscale x 2 x double>, align 16
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %data, ptr %data.addr, align 16
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %data.addr, align 16
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdupq_n_s8(i8 noundef %x0, i8 noundef %x1, i8 noundef %x2, i8 noundef %x3, i8 noundef %x4, i8 noundef %x5, i8 noundef %x6, i8 noundef %x7, i8 noundef %x8, i8 noundef %x9, i8 noundef %x10, i8 noundef %x11, i8 noundef %x12, i8 noundef %x13, i8 noundef %x14, i8 noundef %x15) #0 {
# | entry:
# |   %x0.addr = alloca i8, align 1
# |   %x1.addr = alloca i8, align 1
# |   %x2.addr = alloca i8, align 1
# |   %x3.addr = alloca i8, align 1
# |   %x4.addr = alloca i8, align 1
# |   %x5.addr = alloca i8, align 1
# |   %x6.addr = alloca i8, align 1
# |   %x7.addr = alloca i8, align 1
# |   %x8.addr = alloca i8, align 1
# |   %x9.addr = alloca i8, align 1
# |   %x10.addr = alloca i8, align 1
# |   %x11.addr = alloca i8, align 1
# |   %x12.addr = alloca i8, align 1
# |   %x13.addr = alloca i8, align 1
# |   %x14.addr = alloca i8, align 1
# |   %x15.addr = alloca i8, align 1
# |   store i8 %x0, ptr %x0.addr, align 1
# |   store i8 %x1, ptr %x1.addr, align 1
# |   store i8 %x2, ptr %x2.addr, align 1
# |   store i8 %x3, ptr %x3.addr, align 1
# |   store i8 %x4, ptr %x4.addr, align 1
# |   store i8 %x5, ptr %x5.addr, align 1
# |   store i8 %x6, ptr %x6.addr, align 1
# |   store i8 %x7, ptr %x7.addr, align 1
# |   store i8 %x8, ptr %x8.addr, align 1
# |   store i8 %x9, ptr %x9.addr, align 1
# |   store i8 %x10, ptr %x10.addr, align 1
# |   store i8 %x11, ptr %x11.addr, align 1
# |   store i8 %x12, ptr %x12.addr, align 1
# |   store i8 %x13, ptr %x13.addr, align 1
# |   store i8 %x14, ptr %x14.addr, align 1
# |   store i8 %x15, ptr %x15.addr, align 1
# |   %0 = load i8, ptr %x0.addr, align 1
# |   %1 = load i8, ptr %x1.addr, align 1
# |   %2 = load i8, ptr %x2.addr, align 1
# |   %3 = load i8, ptr %x3.addr, align 1
# |   %4 = load i8, ptr %x4.addr, align 1
# |   %5 = load i8, ptr %x5.addr, align 1
# |   %6 = load i8, ptr %x6.addr, align 1
# |   %7 = load i8, ptr %x7.addr, align 1
# |   %8 = load i8, ptr %x8.addr, align 1
# |   %9 = load i8, ptr %x9.addr, align 1
# |   %10 = load i8, ptr %x10.addr, align 1
# |   %11 = load i8, ptr %x11.addr, align 1
# |   %12 = load i8, ptr %x12.addr, align 1
# |   %13 = load i8, ptr
# | ...
# `---data was truncated (10240/42600) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560f8ff6815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560f8ff650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560f8ff6889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbced533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbced58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbced533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbced51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f8fefde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560f8fefdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560f8fee2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560f8fb920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560f8fb91dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbced51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbced51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbced51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f8fb91cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c (496 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsqrt_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svsqrt_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svsqrt_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsqrt_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svsqrt_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svsqrt_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsqrt_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fsqrt.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svsqrt_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svsqrt_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fsqrt.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560187d5715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560187d540f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560187d5789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc8eb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8eb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc8eb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc8eb231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560187cece2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560187cecc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560187cd1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005601879810b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560187980dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc8eb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8eb2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8eb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560187980cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c (497 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e61001915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e6100160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e61001989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbbdc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbbdc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbbdc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbbdc631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e60ffaee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e60ffaec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e60ff93b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e60fc430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e60fc42dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbbdc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbbdc6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbbdc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e60fc42cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c (498 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2p2 -target-feature +f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2p2 -target-feature +f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_f16(<vscale x 8 x half> %acc, <vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 8 x half>, align 16
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %acc, ptr %acc.addr, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fmmla.nxv8f16.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmmla.nxv8f16.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f16mm,+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557f10b5b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557f10b580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557f10b5b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f680761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68076725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f680761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6807603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f10af0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557f10af0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557f10ad5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557f107850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557f10784dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6807604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68076050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68076050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f10784cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c (499 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsub_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsub_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsub_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsub_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsub_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsub_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsub_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsub_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsub_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/72449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055aa99c9915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aa99c960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aa99c9989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f996c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f996c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f996c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f996c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa99c2ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aa99c2ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aa99c13b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aa998c30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aa998c2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f996c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f996c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f996c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa998c2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c (500 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.add
# | ...
# `---data was truncated (10240/94157) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ffac6c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558ffac690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558ffac6c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6dceb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6dceb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6dceb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6dceb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ffac01e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558ffac01c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558ffabe6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558ffa8960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558ffa895dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6dceb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6dceb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6dceb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ffa895cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c (501 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf8972a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bf897270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bf8972a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96fb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96fb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96fb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96fb031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf896bfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bf896bfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bf896a4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bf893540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bf89353dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f96fb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96fb0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96fb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf89353cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c (502 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmmla_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.smmla.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smmla.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmmla_u32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ummla.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ummla.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svusmmla_s32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %y.addr = alloca <vscale x 16 x i8>, align 16
# |   %z.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   store <vscale x 16 x i8> %y, ptr %y.addr, align 16
# |   store <vscale x 16 x i8> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %y.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.usmmla.nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.usmmla.nxv4i32(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ef880c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ef880c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ef880c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a3501bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a350725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a3501ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a35003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef8805ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ef8805ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ef8803fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ef87cef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ef87ceedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7a35004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a350050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a350050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef87ceecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/rsqrts.c (503 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/rsqrts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrsqrts_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.frsqrts.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frsqrts.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrsqrts_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.frsqrts.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frsqrts.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrsqrts_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.frsqrts.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frsqrts.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x000055692af4b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055692af480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055692af4b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48c7a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48c7aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48c7a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48c7a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055692aee0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055692aee0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055692aec5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055692ab750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055692ab74dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f48c7a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48c7a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48c7a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055692ab74cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c (504 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtblq_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtblq_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tblq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.tblq.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtblq_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tblq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.tblq.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtblq_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tblq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.tblq.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtblq_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtblq_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.tblq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtblq_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.tblq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtblq_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.tblq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtblq_f16(<vscale x 8 x half> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.tblq.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.tblq.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtblq_f32(<vscale x 4 x float> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.tblq.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.tblq.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtblq_f64(<vscale x 2 x double> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.tblq.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.tblq.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtblq_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.tblq.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.tblq.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtblq_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "sta
# | ...
# `---data was truncated (10240/10820) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055c3b504915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c3b50460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c3b504989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9062c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9062ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9062c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9062c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3b4fdee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c3b4fdec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c3b4fc3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c3b4c730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c3b4c72dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9062c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9062c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9062c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3b4c72cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c (505 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpnext_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e3a6e8d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e3a6e8a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e3a6e8d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9eaa049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9eaa0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9eaa049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9eaa031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3a6e22e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e3a6e22c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e3a6e07b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e3a6ab70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e3a6ab6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9eaa032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9eaa0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9eaa0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3a6ab6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c (506 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615b070615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005615b07030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005615b070689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd00a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd00a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd00a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd00a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615b069be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005615b069bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005615b0680b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005615b03300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005615b032fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd00a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd00a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd00a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615b032fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c (507 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32>, <vscale x 2 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   call void @llvm.aarch64.sve.st1.nxv2i32.p0(<vscale x 2 x i32> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32> %3, <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i32>
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i32> %3, <vscale x 2 x i1> %4, <vscale x 2 x i64> %1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   %5 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %5, ptr %1, <vscale x 2 x i64> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0(<vscale x 2 x i32>, <vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #4
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i32>
# |   %5 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0(<vscale x 2 x i32> %4, <vscale x 2 x i1> %5, ptr %1, <vscale x 2 x i64> %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1w_scatter_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = load <vscale x 2 x i64
# | ...
# `---data was truncated (10240/21923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055e848eac15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e848ea90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e848eac89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c2c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c2c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c2c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c2c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e848e41e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e848e41c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e848e26b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e848ad60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e848ad5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9c2c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c2c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c2c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e848ad5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c (508 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.lastp.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.lastp.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.lastp.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlastp_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.lastp.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.lastp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056371854215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056371853f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056371854289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1562449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15624a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1562449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1562431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637184d7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005637184d7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005637184bcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056371816c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056371816bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1562432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15624330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15624330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056371816bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c (509 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpkhi_s16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sunpkhi.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sunpkhi.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpkhi_s32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sunpkhi.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sunpkhi.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpkhi_s64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.sunpkhi.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sunpkhi.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svunpkhi_u16(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.uunpkhi.nxv8i16(<vscale x 16 x i8> %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uunpkhi.nxv8i16(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svunpkhi_u32(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uunpkhi.nxv4i32(<vscale x 8 x i16> %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uunpkhi.nxv4i32(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svunpkhi_u64(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.uunpkhi.nxv2i64(<vscale x 4 x i32> %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uunpkhi.nxv2i64(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svunpkhi_b(<vscale x 16 x i1> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.punpkhi.nxv16i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.punpkhi.nxv16i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005557f4c3515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005557f4c320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005557f4c3589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5e2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5e218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5e2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5e211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557f4bcae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005557f4bcac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005557f4bafb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005557f485f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005557f485edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa5e211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5e211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5e211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557f485ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c (510 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpairo_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <v
# | ...
# `---data was truncated (10240/125480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622f729015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005622f728d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005622f729089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d9df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d9df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d9df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d9df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622f7225e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005622f7225c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005622f720ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005622f6eba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005622f6eb9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4d9df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d9df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d9df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622f6eb9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c (511 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintz_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintz_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintz_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintz_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintz_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintz_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintz_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintz.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintz_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintz_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintz.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556a3cf9615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556a3cf930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556a3cf9689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c7ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c7ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c7ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c7ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a3cf2be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556a3cf2bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556a3cf10b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556a3cbc00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556a3cbbfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5c7ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c7ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c7ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a3cbbfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c (512 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasr_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasr_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasr_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasr_s16_m(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasr_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasr_s64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasr_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.u.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# | 
# | ...
# `---data was truncated (10240/46416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c9f866915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c9f86660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c9f866989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc66c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc66c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc66c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc66c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9f85fee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c9f85fec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c9f85e3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c9f82930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c9f8292dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc66c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc66c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc66c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9f8292cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c (513 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055752ed2415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055752ed210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055752ed2489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe258a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe258aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe258a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe258a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055752ecb9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055752ecb9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055752ec9eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055752e94e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055752e94ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe258a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe258a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe258a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055752e94dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c (514 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/80640) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056067280715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005606728040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056067280789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f4c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f4c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f4c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f4c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056067279ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056067279cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560672781b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005606724310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560672430dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0f4c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f4c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f4c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560672430cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c (515 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svextw_u64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559de549015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559de548d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559de549089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb6801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb680725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb6801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb68003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559de5425e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559de5425c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559de540ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559de50ba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559de50b9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feb68004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb680050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb680050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559de50b9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c (516 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svand_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.and.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.and.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svand_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.and.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.and.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svand_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svand_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.and.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.and.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svand_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.and.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svand_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.and.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svand_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svand_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.and.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svand_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556f7181115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556f7180e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556f7181189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51aac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51aaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51aac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51aac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f717a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556f717a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556f7178bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556f7143b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556f7143add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f51aac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51aac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51aac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f7143acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c (517 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmin_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603bfda715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005603bfda40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005603bfda789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7156d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7156d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7156d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7156ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603bfd3ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005603bfd3cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005603bfd21b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005603bf9d10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005603bf9d0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7156ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7156cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7156cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603bf9d0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c (518 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld4_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld4_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld4_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld4_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld4_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld4_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld4_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld4_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svld4_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld4.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld4.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svld4_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.fr
# | ...
# `---data was truncated (10240/27970) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005617aa49915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005617aa4960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005617aa49989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9694533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f969458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9694533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f969451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617aa42ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005617aa42ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005617aa413b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005617aa0c30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005617aa0c2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f969451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f969451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f969451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617aa0c2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c (519 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055664dbf815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055664dbf50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055664dbf889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff26e01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff26e0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff26e01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff26e003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055664db8de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055664db8dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055664db72b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055664d8220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055664d821dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff26e004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff26e0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff26e0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055664d821cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c (520 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntp_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055942273615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005594227330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055942273689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c8ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c8caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c8ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c8ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594226cbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005594226cbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005594226b0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005594223600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055942235fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2c8ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c8ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c8ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055942235fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c (521 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bff14fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bff14f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bff14fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd80e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd80e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd80e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd80e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bff1491e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bff1491c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bff1476b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bff11260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bff1125dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd80e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd80e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd80e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bff1125cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve/minnmv.c (522 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/minnmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svminnmv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svminnmv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svminnmv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x00005595750c215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005595750bf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005595750c289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1820f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1820f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1820f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1820f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559575057e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559575057c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055957503cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559574cec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559574cebdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1820f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1820f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1820f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559574cebcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c (523 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, al
# | ...
# `---data was truncated (10240/169925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc9c72a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cc9c7270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cc9c72a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25c7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25c758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25c7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25c751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc9c6bfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cc9c6bfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cc9c6a4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cc9c3540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cc9c353dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f25c751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25c751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25c751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc9c353cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c (524 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbxq_u8(<vscale x 16 x i8> %passthru, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 16 x i8>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbxq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.tbxq.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbxq_u16(<vscale x 8 x i16> %passthru, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 8 x i16>, align 16
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbxq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.tbxq.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbxq_u32(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 4 x i32>, align 16
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbxq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.tbxq.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbxq_u64(<vscale x 2 x i64> %passthru, <vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 2 x i64>, align 16
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbxq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.tbxq.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtbxq_s8(<vscale x 16 x i8> %passthru, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 16 x i8>, align 16
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.tbxq.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtbxq_s16(<vscale x 8 x i16> %passthru, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 8 x i16>, align 16
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.tbxq.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtbxq_s32(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 4 x i32>, align 16
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.tbxq.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtbxq_s64(<vscale x 2 x i64> %passthru, <vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 2 x i64>, align 16
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.tbxq.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtbxq_f16(<vscale x 8 x half> %passthru, <vscale x 8 x half> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 8 x half>, align 16
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.tbxq.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.tbxq.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtbxq_f32(<vscale x 4 x float> %passthru, <vscale x 4 x float> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %passthru.addr = alloca <vscale x 4 x float>, align 16
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %passthru, ptr %passthru.addr, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %passthru.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.tbxq.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.
# | ...
# `---data was truncated (10240/14102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055a70895a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a7089570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a70895a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ca4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ca498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ca4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ca491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7088efe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a7088efc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a7088d4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a7085840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a708583dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8ca491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ca491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ca491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a708583cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c (525 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmulx_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fmulx.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmulx.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmulx_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fmulx.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmulx.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmulx_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fmulx.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fmulx.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmulx_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmulx.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmulx_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmulx.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmulx_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fmulx.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmulx_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmulx.u.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmulx.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmulx_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmulx.u.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmulx.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmulx_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 
# | ...
# `---data was truncated (10240/22063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005593e2e2315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005593e2e200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005593e2e2389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f098bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f098bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f098bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f098bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593e2db8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005593e2db8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005593e2d9db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005593e2a4d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005593e2a4cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f098bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f098bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f098bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593e2a4ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c (526 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; F
# | ...
# `---data was truncated (10240/102296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563beceb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005563bece80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005563beceb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f391c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f391c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f391c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f391c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563bec80e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005563bec80c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005563bec65b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005563be9150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005563be914dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f391c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f391c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f391c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563be914cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c (527 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8
# | ...
# `---data was truncated (10240/80508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aff670d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aff670a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aff670d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faadfe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faadfe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faadfe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faadfe03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aff66a2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aff66a2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aff6687b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aff63370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aff6336dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faadfe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faadfe050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faadfe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aff6336cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c (528 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za32_f8_vg1x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za32_f8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load i32, ptr %slice.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %11 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %11)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za16_f8_vg1x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svdot_lane_za16_f8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load i32, ptr %slice.addr, align 4
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 2
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 3
# |   %10 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %11 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %11)
# |   call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32 %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_ra
# | ...
# `---data was truncated (10240/35066) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# |  #0 0x000055ac0c28915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ac0c2860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ac0c28989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff0a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff0a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff0a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff0a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac0c21ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ac0c21ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ac0c203b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ac0beb30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ac0beb2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007eff0a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff0a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff0a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac0beb2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c (529 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svexpand_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svexpand_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.expand.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.expand.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svexpand_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svexpand_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.expand.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svexpand_mf8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.expand.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svexpand_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.expand.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.expand.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svexpand_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.expand.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.expand.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexpand_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.expand.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.expand.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexpand_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.expand.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.expand.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svexpand_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.expand.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svexpand_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.expand.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svexpand_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, al
# | ...
# `---data was truncated (10240/12168) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056335bf5515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056335bf520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056335bf5589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff131649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1316a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff131649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff131631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056335beeae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056335beeac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056335becfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056335bb7f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056335bb7edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff131632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1316330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1316330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056335bb7ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c (530 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1uh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1uh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a62b5f015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a62b5ed0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a62b5f089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38a7905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38a795c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38a7905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38a78ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a62b585e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a62b585c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a62b56ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a62b21a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a62b219dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f38a78eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38a78ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38a78ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a62b219cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c (531 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/65582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb9713f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fb9713c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fb9713f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a48133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a4818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a48133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a4811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb970d4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fb970d4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fb970b9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fb96d690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fb96d68dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3a4811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a4811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a4811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb96d68cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c (532 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a63329d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a63329a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a63329d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc32933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc3298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc32933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc3291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a633232e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a633232c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a633217b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a632ec70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a632ec6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcc3291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc3291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc3291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a632ec6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c (533 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsel_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsel_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsel_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsel_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsel_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsel_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsel_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsel_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsel_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_
# | ...
# `---data was truncated (10240/15264) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055e95754315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e9575400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e95754389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f702ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f702ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f702ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f702ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9574d8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e9574d8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e9574bdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e95716d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e95716cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f702ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f702ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f702ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e95716ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c (534 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_s8_x2(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   %11 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount"), <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_u8_x2(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   %11 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %11
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svsel_mf8_x2(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm.coerce0, <vscale x 16 x i8> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zm.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 0
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %5, 1
# |   %8 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 0
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %8, 1
# |   %11 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %11
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svsel_s16_x2(target("aarch64.svcount") %pn, <vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pn.addr = alloca target("aarch64.svcount"), align 2
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store target("aarch64.svcount") %pn, ptr %pn.addr, align 2
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2
# |   %5 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 0
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %5, 1
# |   %8 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 0
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %8, 1
# |   %11 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount") %4, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount"), <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale 
# | ...
# `---data was truncated (10240/33971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000561eeca9915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561eeca960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561eeca9989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca3c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca3c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca3c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca3c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561eeca2ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561eeca2ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561eeca13b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561eec6c30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561eec6c2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fca3c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca3c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca3c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561eec6c2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl (535 of 27911)
******************** TEST 'Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_first -DTYPE=float -DCONST=256.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_first -DTYPE=float -DCONST=256.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_second -DTYPE=int -DCONST=128.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.1.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_second -DTYPE=int -DCONST=128.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.1.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
# RUN: at line 8
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc
# |  #0 0x000055a03184f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a03184c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a03184f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6ae849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6ae8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6ae849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6ae831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0317e4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a0317e4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a0317c9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a0314790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a031478dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc6ae832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6ae8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6ae8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a031478cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c (536 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.7a -target-feature +f16mm -target-feature +f16f32mm  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.7a -target-feature +f16mm -target-feature +f16f32mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <8 x half> @test_vmmlaq_f16(<8 x half> noundef %acc, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <8 x half> %acc, ptr %acc.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %acc.addr, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %fmmla.i = bitcast <16 x i8> %3 to <8 x half>
# |   %fmmla1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fmmla2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %fmmla3.i = call <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v8f16(<8 x half> %fmmla.i, <8 x half> %fmmla1.i, <8 x half> %fmmla2.i)
# |   store <8 x half> %fmmla3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %6, ptr %__ret.i, align 16
# |   %7 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <4 x float> @test_vmmlaq_f32_f16(<4 x float> noundef %acc, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <4 x float> %acc, ptr %acc.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %acc.addr, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %fmmla.i = bitcast <16 x i8> %3 to <4 x float>
# |   %fmmla1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fmmla2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %fmmla3.i = call <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v8f16(<4 x float> %fmmla.i, <8 x half> %fmmla1.i, <8 x half> %fmmla2.i)
# |   store <4 x float> %fmmla3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v8f16(<8 x half>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f16f32dot,+f16f32mm,+f16mm,+faminmax,+flagm,+fp-armv8,+fprcvt,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+sve2p3,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9.7a,+v9a,+wfxt" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000561939cd715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561939cd40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561939cd789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa53af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa53af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa53af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa53af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561939c6ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561939c6cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561939c51b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005619399010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561939900dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa53af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa53af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa53af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561939900cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c (537 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_s8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_u8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_mf8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svzip_s16_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zn.coerce2, <vscale x 8 x i16> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zn.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 3
# |   %9 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x4.nxv8i16(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %8)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | ...
# `---data was truncated (10240/67329) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055bbe977415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bbe97710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bbe977489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d5e61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d5e6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d5e61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d5e603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbe9709e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bbe9709c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bbe96eeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bbe939e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bbe939ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9d5e604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d5e6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d5e6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbe939dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c (538 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i
# | ...
# `---data was truncated (10240/13153) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d55cc2815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d55cc250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d55cc2889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9060133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f906018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9060133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f906011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d55cbbde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d55cbbdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d55cba2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d55c8520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d55c851dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f906011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f906011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f906011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d55c851cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c (539 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ededf3b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ededf380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ededf3b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc76fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc76faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc76fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc76fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ededed0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ededed0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ededeb5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ededb650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ededb64dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc76fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc76fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc76fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ededb64cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/subtraction.c (540 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/subtraction.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vsub_s8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <8 x i8> %2, %3
# |   store <8 x i8> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vsubq_s8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v1.addr = alloca <16 x i8>, align 16
# |   %v2.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v1, ptr %v1.addr, align 16
# |   store <16 x i8> %v2, ptr %v2.addr, align 16
# |   %0 = load <16 x i8>, ptr %v1.addr, align 16
# |   %1 = load <16 x i8>, ptr %v2.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <16 x i8> %2, %3
# |   store <16 x i8> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vsub_s16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <4 x i16> %2, %3
# |   store <4 x i16> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vsubq_s16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v1.addr = alloca <8 x i16>, align 16
# |   %v2.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %v1, ptr %v1.addr, align 16
# |   store <8 x i16> %v2, ptr %v2.addr, align 16
# |   %0 = load <8 x i16>, ptr %v1.addr, align 16
# |   %1 = load <8 x i16>, ptr %v2.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <8 x i16> %2, %3
# |   store <8 x i16> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsub_s32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <2 x i32> %2, %3
# |   store <2 x i32> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vsubq_s32(<4 x i32> noundef %v1, <4 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v1.addr = alloca <4 x i32>, align 16
# |   %v2.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %v1, ptr %v1.addr, align 16
# |   store <4 x i32> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x i32>, ptr %v1.addr, align 16
# |   %1 = load <4 x i32>, ptr %v2.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <4 x i32> %2, %3
# |   store <4 x i32> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vsub_s64(<1 x i64> noundef %v1, <1 x i64> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %v1.addr = alloca <1 x i64>, align 8
# |   %v2.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %v1, ptr %v1.addr, align 8
# |   store <1 x i64> %v2, ptr %v2.addr, align 8
# |   %0 = load <1 x i64>, ptr %v1.addr, align 8
# |   %1 = load <1 x i64>, ptr %v2.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <1 x i64> %2, %3
# |   store <1 x i64> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vsubq_s64(<2 x i64> noundef %v1, <2 x i64> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v1.addr = alloca <2 x i64>, align 16
# |   %v2.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %v1, ptr %v1.addr, align 16
# |   store <2 x i64> %v2, ptr %v2.addr, align 16
# |   %0 = load <2 x i64>, ptr %v1.addr, align 16
# |   %1 = load <2 x i64>, ptr %v2.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %sub.i = sub <2 x i64> %2, %3
# |   store <2 x i64> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vsub_u8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <8 x i8> %2, %3
# |   store <8 x i8> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vsub_u16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <4 x i16> %2, %3
# |   store <4 x i16> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsub_u32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %sub.i = sub <2 x i32> %2, %3
# |   store <2 x i32> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vsub_u64(<1 x i64> noundef %v1, <1 x i64> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %v1.addr = alloca <1 x i64>, align 8
# |   %v2.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %v1, ptr %v1.addr, align 8
# |   
# | ...
# `---data was truncated (10240/170019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x00005578d4dba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005578d4db70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005578d4dba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb661f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb661f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb661f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb661eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578d4d4fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005578d4d4fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005578d4d34b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005578d49e40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005578d49e3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb661eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb661eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb661eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578d49e3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c (541 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %index.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4_tu(<vscale x 16 x half> %ma
# | ...
# `---data was truncated (10240/619127) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055618861515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005561886120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055618861589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1eb2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1eb278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1eb2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1eb271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561885aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005561885aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055618858fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055618823f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055618823edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1eb271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1eb271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1eb271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055618823ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c (542 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: wri
# | ...
# `---data was truncated (10240/20523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a3692415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560a369210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560a3692489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff59b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff59b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff59b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff59b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a368b9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560a368b9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560a3689eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560a3654e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560a3654ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff59b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff59b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff59b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a3654dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c (543 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svsetffr() #0 {
# | entry:
# |   call void @llvm.aarch64.sve.setffr()
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.sve.setffr() #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005610e559e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005610e559b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005610e559e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f816a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f816a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f816a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f816a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610e5533e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005610e5533c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005610e5518b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005610e51c80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005610e51c7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f816a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f816a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f816a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610e51c7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c (544 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrem_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611407d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005611407d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005611407d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8539b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8539b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8539b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8539b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561140769e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561140769c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056114074eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005611403fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005611403fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8539b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8539b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8539b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611403fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c (545 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svsub_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b63584315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b6358400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b63584389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08aa049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08aa0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08aa049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08aa031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6357d8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b6357d8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b6357bdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b63546d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b63546cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f08aa032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08aa0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08aa0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b63546ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c (546 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8(<vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4(<vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2(<vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vrsub_vx_i16m1(<vscale x 4 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vrsub_vx_i16m2(<vscale x 8 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16
# | ...
# `---data was truncated (10240/84971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557296d7615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557296d730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557296d7689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3382b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3382b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3382b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3382b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557296d0be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557296d0bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557296cf0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005572969a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055729699fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3382b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3382b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3382b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055729699fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c (547 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcls_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcls_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcls_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcls_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcls_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcls_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcls_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svcls_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcls_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcls_s16_x(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svcls_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1
# | ...
# `---data was truncated (10240/11769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005606bb18315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005606bb1800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005606bb18389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa38461bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3846725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa38461ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa384603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606bb118e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005606bb118c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005606bb0fdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005606badad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005606badacdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa384604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3846050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3846050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606badaccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c (548 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld3_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld3_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld3_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld3_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svld3_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svld3_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svld3_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svld3_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svld3_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld3.sret.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.ld3.sret.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svld3_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld3.sret.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld3.sret.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @test_svld3_f64(<vscale x
# | ...
# `---data was truncated (10240/26187) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b768bc715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b768bc40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b768bc789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7185b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7185b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7185b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7185b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b768b5ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b768b5cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b768b41b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b7687f10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b7687f0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7185b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7185b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7185b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7687f0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c (549 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_n_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_n_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmin_bf16_n_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.u.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000556116f2915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556116f260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556116f2989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9be2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9be298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9be2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9be291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556116ebee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556116ebec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556116ea3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556116b530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556116b52dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9be291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9be291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9be291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556116b52cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c (550 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintn_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintn_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintn_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintn_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintn_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintn_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintn_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintn.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintn_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintn_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintn.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055bd6fe4d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bd6fe4a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bd6fe4d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa591f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa591f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa591f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa591f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd6fde2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bd6fde2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bd6fdc7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bd6fa770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bd6fa76dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa591f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa591f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa591f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd6fa76cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c (551 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   st
# | ...
# `---data was truncated (10240/110292) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfb87e915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dfb87e60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dfb87e989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe8c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe8c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe8c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe8c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfb877ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dfb877ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dfb8763b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dfb84130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dfb8412dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efe8c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe8c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe8c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfb8412cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c (552 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(<vscale x 4 x i32> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(<vscale x 4 x i32>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s32(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(<vscale x 4 x i32> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(<vscale x 8 x i16> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(<vscale x 8 x i16>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s16(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(<vscale x 8 x i16> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_u8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(<vscale x 16 x i8> %3, <vscale x 1 x i1> %4, <vscale x 2 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(<vscale x 16 x i8>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1q_scatter_u64base_offset_s8(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %base, i64 noundef %offset, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca <vscale x 2 x i64>, align 16
# |   %offset.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %base, ptr %base.addr, align 16
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %base.addr, align 16
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   %4 = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(<vscale x 16 x i8> %3, <vscale x 1 x i1> %
# | ...
# `---data was truncated (10240/93831) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000556e92f6a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556e92f670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556e92f6a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc7ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc7eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc7ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc7ea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e92effe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556e92effc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556e92ee4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556e92b940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556e92b93dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efc7ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc7ea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc7ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e92b93cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c (553 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bba53115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563bba52e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563bba53189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa21ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa21ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa21ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa21ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bba4c6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563bba4c6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563bba4abb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563bba15b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563bba15add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa21ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa21ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa21ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bba15acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c (554 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrw_u32base_s32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrw_u64base_s64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrw_u32base_u32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrw.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrw_u64base_u64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrw.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055574e60015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055574e5fd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055574e60089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb755849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7558a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb755849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb755831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055574e595e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055574e595c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055574e57ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055574e22a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055574e229dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb755832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7558330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7558330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055574e229cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c (555 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf6c7df15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bf6c7dc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bf6c7df89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d10d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d10d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d10d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d10d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf6c774e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bf6c774c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bf6c759b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bf6c4090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bf6c408dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5d10d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d10d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d10d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf6c408cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c (556 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f16f16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f16f16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_cvtl_f32_x2(<vscale x 8 x half> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fcvtl.widen.x2.nxv4f32(<vscale x 8 x half> %0)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fcvtl.widen.x2.nxv4f32(<vscale x 8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f16f16" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005652a8ac315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005652a8ac00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005652a8ac389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe278b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe278b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe278b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe278b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652a8a58e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005652a8a58c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005652a8a3db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005652a86ed0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005652a86ecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe278b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe278b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe278b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652a86eccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c (557 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1>, ptr, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %2, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i32>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv4i1.p0(<vscale x 4 x i1> %3, ptr %4, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfw_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store 
# | ...
# `---data was truncated (10240/17826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d88f09c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d88f0990f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d88f09c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92f4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92f4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92f4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92f4f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d88f031e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d88f031c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d88f016b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d88ecc60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d88ecc5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f92f4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92f4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92f4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d88ecc5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c (558 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not=' @llvm.fma.'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vfma_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <4 x half>
# |   %7 = bitcast <8 x i8> %4 to <4 x half>
# |   %8 = bitcast <8 x i8> %5 to <4 x half>
# |   %9 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %7, <4 x half> %8, <4 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %10, ptr %__ret.i, align 8
# |   %11 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <8 x half>
# |   %7 = bitcast <16 x i8> %4 to <8 x half>
# |   %8 = bitcast <16 x i8> %5 to <8 x half>
# |   %9 = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %7, <8 x half> %8, <8 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <8 x half> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %10, ptr %__ret.i, align 16
# |   %11 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vfma_lane_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   %fmla = bitcast <8 x i8> %4 to <4 x half>
# |   %fmla1 = bitcast <8 x i8> %3 to <4 x half>
# |   %fmla2 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %fmla, <4 x half> %lane, <4 x half> %fmla1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %7, ptr %__ret, align 8
# |   %8 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %8, ptr %tmp, align 8
# |   %9 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half>, <4 x half>, <4 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vfmaq_lane_f16(<8 x half> noundef %a, <8 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   %fmla = bitcast <16 x i8> %4 to <8 x half>
# |   %fmla1 = bitcast <16 x i8> %3 to <8 x half>
# |   %fmla2 = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %fmla, <8 x half> %lane, <8 x half> %fmla1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <8 x half> %fmla2, ptr %ref.tmp, align 16
# |   %7 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %7, ptr %__ret, align 16
# |   %8 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %8, ptr %tmp, align 16
# |   %9 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half>, <8 x half>, <8 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vfma_laneq_f16(<4 x half> noundef %a, <4 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <8 x i8> %3 to <4 x half>
# |   %7 = bitcast <8 x i8> %4 to <4 x half>
# |   %8 = bitcast <16 x i8> %5 to <8 x half>
# |   %lane = shufflevector <8 x half> %8, <8 x half> %8, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   %9 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %lane, <4 x half> %7, <4 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %9, ptr %ref.tmp, align 8
# |   %10 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %10, ptr %__ret, align 8
# |   %11 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %11, ptr %tmp, align 8
# |   %12 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vfmaq_laneq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16
# | ...
# `---data was truncated (10240/13273) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000561951e0615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561951e030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561951e0689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3aa8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3aa818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3aa8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3aa811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561951d9be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561951d9bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561951d80b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561951a300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561951a2fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3aa811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3aa811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3aa811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561951a2fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap '--implicit-check-not= @llvm.fma.'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not= @llvm.fma.
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c (559 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.trn2q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.trn2q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.trn2q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.trn2q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svtrn2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.trn2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svtrn2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.trn2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svtrn2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.trn2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svtrn2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.trn2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtrn2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.trn2q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.trn2q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtrn2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.trn2q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.trn2q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtrn2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.trn2q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.trn2q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svtrn2_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.trn2q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.trn2q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055895408615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005589540830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055895408689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc835533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc83558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc835533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc83551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055895401be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055895401bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558954000b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558953cb00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558953cafdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc83551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc83551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc83551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558953cafcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c (560 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_i16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |  
# | ...
# `---data was truncated (10240/19083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bde319c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bde31990f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bde319c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f8a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f8a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f8a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f8a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bde3131e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bde3131c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bde3116b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bde2dc60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bde2dc5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6f8a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f8a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f8a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bde2dc5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c (561 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f32mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f32mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmmla_f32(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 4 x float>, align 16
# |   %z.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 4 x float> %y, ptr %y.addr, align 16
# |   store <vscale x 4 x float> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %y.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f32mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560997fc315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560997fc00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560997fc389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd394e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd394e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd394e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd394e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560997f58e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560997f58c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560997f3db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560997bed0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560997becdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd394e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd394e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd394e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560997beccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c (562 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 1
# | ...
# `---data was truncated (10240/68509) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564412bef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564412bec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564412bef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9d6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9d6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9d6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9d6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564412b84e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564412b84c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564412b69b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005644128190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564412818dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff9d6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9d6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9d6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564412818cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c (563 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055982e77c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055982e7790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055982e77c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38f3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38f318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38f3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38f311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055982e711e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055982e711c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055982e6f6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055982e3a60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055982e3a5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f38f311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38f311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38f311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055982e3a5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c (564 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @and_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %and = and <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @and_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %and = and <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @and_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %and = and <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @and_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %and = and <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @and_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %and = and <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @and_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %and = and <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @and_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %and = and <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @and_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %and = and <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @and_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %and = and <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %and
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @or_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %or = or <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @or_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %or = or <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @or_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %or = or <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @or_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %or = or <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @or_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %or = or <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @or_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %or = or <vscale x 16 x i8> %0, %1
# |   ret <vscale x 16 x i8> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @or_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %or = or <vscale x 8 x i16> %0, %1
# |   ret <vscale x 8 x i16> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @or_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %or = or <vscale x 4 x i32> %0, %1
# |   ret <vscale x 4 x i32> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @or_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %or = or <vscale x 2 x i64> %0, %1
# |   ret <vscale x 2 x i64> %or
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @xor_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vsca
# | ...
# `---data was truncated (10240/18831) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005647ccbcb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005647ccbc80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005647ccbcb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d7eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d7eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d7eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d7eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647ccb60e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005647ccb60c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005647ccb45b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005647cc7f50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005647cc7f4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7d7eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d7eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d7eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647cc7f4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c (565 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svcreate4_b(<vscale x 16 x i1> %x0, <vscale x 16 x i1> %x1, <vscale x 16 x i1> %x2, <vscale x 16 x i1> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i1>, align 2
# |   %x1.addr = alloca <vscale x 16 x i1>, align 2
# |   %x2.addr = alloca <vscale x 16 x i1>, align 2
# |   %x4.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %x0, ptr %x0.addr, align 2
# |   store <vscale x 16 x i1> %x1, ptr %x1.addr, align 2
# |   store <vscale x 16 x i1> %x2, ptr %x2.addr, align 2
# |   store <vscale x 16 x i1> %x4, ptr %x4.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %x0.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %x1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %x2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %x4.addr, align 2
# |   %4 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %0, 0
# |   %5 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %1, 1
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %5, <vscale x 16 x i1> %2, 2
# |   %7 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6, <vscale x 16 x i1> %3, 3
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %7
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563377a8c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563377a890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563377a8c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e72d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e72d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e72d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e72ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563377a21e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563377a21c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563377a06b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005633776b60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005633776b5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5e72ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e72cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e72cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633776b5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGenCXX/inline-then-fold-variadics.cpp (566 of 27911)
******************** TEST 'Clang :: CodeGenCXX/inline-then-fold-variadics.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp -triple wasm32-unknown-unknown -Wno-varargs -O1 -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S --passes='module(expand-variadics,default<O1>)' --expand-variadics-override=optimize -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp -triple wasm32-unknown-unknown -Wno-varargs -O1 -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp"
# | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"
# | target triple = "wasm32-unknown-unknown"
# | 
# | %struct.asc = type { i8, i16, i32, i32, float, double }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @first_pair_i32(i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL5firstIiiET_z(i32 noundef %x, i32 noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL5firstIiiET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   store ptr %argp.next, ptr %va, align 4
# |   %0 = load i32, ptr %argp.cur, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @second_pair_i32(i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL6secondIiiET0_z(i32 noundef %x, i32 noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL6secondIiiET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 8
# |   store ptr %argp.next2, ptr %va, align 4
# |   %0 = load i32, ptr %argp.next, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @first_pair_f64(double noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL5firstIddET_z(double noundef %x, double noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL5firstIddET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   store ptr %argp.next, ptr %va, align 4
# |   %1 = load double, ptr %argp.cur.aligned, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @second_pair_f64(double noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL6secondIddET0_z(double noundef %x, double noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL6secondIddET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %1 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 16
# |   store ptr %argp.next2, ptr %va, align 4
# |   %2 = load double, ptr %1, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %2
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @first_i32_f64(i32 noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL5firstIidET_z(i32 noundef %x, double noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL5firstIidET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   store ptr %argp.next, ptr %va, align 4
# |   %0 = load i32, ptr %argp.cur, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @second_i32_f64(i32 noundef %x, double noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL6secondIidET0_z(i32 noundef %x, double noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL6secondIidET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 11
# |   %argp.cur1.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur1.aligned, i32 8
# |   store ptr %argp.next2, ptr %va, align 4
# |   %1 = load double, ptr %argp.cur1.aligned, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef double @first_f64_i32(double noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef double (...) @_ZL5firstIdiET_z(double noundef %x, i32 noundef %y)
# |   ret double %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef double @_ZL5firstIdiET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   store ptr %argp.next, ptr %va, align 4
# |   %1 = load double, ptr %argp.cur.aligned, align 8, !tbaa !7
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret double %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @second_f64_i32(double noundef %x, i32 noundef %y) local_unnamed_addr #0 {
# | entry:
# |   %call = tail call noundef i32 (...) @_ZL6secondIdiET0_z(double noundef %x, i32 noundef %y)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL6secondIdiET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7
# |   %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8)
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8
# |   %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 12
# |   store ptr %argp.next2, ptr %va, align 4
# |   %1 = load i32, ptr %argp.next, align 8, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define noundef i32 @first_i32_ulong2(i32 noundef %x, ptr nofree noundef readonly captures(none) %y) local_unnamed_addr #0 {
# | entry:
# |   %0 = load <2 x i64>, ptr %y, align 16, !tbaa !9
# |   %call = tail call noundef i32 (...) @_ZL5firstIiDv2_yET_z(i32 noundef %x, <2 x i64> noundef %0)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef i32 @_ZL5firstIiDv2_yET_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr nonnull %va)
# |   %argp.cur = load ptr, ptr %va, align 4
# |   %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4
# |   store ptr %argp.next, ptr %va, align 4
# |   %0 = load i32, ptr %argp.cur, align 4, !tbaa !6
# |   call void @llvm.va_end.p0(ptr %va)
# |   call void @llvm.lifetime.end.p0(ptr nonnull %va) #4
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define void @second_i32_ulong2(i32 noundef %x, ptr nofree noundef readonly captures(none) %y, ptr nofree noundef writeonly captures(none) initializes((0, 16)) %r) local_unnamed_addr #0 {
# | entry:
# |   %0 = load <2 x i64>, ptr %y, align 16, !tbaa !9
# |   %call = tail call noundef <2 x i64> (...) @_ZL6secondIiDv2_yET0_z(i32 noundef %x, <2 x i64> noundef %0)
# |   store <2 x i64> %call, ptr %r, align 16, !tbaa !9
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
# | define internal noundef <2 x i64> @_ZL6secondIiDv2_yET0_z(...) unnamed_addr #0 {
# | entry:
# |   %va = alloca ptr, align 4
# |   call void @llvm.lifetime.start.p0(ptr nonnull %va) #4
# |   call void @llvm.va_start.p0(ptr n
# | ...
# `---data was truncated (10240/20646) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S '--passes=module(expand-variadics,default<O1>)' --expand-variadics-override=optimize -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S --passes=module(expand-variadics,default<O1>) --expand-variadics-override=optimize -o -
# |  #0 0x0000557f2968d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557f2968a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557f2968d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0db4d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0db4d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0db4d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0db4ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f29622e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557f29622c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557f29607b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557f292b70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557f292b6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0db4ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0db4cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0db4cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f292b6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c (567 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d22de815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561d22de50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561d22de889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1df1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1df138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1df1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1df131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d22d7de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561d22d7dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561d22d62b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561d22a120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561d22a11dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1df131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1df131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1df131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d22a11cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c (568 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cdea47f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cdea47c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cdea47f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6edab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6edab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6edab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6edab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cdea414e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cdea414c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cdea3f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cdea0a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cdea0a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6edab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6edab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6edab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cdea0a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c (569 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f90735515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f9073520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f90735589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1818a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1818aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1818a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1818a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9072eae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f9072eac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f9072cfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f906f7f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f906f7edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1818a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1818a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1818a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f906f7ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c (570 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   
# | ...
# `---data was truncated (10240/25616) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b451c8d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b451c8a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b451c8d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7c7d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7c7d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7c7d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7c7ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b451c22e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b451c22c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b451c07b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b4518b70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b4518b6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd7c7ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7c7cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7c7cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4518b6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c (571 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svindex_s8(i8 noundef %base, i8 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i8, align 1
# |   %step.addr = alloca i8, align 1
# |   store i8 %base, ptr %base.addr, align 1
# |   store i8 %step, ptr %step.addr, align 1
# |   %0 = load i8, ptr %base.addr, align 1
# |   %1 = load i8, ptr %step.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8, i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svindex_s16(i16 noundef %base, i16 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i16, align 2
# |   %step.addr = alloca i16, align 2
# |   store i16 %base, ptr %base.addr, align 2
# |   store i16 %step, ptr %step.addr, align 2
# |   %0 = load i16, ptr %base.addr, align 2
# |   %1 = load i16, ptr %step.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16, i16) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svindex_s32(i32 noundef %base, i32 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   %step.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   store i32 %step, ptr %step.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = load i32, ptr %step.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svindex_s64(i64 noundef %base, i64 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i64, align 8
# |   %step.addr = alloca i64, align 8
# |   store i64 %base, ptr %base.addr, align 8
# |   store i64 %step, ptr %step.addr, align 8
# |   %0 = load i64, ptr %base.addr, align 8
# |   %1 = load i64, ptr %step.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svindex_u8(i8 noundef %base, i8 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i8, align 1
# |   %step.addr = alloca i8, align 1
# |   store i8 %base, ptr %base.addr, align 1
# |   store i8 %step, ptr %step.addr, align 1
# |   %0 = load i8, ptr %base.addr, align 1
# |   %1 = load i8, ptr %step.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.index.nxv16i8(i8 %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svindex_u16(i16 noundef %base, i16 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i16, align 2
# |   %step.addr = alloca i16, align 2
# |   store i16 %base, ptr %base.addr, align 2
# |   store i16 %step, ptr %step.addr, align 2
# |   %0 = load i16, ptr %base.addr, align 2
# |   %1 = load i16, ptr %step.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.index.nxv8i16(i16 %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svindex_u32(i32 noundef %base, i32 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   %step.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   store i32 %step, ptr %step.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = load i32, ptr %step.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.index.nxv4i32(i32 %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svindex_u64(i64 noundef %base, i64 noundef %step) #0 {
# | entry:
# |   %base.addr = alloca i64, align 8
# |   %step.addr = alloca i64, align 8
# |   store i64 %base, ptr %base.addr, align 8
# |   store i64 %step, ptr %step.addr, align 8
# |   %0 = load i64, ptr %base.addr, align 8
# |   %1 = load i64, ptr %step.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.index.nxv2i64(i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559cce4d315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559cce4d00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559cce4d389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56ea249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56ea2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56ea249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56ea231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559cce468e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559cce468c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559cce44db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559cce0fd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559cce0fcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f56ea232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56ea2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56ea2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cce0fccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c (572 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrol_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.a
# | ...
# `---data was truncated (10240/97683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa383c915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fa383c60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fa383c989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55ca21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55ca2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55ca21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55ca203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa3835ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fa3835ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fa38343b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fa37ff30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fa37ff2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f55ca204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55ca2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55ca2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa37ff2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c (573 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x
# | ...
# `---data was truncated (10240/15375) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f10184915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f1018460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f10184989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8321f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8321f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8321f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8321f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1017dee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f1017dec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f1017c3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f1014730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f101472dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8321f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8321f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8321f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f101472cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c (574 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.ad
# | ...
# `---data was truncated (10240/150649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ddf728615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ddf72830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ddf728689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe561849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5618a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe561849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe561831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddf721be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ddf721bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ddf7200b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ddf6eb00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ddf6eafdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe561832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5618330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5618330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddf6eafcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c (575 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/69677) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dad71bf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dad71bc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dad71bf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9e9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9e9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9e9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9e9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dad7154e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dad7154c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dad7139b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dad6de90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dad6de8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff9e9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9e9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9e9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dad6de8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c (576 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, a
# | ...
# `---data was truncated (10240/26721) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557360fa315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557360fa00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557360fa389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4989b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4989b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4989b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4989aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557360f38e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557360f38c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557360f1db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557360bcd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557360bccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4989aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4989aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4989aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557360bcccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c (577 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ccca9e415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ccca9e10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ccca9e489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75aca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75aca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75aca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75aca03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccca979e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ccca979c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ccca95eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ccca60e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ccca60ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f75aca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75aca050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75aca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccca60dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c (578 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = sext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1sh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = sext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1sh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg,
# | ...
# `---data was truncated (10240/37388) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560d4be0e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560d4be0b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560d4be0e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e8d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e8d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e8d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e8d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d4bda3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560d4bda3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560d4bd88b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560d4ba380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560d4ba37dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2e8d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e8d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e8d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d4ba37cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c (579 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x ha
# | ...
# `---data was truncated (10240/58653) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ec437915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558ec43760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558ec437989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c24b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c24b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c24b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c24b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ec430ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558ec430ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558ec42f3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558ec3fa30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558ec3fa2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5c24b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c24b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c24b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ec3fa2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c (580 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzp2q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzp2q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzp2q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzp2q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzp2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzp2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzp2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzp2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzp2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzp2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzp2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzp2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzp2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzp2q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzp2q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzp2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzp2q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzp2q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzp2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzp2q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzp2q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzp2_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp2q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzp2q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561df92eb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561df92e80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561df92eb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ce1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ce12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ce1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ce1231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561df9280e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561df9280c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561df9265b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561df8f150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561df8f14dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4ce1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ce12330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ce12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561df8f14cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c (581 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vxor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056014183615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005601418330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056014183689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56f0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56f058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56f0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56f051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601417cbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005601417cbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005601417b0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005601414600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056014145fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f56f051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56f051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56f051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056014145fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c (582 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4_tu(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2_tu(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1_tu(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2_tu(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4_tu(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8_tu(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2_tu(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1_tu(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2_tu(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, ali
# | ...
# `---data was truncated (10240/280217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610e072815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005610e07250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005610e072889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c7e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c7e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c7e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c7e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610e06bde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005610e06bdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005610e06a2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005610e03520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005610e0351dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2c7e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c7e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c7e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610e0351cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c (583 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale 
# | ...
# `---data was truncated (10240/32694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b85710415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b8571010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b85710489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad29d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad29d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad29d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad29d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b857099e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b857099c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b85707eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b856d2e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b856d2ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fad29d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad29d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad29d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b856d2dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c (584 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/296951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588d2b5e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005588d2b5b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005588d2b5e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa31fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa31fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa31fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa31fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588d2af3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005588d2af3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005588d2ad8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005588d27880b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005588d2787dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa31fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa31fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa31fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588d2787cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c (585 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %
# | ...
# `---data was truncated (10240/414517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac804e915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ac804e60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ac804e989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa946049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9460a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa946049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa946031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac8047ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ac8047ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ac80463b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ac801130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ac80112dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa946032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9460330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9460330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac80112cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c (586 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not=' @llvm.sqrt.'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <4 x half> @test_vsqrt_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %vsqrt.i = call <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <4 x half> %vsqrt.i, ptr %ref.tmp.i, align 8
# |   %3 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %3, ptr %__ret.i, align 8
# |   %4 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <8 x half> @test_vsqrtq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %vsqrt.i = call <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <8 x half> %vsqrt.i, ptr %ref.tmp.i, align 16
# |   %3 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %3, ptr %__ret.i, align 16
# |   %4 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <2 x double> @test_vsqrtq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <2 x double>
# |   %vsqrt.i = call <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <2 x double> %vsqrt.i, ptr %ref.tmp.i, align 16
# |   %3 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half>, metadata, metadata) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double>, metadata, metadata) #1
# | 
# | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
# | attributes #2 = { strictfp }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056122bae915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056122bae60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056122bae989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa7161bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa716725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa7161ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa71603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056122ba7ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056122ba7ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056122ba63b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056122b7130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056122b712dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faa71604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa716050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa716050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056122b712cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap '--implicit-check-not= @llvm.sqrt.'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not= @llvm.sqrt.
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c (587 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e8261615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560e826130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560e8261689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c22849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c228a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c22849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c22831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e825abe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560e825abc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560e82590b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560e822400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560e8223fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8c22832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c228330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c228330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e8223fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c (588 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfms_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <4 x half>, align 8
# |   %__p1.addr.i2 = alloca <4 x half>, align 8
# |   %__p2.addr.i3 = alloca <4 x half>, align 8
# |   %__ret.i4 = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x half>, ptr %__p1.addr.i, align 8
# |   %fneg.i = fneg <4 x half> %4
# |   %5 = load <4 x half>, ptr %__p2.addr.i, align 8
# |   store <4 x half> %3, ptr %__p0.addr.i1, align 8
# |   store <4 x half> %fneg.i, ptr %__p1.addr.i2, align 8
# |   store <4 x half> %5, ptr %__p2.addr.i3, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8
# |   %8 = load <8 x i8>, ptr %__p2.addr.i3, align 8
# |   %9 = bitcast <8 x i8> %6 to <4 x half>
# |   %10 = bitcast <8 x i8> %7 to <4 x half>
# |   %11 = bitcast <8 x i8> %8 to <4 x half>
# |   %12 = call <4 x half> @llvm.fma.v4f16(<4 x half> %10, <4 x half> %11, <4 x half> %9)
# |   store <4 x half> %12, ptr %ref.tmp.i, align 8
# |   %13 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %13, ptr %__ret.i4, align 8
# |   %14 = load <4 x half>, ptr %__ret.i4, align 8
# |   store <4 x half> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x half>, align 16
# |   %__p1.addr.i2 = alloca <8 x half>, align 16
# |   %__p2.addr.i3 = alloca <8 x half>, align 16
# |   %__ret.i4 = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %4 = load <8 x half>, ptr %__p1.addr.i, align 16
# |   %fneg.i = fneg <8 x half> %4
# |   %5 = load <8 x half>, ptr %__p2.addr.i, align 16
# |   store <8 x half> %3, ptr %__p0.addr.i1, align 16
# |   store <8 x half> %fneg.i, ptr %__p1.addr.i2, align 16
# |   store <8 x half> %5, ptr %__p2.addr.i3, align 16
# |   %6 = load <16 x i8>, ptr %__p0.addr.i1, align 16
# |   %7 = load <16 x i8>, ptr %__p1.addr.i2, align 16
# |   %8 = load <16 x i8>, ptr %__p2.addr.i3, align 16
# |   %9 = bitcast <16 x i8> %6 to <8 x half>
# |   %10 = bitcast <16 x i8> %7 to <8 x half>
# |   %11 = bitcast <16 x i8> %8 to <8 x half>
# |   %12 = call <8 x half> @llvm.fma.v8f16(<8 x half> %10, <8 x half> %11, <8 x half> %9)
# |   store <8 x half> %12, ptr %ref.tmp.i, align 16
# |   %13 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %13, ptr %__ret.i4, align 16
# |   %14 = load <8 x half>, ptr %__ret.i4, align 16
# |   store <8 x half> %14, ptr %__ret.i, align 16
# |   %15 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfma_n_f16(<4 x half> noundef %a, <4 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca half, align 2
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca half, align 2
# |   %.compoundliteral = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load half, ptr %c.addr, align 2
# |   store half %2, ptr %__s2, align 2
# |   %3 = load <4 x half>, ptr %__s0, align 8
# |   %4 = load <4 x half>, ptr %__s1, align 8
# |   %5 = load half, ptr %__s2, align 2
# |   %vecinit = insertelement <4 x half> poison, half %5, i32 0
# |   %6 = load half, ptr %__s2, align 2
# |   %vecinit1 = insertelement <4 x half> %vecinit, half %6, i32 1
# |   %7 = load half, ptr %__s2, align 2
# |   %vecinit2 = insertelement <4 x half> %vecinit1, half %7, i32 2
# |   %8 = load half, ptr %__s2, align 2
# |   %vecinit3 = insertelement <4 x half> %vecinit2, half %8, i32 3
# |   store <4 x half> %vecinit3, ptr %.compoundliteral, align 8
# |   %9 = load <4 x half>, ptr %.compoundliteral, align 8
# |   store <4 x half> %3, ptr %__p0.addr.i, align 8
# |   store <4 x half> %4, ptr %__p1.addr.i, align 8
# |   store <4 x half> %9, ptr %__p2.addr.i, align 8
# |   %10 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %13 = bitcast <8 x i8> %10 to <4 x half>
# |   %14 = bitcast <8 x i8> %11 to <4 x half>
# |   %15 = bitcast <8 x i8> %12 to <4 x half>
# |   %16 = call <4 x half> @llvm.fma.v4f16(<4 x half> %14, <4 x half> %15, <4 x half> %13)
# |   store <4 x half> %16, ptr %ref.tmp.i, align 8
# |   %17 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %17, ptr %__ret.i, align 8
# |   %18 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %18, ptr %__ret, align 8
# |   %19 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %19, ptr %tmp, align 8
# |   %20 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %20
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmaq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca half, align 2
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca half, align 2
# |   %.compoundliteral = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load half, ptr %c.addr, align 2
# |   store half %2, ptr %__s2, align 2
# |   %3 = load <8 x half>, ptr %__s0, align 16
# |   %4 = load <8 x half>, ptr %__s1, align 16
# |   %5 = load half, ptr %__s2, align 2
# |   %vecinit = insertelement <8 x half> poison, half %5, i32 0
# |   %6 = load half, ptr %__s2, align 2
# |   %vecinit1 = insertelement <8 x half> %vecinit, half %6, i32 1
# |   %7 = load half, ptr %__s2, align 2
# |   %vecinit2 = insertelement <8 x half> %vecinit1, half %7, i32 2
# |   %8 = load half, ptr %__s2, align 2
# |   %vecinit3 = insertelement <8 x half> %vecinit2, half %8, i32 3
# |   %9 = load half, ptr %__s2, align 2
# |   %vecinit4 = insertelement <8 x half> %vecinit3, half %9, i32 4
# |   %10 = load half, ptr %__s2, align 2
# |   %vecinit5 = insertelement <8 x half> %vecinit4, half %10, i32 5
# |   %11 = load half, ptr %__s2, align 2
# |   %vecinit6 = insertelement <8 x half> %vecinit5, half %11, i32 6
# |   %12 = load half, ptr %__s2, align 2
# |   %vecinit7 = insertelement <8 x half> %vecinit6, half %12, i32 7
# |   store <8 x half> %vecinit7, ptr %.compoundliteral, align 16
# |   %13 = load <8 x half>, ptr %.compoundliteral, align 16
# |   store <8 x half> %3, ptr %__p0.addr.i, align 16
# |   store <8 x half> %4, ptr %__p1.addr.i, align 16
# |   store <8 x half> %13, ptr %__p2.addr.i, align 16
# |   %14 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %15 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %16 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %17 = bitcast <16 x i8> %14 to <8 x half>
# |   %18 = bitcast <16 x i8> %15 to <8 x half>
# |   %19 = bitcast <16 x i8> %16 to <8 x half>
# |   %20 = call <8 x half> @llvm.fma.v8f16(<8 x half> %18, <8 x half> %19, <8 x half> %17)
# |   store <8 x half> %20, ptr %ref.tmp.i, align 16
# |   %21 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %21, ptr %__ret.i, align 16
# |   %22 = load <8 x half>, ptr %__ret.i, align 16
# |   store <8 x half> %22, ptr %__ret, align 16
# |   %23 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %23, ptr %tmp, align 16
# |   %24 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half
# | ...
# `---data was truncated (10240/31903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055bba92ee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bba92eb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bba92ee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc95d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc95d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc95d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc95d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bba9283e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bba9283c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bba9268b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bba8f180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bba8f17dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc95d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc95d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc95d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bba8f17cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c (589 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq2_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq2_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzpq2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq2_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzpq2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq2_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzpq2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq2_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq2_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq2.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq2_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq2.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq2_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq2.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzpq2_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzpq2.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzpq2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzpq2_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzpq2.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzpq2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzpq2_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzpq2.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzpq2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzpq2_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq2.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq2_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq2.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005648d199215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005648d198f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005648d199289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa863f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa863f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa863f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa863eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648d1927e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005648d1927c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005648d190cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005648d15bc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005648d15bbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa863eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa863eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa863eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648d15bbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c (590 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   
# | ...
# `---data was truncated (10240/415319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d90bb0515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d90bb020f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d90bb0589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f170a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f170a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f170a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f170a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d90ba9ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d90ba9ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d90ba7fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d90b72f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d90b72edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f170a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f170a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f170a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d90b72ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c (591 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, 
# | ...
# `---data was truncated (10240/211231) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d4339515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558d433920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558d4339589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f986cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f986cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f986cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f986cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d4332ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558d4332ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558d4330fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558d42fbf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558d42fbedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f986cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f986cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f986cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d42fbecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c (592 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define
# | ...
# `---data was truncated (10240/37564) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f89f47815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f89f4750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f89f47889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe95d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe95d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe95d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe95ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f89f40de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f89f40dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f89f3f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f89f0a20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f89f0a1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbe95ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe95cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe95cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f89f0a1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c (593 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_luti4_zt_u8_x4(<vscale x 16 x i8> %op.coerce0, <vscale x 16 x i8> %op.coerce1) #0 {
# | entry:
# |   %op = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %op, align 16
# |   %op1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %op1, ptr %op.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_luti4_zt_s8_x4(<vscale x 16 x i8> %op.coerce0, <vscale x 16 x i8> %op.coerce1) #0 {
# | entry:
# |   %op = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %op, align 16
# |   %op1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %op1, ptr %op.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-lutv2,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557bddf0915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557bddf060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557bddf0989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7756933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f775698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7756933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f775691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557bdde9ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557bdde9ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557bdde83b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557bddb330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557bddb32dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f775691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f775691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f775691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557bddb32cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c (594 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f16mm -target-feature +fp8  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f16mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <8 x half> @test_vmmlaq_f16_mf8(<8 x half> noundef %p0, <16 x i8> %p1, <16 x i8> %p2, i64 noundef %p3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %p0.addr = alloca <8 x half>, align 16
# |   %p1.addr = alloca <16 x i8>, align 16
# |   %p2.addr = alloca <16 x i8>, align 16
# |   %p3.addr = alloca i64, align 8
# |   store <8 x half> %p0, ptr %p0.addr, align 16
# |   store <16 x i8> %p1, ptr %p1.addr, align 16
# |   store <16 x i8> %p2, ptr %p2.addr, align 16
# |   store i64 %p3, ptr %p3.addr, align 8
# |   %0 = load <8 x half>, ptr %p0.addr, align 16
# |   %1 = load <16 x i8>, ptr %p1.addr, align 16
# |   %2 = load <16 x i8>, ptr %p2.addr, align 16
# |   %3 = load i64, ptr %p3.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fmmla.i = bitcast <16 x i8> %4 to <8 x half>
# |   %fmmla1.i = call <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v16i8(<8 x half> %fmmla.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %fmmla1.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v16i8(<8 x half>, <16 x i8>, <16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f8f16mm,+faminmax,+flagm,+fp-armv8,+fp8,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9a,+wfxt" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056113055c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005611305590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056113055c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f370e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f370e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f370e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f370e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611304f1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005611304f1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005611304d6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005611301860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561130185dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f370e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f370e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f370e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561130185cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c (595 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ac326d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559ac326a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559ac326d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9806333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f980638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9806333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f980631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ac3202e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559ac3202c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559ac31e7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559ac2e970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559ac2e96dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f980631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f980631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f980631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ac2e96cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c (596 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/208191) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056172a14f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056172a14c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056172a14f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9720f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9720f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9720f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9720eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056172a0e4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056172a0e4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056172a0c9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561729d790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561729d78dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9720eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9720eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9720eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561729d78cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c (597 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005635b488815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005635b48850f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005635b488889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ec0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ec0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ec0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ec0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635b481de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005635b481dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005635b4802b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005635b44b20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005635b44b1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6ec0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ec0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ec0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635b44b1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c (598 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16           -emit-llvm  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcvt_s16_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %vcvtz.i = call <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half> %2)
# |   store <4 x i16> %vcvtz.i, ptr %ref.tmp.i, align 8
# |   %3 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %3, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcvtq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %vcvtz.i = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %2)
# |   store <8 x i16> %vcvtz.i, ptr %ref.tmp.i, align 16
# |   %3 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %3, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcvt_u16_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %vcvtz.i = call <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half> %2)
# |   store <4 x i16> %vcvtz.i, ptr %ref.tmp.i, align 8
# |   %3 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %3, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcvtq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %vcvtz.i = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half> %2)
# |   store <8 x i16> %vcvtz.i, ptr %ref.tmp.i, align 16
# |   %3 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %3, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000558e09c3d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558e09c3a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558e09c3d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f066b01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f066b0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f066b01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f066b003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e09bd2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558e09bd2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558e09bb7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558e098670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558e09866dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f066b004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f066b0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f066b0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e09866cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c (599 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d14f4b515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d14f4b20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d14f4b589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2035a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2035aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2035a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2035a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d14f44ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d14f44ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d14f42fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d14f0df0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d14f0dedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2035a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2035a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2035a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d14f0decc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c (600 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c79086e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c79086b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c79086e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b33733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b3378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b33733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b3371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c790803e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c790803c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c7907e8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c7904980b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c790497dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6b3371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b3371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b3371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c790497cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c (601 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmmla_f64(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 2 x double>, align 16
# |   %y.addr = alloca <vscale x 2 x double>, align 16
# |   %z.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %x, ptr %x.addr, align 16
# |   store <vscale x 2 x double> %y, ptr %y.addr, align 16
# |   store <vscale x 2 x double> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %x.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %y.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %z.addr, align 16
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055cb1213b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cb121380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cb1213b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdaacf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdaacf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdaacf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdaacf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb120d0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cb120d0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cb120b5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cb11d650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cb11d64dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdaacf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdaacf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdaacf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb11d64cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c (602 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be1610f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055be1610c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055be1610f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc96a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc96a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc96a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc96a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be160a4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055be160a4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055be16089b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055be15d390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055be15d38dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc96a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc96a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc96a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be15d38cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c (603 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c87dfe915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c87dfe60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c87dfe989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff019505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff01955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff019505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0194ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c87df7ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c87df7ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c87df63b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c87dc130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c87dc12dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff0194eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0194ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0194ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c87dc12cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/neon-tbl.c (604 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-tbl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl1.i = shufflevector <8 x i8> %2, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl11.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %3)
# |   store <8 x i8> %vtbl11.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqtbl1_s8(<16 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl1.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %2, <8 x i8> %3)
# |   store <8 x i8> %vtbl1.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl2_s8([2 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x8x2_t, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x8x2_t, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x8x2_t, ptr %a, i32 0, i32 0
# |   store [2 x <8 x i8>] %a.coerce, ptr %coerce.dive, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x8x2_t, ptr %a, i32 0, i32 0
# |   %1 = load [2 x <8 x i8>], ptr %coerce.dive1, align 8
# |   store [2 x <8 x i8>] %1, ptr %__p0.i, align 8
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.i, align 8
# |   %arrayidx2.i = getelementptr inbounds [2 x <8 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <8 x i8>, ptr %arrayidx2.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl1.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl13.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %4)
# |   store <8 x i8> %vtbl13.i, ptr %ref.tmp.i, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqtbl2_s8([2 x <16 x i8>] alignstack(16) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x16x2_t, align 16
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x16x2_t, align 16
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x16x2_t, ptr %a, i32 0, i32 0
# |   store [2 x <16 x i8>] %a.coerce, ptr %coerce.dive, align 16
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x16x2_t, ptr %a, i32 0, i32 0
# |   %1 = load [2 x <16 x i8>], ptr %coerce.dive1, align 16
# |   store [2 x <16 x i8>] %1, ptr %__p0.i, align 16
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.i, align 16
# |   %arrayidx2.i = getelementptr inbounds [2 x <16 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <16 x i8>, ptr %arrayidx2.i, align 16
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl2.i = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %2, <16 x i8> %3, <8 x i8> %4)
# |   store <8 x i8> %vtbl2.i, ptr %ref.tmp.i, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl3_s8([3 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x8x3_t, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x8x3_t, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x8x3_t, ptr %a, i32 0, i32 0
# |   store [3 x <8 x i8>] %a.coerce, ptr %coerce.dive, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x8x3_t, ptr %a, i32 0, i32 0
# |   %1 = load [3 x <8 x i8>], ptr %coerce.dive1, align 8
# |   store [3 x <8 x i8>] %1, ptr %__p0.i, align 8
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.i, align 8
# |   %arrayidx2.i = getelementptr inbounds [3 x <8 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <8 x i8>, ptr %arrayidx2.i, align 8
# |   %arrayidx4.i = getelementptr inbounds [3 x <8 x i8>], ptr %__p0.i, i64 0, i64 2
# |   %4 = load <8 x i8>, ptr %arrayidx4.i, align 8
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl2.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl25.i = shufflevector <8 x i8> %4, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %vtbl26.i = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %vtbl2.i, <16 x i8> %vtbl25.i, <8 x i8> %5)
# |   store <8 x i8> %vtbl26.i, ptr %ref.tmp.i, align 8
# |   %6 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %6, ptr %__ret.i, align 8
# |   %7 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vqtbl3_s8([3 x <16 x i8>] alignstack(16) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x16x3_t, align 16
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x16x3_t, align 16
# |   %b.addr = alloca <8 x i8>, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.int8x16x3_t, ptr %a, i32 0, i32 0
# |   store [3 x <16 x i8>] %a.coerce, ptr %coerce.dive, align 16
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %b.addr, align 8
# |   %coerce.dive1 = getelementptr inbounds nuw %struct.int8x16x3_t, ptr %a, i32 0, i32 0
# |   %1 = load [3 x <16 x i8>], ptr %coerce.dive1, align 16
# |   store [3 x <16 x i8>] %1, ptr %__p0.i, align 16
# |   store <8 x i8> %0, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.i, align 16
# |   %arrayidx2.i = getelementptr inbounds [3 x <16 x i8>], ptr %__p0.i, i64 0, i64 1
# |   %3 = load <16 x i8>, ptr %arrayidx2.i, align 16
# |   %arrayidx4.i = getelementptr inbounds [3 x <16 x i8>], ptr %__p0.i, i64 0, i64 2
# |   %4 = load <16 x i8>, ptr %arrayidx4.i, align 16
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vtbl3.i = call <8 x i8> @llvm.aarch64.neon.tbl3.v8i8(<16 x i8> %2, <16 x i8> %3, <16 x i8> %4, <8 x i8> %5)
# |   store <8 x i8> %vtbl3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %6, ptr %__ret.i, align 8
# |   %7 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vtbl4_s8([4 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.i = alloca %struct.int8x8x4_t, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a = alloca %struct.int8x8x4_t, align 8
# |   %b.a
# | ...
# `---data was truncated (10240/125901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e13cb415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564e13cb10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564e13cb489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9dea933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9dea98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9dea933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9dea91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e13c49e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564e13c49c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564e13c2eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564e138de0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564e138dddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9dea91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9dea91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9dea91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e138ddcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c (605 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b1(ptr noundef %base, <vscale x 64 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b2(ptr noundef %base, <vscale x 32 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b4(ptr noundef %base, <vscale x 16 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b8(ptr noundef %base, <vscale x 8 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b16(ptr noundef %base, <vscale x 4 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b32(ptr noundef %base, <vscale x 2 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b64(ptr noundef %base, <vscale x 1 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1>, ptr captures(none), i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f43278915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f4327860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f43278989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5641d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5641d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5641d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5641d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f43271ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f43271ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f432703b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f4323b30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f4323b2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5641d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5641d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5641d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4323b2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c (606 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_za16_mf8_m(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %4 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %4)
# |   call void @llvm.aarch64.sme.fp8.fmopa.za16(i32 1, <vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmopa.za16(i32 immarg, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svmopa_za32_mf8_m(<vscale x 16 x i1> %pn, <vscale x 16 x i1> %pm, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   %pm.addr = alloca <vscale x 16 x i1>, align 2
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   store <vscale x 16 x i1> %pm, ptr %pm.addr, align 2
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %pm.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %4 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %4)
# |   call void @llvm.aarch64.sme.fp8.fmopa.za32(i32 3, <vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fmopa.za32(i32 immarg, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f8f16,+sme-f8f32" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005611ed68815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005611ed6850f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005611ed68889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca23f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca23f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca23f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca23eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611ed61de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005611ed61dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005611ed602b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005611ed2b20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005611ed2b1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fca23eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca23eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca23eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611ed2b1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c (607 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/99851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056303155115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056303154e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056303155189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb546733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb54678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb546733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb54671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630314e6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005630314e6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005630314cbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056303117b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056303117add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb54671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb54671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb54671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056303117acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c (608 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = loa
# | ...
# `---data was truncated (10240/415311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1327c615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a1327c30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a1327c689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f199e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f199e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f199e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f199e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a13275be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a13275bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a132740b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a1323f00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a1323efdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f199e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f199e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f199e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1323efcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c (609 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_viota_m_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_viota_m_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_viota_m_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_viota_m_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_viota_m_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_viota_m_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_viota_m_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_viota_m_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_viota_m_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_viota_m_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_viota_m_u16m2
# | ...
# `---data was truncated (10240/94673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056182329d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056182329a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056182329d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa026f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa026f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa026f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa026f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561823232e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561823232c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561823217b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561822ec70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561822ec6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa026f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa026f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa026f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561822ec6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c (610 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4a658015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c4a657d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c4a658089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f496161bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49616725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f496161ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4961603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4a6515e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c4a6515c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c4a64fab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c4a61aa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c4a61a9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4961604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49616050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49616050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4a61a9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c (611 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmsb_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %6 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmsb.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %5, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fnmsb.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmsb_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %6 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmsb.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %5, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fnmsb.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmsb_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = select <vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %6 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmsb.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %5, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fnmsb.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmsb_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmsb.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svnmsb_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fnmsb.nxv4f32(<vscale x 4 x i1> %4, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svnmsb_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fnmsb.nxv2f64(<vscale x 2 x i1> %4, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svnmsb_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fnmls.u.nxv8f16(<vscale x 8 x i1> %4, <vscale x 8 x half> %3, <vscale x 8 x half> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/26173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b3de57f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b3de57c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b3de57f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91fcc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91fcc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91fcc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91fcc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3de514e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b3de514c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b3de4f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b3de1a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b3de1a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f91fcc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91fcc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91fcc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3de1a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c (612 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1>, ptr, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_1(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_2(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_3(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_4(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_5(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_6(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 8)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_7(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 9)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 10)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_9(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 11)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_10(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 12)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_11(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %2, ptr %1, i32 13)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_vnum(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i64>, ptr %1, i64 %2
# |   call void @llvm.aarch64.sve.prf.nxv2i1.p0(<vscale x 2 x i1> %3, ptr %4, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_gather_u32base(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64, i32 immarg) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svprfd_gather_u64base(<vscale x 16 x i1> %pg, <vscale x 2 x i64
# | ...
# `---data was truncated (10240/17826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055d2c735a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d2c73570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d2c735a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b1e305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b1e35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b1e305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b1e2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2c72efe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d2c72efc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d2c72d4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d2c6f840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d2c6f83dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0b1e2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b1e2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b1e2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2c6f83cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c (613 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x hal
# | ...
# `---data was truncated (10240/514165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625f469b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005625f46980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005625f469b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb90105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb9015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb90105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb900ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625f4630e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005625f4630c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005625f4615b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005625f42c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005625f42c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbb900eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb900ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb900ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625f42c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c (614 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasrd_n_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, i32 1)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasrd_n_s8_z_1(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, i32 8)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasrd_n_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 8 x i1> %2, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %3, i32 1)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasrd_n_s16_z_1(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 8 x i1> %2, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %3, i32 16)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasrd_n_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 4 x i1> %2, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %3, i32 1)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasrd_n_s32_z_1(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 4 x i1> %2, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %3, i32 32)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasrd_n_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 2 x i1> %2, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %3, i32 1)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svasrd_n_s64_z_1(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = select <vscale x 2 x i1> %2, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %3, i32 64)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svasrd_n_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i32 1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svasrd_n_s16_m(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1, i32 1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svasrd_n_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %2, 
# | ...
# `---data was truncated (10240/14353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055a85849b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a8584980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a85849b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03d3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03d338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03d3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03d331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a858430e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a858430c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a858415b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a8580c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a8580c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f03d331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03d331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03d331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8580c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c (615 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 31, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqincw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_n_s32_1(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqincw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincw.n32(i32 %0, i32 31, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqincw.n32(i32, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincw.n64(i64 %0, i32 31, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uqincw.n64(i64, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_pat_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 4, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_pat_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %0, i32 5, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqincw_pat_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call i32 @llvm.aarch64.sve.uqincw.n32(i32 %0, i32 6, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqincw_pat_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call i64 @llvm.aarch64.sve.uqincw.n64(i64 %0, i32 7, i32 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqincw.nxv4i32(<vscale x 4 x i32> %0, i32 31, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqincw.nxv4i32(<vscale x 4 x i32>, i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_pat_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqincw.nxv4i32(<vscale x 4 x i32> %0, i32 8, i32 16)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqincw_pat_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqincw.nxv4i32(<vscale x 4 x i32> %0, i32 9, i32 1)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556b7ed6715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556b7ed640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556b7ed6789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1504a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1504a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1504a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1504a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b7ecfce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556b7ecfcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556b7ece1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556b7e9910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556b7e990dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1504a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1504a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1504a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b7e990cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c (616 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vsca
# | ...
# `---data was truncated (10240/154601) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0ae3e315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f0ae3e00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f0ae3e389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20cec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20ceca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20cec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20cec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0ae378e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f0ae378c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f0ae35db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f0ae00d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f0ae00cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f20cec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20cec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20cec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0ae00ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c (617 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_t
# | ...
# `---data was truncated (10240/128436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607fb81d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005607fb81a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005607fb81d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf95a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf95aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf95a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf95a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607fb7b2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005607fb7b2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005607fb797b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005607fb4470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005607fb446dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbf95a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf95a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf95a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607fb446cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c (618 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583afee615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005583afee30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005583afee689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99ce305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99ce35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99ce305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99ce2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583afe7be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005583afe7bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005583afe60b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005583afb100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005583afb0fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f99ce2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99ce2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99ce2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583afb0fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c (619 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue
# | ...
# `---data was truncated (10240/81764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562182e5015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562182e4d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562182e5089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14af849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14af8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14af849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14af831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562182de5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562182de5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562182dcab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562182a7a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562182a79dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f14af832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14af8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14af8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562182a79cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c (620 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_f32m8(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_f32m8(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %o
# | ...
# `---data was truncated (10240/76627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfa328e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dfa328b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dfa328e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7884333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f788438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7884333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f788431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfa3223e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dfa3223c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dfa3208b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dfa2eb80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dfa2eb7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f788431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f788431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f788431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfa2eb7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c (621 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056554452e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056554452b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056554452e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f5cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f5cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f5cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f5cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005655444c3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005655444c3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005655444a8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005655441580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000565544157dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1f5cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f5cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f5cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565544157cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c (622 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2,
# | ...
# `---data was truncated (10240/65194) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5b37f215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c5b37ef0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c5b37f289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b38933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b3898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b38933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b3891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5b3787e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c5b3787c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c5b376cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c5b341c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c5b341bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8b3891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b3891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b3891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5b341bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-bf16-convert-intrinsics.c (623 of 27911)
******************** TEST 'Clang :: CodeGen/arm-bf16-convert-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc    -triple aarch64 -target-feature +neon -target-feature +bf16    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvt_f32_bf16(<4 x bfloat> noundef %a) #0 {
# | entry:
# |   %__p0_824.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret_824.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %__s0.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %0, ptr %__p0_824.addr.i, align 8
# |   %1 = load <4 x i16>, ptr %__p0_824.addr.i, align 8
# |   store <4 x i16> %1, ptr %__s0.i, align 8
# |   %2 = load <8 x i8>, ptr %__s0.i, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x i16>
# |   %4 = zext <4 x i16> %3 to <4 x i32>
# |   %vshll_n.i = shl <4 x i32> %4, splat (i32 16)
# |   store <4 x i32> %vshll_n.i, ptr %ref.tmp1.i, align 16
# |   %5 = load <4 x i32>, ptr %ref.tmp1.i, align 16
# |   store <4 x i32> %5, ptr %__ret.i, align 16
# |   %6 = load <4 x i32>, ptr %__ret.i, align 16
# |   store <4 x i32> %6, ptr %tmp.i, align 16
# |   %7 = load <4 x i32>, ptr %tmp.i, align 16
# |   store <4 x i32> %7, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret_824.i, align 16
# |   %9 = load <4 x float>, ptr %__ret_824.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvtq_low_f32_bf16(<8 x bfloat> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x bfloat>, align 16
# |   %__ret.i2 = alloca <4 x bfloat>, align 8
# |   %__p0_824.addr.i.i = alloca <4 x bfloat>, align 8
# |   %__ret_824.i.i = alloca <4 x float>, align 16
# |   %ref.tmp.i.i = alloca <4 x i32>, align 16
# |   %__ret.i.i = alloca <4 x i32>, align 16
# |   %__s0.i.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i.i = alloca <16 x i8>, align 16
# |   %tmp.i.i = alloca <4 x i32>, align 16
# |   %__p0.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__p0.addr.i1, align 16
# |   %2 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %3 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <8 x bfloat> %2, <8 x bfloat> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x bfloat> %shuffle.i, ptr %__ret.i2, align 8
# |   %4 = load <4 x bfloat>, ptr %__ret.i2, align 8
# |   store <4 x bfloat> %4, ptr %__p0_824.addr.i.i, align 8
# |   %5 = load <4 x i16>, ptr %__p0_824.addr.i.i, align 8
# |   store <4 x i16> %5, ptr %__s0.i.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %8 = zext <4 x i16> %7 to <4 x i32>
# |   %vshll_n.i.i = shl <4 x i32> %8, splat (i32 16)
# |   store <4 x i32> %vshll_n.i.i, ptr %ref.tmp1.i.i, align 16
# |   %9 = load <4 x i32>, ptr %ref.tmp1.i.i, align 16
# |   store <4 x i32> %9, ptr %__ret.i.i, align 16
# |   %10 = load <4 x i32>, ptr %__ret.i.i, align 16
# |   store <4 x i32> %10, ptr %tmp.i.i, align 16
# |   %11 = load <4 x i32>, ptr %tmp.i.i, align 16
# |   store <4 x i32> %11, ptr %ref.tmp.i.i, align 16
# |   %12 = load <4 x float>, ptr %ref.tmp.i.i, align 16
# |   store <4 x float> %12, ptr %__ret_824.i.i, align 16
# |   %13 = load <4 x float>, ptr %__ret_824.i.i, align 16
# |   store <4 x float> %13, ptr %__ret.i, align 16
# |   %14 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvtq_high_f32_bf16(<8 x bfloat> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x bfloat>, align 16
# |   %__ret.i2 = alloca <4 x bfloat>, align 8
# |   %__p0_824.addr.i.i = alloca <4 x bfloat>, align 8
# |   %__ret_824.i.i = alloca <4 x float>, align 16
# |   %ref.tmp.i.i = alloca <4 x i32>, align 16
# |   %__ret.i.i = alloca <4 x i32>, align 16
# |   %__s0.i.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i.i = alloca <16 x i8>, align 16
# |   %tmp.i.i = alloca <4 x i32>, align 16
# |   %__p0.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__p0.addr.i1, align 16
# |   %2 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %3 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <8 x bfloat> %2, <8 x bfloat> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x bfloat> %shuffle.i, ptr %__ret.i2, align 8
# |   %4 = load <4 x bfloat>, ptr %__ret.i2, align 8
# |   store <4 x bfloat> %4, ptr %__p0_824.addr.i.i, align 8
# |   %5 = load <4 x i16>, ptr %__p0_824.addr.i.i, align 8
# |   store <4 x i16> %5, ptr %__s0.i.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %8 = zext <4 x i16> %7 to <4 x i32>
# |   %vshll_n.i.i = shl <4 x i32> %8, splat (i32 16)
# |   store <4 x i32> %vshll_n.i.i, ptr %ref.tmp1.i.i, align 16
# |   %9 = load <4 x i32>, ptr %ref.tmp1.i.i, align 16
# |   store <4 x i32> %9, ptr %__ret.i.i, align 16
# |   %10 = load <4 x i32>, ptr %__ret.i.i, align 16
# |   store <4 x i32> %10, ptr %tmp.i.i, align 16
# |   %11 = load <4 x i32>, ptr %tmp.i.i, align 16
# |   store <4 x i32> %11, ptr %ref.tmp.i.i, align 16
# |   %12 = load <4 x float>, ptr %ref.tmp.i.i, align 16
# |   store <4 x float> %12, ptr %__ret_824.i.i, align 16
# |   %13 = load <4 x float>, ptr %__ret_824.i.i, align 16
# |   store <4 x float> %13, ptr %__ret.i, align 16
# |   %14 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcvt_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fptrunc <4 x float> %2 to <4 x bfloat>
# |   store <4 x bfloat> %3, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp.i, align 8
# |   store <4 x bfloat> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvtq_low_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fptrunc <4 x float> %2 to <4 x bfloat>
# |   %4 = shufflevector <4 x bfloat> %3, <4 x bfloat> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x bfloat> %4, ptr %ref.tmp.i, align 16
# |   %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %5, ptr %__ret.i, align 16
# |   %6 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcvtq_high_bf16_f32(<8 x bfloat> noundef %inactive, <4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x bfloat>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %inactive.addr = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <8 x bfloat> %inactive, ptr %inactive.addr, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %inactive.addr, align 16
# |   %1 = load <4 x float>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x bfloat>
# |   %5 = shufflevector <8 x bfloat> %4, <8 x bfloat> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   %6 = bitcast <16 x i8> %3 to <4 x float>
# |   %7 = fptrunc <4 x float> %6 to <4 x bfloat>
# |   %8 = shufflevector <4 x bfloat> %5, <4 x bfloat> %7, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x bfloat> %8, ptr %ref.tmp.i, align 16
# |   %9 = load <8 x bfloat>, ptr %ref.tmp.i, align 16
# |   store <8 x bfloat> %9, ptr %__ret.i, align 16
# |   %10 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_vcvth_bf16_f32(float noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__ret.i = alloca bfloat, align 2
# |   %ref.tmp.i = alloca bfloat, align 2
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__p0.addr.i, align 4
# |   %1 = load float, ptr %__p0.addr.i, align 4
# |   %2 = fptrunc float %1 to bfloat
# |   store bfloat %2, ptr %ref.tmp.i, align 2
# |   %3 = load bfloat, ptr %ref.tmp.i, align 2
# |   store bfloat %3, ptr %__ret.i, align 2
# |   %4 = load bfloat, ptr %__ret.i, align 2
# |   ret bfloat %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vcvtah_f32_bf16(bfloat noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca bfloat, align 2
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca i32, align 4
# |   %a.addr = alloca bfloat, align 2
# |   store bfloat %a, ptr %a.addr, align 2
# |   %0 = load 
# | ...
# `---data was truncated (10240/10974) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055c06ead515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c06ead20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c06ead589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc25b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc25b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc25b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc25b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c06ea6ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c06ea6ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c06ea4fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c06e6ff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c06e6fedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcc25b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc25b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc25b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c06e6fecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c (624 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651ff43a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005651ff4370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005651ff43a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b97533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b9758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b97533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b9751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651ff3cfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005651ff3cfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005651ff3b4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005651ff0640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005651ff063dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3b9751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b9751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b9751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651ff063cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c (625 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f218ea15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563f218e70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563f218ea89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1bb8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1bb84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1bb8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1bb8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f2187fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563f2187fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563f21864b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563f215140b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563f21513dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1bb8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1bb84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1bb84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f21513cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c (626 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtnt_bf16_f32_x(<vscale x 8 x bfloat> %even, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %even.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 8 x bfloat> %even, ptr %even.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %even.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvtnt.bf16f32.v2(<vscale x 8 x bfloat> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvtnt.bf16f32.v2(<vscale x 8 x bfloat>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcvtnt_bf16_f32_m(<vscale x 8 x bfloat> %even, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %even.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 8 x bfloat> %even, ptr %even.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %even.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvtnt.bf16f32.v2(<vscale x 8 x bfloat> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557ef128915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557ef12860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557ef128989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d7f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d7f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d7f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d7f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ef121ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557ef121ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557ef1203b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557ef0eb30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557ef0eb2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7d7f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d7f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d7f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ef0eb2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c (627 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <
# | ...
# `---data was truncated (10240/117389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a0213115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557a0212e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557a0213189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01c2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01c2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01c2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01c2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a020c6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557a020c6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557a020abb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557a01d5b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557a01d5add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f01c2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01c2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01c2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a01d5acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c (628 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/414525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab50c0915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ab50c060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ab50c0989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f357b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f357b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f357b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f357b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab50b9ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ab50b9ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ab50b83b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ab508330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ab50832dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f357b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f357b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f357b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab50832cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c (629 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.udiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.udiv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_s32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_s64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_u32_m(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdiv_u64_m(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.udiv.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdiv_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call
# | ...
# `---data was truncated (10240/48703) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556c82b2115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556c82b1e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556c82b2189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f993df05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f993df5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f993df05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f993deed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c82ab6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556c82ab6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556c82a9bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556c8274b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556c8274add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f993deeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f993deef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f993deef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c8274acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c (630 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data.coerce0, <vscale x 16 x i8> %data.coerce1, <vscale x 16 x i8> %data.coerce2, <vscale x 16 x i8> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %data.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %data, align 16
# |   %data1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %data1, ptr %data.addr, align 16
# |   %4 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %5 = load ptr, ptr %base.addr, align 8
# |   %6 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %data.addr, align 16
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 0
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 1
# |   %9 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 2
# |   %10 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, 3
# |   call void @llvm.aarch64.sve.st4.nxv16i8.p0(<vscale x 16 x i8> %7, <vscale x 16 x i8> %8, <vscale x 16 x i8> %9, <vscale x 16 x i8> %10, <vscale x 16 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st4.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data.coerce0, <vscale x 8 x i16> %data.coerce1, <vscale x 8 x i16> %data.coerce2, <vscale x 8 x i16> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %data.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %data, align 16
# |   %data1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %data1, ptr %data.addr, align 16
# |   %4 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %5 = load ptr, ptr %base.addr, align 8
# |   %6 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %data.addr, align 16
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 0
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 1
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 2
# |   %10 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, 3
# |   %11 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %4)
# |   call void @llvm.aarch64.sve.st4.nxv8i16.p0(<vscale x 8 x i16> %7, <vscale x 8 x i16> %8, <vscale x 8 x i16> %9, <vscale x 8 x i16> %10, <vscale x 8 x i1> %11, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st4.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data.coerce0, <vscale x 4 x i32> %data.coerce1, <vscale x 4 x i32> %data.coerce2, <vscale x 4 x i32> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %data.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %data, align 16
# |   %data1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %data1, ptr %data.addr, align 16
# |   %4 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %5 = load ptr, ptr %base.addr, align 8
# |   %6 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %data.addr, align 16
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 0
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 1
# |   %9 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 2
# |   %10 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, 3
# |   %11 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %4)
# |   call void @llvm.aarch64.sve.st4.nxv4i32.p0(<vscale x 4 x i32> %7, <vscale x 4 x i32> %8, <vscale x 4 x i32> %9, <vscale x 4 x i32> %10, <vscale x 4 x i1> %11, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st4.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst4_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data.coerce0, <vscale x 2 x i64> %data.coerce1, <vscale x 2 x i64> %data.coerce2, <vscale x 2 x i64> %data.coerce3) #0 {
# | entry:
# |   %data = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %data.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %data.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %data.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %da
# | ...
# `---data was truncated (10240/73307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005566e015a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005566e01570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005566e015a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae91733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae9178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae91733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae9171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566e00efe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005566e00efc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005566e00d4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005566dfd840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005566dfd83dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fae9171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae9171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae9171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566dfd83cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c (631 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vsc
# | ...
# `---data was truncated (10240/69951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7cdad715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e7cdad40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e7cdad789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f11f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f11f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f11f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f11f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7cda6ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e7cda6cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e7cda51b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e7cd7010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e7cd700dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2f11f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f11f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f11f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7cd700cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c (632 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = 
# | ...
# `---data was truncated (10240/210435) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b0ec5615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558b0ec530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558b0ec5689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45a0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45a04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45a0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45a0431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b0ebebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558b0ebebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558b0ebd0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558b0e8800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558b0e87fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f45a0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45a04330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45a04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b0e87fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c (633 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4acfcf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d4acfcc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d4acfcf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f471c41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f471c4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f471c41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f471c403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4acf64e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d4acf64c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d4acf49b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d4acbf90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d4acbf8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f471c404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f471c4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f471c4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4acbf8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c (634 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.facge.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.facge.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svacge_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.facge.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000564c2a8e115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564c2a8de0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564c2a8e189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdefe61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdefe6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdefe61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdefe603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c2a876e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564c2a876c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564c2a85bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564c2a50b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564c2a50add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdefe604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdefe6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdefe6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c2a50acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c (635 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vrhadd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vrhadd.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vrhadd.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vrhadd.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vrhadd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vrhadd.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a3a71f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562a3a71c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562a3a71f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f5e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f5e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f5e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f5e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a3a6b4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562a3a6b4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562a3a699b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562a3a3490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562a3a348dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3f5e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f5e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f5e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a3a348cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c (636 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, 
# | ...
# `---data was truncated (10240/30635) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e4c7e015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563e4c7dd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563e4c7e089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ca8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ca838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ca8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ca831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e4c775e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563e4c775c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563e4c75ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563e4c40a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563e4c409dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8ca831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ca831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ca831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e4c409cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c (637 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svbfmlalt_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalt_lane_0_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 0)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt.lane.v2(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalt_lane_7_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfmlalt_n_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, bfloat noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca bfloat, align 2
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store bfloat %z, ptr %z.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load bfloat, ptr %z.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalt(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556f3db5115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556f3db4e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556f3db5189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c90933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c9098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c90933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c9091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f3dae6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556f3dae6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556f3dacbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556f3d77b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556f3d77add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2c9091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c9091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c9091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f3d77acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c (638 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpx_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpx_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpx_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpx_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpx_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpx_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrecpx_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frecpx.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrecpx_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrecpx_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frecpx.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c61bb3115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c61bb2e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c61bb3189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54c3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54c30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54c3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54c3031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c61bac6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c61bac6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c61baabb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c61b75b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c61b75add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f54c3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54c30330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54c30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c61b75acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c (639 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %o
# | ...
# `---data was truncated (10240/427567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9b4db215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f9b4daf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f9b4db289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd47eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd47eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd47eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd47eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9b4d47e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f9b4d47c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f9b4d2cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f9b49dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f9b49dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd47eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd47eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd47eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9b49dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c (640 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_f32mf8(<vscale x 4 x float> %acc, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i64 noundef %fpmr) #0 {
# | entry:
# |   %acc.addr = alloca <vscale x 4 x float>, align 16
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %acc, ptr %acc.addr, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %acc.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %3 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %3)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmmla.nxv4f32(<vscale x 4 x float> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmmla.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f8f32mm,+sve,+sve2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557d2ae8515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557d2ae820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557d2ae8589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04ada49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04adaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04ada49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04ada31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d2ae1ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557d2ae1ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557d2adffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557d2aaaf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557d2aaaedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f04ada32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04ada330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04ada330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d2aaaecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c (641 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i6
# | ...
# `---data was truncated (10240/90867) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d9a53715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560d9a5340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560d9a53789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f445b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f445b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f445b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f445b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d9a4cce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560d9a4ccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560d9a4b1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560d9a1610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560d9a160dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f445b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f445b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f445b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d9a160cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c (642 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i6
# | ...
# `---data was truncated (10240/132470) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607e5bb715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005607e5bb40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005607e5bb789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbade533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbade58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbade533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbade51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607e5b4ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005607e5b4cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005607e5b31b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005607e57e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005607e57e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbade51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbade51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbade51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607e57e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c (643 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svluti2_lane_zt_mf8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_u16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svluti2_lane_zt_s16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svluti2_lane_zt_f16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svluti2_lane_zt_bf16(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_u32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svluti2_lane_zt_s32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svluti2_lane_zt_f32(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 0, <vscale x 16 x i8> %0, i32 7)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 immarg, <vscale x 16 x i8>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056177087615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005617708730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056177087689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fff533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fff58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fff533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fff51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056177080be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056177080bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005617707f0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005617704a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056177049fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9fff51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fff51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fff51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056177049fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c (644 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, al
# | ...
# `---data was truncated (10240/226593) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4146dc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a4146d90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a4146dc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0bb7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0bb778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0bb7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0bb771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a414671e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a414671c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a414656b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a4143060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a414305dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0bb771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0bb771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0bb771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a414305cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c (645 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c7c46415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562c7c4610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562c7c46489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78f1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78f1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78f1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78f1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c7c3f9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562c7c3f9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562c7c3deb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562c7c08e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562c7c08ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f78f1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78f1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78f1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c7c08dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c (646 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_x_i8mf8_tu(<vscale x 1 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_x_i8mf4_tu(<vscale x 2 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_x_i8mf2_tu(<vscale x 4 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_x_i8m1_tu(<vscale x 8 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_x_i8m2_tu(<vscale x 16 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = l
# | ...
# `---data was truncated (10240/134736) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055596fe4b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055596fe480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055596fe4b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82c9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82c98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82c9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82c9831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055596fde0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055596fde0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055596fdc5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055596fa750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055596fa74dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f82c9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82c98330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82c98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055596fa74cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c (647 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056369a52b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056369a5280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056369a52b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27ceb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27ceb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27ceb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27ceaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056369a4c0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056369a4c0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056369a4a5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056369a1550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056369a154dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f27ceaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27ceaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27ceaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056369a154cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c (648 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab78b0d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ab78b0a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ab78b0d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f80649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f806a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f80649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f80631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab78aa2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ab78aa2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ab78a87b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ab787370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ab78736dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7f80632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f806330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f806330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab78736cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c (649 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfd627615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cfd62730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cfd627689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4159133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f415918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4159133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f415911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfd620be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cfd620bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cfd61f0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cfd5ea00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cfd5e9fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f415911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f415911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f415911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfd5e9fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c (650 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vsc
# | ...
# `---data was truncated (10240/99843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612d3b5715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005612d3b540f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005612d3b5789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5291849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52918a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5291849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5291831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612d3aece2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005612d3aecc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005612d3ad1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005612d37810b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005612d3780dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5291832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52918330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52918330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612d3780cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/neon-vget-hilo.c (651 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vget-hilo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_high_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vget_high_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vget_high_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 2, i32 3>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vget_high_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_high_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vget_high_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vget_high_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 2, i32 3>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vget_high_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vget_high_p64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vget_high_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x half> %1, <8 x half> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x half> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vget_high_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x float> %1, <4 x float> %2, <2 x i32> <i32 2, i32 3>
# |   store <2 x float> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_high_p8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vget_high_p16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vget_high_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <1 x double>, align 8
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x double> %1, <2 x double> %2, <1 x i32> <i32 1>
# |   store <1 x double> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vget_low_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = allo
# | ...
# `---data was truncated (10240/20383) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588e6d5315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005588e6d500f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005588e6d5389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f958f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f958f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f958f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f958f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588e6ce8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005588e6ce8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005588e6ccdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005588e697d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005588e697cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f958f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f958f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f958f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588e697ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c (652 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3,
# | ...
# `---data was truncated (10240/15512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555613d4f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555613d4c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555613d4f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2523933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f252398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2523933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f252391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555613ce4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555613ce4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555613cc9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005556139790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555613978dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f252391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f252391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f252391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555613978cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c (653 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1down_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64)
# | ...
# `---data was truncated (10240/34765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6e1d5915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b6e1d560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b6e1d5989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f258bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f258bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f258bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f258bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6e1ceee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b6e1ceec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b6e1cd3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b6e19830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b6e1982dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f258bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f258bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f258bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6e1982cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve/len.c (654 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/len.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c         | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 16
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.vscale.i64() #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 16
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_bf16(<vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 8
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 4
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 4
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 4
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 2
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 2
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svlen_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call i64 @llvm.vscale.i64()
# |   %2 = mul nuw i64 %1, 2
# |   ret i64 %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x00005571dbb2415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005571dbb210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005571dbb2489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec10705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec1075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec10705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec106ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571dbab9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005571dbab9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005571dba9eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005571db74e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005571db74ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fec106eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec106ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec106ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571db74dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c (655 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/123663) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562618c7115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562618c6e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562618c7189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd856b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd856b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd856b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd856b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562618c06e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562618c06c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562618bebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056261889b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056261889add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd856b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd856b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd856b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056261889acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c (656 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { targe
# | ...
# `---data was truncated (10240/68233) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619d552615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005619d55230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005619d552689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbaaff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbaaff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbaaff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbaaff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619d54bbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005619d54bbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005619d54a0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005619d51500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005619d514fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbaaff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbaaff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbaaff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619d514fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c (657 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_u32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_u32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1
# | ...
# `---data was truncated (10240/24072) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055833f71515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055833f7120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055833f71589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3563249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35632a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3563249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3563231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055833f6aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055833f6aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055833f68fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055833f33f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055833f33edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3563232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35632330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35632330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055833f33ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c (658 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = c
# | ...
# `---data was truncated (10240/207083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c08f4cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c08f4c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c08f4cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6913d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6913d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6913d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6913d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c08f460e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c08f460c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c08f445b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c08f0f50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c08f0f4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6913d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6913d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6913d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c08f0f4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c (659 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqsub_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqsub_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqsub_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqsub_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqsub_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.x.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqsub_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.x.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqsub_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.x.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqsub_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.x.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svqsub_n_s8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %.splatinsert = insertelement <vscale x 16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <vscale x 16 x i8> %.splatinsert, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %.splat)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqsub_n_s16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svqsub_n_s32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %.splatinsert = insertelement <vscale x 4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <vscale x 4 x i32> %.splatinsert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %.splat)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svqsub_n_s64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %.splatinsert = insertelement <vscale x 2 x i64> poison, i64 %1, i64 0
# |   %.splat = shufflevector <vscale x 2 x i64> %.splatinsert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %.splat)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_l
# | ...
# `---data was truncated (10240/13780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000560dcf3c615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560dcf3c30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560dcf3c689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f362d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f362d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f362d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f362d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560dcf35be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560dcf35bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560dcf340b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560dceff00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560dcefefdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f362d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f362d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f362d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560dcefefcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c (660 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_u8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_s8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_mf8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_u8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_s8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_mf8_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_u8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_s8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_hor_za8_mf8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_u8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_s8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svread_ver_za8_mf8_vg4(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svread_hor_za16_u16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32 1, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svread_hor_za16_bf16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.read.hor.vg2.nxv8bf16(i32 1, i32 %0)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.read.hor.vg2.nxv8bf16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svread_hor_za16_f16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.read.hor.vg2.nxv8f16(i32 1, i32 %0)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.read.hor.vg2.nxv8f16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svread_hor_za16_s16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32 1, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svread_ver_za16_u16_vg2(i32 noundef %base) #0 {
# | entry:
# |   %base.addr = alloca i32, align 4
# |   store i32 %base, ptr %base.addr, align 4
# |   %0 = load i32, ptr %base.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x
# | ...
# `---data was truncated (10240/51854) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005628ea48e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005628ea48b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005628ea48e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f4b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f4b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f4b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f4b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628ea423e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005628ea423c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005628ea408b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005628ea0b80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005628ea0b7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9f4b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f4b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f4b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628ea0b7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c (661 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwi
# | ...
# `---data was truncated (10240/235604) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055faa41b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055faa41ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055faa41b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2489449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24894a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2489449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2489431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055faa4146e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055faa4146c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055faa412bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055faa3ddb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055faa3ddadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2489432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24894330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24894330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055faa3ddacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c (662 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsplice_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.splice.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.splice.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsplice_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.splice.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.splice.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsplice_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.splice.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.splice.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsplice_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.splice.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.splice.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsplice_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.splice.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsplice_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.splice.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsplice_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.splice.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsplice_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.splice.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svsplice_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.splice.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.splice.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x 
# | ...
# `---data was truncated (10240/14328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563f76b6d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563f76b6a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563f76b6d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f485c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f485c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f485c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f485c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f76b02e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563f76b02c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563f76ae7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563f767970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563f76796dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f485c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f485c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f485c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f76796cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-neon-vget.c (663 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin    -target-abi apcs-gnu    -target-cpu cortex-a8    -mfloat-abi soft    -target-feature +soft-float-abi    -ffreestanding    -disable-O0-optnone -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -target-abi apcs-gnu -target-cpu cortex-a8 -mfloat-abi soft -target-feature +soft-float-abi -ffreestanding -disable-O0-optnone -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c"
# | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "thumbv7-apple-darwin"
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @low_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @low_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @low_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @low_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x i32> @low_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 0, i32 1>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x i32> @low_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> <i32 0, i32 1>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <1 x i64> @low_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> zeroinitializer
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <1 x i64> @low_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> zeroinitializer
# |   store <1 x i64> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @low_p8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @low_p16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x float> @low_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x float> %1, <4 x float> %2, <2 x i32> <i32 0, i32 1>
# |   store <2 x float> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @high_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i8> @high_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @high_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i16> @high_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr
# | ...
# `---data was truncated (10240/15571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea9f2bc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ea9f2b90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ea9f2bc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88e9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88e9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88e9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88e9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea9f251e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ea9f251c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ea9f236b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ea9eee60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ea9eee5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f88e9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88e9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88e9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea9eee5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c (664 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x i16> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.single.x4.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zm.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %7, 1
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.x2.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x i16> %8, <vscale x 8 x i16> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fscale.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svscale_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x i16> %zm.coerce0, <vscale x 8 x i16> %zm.coerce1, <vscale x 8 x i16> %zm.coerce2, <vscale x 8 x i16> %zm.coerce3) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %zm.coerce2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %zm.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 
# | ...
# `---data was truncated (10240/13379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005634503db15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005634503d80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005634503db89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fab249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fab2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fab249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fab231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563450370e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563450370c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563450355b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005634500050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563450004dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7fab232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fab2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fab2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563450004cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/neon/rounding-v8.5.c (665 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/rounding-v8.5.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +v8.5a           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +v8.5a -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd32x_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32x_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd32x_f321.i = call <2 x float> @llvm.aarch64.neon.frint32x.v2f32(<2 x float> %vrnd32x_f32.i)
# |   %vrnd32x_f322.i = bitcast <2 x float> %vrnd32x_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd32x_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd32xq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd32xq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd32xq_f321.i = call <4 x float> @llvm.aarch64.neon.frint32x.v4f32(<4 x float> %vrnd32xq_f32.i)
# |   %vrnd32xq_f322.i = bitcast <4 x float> %vrnd32xq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd32xq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd32z_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32z_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd32z_f321.i = call <2 x float> @llvm.aarch64.neon.frint32z.v2f32(<2 x float> %vrnd32z_f32.i)
# |   %vrnd32z_f322.i = bitcast <2 x float> %vrnd32z_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd32z_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd32zq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd32zq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd32zq_f321.i = call <4 x float> @llvm.aarch64.neon.frint32z.v4f32(<4 x float> %vrnd32zq_f32.i)
# |   %vrnd32zq_f322.i = bitcast <4 x float> %vrnd32zq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd32zq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd64x_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd64x_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd64x_f321.i = call <2 x float> @llvm.aarch64.neon.frint64x.v2f32(<2 x float> %vrnd64x_f32.i)
# |   %vrnd64x_f322.i = bitcast <2 x float> %vrnd64x_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd64x_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd64xq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd64xq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd64xq_f321.i = call <4 x float> @llvm.aarch64.neon.frint64x.v4f32(<4 x float> %vrnd64xq_f32.i)
# |   %vrnd64xq_f322.i = bitcast <4 x float> %vrnd64xq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd64xq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd64z_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd64z_f32.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrnd64z_f321.i = call <2 x float> @llvm.aarch64.neon.frint64z.v2f32(<2 x float> %vrnd64z_f32.i)
# |   %vrnd64z_f322.i = bitcast <2 x float> %vrnd64z_f321.i to <8 x i8>
# |   store <8 x i8> %vrnd64z_f322.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrnd64zq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd64zq_f32.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrnd64zq_f321.i = call <4 x float> @llvm.aarch64.neon.frint64z.v4f32(<4 x float> %vrnd64zq_f32.i)
# |   %vrnd64zq_f322.i = bitcast <4 x float> %vrnd64zq_f321.i to <16 x i8>
# |   store <16 x i8> %vrnd64zq_f322.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrnd32x_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32x_f64.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrnd32x_f641.i = call <1 x double> @llvm.aarch64.neon.frint32x.v1f64(<1 x double> %vrnd32x_f64.i)
# |   %vrnd32x_f642.i = bitcast <1 x double> %vrnd32x_f641.i to <8 x i8>
# |   store <8 x i8> %vrnd32x_f642.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrnd32xq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnd32xq_f64.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrnd32xq_f641.i = call <2 x double> @llvm.aarch64.neon.frint32x.v2f64(<2 x double> %vrnd32xq_f64.i)
# |   %vrnd32xq_f642.i = bitcast <2 x double> %vrnd32xq_f641.i to <16 x i8>
# |   store <16 x i8> %vrnd32xq_f642.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrnd32z_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrnd32z_f64.i = bitcast <8 x i8> %1 
# | ...
# `---data was truncated (10240/18543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000562c8711e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562c8711b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562c8711e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5e4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5e44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5e4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5e4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c870b3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562c870b3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562c87098b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562c86d480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562c86d47dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe5e4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5e44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5e44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c86d47cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c (666 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i
# | ...
# `---data was truncated (10240/306017) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563569b1f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563569b1c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563569b1f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc557b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc557b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc557b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc557aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563569ab4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563569ab4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563569a99b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005635697490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563569748dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc557aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc557aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc557aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563569748cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c (667 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function 
# | ...
# `---data was truncated (10240/66322) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a34f5a415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a34f5a10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a34f5a489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f1f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f1f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f1f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f1f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a34f539e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a34f539c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a34f51eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a34f1ce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a34f1cddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0f1f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f1f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f1f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a34f1cdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c (668 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056545c24415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056545c2410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056545c24489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef68333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef6838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef68333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef6831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056545c1d9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056545c1d9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056545c1beb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056545be6e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056545be6ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fef6831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef6831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef6831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056545be6dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c (669 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.
# | ...
# `---data was truncated (10240/30759) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d44235e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d44235b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d44235e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6807533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f680758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6807533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f680751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4422f3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d4422f3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d4422d8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d441f880b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d441f87dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f680751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f680751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f680751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d441f87cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c (670 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2_tu(target("riscv.vector.
# | ...
# `---data was truncated (10240/295525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624fad4a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005624fad470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005624fad4a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad0dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad0dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad0dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad0dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624facdfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005624facdfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005624facc4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005624fa9740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005624fa973dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fad0dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad0dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad0dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624fa973cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c (671 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4_tu(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2_tu(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1_tu(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2_tu(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4_tu(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8_tu(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2_tu(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1_tu(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2_tu(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   s
# | ...
# `---data was truncated (10240/280209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f591a9915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f591a960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f591a9989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d9c01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d9c0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d9c01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d9c003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f591a2ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f591a2ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f591a13b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f5916c30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f5916c2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7d9c004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d9c0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d9c0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5916c2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c (672 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, al
# | ...
# `---data was truncated (10240/225213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc12eae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dc12eab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dc12eae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f528b61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f528b6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f528b61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f528b603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc12e43e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dc12e43c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dc12e28b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dc12ad80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dc12ad7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f528b604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f528b6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f528b6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc12ad7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c (673 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vsc
# | ...
# `---data was truncated (10240/147382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c25550915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c2555060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c25550989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69d5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69d598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69d5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69d591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c25549ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c25549ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c255483b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c2551330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c255132dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f69d591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69d591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69d591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c255132cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c (674 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566b09a315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005566b09a00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005566b09a389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1b7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1b78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1b7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1b7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566b0938e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005566b0938c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005566b091db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005566b05cd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005566b05ccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc1b7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1b78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1b78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566b05cccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c (675 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.fcmpuo.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.fcmpuo.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.fcmpuo.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.fcmpuo.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.fcmpuo.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.fcmpuo.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_n_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, half noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca half, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store half %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x half> poison, half %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x half> %.splatinsert, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.fcmpuo.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_n_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 4 x float> poison, float %2, i64 0
# |   %.splat = shufflevector <vscale x 4 x float> %.splatinsert, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.fcmpuo.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpuo_n_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load double, ptr %op2.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 2 x double> poison, double %2, i64 0
# |   %.splat = shufflevector <vscale x 2 x double> %.splatinsert, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.fcmpuo.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %.splat)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c435cce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c435ccb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c435cce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0083c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0083c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0083c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0083c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c435c63e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c435c63c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c435c48b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c4358f80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c4358f7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0083c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0083c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0083c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4358f7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c (676 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.r
# | ...
# `---data was truncated (10240/65582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576f483b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005576f48380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005576f483b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61aac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61aaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61aac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61aac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576f47d0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005576f47d0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005576f47b5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005576f44650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005576f4464dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f61aac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61aac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61aac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576f4464cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/distributed-thin-lto/backend-skip.ll (677 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/backend-skip.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll
# |  #0 0x00005617d969915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005617d96960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005617d969989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa149e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa149e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa149e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa149e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617d962ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005617d962ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005617d9613b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005617d92c30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005617d92c2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa149e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa149e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa149e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617d92c2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/neon-intrinsics.c (678 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vmul_s8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <8 x i8> %2, %3
# |   store <8 x i8> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmul_s16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <4 x i16> %2, %3
# |   store <4 x i16> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vmul_s32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <2 x i32> %2, %3
# |   store <2 x i32> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmul_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %mul.i = fmul <2 x float> %2, %3
# |   store <2 x float> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vmul_u8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v1.addr = alloca <8 x i8>, align 8
# |   %v2.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v1, ptr %v1.addr, align 8
# |   store <8 x i8> %v2, ptr %v2.addr, align 8
# |   %0 = load <8 x i8>, ptr %v1.addr, align 8
# |   %1 = load <8 x i8>, ptr %v2.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <8 x i8> %2, %3
# |   store <8 x i8> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vmul_u16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v1.addr = alloca <4 x i16>, align 8
# |   %v2.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %v1, ptr %v1.addr, align 8
# |   store <4 x i16> %v2, ptr %v2.addr, align 8
# |   %0 = load <4 x i16>, ptr %v1.addr, align 8
# |   %1 = load <4 x i16>, ptr %v2.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <4 x i16> %2, %3
# |   store <4 x i16> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vmul_u32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %v1.addr = alloca <2 x i32>, align 8
# |   %v2.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %v1, ptr %v1.addr, align 8
# |   store <2 x i32> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x i32>, ptr %v1.addr, align 8
# |   %1 = load <2 x i32>, ptr %v2.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %mul.i = mul <2 x i32> %2, %3
# |   store <2 x i32> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vmulq_s8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v1.addr = alloca <16 x i8>, align 16
# |   %v2.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v1, ptr %v1.addr, align 16
# |   store <16 x i8> %v2, ptr %v2.addr, align 16
# |   %0 = load <16 x i8>, ptr %v1.addr, align 16
# |   %1 = load <16 x i8>, ptr %v2.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <16 x i8> %2, %3
# |   store <16 x i8> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmulq_s16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v1.addr = alloca <8 x i16>, align 16
# |   %v2.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %v1, ptr %v1.addr, align 16
# |   store <8 x i16> %v2, ptr %v2.addr, align 16
# |   %0 = load <8 x i16>, ptr %v1.addr, align 16
# |   %1 = load <8 x i16>, ptr %v2.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <8 x i16> %2, %3
# |   store <8 x i16> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmulq_s32(<4 x i32> noundef %v1, <4 x i32> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v1.addr = alloca <4 x i32>, align 16
# |   %v2.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %v1, ptr %v1.addr, align 16
# |   store <4 x i32> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x i32>, ptr %v1.addr, align 16
# |   %1 = load <4 x i32>, ptr %v2.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <4 x i32> %2, %3
# |   store <4 x i32> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vmulq_u8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v1.addr = alloca <16 x i8>, align 16
# |   %v2.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v1, ptr %v1.addr, align 16
# |   store <16 x i8> %v2, ptr %v2.addr, align 16
# |   %0 = load <16 x i8>, ptr %v1.addr, align 16
# |   %1 = load <16 x i8>, ptr %v2.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %mul.i = mul <16 x i8> %2, %3
# |   store <16 x i8> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmulq_u16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v1.addr = alloca <8 x i16>, align 16
# |   %v2.addr = alloca <8 x i16>, align 16
# |   s
# | ...
# `---data was truncated (10240/798827) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055a4f610d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a4f610a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a4f610d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24d9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24d98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24d9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24d9831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4f60a2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a4f60a2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a4f6087b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a4f5d370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a4f5d36dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f24d9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24d98330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24d98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a4f5d36cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c (679 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr
# | ...
# `---data was truncated (10240/15320) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb40dc315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bb40dc00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bb40dc389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33f8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33f818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33f8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33f811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb40d58e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bb40d58c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bb40d3db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bb409ed0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bb409ecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f33f811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33f811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33f811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb409eccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c (680 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615a1aaa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005615a1aa70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005615a1aaa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb88841bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8884725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb88841ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb888403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615a1a3fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005615a1a3fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005615a1a24b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005615a16d40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005615a16d3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb888404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8884050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8884050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615a16d3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c (681 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4(<vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2(<vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1(<vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2(<vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vx_f16m4(<vscale x 16 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willre
# | ...
# `---data was truncated (10240/273697) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557207c2315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557207c200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557207c2389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc8e3705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8e375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc8e3705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc8e36ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557207bb8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557207bb8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557207b9db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055720784d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055720784cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc8e36eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8e36ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8e36ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055720784ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c (682 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svinsr_n_s8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8>, i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svinsr_n_s16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16>, i16) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svinsr_n_s32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32> %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svinsr_n_s64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svinsr_n_u8(<vscale x 16 x i8> %op1, i8 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca i8, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store i8 %op2, ptr %op2.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svinsr_n_u16(<vscale x 8 x i16> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> %0, i16 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svinsr_n_u32(<vscale x 4 x i32> %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32> %0, i32 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svinsr_n_u64(<vscale x 2 x i64> %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svinsr_n_f16(<vscale x 8 x half> %op1, half noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca half, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store half %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.insr.nxv8f16(<vscale x 8 x half> %0, half %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.insr.nxv8f16(<vscale x 8 x half>, half) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svinsr_n_f32(<vscale x 4 x float> %op1, float noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca float, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store float %op2, ptr %op2.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.insr.nxv4f32(<vscale x 4 x float> %0, float %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.insr.nxv4f32(<vscale x 4 x float>, float) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svinsr_n_f64(<vscale x 2 x double> %op1, double noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca double, align 8
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store double %op2, ptr %op2.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load double, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.insr.nxv2f64(<vscale x 2 x double> %0, double %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.insr.nxv2f64(<vscale x 2 x double>, double) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svinsr_n_bf16(<vscale x 8 x bfloat> %op1, bfloat noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca bfloat, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.insr.nxv8bf16(<vscale x 8 x bfloat> %0, bfloat %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.insr.nxv8bf16(<vscale x 8 x bfloat>, bfloat) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562c8c0c315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562c8c0c00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562c8c0c389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa25681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2568725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa25681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa256803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c8c058e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562c8c058c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562c8c03db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562c8bced0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562c8bcecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa256804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2568050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2568050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c8bceccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c (683 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractval
# | ...
# `---data was truncated (10240/13669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056210181d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056210181a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056210181d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff154933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff15498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff154933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff15491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621017b2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005621017b2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562101797b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005621014470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562101446dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff15491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff15491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff15491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562101446cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c (684 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svneg_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svneg_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svneg_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svneg_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svneg_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svneg_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svneg_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svneg_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.neg.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svneg_s8_x(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.neg.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svneg_s16_x(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.neg.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svneg_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1
# | ...
# `---data was truncated (10240/20016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000056506810615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005650681030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056506810689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b49d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b49d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b49d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b49ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056506809be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056506809bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565068080b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000565067d300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000565067d2fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6b49ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b49cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b49cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565067d2fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c (685 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1ro_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1ro_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ro_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ro_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ro_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1ro_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ro_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ro_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ro_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svld1ro_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1ro_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1ro_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svld1ro_bf16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr 
# | ...
# `---data was truncated (10240/11274) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005640915e315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005640915e00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005640915e389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa968849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9688a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa968849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa968831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564091578e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564091578c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056409155db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056409120d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056409120cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa968832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9688330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9688330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056409120ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c (686 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/153905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2d2d7e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e2d2d7b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e2d2d7e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5950449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59504a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5950449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5950431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2d2d13e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e2d2d13c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e2d2cf8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e2d29a80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e2d29a7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5950432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59504330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59504330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2d29a7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c (687 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqrshrn_s16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqrshrn_u16_u32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svqrshrun_u16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrun.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrun.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055b453e7915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b453e760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b453e7989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc3cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc3cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc3cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc3cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b453e0ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b453e0ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b453df3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b453aa30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b453aa2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcc3cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc3cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc3cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b453aa2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c (688 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32mf2(ptr noundef %base, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m1(ptr noundef %base, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m2(ptr noundef %base, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m4(ptr noundef %base, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m8(ptr noundef %base, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m2(ptr noundef %base, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m4(ptr noundef %base, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m8(ptr noundef %base, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1,
# | ...
# `---data was truncated (10240/28354) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f13dcf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561f13dcc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561f13dcf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f671ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f671ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f671ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f671ff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f13d64e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561f13d64c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561f13d49b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561f139f90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561f139f8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f671ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f671ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f671ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f139f8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c (689 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, fl
# | ...
# `---data was truncated (10240/25099) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f96907f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f96907c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f96907f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b4b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b4b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b4b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b4b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f969014e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f969014c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f968ff9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f968ca90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f968ca8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9b4b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b4b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b4b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f968ca8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c (690 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcompact_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcompact_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.compact.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.compact.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcompact_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svcompact_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.compact.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svcompact_mf8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.compact.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svcompact_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.compact.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.compact.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svcompact_bf16(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.compact.nxv8bf16(<vscale x 8 x i1> %2, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.compact.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055de8b3b915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055de8b3b60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055de8b3b989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62bf733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62bf78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62bf733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62bf71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de8b34ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055de8b34ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055de8b333b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055de8afe30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055de8afe2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f62bf71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62bf71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62bf71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de8afe2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c (691 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7ed69215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e7ed68f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e7ed69289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb424b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb424b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb424b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb424b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7ed627e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e7ed627c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e7ed60cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e7ed2bc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e7ed2bbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb424b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb424b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb424b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7ed2bbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c (692 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2_tu(<vscale
# | ...
# `---data was truncated (10240/156471) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556cca77715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556cca7740f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556cca77789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2efbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2efbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2efbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2efbd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556cca70ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556cca70cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556cca6f1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556cca3a10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556cca3a0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2efbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2efbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2efbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556cca3a0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c (693 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.add
# | ...
# `---data was truncated (10240/424041) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055720771415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005572077110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055720771489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3899f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3899f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3899f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3899f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572076a9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005572076a9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055720768eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055720733e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055720733ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3899f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3899f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3899f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055720733dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve/dup.c (694 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/dup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o -        /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_n_s8(i8 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   store i8 %op, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_n_s16(i16 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i16, align 2
# |   store i16 %op, ptr %op.addr, align 2
# |   %0 = load i16, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_n_s32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_n_s64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_n_u8(i8 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   store i8 %op, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_n_u16(i16 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i16, align 2
# |   store i16 %op, ptr %op.addr, align 2
# |   %0 = load i16, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svdup_n_u32(i32 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   store i32 %op, ptr %op.addr, align 4
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svdup_n_u64(i64 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   store i64 %op, ptr %op.addr, align 8
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %0)
# |   ret <vscale x 2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svdup_n_f16(half noundef %op) #0 {
# | entry:
# |   %op.addr = alloca half, align 2
# |   store half %op, ptr %op.addr, align 2
# |   %0 = load half, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svdup_n_f32(float noundef %op) #0 {
# | entry:
# |   %op.addr = alloca float, align 4
# |   store float %op, ptr %op.addr, align 4
# |   %0 = load float, ptr %op.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svdup_n_f64(double noundef %op) #0 {
# | entry:
# |   %op.addr = alloca double, align 8
# |   store double %op, ptr %op.addr, align 8
# |   %0 = load double, ptr %op.addr, align 8
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b8(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 16 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 16 x i1> %.splatinsert, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
# |   ret <vscale x 16 x i1> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b16(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 8 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 8 x i1> %.splatinsert, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %.splat)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b32(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 4 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 4 x i1> %.splatinsert, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %.splat)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svdup_n_b64(i1 noundef %op) #0 {
# | entry:
# |   %op.addr = alloca i8, align 1
# |   %storedv = zext i1 %op to i8
# |   store i8 %storedv, ptr %op.addr, align 1
# |   %0 = load i8, ptr %op.addr, align 1
# |   %loadedv = icmp ne i8 %0, 0
# |   %.splatinsert = insertelement <vscale x 2 x i1> poison, i1 %loadedv, i64 0
# |   %.splat = shufflevector <vscale x 2 x i1> %.splatinsert, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %.splat)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svdup_n_bf16(bfloat noundef %op) #0 {
# | entry:
# |   %op.addr = alloca bfloat, align 2
# |   store bfloat %op, ptr %op.addr, align 2
# |   %0 = load bfloat, ptr %op.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat %0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svdup_n_s8_z(<vscale x 16 x i1> %pg, i8 noundef %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca i8, align 1
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store i8 %op, ptr %op.addr, align 1
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load i8, ptr %op.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, i8 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i8) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svdup_n_s16_z(<vscale x 16 x i1> %pg, i16 noundef %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store i16 %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load i16, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vsca
# | ...
# `---data was truncated (10240/49557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# |  #0 0x000055cc940d915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cc940d60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cc940d989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c27933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c2798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c27933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c2791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc9406ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cc9406ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cc94053b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cc93d030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cc93d02dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2c2791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c2791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c2791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc93d02cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c (695 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e933ad315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e933ad00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e933ad389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff432c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff432ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff432c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff432c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e933a68e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e933a68c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e933a4db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e9336fd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e9336fcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff432c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff432c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff432c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9336fccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c (696 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c8d8d815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559c8d8d50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559c8d8d889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24f1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24f1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24f1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24f1c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c8d86de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559c8d86dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559c8d852b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559c8d5020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559c8d501dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f24f1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24f1c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24f1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c8d501cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c (697 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %
# | ...
# `---data was truncated (10240/414517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2dc9fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e2dc9f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e2dc9fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efebc21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efebc2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efebc21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efebc203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2dc990e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e2dc990c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e2dc975b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e2dc6250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e2dc624dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efebc204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efebc2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efebc2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2dc624cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp (698 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z16test_vbicq_n_s1617__simd128_int16_t(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = and <8 x i16> %0, splat (i16 11007)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <4 x i32> @_Z16test_vbicq_n_u3218__simd128_uint32_t(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = and <4 x i32> %0, splat (i32 -8193)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <4 x i32> @_Z16test_vorrq_n_s3217__simd128_int32_t(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = or <4 x i32> %0, splat (i32 65536)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z16test_vorrq_n_u1618__simd128_uint16_t(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = or <8 x i16> %0, splat (i16 -4096)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef zeroext i16 @_Z16test_vcmpeqq_f1619__simd128_float16_tS_(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fcmp oeq <8 x half> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef zeroext i16 @_Z18test_vcmpeqq_n_f1619__simd128_float16_tDh(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fcmp oeq <8 x half> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z14test_vld1q_u16PKt(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @_Z16test_vst1q_p_s32Pi17__simd128_int32_tt(ptr noundef %base, <4 x i32> noundef %value, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %value.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %value, ptr %value.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %value.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 4
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   call void @llvm.masked.store.v4i32.p0(<4 x i32> %0, ptr align 4 %1, <4 x i1> %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr captures(none), <4 x i1>) #2
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc noundef <2 x i64> @_Z30test_vldrdq_gather_base_wb_s64P18__simd128_uint64_t(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <2 x i64>, ptr %0, align 8
# |   %2 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64> %1, i32 576)
# |   %3 = extractvalue { <2 x i64>, <2 x i64> } %2, 1
# |   store <2 x i64> %3, ptr %0, align 8
# |   %4 = extractvalue { <2 x i64>, <2 x i64> } %2, 0
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64>, i32) #3
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local arm_aapcs_vfpcc void @_Z31test_vstrwq_scatter_base_wb_u32P18__simd128_uint32_tS_(ptr noundef %addr, <4 x i32> noundef %value) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %value.addr = alloca <4 x i32>, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store <4 x i32> %value, ptr %value.addr, align 8
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 8
# |   %2 = load <4 x i32>, ptr %value.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32> %1, i32 64, <4 x i32> %2)
# |   store <4 x i32> %3, ptr %0, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32>, i32, <4 x i32>) #4
# | 
# | attributes #0 = { mustprogress noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #4 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559ef3ef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005559ef3ec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005559ef3ef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfd1e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfd1e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfd1e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfd1e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559ef384e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005559ef384c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005559ef369b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005559ef0190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005559ef018dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcfd1e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfd1e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfd1e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559ef018cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c (699 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvt_f16_x2(<vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvt_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %9)
# |   %10 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret <vscale x 16 x i8> %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvtn_f32_x4(<vscale x 4 x float> %zn.coerce0, <vscale x 4 x float> %zn.coerce1, <vscale x 4 x float> %zn.coerce2, <vscale x 4 x float> %zn.coerce3, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } poison, <vscale x 4 x float> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %0, <vscale x 4 x float> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, <vscale x 4 x float> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %2, <vscale x 4 x float> %zn.coerce3, 3
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn, align 16
# |   store { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %4 = load { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %4, 3
# |   %9 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %9)
# |   %10 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.x4(<vscale x 4 x float> %5, <vscale x 4 x float> %6, <vscale x 4 x float> %7, <vscale x 4 x float> %8)
# |   ret <vscale x 16 x i8> %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.x4(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_cvt_bf16_x2(<vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %5)
# |   %6 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret <vscale x 16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_cvt1_f16_x2(<vscale x 16 x i8> %zn, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %1)
# |   %2 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8f16(<vscale x 16 x i8> %0)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8f16(<vscale x 16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_cvt2_f16_x2(<vscale x 16 x i8> %zn, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr
# | ...
# `---data was truncated (10240/17058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000557d6e27f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557d6e27c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557d6e27f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc392733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc39278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc392733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc39271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d6e214e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557d6e214c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557d6e1f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557d6dea90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557d6dea8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc39271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc39271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc39271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d6dea8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c (700 of 27911)
******************** TEST 'Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +fullfp16 -target-feature +i8mm  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +fullfp16 -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.6a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %r, ptr %r.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %r.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.arm.neon.smmla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmmlaq_u32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %r, ptr %r.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %r.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vmmla1.i = call <4 x i32> @llvm.arm.neon.ummla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vusmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %r, ptr %r.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %r.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vusmmla.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vusmmla1.i = call <4 x i32> @llvm.arm.neon.usmmla.v4i32.v16i8(<4 x i32> %vusmmla.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vusmmla1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vusdot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_845 = alloca <2 x i32>, align 8
# |   %__s0_845 = alloca <2 x i32>, align 8
# |   %__s1_845 = alloca <8 x i8>, align 8
# |   %__s2_845 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_845, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_845, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_845, align 8
# |   %3 = load <2 x i32>, ptr %__s0_845, align 8
# |   %4 = load <8 x i8>, ptr %__s1_845, align 8
# |   %5 = load <2 x i32>, ptr %__s2_845, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> zeroinitializer
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vusdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vusdot1.i = call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_845, align 8
# |   %17 = load <2 x i32>, ptr %__ret_845, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vsudot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x i32>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret_841 = alloca <2 x i32>, align 8
# |   %__s0_841 = alloca <2 x i32>, align 8
# |   %__s1_841 = alloca <8 x i8>, align 8
# |   %__s2_841 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %r, ptr %r.addr, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %r.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_841, align 8
# |   %1 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_841, align 8
# |   %2 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_841, align 8
# |   %3 = load <2 x i32>, ptr %__s0_841, align 8
# |   %4 = load <2 x i32>, ptr %__s2_841, align 8
# |   store <2 x i32> %4, ptr %__s0, align 8
# |   %5 = load <8 x i8>, ptr %__s0, align 8
# |   %6 = bitcast <8 x i8> %5 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %6, <2 x i32> %6, <2 
# | ...
# `---data was truncated (10240/18482) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056511047015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056511046d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056511047089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc22a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc22a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc22a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc22a631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565110405e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565110405c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005651103eab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056511009a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000565110099dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc22a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc22a6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc22a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565110099cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c (701 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650b053d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005650b053a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005650b053d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d5be1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d5be725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d5be1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d5be03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650b04d2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005650b04d2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005650b04b7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005650b01670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005650b0166dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0d5be04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d5be050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d5be050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650b0166cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c (702 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646182e815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005646182e50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005646182e889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4f1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4f1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4f1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4f1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056461827de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056461827dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564618262b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564617f120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564617f11dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb4f1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4f1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4f1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564617f11cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c (703 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd31da515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dd31da20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dd31da589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f801a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f801a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f801a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f801a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd31d3ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dd31d3ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dd31d1fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dd319cf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dd319cedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f801a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f801a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f801a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd319cecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c (704 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpgt.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmpgt_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055edc60b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055edc60b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055edc60b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0aae249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0aae2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0aae249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0aae231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055edc604ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055edc604cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055edc6031b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055edc5ce10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055edc5ce0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0aae232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0aae2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0aae2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055edc5ce0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c (705 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrd_u32base_s32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrd_u64base_s64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svadrd_u32base_u32index(<vscale x 4 x i32> %bases, <vscale x 4 x i32> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %indices.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.adrd.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svadrd_u64base_u64index(<vscale x 2 x i64> %bases, <vscale x 2 x i64> %indices) #0 {
# | entry:
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   %indices.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   store <vscale x 2 x i64> %indices, ptr %indices.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %indices.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.adrd.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000563109d7315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563109d700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563109d7389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0796933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f079698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0796933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f079691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563109d08e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563109d08c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563109cedb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056310999d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056310999cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f079691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f079691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f079691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056310999ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c (706 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/70863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d42a21315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d42a2100f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d42a21389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6e2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6e28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6e2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6e2831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d42a1a8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d42a1a8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d42a18db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d429e3d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d429e3cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb6e2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6e28330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6e28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d429e3ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c (707 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e935a5915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e935a560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e935a5989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9dc2d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9dc2d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9dc2d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9dc2ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9359eee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e9359eec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e9359d3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e9356830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e935682dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9dc2ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9dc2cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9dc2cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e935682cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c (708 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = a
# | ...
# `---data was truncated (10240/288050) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056269b4f615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056269b4f30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056269b4f689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd909533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd90958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd909533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd90951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056269b48be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056269b48bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056269b470b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056269b1200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056269b11fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd90951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd90951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd90951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056269b11fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c (709 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/116259) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629d00f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005629d00f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005629d00f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa088849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0888a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa088849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa088831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629d008de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005629d008dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005629d0072b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005629cfd220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005629cfd21dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa088832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0888330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0888330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629cfd21cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c (710 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i6
# | ...
# `---data was truncated (10240/157165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c4164d615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c4164d30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c4164d689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe44f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe44f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe44f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe44f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c41646be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c41646bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c416450b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c4161000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c4160ffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe44f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe44f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe44f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4160ffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c (711 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, pt
# | ...
# `---data was truncated (10240/32402) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0a515215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d0a514f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d0a515289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ae7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ae7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ae7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ae7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0a50e7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d0a50e7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d0a50ccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d0a4d7c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d0a4d7bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3ae7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ae7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ae7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0a4d7bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve/rsqrte.c (712 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/rsqrte.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrsqrte_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = call <vscale x 8 x half> @llvm.aarch64.sve.frsqrte.x.nxv8f16(<vscale x 8 x half> %0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frsqrte.x.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrsqrte_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = call <vscale x 4 x float> @llvm.aarch64.sve.frsqrte.x.nxv4f32(<vscale x 4 x float> %0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frsqrte.x.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrsqrte_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = call <vscale x 2 x double> @llvm.aarch64.sve.frsqrte.x.nxv2f64(<vscale x 2 x double> %0)
# |   ret <vscale x 2 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frsqrte.x.nxv2f64(<vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000559c84be515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559c84be20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559c84be589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5c6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5c62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5c6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5c6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c84b7ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559c84b7ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559c84b5fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559c8480f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559c8480edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc5c6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5c62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5c62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c8480ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c (713 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vsc
# | ...
# `---data was truncated (10240/99843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560644be315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560644be00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560644be389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a1fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a1faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a1fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a1fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560644b78e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560644b78c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560644b5db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056064480d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056064480cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0a1fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a1fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a1fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056064480ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c (714 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005597f711f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005597f711c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005597f711f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71fc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71fc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71fc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71fc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005597f70b4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005597f70b4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005597f7099b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005597f6d490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005597f6d48dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f71fc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71fc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71fc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597f6d48cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c (715 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4_tu(<vscale x 16 x half> %maske
# | ...
# `---data was truncated (10240/157777) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6b9c4215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d6b9c3f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d6b9c4289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91e2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91e26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91e2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91e2631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6b9bd7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d6b9bd7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d6b9bbcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d6b986c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d6b986bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f91e2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91e26330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91e26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6b986bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c (716 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e93395d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e93395a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e93395d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad2af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad2af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad2af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad2af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9338f2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e9338f2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e9338d7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e9335870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e933586dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fad2af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad2af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad2af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e933586cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c (717 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsa
# | ...
# `---data was truncated (10240/179511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560dcf76c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560dcf7690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560dcf76c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30dfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30dfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30dfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30dfd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560dcf701e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560dcf701c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560dcf6e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560dcf3960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560dcf395dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f30dfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30dfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30dfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560dcf395cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c (718 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_s8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_u8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svzip_mf8_x2(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svzip_s16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svzip_u16_x2(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svzip_f16_x2(<vscale x 8 x half> %zn.coerce0, <vscale x 8 x half> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x half>, <vscale x 8 x half> }, align 16
# |   %0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } poison, <vscale x 8 x half> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %0, <vscale x 8 x half> %zn.coerce1, 1
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn, align 16
# |   store { <vscale x 8 x half>, <vscale x 8 x half> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x half>, <vscale x 8 x half> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %2, 1
# |   %5 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.zip.x2.nxv8f16(<vscale x 8 x half> %3, <vscale x 8 x half> %4)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.zip.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svzip_bf16_x2(<vscale x 8 x bfloat> %zn.coerce0, <vscale x 8 x bfloat> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.zip.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.zip.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svzip_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.c
# | ...
# `---data was truncated (10240/35785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055b50127215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b50126f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b50127289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde70849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde708a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde70849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde70831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b501207e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b501207c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b5011ecb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b500e9c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b500e9bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fde70832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde708330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde708330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b500e9bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c (719 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d336c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556d336c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556d336c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88b4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88b478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88b4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88b471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d3365ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556d3365ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556d3363fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556d332ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556d332eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f88b471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88b471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88b471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d332eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c (720 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea3a1a115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ea3a19e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ea3a1a189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2b9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2b9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2b9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2b9a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea3a136e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ea3a136c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ea3a11bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ea39dcb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ea39dcadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa2b9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2b9a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2b9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea39dcacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c (721 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call
# | ...
# `---data was truncated (10240/39914) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561afa48015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561afa47d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561afa48089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd37533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd3758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd37533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd3751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561afa415e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561afa415c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561afa3fab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561afa0aa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561afa0a9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcd3751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd3751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd3751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561afa0a9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c (722 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdivu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a9ccbc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556a9ccb90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556a9ccbc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa89ef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa89ef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa89ef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa89eeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a9cc51e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556a9cc51c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556a9cc36b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556a9c8e60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556a9c8e5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa89eeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa89eeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa89eeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a9c8e5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/neon-extract.c (723 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-extract.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vext_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vext = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
# |   store <8 x i8> %vext, ptr %ref.tmp, align 8
# |   %4 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %4, ptr %__ret, align 8
# |   %5 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %5, ptr %tmp, align 8
# |   %6 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vext_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i16>, align 8
# |   %__s1 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = bitcast <8 x i8> %2 to <4 x i16>
# |   %5 = bitcast <8 x i8> %3 to <4 x i16>
# |   %vext = shufflevector <4 x i16> %4, <4 x i16> %5, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
# |   store <4 x i16> %vext, ptr %ref.tmp, align 8
# |   %6 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %6, ptr %__ret, align 8
# |   %7 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %7, ptr %tmp, align 8
# |   %8 = load <4 x i16>, ptr %tmp, align 8
# |   ret <4 x i16> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vext_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %__s1 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = bitcast <8 x i8> %2 to <2 x i32>
# |   %5 = bitcast <8 x i8> %3 to <2 x i32>
# |   %vext = shufflevector <2 x i32> %4, <2 x i32> %5, <2 x i32> <i32 1, i32 2>
# |   store <2 x i32> %vext, ptr %ref.tmp, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp, align 8
# |   store <2 x i32> %6, ptr %__ret, align 8
# |   %7 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %7, ptr %tmp, align 8
# |   %8 = load <2 x i32>, ptr %tmp, align 8
# |   ret <2 x i32> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vext_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s0 = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__s0, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = bitcast <8 x i8> %2 to <1 x i64>
# |   %5 = bitcast <8 x i8> %3 to <1 x i64>
# |   %vext = shufflevector <1 x i64> %4, <1 x i64> %5, <1 x i32> zeroinitializer
# |   store <1 x i64> %vext, ptr %ref.tmp, align 8
# |   %6 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %6, ptr %__ret, align 8
# |   %7 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %7, ptr %tmp, align 8
# |   %8 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vextq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %__ret = alloca <16 x i8>, align 16
# |   %__s0 = alloca <16 x i8>, align 16
# |   %__s1 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__s0, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %vext = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
# |   store <16 x i8> %vext, ptr %ref.tmp, align 16
# |   %4 = load <16 x i8>, ptr %ref.tmp, align 16
# |   store <16 x i8> %4, ptr %__ret, align 16
# |   %5 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %5, ptr %tmp, align 16
# |   %6 = load <16 x i8>, ptr %tmp, align 16
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vextq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca <8 x i16>, align 16
# |   %__s1 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x i16>
# |   %5 = bitcast <16 x i8> %3 to <8 x i16>
# |   %vext = shufflevector <8 x i16> %4, <8 x i16> %5, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
# |   store <8 x i16> %vext, ptr %ref.tmp, align 16
# |   %6 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %6, ptr %__ret, align 16
# |   %7 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %7, ptr %tmp, align 16
# |   %8 = load <8 x i16>, ptr %tmp, align 16
# |   ret <8 x i16> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vextq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <4 x i32>, align 16
# |   %__s1 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %4 = bitcast <16 x i8> %2 to <4 x i32>
# |   %5 = bitcast <16 x i8> %3 to <4 x i32>
# |   %vext = shufflevector <4 x i32> %4, <4 x i32> %5, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
# |   store <4 x i32> %vext, ptr %ref.tmp, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp, align 16
# |   store <4 x i32> %6, ptr %__ret, align 16
# |   %7 = load <4 x i32>, ptr %__ret, align 16
# |   store <4 x i32> %7, ptr %tmp, align 16
# |   %8 = load <4 x i32>, ptr %tmp, align 16
# |   ret <4 x i32> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vextq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s0 = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__s0, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %1, ptr %__s1, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = load <16 x i8>, ptr %__s1, align 16
# |   %4 = bitcast <16 x i8> %2 to <2 x i64>
# |   %5 = bitcast <16 x i8> %3 to <2 x i64>
# |   %vext = shufflevector <2 x i64> %4, <2 x i64> %5, <2 x i32> <i32 1, i32 2>
# |   store <2 x i64> %vext, ptr %ref.tmp, align 16
# |   %6 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %6, ptr %__ret, align 16
# |   %7 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %7, ptr %tmp, align 16
# |   %8 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vext_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8>
# | ...
# `---data was truncated (10240/29598) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000562cf51de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562cf51db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562cf51de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd353f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd353f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd353f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd353f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562cf5173e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562cf5173c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562cf5158b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562cf4e080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562cf4e07dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd353f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd353f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd353f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562cf4e07cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c (724 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_u8mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_u8m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aac0fce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aac0fcb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aac0fce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc0db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc0db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc0db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc0db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aac0f63e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aac0f63c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aac0f48b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aac0bf80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aac0bf7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbc0db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc0db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc0db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aac0bf7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c (725 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sb_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sb_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = sext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1sb_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1sb_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1sb_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = sext <vscale x 4
# | ...
# `---data was truncated (10240/27977) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055644e21515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055644e2120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055644e21589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa4ba61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4ba6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa4ba61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa4ba603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055644e1aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055644e1aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055644e18fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055644de3f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055644de3edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa4ba604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4ba6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4ba6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055644de3ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c (726 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055818c9d115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055818c9ce0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055818c9d189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7c2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7c22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7c2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7c2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055818c966e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055818c966c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055818c94bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055818c5fb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055818c5fadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb7c2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7c22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7c22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055818c5facc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c (727 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmladhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8>, <16 x i8>, <16 x i8>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmladhq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16>, <8 x i16>, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmladhq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, i32 0, i32 0)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32>, <4 x i32>, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmladhxq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 1, i32 0, i32 0)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmladhxq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 1, i32 0, i32 0)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmladhxq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 1, i32 0, i32 0)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, i32 0, i32 1)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhxq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 1, i32 0, i32 1)
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhxq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 1, i32 0, i32 1)
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhxq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 1, i32 0, i32 1)
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmladhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 1, i32 0)
# |   r
# | ...
# `---data was truncated (10240/43005) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005565c54d115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005565c54ce0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005565c54d189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c86f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c86f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c86f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c86f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565c5466e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005565c5466c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005565c544bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005565c50fb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005565c50fadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8c86f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c86f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c86f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565c50facc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c (728 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8b5d0915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e8b5d060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e8b5d0989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fedbc133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fedbc18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fedbc133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fedbc11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8b5c9ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e8b5c9ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e8b5c83b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e8b59330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e8b5932dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fedbc11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fedbc11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fedbc11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8b5932cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c (729 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_hor_za8_s8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_hor_za8_u8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_hor_za8_mf8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svreadz_hor_za16_s16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 0, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svreadz_hor_za16_u16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 1, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half> } @test_svreadz_hor_za16_f16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 0, i32 %0)
# |   ret { <vscale x 8 x half>, <vscale x 8 x half> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svreadz_hor_za16_bf16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 1, i32 %0)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svreadz_hor_za32_s32_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 0, i32 %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svreadz_hor_za32_u32_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 2, i32 %0)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float> } @test_svreadz_hor_za32_f32_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.readz.horiz.x2.nxv4f32(i32 3, i32 %0)
# |   ret { <vscale x 4 x float>, <vscale x 4 x float> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.readz.horiz.x2.nxv4f32(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svreadz_hor_za64_s64_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 0, i32 %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svreadz_hor_za64_u64_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 4, i32 %0)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double> } @test_svreadz_hor_za64_f64_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.readz.horiz.x2.nxv2f64(i32 7, i32 %0)
# |   ret { <vscale x 2 x double>, <vscale x 2 x double> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.readz.horiz.x2.nxv2f64(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_ver_za8_s8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_ver_za8_u8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svreadz_ver_za8_mf8_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svreadz_ver_za16_s16_x2(i32 noundef %slice) #0 {
# | entry:
# |   %slice.addr = alloca i32, align 4
# |   store i32 %slice, ptr %slice.addr, align 4
# |   %0 = load i32, ptr %slice.addr, align 4
# |   %1 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sme.readz.vert.x2.nxv8i16(i32 0, i32 %0)
# |   ret { <vscale x 8 x i16>, <vscale x
# | ...
# `---data was truncated (10240/66009) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000555edeee315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555edeee00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555edeee389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e38d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e38d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e38d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e38d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555edee78e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555edee78c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555edee5db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555edeb0d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555edeb0cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0e38d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e38d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e38d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555edeb0ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c (730 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d698c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559d698c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559d698c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e01649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e016a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e01649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e01631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d6985ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559d6985ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559d6983fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559d694ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559d694eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0e01632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e016330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e016330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d694eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c (731 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 
# | ...
# `---data was truncated (10240/14429) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ffcd2d615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ffcd2d30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ffcd2d689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf8ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf8baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf8ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf8ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffcd26be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ffcd26bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ffcd250b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ffccf000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ffcceffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbf8ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf8ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf8ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffcceffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c (732 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svundef2_b() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svundef4_b() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055727ad8d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055727ad8a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055727ad8d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f605bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f605bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f605bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f605bd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055727ad22e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055727ad22c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055727ad07b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055727a9b70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055727a9b6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f605bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f605bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f605bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055727a9b6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c (733 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f99c5015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562f99c4d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562f99c5089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f4f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f4f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f4f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f4f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f99be5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562f99be5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562f99bcab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562f9987a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562f99879dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3f4f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f4f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f4f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f99879cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c (734 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vr
# | ...
# `---data was truncated (10240/96265) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff569ea15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ff569e70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ff569ea89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69d5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69d598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69d5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69d591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff5697fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ff5697fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ff56964b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ff566140b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ff56613dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f69d591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69d591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69d591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff56613cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c (735 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %binde
# | ...
# `---data was truncated (10240/110121) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056105810d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056105810a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056105810d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8fcd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8fcd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8fcd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8fcd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610580a2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005610580a2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561058087b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561057d370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561057d36dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8fcd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8fcd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8fcd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561057d36cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c (736 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr
# | ...
# `---data was truncated (10240/15320) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606fb46015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005606fb45d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005606fb46089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58e0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58e0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58e0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58e0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606fb3f5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005606fb3f5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005606fb3dab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005606fb08a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005606fb089dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f58e0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58e0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58e0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606fb089cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c (737 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc0dbc815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cc0dbc50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cc0dbc889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f79133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f7918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f79133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f7911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc0db5de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cc0db5dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cc0db42b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cc0d7f20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cc0d7f1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8f7911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f7911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f7911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc0d7f1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vaddv.c (738 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vaddv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.v16i8(<16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.v8i16(<8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 1)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s8(i32 noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 0)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s16(i32 noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 0)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 0)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u8(i32 noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 1)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u16(i32 noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 1)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 1)
# |   %2 = load i32, ptr %a.addr, align 4
# |   %3 = add i32 %1, %2
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %0, i32 0, <16 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %0, i32 0, <8 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %0, i32 1, <16 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %0, i32 1, <8 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 1, <4 x i1> %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_p_s8(i32 noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 =
# | ...
# `---data was truncated (10240/19190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a6711815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561a671150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561a6711889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f503a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f503a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f503a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f503a91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a670ade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561a670adc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561a67092b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561a66d420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561a66d41dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f503a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f503a91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f503a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a66d41cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c (739 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %zt.coerce0, <vscale x 16 x i8> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zt.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2q.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2q.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %zt.coerce0, <vscale x 16 x i8> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zt.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   call void @llvm.aarch64.sve.st2q.nxv16i8.p0(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i1> %2, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %zt.coerce0, <vscale x 8 x i16> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zt.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv8i16.p0(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2q.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %zt.coerce0, <vscale x 8 x i16> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zt.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv8i16.p0(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %zt.coerce0, <vscale x 4 x i32> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zt.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv4i32.p0(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i1> %7, ptr %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st2q.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst2q_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %zt.coerce0, <vscale x 4 x i32> %zt.coerce1) #0 {
# | entry:
# |   %zt = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %zt.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zt.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zt.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zt, align 16
# |   %zt1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zt1, ptr %zt.addr, align 16
# |   %2 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %3 = load ptr, ptr %base.addr, align 8
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zt.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %2)
# |   call void @llvm.aarch64.sve.st2q.nxv4i32.p0(<vscale x 
# | ...
# `---data was truncated (10240/172384) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005564a64fa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005564a64f70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005564a64fa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ddd905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ddd95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ddd905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ddd8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564a648fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005564a648fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005564a6474b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005564a61240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005564a6123dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1ddd8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ddd8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ddd8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564a6123cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c (740 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9d3dee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c9d3deb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c9d3dee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c00933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c0098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c00933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c0091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9d3d83e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c9d3d83c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c9d3d68b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c9d3a180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c9d3a17dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4c0091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c0091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c0091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9d3a17cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c (741 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b43dca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560b43dc70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560b43dca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fe4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fe478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fe4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fe471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b43d5fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560b43d5fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560b43d44b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560b439f40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560b439f3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4fe471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fe471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fe471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b439f3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/distributed-thin-lto/newpm.ll (742 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/newpm.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 11
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll
# |  #0 0x00005629e0dc215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005629e0dbf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005629e0dc289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4c6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4c698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4c6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4c691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629e0d57e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005629e0d57c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005629e0d3cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005629e09ec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005629e09ebdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb4c691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4c691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4c691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629e09ebcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c (743 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d2469915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561d246960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561d2469989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3728b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3728b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3728b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3728aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d2462ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561d2462ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561d24613b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561d242c30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561d242c2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3728aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3728aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3728aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d242c2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c (744 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svclamp_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   %op3.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x half> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.fclamp.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fclamp.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svclamp_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   %op3.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x float> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.fclamp.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fclamp.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svclamp_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   %op3.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x double> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.fclamp.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fclamp.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000056061272115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056061271e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056061272189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1647333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f164738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1647333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f164731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606126b6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005606126b6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056061269bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056061234b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056061234add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f164731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f164731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f164731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056061234acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c (745 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/170497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583c4c9d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005583c4c9a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005583c4c9d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06ad049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06ad0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06ad049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06ad031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583c4c32e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005583c4c32c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005583c4c17b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005583c48c70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005583c48c6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f06ad032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06ad0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06ad0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583c48c6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c (746 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1   -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_u16_m(<vscale x 8 x i16> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %2, i32 1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_s16_m(<vscale x 8 x i16> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %2, i32 1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_u32_m(<vscale x 4 x i32> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %2, i32 1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_s32_m(<vscale x 4 x i32> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %2, i32 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svpmov_lane_u64_m(<vscale x 2 x i64> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %2, i32 1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svpmov_lane_s64_m(<vscale x 2 x i64> %zn, <vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %2, i32 7)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svpmov_lane_u8_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svpmov_lane_s8_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1> %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_u16_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svpmov_lane_s16_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_u32_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svpmov_lane_s32_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svpmov_lane_u64_z(<vscale x 16 x i1> %pn) #0 {
# | entry:
# |   %pn.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pn, ptr %pn.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pn.addr, align 2
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# | ...
# `---data was truncated (10240/11780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055abbe05515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055abbe0520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055abbe05589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fea533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fea58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fea533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fea51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055abbdfeae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055abbdfeac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055abbdfcfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055abbdc7f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055abbdc7edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0fea51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fea51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fea51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055abbdc7ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c (747 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu
# | ...
# `---data was truncated (10240/156765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645d2c9815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005645d2c950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005645d2c9889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03bde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03bdea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03bde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03bde31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645d2c2de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005645d2c2dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005645d2c12b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005645d28c20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005645d28c1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f03bde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03bde330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03bde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645d28c1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c (748 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_asrl(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.asrl(i32 %3, i32 %2, i32 %4)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.asrl(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_lsll(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %3, i32 %2, i32 %4)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.lsll(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_sqrshr(i32 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   %shift.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = load i32, ptr %shift.addr, align 4
# |   %2 = call i32 @llvm.arm.mve.sqrshr(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.sqrshr(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_sqrshrl(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %3, i32 %2, i32 %4, i32 64)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.sqrshrl(i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_sqrshrl_sat48(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %3, i32 %2, i32 %4, i32 48)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_sqshl(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.sqshl(i32 %0, i32 2)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.sqshl(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_sqshll(i64 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   store i64 %value, ptr %value.addr, align 8
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.mve.sqshll(i32 %3, i32 %2, i32 17)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.sqshll(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_srshr(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.srshr(i32 %0, i32 6)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.srshr(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_srshrl(i64 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   store i64 %value, ptr %value.addr, align 8
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.mve.srshrl(i32 %3, i32 %2, i32 26)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.srshrl(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_uqrshl(i32 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   %shift.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = load i32, ptr %shift.addr, align 4
# |   %2 = call i32 @llvm.arm.mve.uqrshl(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.uqrshl(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_uqrshll(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %3, i32 %2, i32 %4, i32 64)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.uqrshll(i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_uqrshll_sat48(i64 noundef %value, i32 noundef %shift) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   %shift.addr = alloca i32, align 4
# |   store i64 %value, ptr %value.addr, align 8
# |   store i32 %shift, ptr %shift.addr, align 4
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %shift.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %3, i32 %2, i32 %4, i32 48)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_uqshl(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.uqshl(i32 %0, i32 21)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.uqshl(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_uqshll(i64 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i64, align 8
# |   store i64 %value, ptr %value.addr, align 8
# |   %0 = load i64, ptr %value.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.mve.uqshll(i32 %3, i32 %2, i32 16)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.uqshll(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_urshr(i32 noundef %value) #0 {
# | entry:
# |   %value.addr = alloca i32, align 4
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load i32, ptr %value.addr, align 4
# |   %1 = call i32 @llvm.arm.mve.urshr(i32 %0, i32 22)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nos
# | ...
# `---data was truncated (10240/11578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a1735c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558a173590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558a1735c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f359c305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f359c35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f359c305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f359c2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a172f1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558a172f1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558a172d6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558a16f860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558a16f85dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f359c2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f359c2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f359c2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a16f85cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve/nand.c (749 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/nand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svnand_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000560d1da6b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560d1da680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560d1da6b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b62249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b622a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b62249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b62231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d1da00e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560d1da00c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560d1d9e5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560d1d6950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560d1d694dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0b62232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b622330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b622330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d1d694cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c (750 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.
# | ...
# `---data was truncated (10240/14900) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560fa0a515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005560fa0a20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005560fa0a589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b95d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b95d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b95d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b95d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560fa03ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005560fa03ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005560fa01fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005560f9ccf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005560f9ccedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5b95d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b95d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b95d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560f9ccecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c (751 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, a
# | ...
# `---data was truncated (10240/28358) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec95c9c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ec95c990f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ec95c9c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9992305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f999235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9992305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99922ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec95c31e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ec95c31c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ec95c16b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ec958c60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ec958c5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f99922eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99922ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99922ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec958c5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c (752 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | d
# | ...
# `---data was truncated (10240/95223) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560c679b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005560c67980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005560c679b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12b881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12b88725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12b881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12b8803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560c6730e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005560c6730c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005560c6715b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005560c63c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005560c63c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f12b8804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12b88050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12b88050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560c63c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c (753 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsubr_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsubr_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsubr_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsubr_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsubr_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsubr_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svsubr_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svsubr_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsubr_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vsc
# | ...
# `---data was truncated (10240/72568) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561f9b91415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561f9b9110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561f9b91489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc36933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc3698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc36933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc3691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f9b8a9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561f9b8a9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561f9b88eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561f9b53e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561f9b53ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbc3691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc3691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc3691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f9b53dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c (754 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.riscv
# | ...
# `---data was truncated (10240/83637) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f86bda15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557f86bd70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557f86bda89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdae2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdae2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdae2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdae2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f86b6fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557f86b6fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557f86b54b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557f868040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557f86803dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdae2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdae2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdae2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f86803cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c (755 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639393d715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005639393d40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005639393d789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5539733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f553978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5539733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f553971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056393936ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056393936cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563939351b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005639390010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563939000dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f553971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f553971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f553971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563939000cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c (756 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_s8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_u8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svuzp_mf8_x4(<vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zn.coerce2, <vscale x 16 x i8> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %zn.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 3
# |   %9 = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x4.nxv16i8(<vscale x 16 x i8> %5, <vscale x 16 x i8> %6, <vscale x 16 x i8> %7, <vscale x 16 x i8> %8)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %9
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svuzp_s16_x4(<vscale x 8 x i16> %zn.coerce0, <vscale x 8 x i16> %zn.coerce1, <vscale x 8 x i16> %zn.coerce2, <vscale x 8 x i16> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %zn.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, 3
# |   %9 = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x4.nxv8i16(<vscale x 8 x i16> %5, <vscale x 8 x i16> %6, <vscale x 8 x i16> %7, <vscale x 8 x i16> %8)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | ...
# `---data was truncated (10240/67329) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000561ea7a4c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561ea7a490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561ea7a4c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94f4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94f42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94f4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94f4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ea79e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561ea79e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561ea79c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561ea76760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561ea7675dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f94f4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94f42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94f42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ea7675cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c (757 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdot_lane_za16_mf8_vg1x2(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 7)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdotb_lane_za32_mf8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svvdott_lane_za32_mf8_vg1x4(i32 noundef %slice, <vscale x 16 x i8> %zn.coerce0, <vscale x 16 x i8> %zn.coerce1, <vscale x 16 x i8> %zm, i64 noundef %fpmr) #0 {
# | entry:
# |   %zn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %slice.addr = alloca i32, align 4
# |   %zn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %fpmr.addr = alloca i64, align 8
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn, align 16
# |   store i32 %slice, ptr %slice.addr, align 4
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zn1, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   store i64 %fpmr, ptr %fpmr.addr, align 8
# |   %2 = load i32, ptr %slice.addr, align 4
# |   %3 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zn.addr, align 16
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %3, 1
# |   %6 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %7 = load i64, ptr %fpmr.addr, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   call void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32 %2, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite)
# | declare void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f8f16,+sme-f8f32" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim
# |  #0 0x000055587d6fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055587d6fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055587d6fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02b8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02b838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02b8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02b831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055587d692e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055587d692c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055587d677b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055587d3270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055587d326dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f02b831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02b831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02b831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055587d326cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c (758 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cnth(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcnth_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cnth(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005651e0e2e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005651e0e2b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005651e0e2e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31a1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31a1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31a1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31a1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651e0dc3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005651e0dc3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005651e0da8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005651e0a580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005651e0a57dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f31a1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31a1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31a1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651e0a57cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c (759 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcreate_v_f16m1_f16m2(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x half>, align 2
# |   %v1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x half> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   %3 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %2, <vscale x 4 x half> %1, i64 4)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcreate_v_f16m1_f16m4(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x half>, align 2
# |   %v1.addr = alloca <vscale x 4 x half>, align 2
# |   %v2.addr = alloca <vscale x 4 x half>, align 2
# |   %v3.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x half> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x half> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x half> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   %5 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %4, <vscale x 4 x half> %1, i64 4)
# |   %6 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %5, <vscale x 4 x half> %2, i64 8)
# |   %7 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %6, <vscale x 4 x half> %3, i64 12)
# |   ret <vscale x 16 x half> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcreate_v_f16m1_f16m8(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3, <vscale x 4 x half> %v4, <vscale x 4 x half> %v5, <vscale x 4 x half> %v6, <vscale x 4 x half> %v7) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x half>, align 2
# |   %v1.addr = alloca <vscale x 4 x half>, align 2
# |   %v2.addr = alloca <vscale x 4 x half>, align 2
# |   %v3.addr = alloca <vscale x 4 x half>, align 2
# |   %v4.addr = alloca <vscale x 4 x half>, align 2
# |   %v5.addr = alloca <vscale x 4 x half>, align 2
# |   %v6.addr = alloca <vscale x 4 x half>, align 2
# |   %v7.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x half> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x half> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x half> %v3, ptr %v3.addr, align 2
# |   store <vscale x 4 x half> %v4, ptr %v4.addr, align 2
# |   store <vscale x 4 x half> %v5, ptr %v5.addr, align 2
# |   store <vscale x 4 x half> %v6, ptr %v6.addr, align 2
# |   store <vscale x 4 x half> %v7, ptr %v7.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %v3.addr, align 2
# |   %4 = load <vscale x 4 x half>, ptr %v4.addr, align 2
# |   %5 = load <vscale x 4 x half>, ptr %v5.addr, align 2
# |   %6 = load <vscale x 4 x half>, ptr %v6.addr, align 2
# |   %7 = load <vscale x 4 x half>, ptr %v7.addr, align 2
# |   %8 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   %9 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %8, <vscale x 4 x half> %1, i64 4)
# |   %10 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %9, <vscale x 4 x half> %2, i64 8)
# |   %11 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %10, <vscale x 4 x half> %3, i64 12)
# |   %12 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %11, <vscale x 4 x half> %4, i64 16)
# |   %13 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %12, <vscale x 4 x half> %5, i64 20)
# |   %14 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %13, <vscale x 4 x half> %6, i64 24)
# |   %15 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %14, <vscale x 4 x half> %7, i64 28)
# |   ret <vscale x 32 x half> %15
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcreate_v_f16m2_f16m4(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x half>, align 2
# |   %v1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x half> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   %3 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> %2, <vscale x 8 x half> %1, i64 8)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcreate_v_f16m2_f16m8(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x half>, align 2
# |   %v1.addr = alloca <vscale x 8 x half>, align 2
# |   %v2.addr = alloca <vscale x 8 x half>, align 2
# |   %v3.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x half> %v1, ptr %v1.addr, align 2
# |   store <vscale x 8 x half> %v2, ptr %v2.addr, align 2
# |   store <vscale x 8 x half> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   %5 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %4, <vscale x 8 x half> %1, i64 8)
# |   %6 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %5, <vscale x 8 x half> %2, i64 16)
# |   %7 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %6, <vscale x 8 x half> %3, i64 24)
# |   ret <vscale x 32 x half> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcreate_v_f16m4_f16m8(<vscale x 16 x half> %v0, <vscale x 16 x half> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 16 x half>, align 2
# |   %v1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %v0, ptr %v0.addr, align 2
# |   store <vscale x 16 x half> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> poison, <vscale x 16 x half> %0, i64 0)
# |   %3 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> %2, <vscale x 16 x half> %1, i64 16)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half>, <vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vcreate_v_f32m1_f32m2(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 2 x float>, align 4
# |   %v1.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %v0, ptr %v0.addr, align 4
# |   store <vscale x 2 x float> %v1, ptr %v1.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %v0.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %v1.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> poison, <vscale x 2 x float> %0, i64 0)
# |   %3 = call <vscale x 4 x float> @llvm.
# | ...
# `---data was truncated (10240/593252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e955a8115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e955a7e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e955a8189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8956333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f895638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8956333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f895631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e955a16e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e955a16c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e9559fbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e9556ab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e9556aadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f895631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f895631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f895631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9556aacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c (760 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vabd
# | ...
# `---data was truncated (10240/215044) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f1e282f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f1e282c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f1e282f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdaabe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdaabea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdaabe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdaabe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1e27c4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f1e27c4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f1e27a9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f1e24590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f1e2458dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdaabe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdaabe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdaabe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f1e2458cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c (761 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560664a715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005560664a40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005560664a789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36f9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36f918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36f9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36f911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055606643ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055606643cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556066421b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005560660d10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005560660d0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f36f911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36f911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36f911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560660d0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c (762 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsaddu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vsca
# | ...
# `---data was truncated (10240/98171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641ed1ed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005641ed1ea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005641ed1ed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b1db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b1db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b1db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b1db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641ed182e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005641ed182c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005641ed167b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005641ece170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005641ece16dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3b1db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b1db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b1db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641ece16cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c (763 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmaxu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c10d2415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564c10d210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564c10d2489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f5ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f5baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f5ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f5ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c10cb9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564c10cb9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564c10c9eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564c1094e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564c1094ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2f5ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f5ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f5ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c1094dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c (764 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svclamp_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fclamp.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fclamp.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055640164015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055640163d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055640164089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7317249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73172a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7317249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7317231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564015d5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005564015d5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005564015bab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055640126a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556401269dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7317232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73172330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73172330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556401269cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c (765 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_wv_i16m1(<vscal
# | ...
# `---data was truncated (10240/134557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a972cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558a972c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558a972cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e97733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e9778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e97733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e9771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a97260e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558a97260c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558a97245b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558a96ef50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558a96ef4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4e9771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e9771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e9771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a96ef4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c (766 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fdcbeec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fdcbee90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fdcbeec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3ce733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3ce78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3ce733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3ce71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fdcbe81e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fdcbe81c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fdcbe66b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fdcbb160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fdcbb15dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe3ce71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3ce71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3ce71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fdcbb15cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c (767 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmaxnm_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> zeroinitializer
# |   %5 = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %4, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmaxnm_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> zeroinitializer
# |   %5 = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %4, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmaxnm_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> zeroinitializer
# |   %5 = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %4, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmaxnm_f16_m(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmaxnm_f32_m(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmaxnm_f64_m(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1> %3, <vscale x 2 x double> %1, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svmaxnm_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.u.nxv8f16(<vscale x 8 x i1> %3, <vscale x 8 x half> %1, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svmaxnm_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.u.nxv4f32(<vscale x 4 x i1> %3, <vscale x 4 x float> %1, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svmaxnm_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.ad
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005580dc2b215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005580dc2af0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005580dc2b289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8024c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8024ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8024c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8024c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580dc247e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005580dc247c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005580dc22cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005580dbedc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005580dbedbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8024c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8024c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8024c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580dbedbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c (768 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   re
# | ...
# `---data was truncated (10240/120915) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0f937415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c0f93710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c0f937489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feaba533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feaba58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feaba533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feaba51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0f9309e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c0f9309c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c0f92eeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c0f8f9e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c0f8f9ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feaba51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feaba51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feaba51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0f8f9dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c (769 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsqrshr_u16_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsqrshr_s16_s32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshr.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, i32 16)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshr.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsqrshr_u8_u32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.uqrshr.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, i32 8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uqrshr.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svsqrshr_s8_s32_x4(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1, <vscale x 4 x i32> %zn.coerce2, <vscale x 4 x i32> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %zn.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 1
# |   %7 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 2
# |   %8 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, 3
# |   %9 = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshr.x4.nxv4i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %6, <vscale x 4 x i32> %7, <vscale x 4 x i32> %8, i32 8)
# |   ret <vscale x 16 x i8> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrshr.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svsqrshr_u16_u64_x4(<vscale x 2 x i64> %zn.coerce0, <vscale x 2 x i64> %zn.coerce1, <vscale x 2 x i64> %zn.coerce2, <vscale x 2 x i64> %zn.coerce3) #0 {
# | entry:
# |   %zn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zn.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %zn.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %zn.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %zn, align 16
# |   %zn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %zn1, ptr %zn.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zn.addr, align 16
# |   %5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 1
# |   %7 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 2
# |   %8 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, 3
# |   %9 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x4.nxv2i64(<vscale x 2 x i64> %5, <vscale x 2 x i64> %6, <vscale x 2 x i64> %7, <vscale x 2 x i64> %8, i32 16)
# |   ret <vscale x 8 x i16> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshr.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/33461) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055b0b6c8215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b0b6c7f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b0b6c8289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a65133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a6518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a65133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a6511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0b6c17e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b0b6c17c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b0b6bfcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b0b68ac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b0b68abdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0a6511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a6511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a6511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0b68abcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c (770 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.stnt1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv16i8.p0(<vscale x 16 x i8>, <vscale x 16 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv8i16.p0(<vscale x 8 x i16>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv4i32.p0(<vscale x 4 x i32>, <vscale x 4 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv2i64.p0(<vscale x 2 x i64>, <vscale x 2 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u8(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 16 x i8> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %data.addr, align 16
# |   call void @llvm.aarch64.sve.stnt1.nxv16i8.p0(<vscale x 16 x i8> %2, <vscale x 16 x i1> %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv8i16.p0(<vscale x 8 x i16> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv4i32.p0(<vscale x 4 x i32> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv2i64.p0(<vscale x 2 x i64> %2, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_f16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x half> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv8f16.p0(<vscale x 8 x half> %2, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv8f16.p0(<vscale x 8 x half>, <vscale x 8 x i1>, ptr captures(none)) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svstnt1_f32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x float> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.stnt1.nxv4f32.p0(<vscale x 4 x float> %2, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.stnt1.nxv4f32.p0(<vscale x 4 x float>, <vscale x 4 x i1>, ptr
# | ...
# `---data was truncated (10240/26796) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055de6d02b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055de6d0280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055de6d02b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb350e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb350e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb350e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb350e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de6cfc0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055de6cfc0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055de6cfa5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055de6cc550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055de6cc54dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb350e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb350e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb350e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de6cc54cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c (771 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c89822615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c8982230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c89822689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ac6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ac6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ac6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ac6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8981bbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c8981bbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c8981a0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c897e500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c897e4fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6ac6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ac6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ac6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c897e4fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c (772 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulh_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vsc
# | ...
# `---data was truncated (10240/65701) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c434b915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563c434b60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563c434b989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effaf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effaf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effaf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effaf91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c4344ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563c4344ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563c43433b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563c430e30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563c430e2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007effaf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effaf91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effaf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c430e2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c (773 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ee4c4a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558ee4c470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558ee4c4a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd643733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd64378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd643733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd64371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ee4bdfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558ee4bdfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558ee4bc4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558ee48740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558ee4873dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd64371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd64371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd64371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ee4873cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c (774 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <
# | ...
# `---data was truncated (10240/18691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652de79115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005652de78e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005652de79189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8453733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f845378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8453733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f845371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652de726e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005652de726c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005652de70bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005652de3bb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005652de3badd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f845371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f845371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f845371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652de3bacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c (775 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/223863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653ee6c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005653ee6c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005653ee6c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc097d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc097d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc097d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc097d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653ee65ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005653ee65ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005653ee63fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005653ee2ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005653ee2eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc097d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc097d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc097d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653ee2eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c (776 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0a969d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e0a969a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e0a969d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa961e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa961ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa961e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa961e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0a9632e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e0a9632c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e0a9617b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e0a92c70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e0a92c6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa961e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa961e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa961e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0a92c6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c (777 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056186413f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056186413c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056186413f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9bfd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9bfd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9bfd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9bfd71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618640d4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005618640d4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005618640b9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561863d690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561863d68dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9bfd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9bfd71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9bfd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561863d68cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c (778 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eadecc115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eadecbe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eadecc189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad31c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad31ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad31c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad31c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eadec56e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eadec56c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eadec3bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eade8eb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eade8eadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fad31c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad31c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad31c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eade8eacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c (779 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op
# | ...
# `---data was truncated (10240/154517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac095d215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ac095cf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ac095d289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff51b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff51b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff51b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff51b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac09567e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ac09567c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ac0954cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ac091fc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ac091fbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff51b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff51b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff51b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac091fbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c (780 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f10fe415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555f10fe10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555f10fe489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73d2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73d2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73d2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73d2c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f10f79e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555f10f79c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555f10f5eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555f10c0e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555f10c0ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f73d2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73d2c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73d2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f10c0dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c (781 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallbac
# | ...
# `---data was truncated (10240/66028) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c200b8015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c200b7d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c200b8089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb63449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb634a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb63449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb63431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c200b15e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c200b15c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c200afab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c2007aa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c2007a9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbb63432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb634330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb634330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2007a9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c (782 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vaadd_vv_i8
# | ...
# `---data was truncated (10240/99577) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a3a76815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560a3a7650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560a3a76889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde27f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde27f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde27f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde27f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a3a6fde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560a3a6fdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560a3a6e2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560a3a3920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560a3a391dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fde27f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde27f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde27f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a3a391cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c (783 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5ab2c715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e5ab2c40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e5ab2c789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0eb2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0eb258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0eb2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0eb251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5ab25ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e5ab25cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e5ab241b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e5aaef10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e5aaef0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0eb251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0eb251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0eb251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5aaef0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c (784 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_single_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, 1
# |   %5 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x bfloat> %5)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_single_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 2
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 3
# |   %9 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x4.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %7, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.single.x4.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_bf16_x2(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zm, align 16
# |   %zm2 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zdn1, ptr %zdn.addr, align 16
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %zm2, ptr %zm.addr, align 16
# |   %4 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn.addr, align 16
# |   %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1
# |   %7 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zm.addr, align 16
# |   %8 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %7, 0
# |   %9 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %7, 1
# |   %10 = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.x2.nxv8bf16(<vscale x 8 x bfloat> %5, <vscale x 8 x bfloat> %6, <vscale x 8 x bfloat> %8, <vscale x 8 x bfloat> %9)
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmul.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svmul_bf16_x4(<vscale x 8 x bfloat> %zdn.coerce0, <vscale x 8 x bfloat> %zdn.coerce1, <vscale x 8 x bfloat> %zdn.coerce2, <vscale x 8 x bfloat> %zdn.coerce3, <vscale x 8 x bfloat> %zm.coerce0, <vscale x 8 x bfloat> %zm.coerce1, <vscale x 8 x bfloat> %zm.coerce2, <vscale x 8 x bfloat> %zm.coerce3) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %zm.addr = alloca { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, align 16
# |   %0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %0, <vscale x 8 x bfloat> %zdn.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, <vscale x 8 x bfloat> %zdn.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %2, <vscale x 8 x bfloat> %zdn.coerce3, 3
# |   store { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %3, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> }, ptr %zdn, align 16
# |   %4 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } poison, <vscale x 8 x bfloat> %zm.coerce0, 0
# |   %5 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, <vscale x 8 x bfloat> %zm.coerce1, 1
# |   %6 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %5, <vscale x 8 x bfloat> %zm.coerce2, 2
# |   %7 = insertvalue { <v
# | ...
# `---data was truncated (10240/13687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055cc022b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cc022b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cc022b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f451a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f451a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f451a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f451a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc0224ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cc0224cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cc02231b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cc01ee10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cc01ee0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f451a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f451a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f451a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc01ee0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c (785 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsrl_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/98351) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592f439415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005592f43910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005592f439489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd35249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd352a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd35249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd35231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592f4329e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005592f4329c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005592f430eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005592f3fbe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005592f3fbddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdd35232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd352330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd352330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592f3fbdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c (786 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16  -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %4 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %5 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x bfloat>, align 16
# |   %__p2.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <8 x bfloat>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <8 x bfloat> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 16
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__p1.addr.i, align 16
# |   store <8 x bfloat> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbfdot.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %4 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %5 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_lane_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_810 = alloca <2 x float>, align 8
# |   %__s0_810 = alloca <2 x float>, align 8
# |   %__s1_810 = alloca <4 x bfloat>, align 8
# |   %__s2_810 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   %tmp2 = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0_810, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s1_810, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %2, ptr %__s2_810, align 8
# |   %3 = load <2 x float>, ptr %__s0_810, align 8
# |   %4 = load <4 x bfloat>, ptr %__s1_810, align 8
# |   %5 = load <2 x float>, ptr %__s2_810, align 8
# |   store <2 x float> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x float>
# |   %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer
# |   store <2 x float> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x float>, ptr %ref.tmp1, align 8
# |   store <2 x float> %8, ptr %__ret, align 8
# |   %9 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %9, ptr %tmp, align 8
# |   %10 = load <2 x float>, ptr %tmp, align 8
# |   store <2 x float> %10, ptr %ref.tmp, align 8
# |   %11 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <2 x float> %3, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %4, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %12 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %13 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %14 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %16, ptr %__ret_810, align 8
# |   %17 = load <2 x float>, ptr %__ret_810, align 8
# |   store <2 x float> %17, ptr %tmp2, align 8
# |   %18 = load <2 x float>, ptr %tmp2, align 8
# |   ret <2 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_laneq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x bfloat>, align 16
# |   %__p2.addr.i = alloca <8 x bfloat>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <8 x bfloat>, align 16
# |   %__ret_812 = alloca <4 x float>, align 16
# |   %__s0_812 = alloca <4 x float>, align 16
# |   %__s1_812 = alloca <8 x bfloat>, align 16
# |   %__s2_812 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <4 x float>, align 16
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <4 x float>, align 16
# |   %ref.tmp1 = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   %tmp2 = alloca <4 x float>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <8 x bfloat> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   store <4 x float> %0, ptr %__s0_812, align 16
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %1, ptr %__s1_812, align 16
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 16
# |   store <8 x bfloat> %2, ptr %__s2_812, align 16
# |   %3 = load <4 x float>, ptr %__s0_812, align 16
# |   %4 = load <8 x bfloat>, ptr %__s1_812, align 16
# |   %5 = load <4 x float>, ptr %__s2_812, align 16
# |   store <4 x float> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <4 x float>
# |   %lane = shufflevector <4 x float> %7, <4 x float> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x float> %lane, ptr %ref.tmp1, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp1, align 16
# |   store <4 x float> %8, ptr %__ret, align 16
# |   %9 = load <4 x float>, ptr %__ret, align 16
# |   store <4 x float> %9, ptr %tmp, align 16
# |   %10 = load <4 x float>, ptr %tmp, align 16
# |   store <4 x float> %10, ptr %ref.tmp, align 16
# |   %11 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <4 x float> %3, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %4, ptr %__p1.addr.i, align 16
# |   store <8 x bfloat> %11, ptr %__p2.addr.i, align 16
# |   %12 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %13 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %14 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbfdot.i = bitcast <16 x i8> %12 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %13 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %14 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 16
# |   %15 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %15, ptr %__ret.i, align 16
# |   %16 = load <4 x float>, ptr %__ret.i, align 16
# |   store <4 x float> %16, ptr %__ret_812, align 16
# |   %17 = load <4 x float>, ptr %__ret_812, align 16
# |   store <4 x float> %17, ptr %tmp2, align 16
# |   %18 = load <4 x float>, ptr %tmp2, align 16
# |   ret <4 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_laneq_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>,
# | ...
# `---data was truncated (10240/54685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055b7753e415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b7753e10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b7753e489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6828c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6828c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6828c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6828c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b775379e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b775379c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b77535eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b77500e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b77500ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6828c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6828c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6828c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b77500dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c (787 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/113039) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561788ada15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561788ad70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561788ada89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8cee049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8cee0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8cee049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8cee031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561788a6fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561788a6fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561788a54b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005617887040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561788703dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8cee032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8cee0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8cee0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561788703cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c (788 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabd_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64
# | ...
# `---data was truncated (10240/97248) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056147f99d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056147f99a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056147f99d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9ee333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9ee38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9ee333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9ee31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056147f932e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056147f932c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056147f917b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056147f5c70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056147f5c6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd9ee31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9ee31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9ee31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056147f5c6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c (789 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564fa088415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564fa08810f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564fa088489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc311c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc311ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc311c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc311c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564fa0819e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564fa0819c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564fa07feb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564fa04ae0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564fa04addd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc311c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc311c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc311c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564fa04adcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c (790 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577e0fb615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005577e0fb30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005577e0fb689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff72b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff72b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff72b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff72b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577e0f4be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005577e0f4bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005577e0f30b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005577e0be00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005577e0bdfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007eff72b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff72b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff72b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577e0bdfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c (791 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f51b36b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f51b3680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f51b36b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f72249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f722a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f72249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f72231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f51b300e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f51b300c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f51b2e5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f51af950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f51af94dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6f72232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f722330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f722330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f51af94cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c (792 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsne_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/171389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c2129515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564c212920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564c2129589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac13133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac1318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac13133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac1311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c2122ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564c2122ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564c2120fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564c20ebf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564c20ebedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fac1311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac1311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac1311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c20ebecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c (793 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 
# | ...
# `---data was truncated (10240/215949) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561444b1915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561444b160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561444b1989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe233b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe233b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe233b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe233b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561444aaee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561444aaec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561444a93b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005614447430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561444742dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe233b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe233b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe233b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561444742cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c (794 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsleu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsleu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsleu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565330dca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000565330dc70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000565330dca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c5f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c5f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c5f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c5f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565330d5fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565330d5fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565330d44b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005653309f40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005653309f3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7c5f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c5f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c5f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653309f3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm64-lanes.c (795 of 27911)
******************** TEST 'Clang :: CodeGen/arm64-lanes.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind
# | define i8 @test_vdupb_lane_s8(<8 x i8> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %src, ptr %src.addr, align 8
# |   %0 = load <8 x i8>, ptr %src.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 2
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i8 @test_vdupb_lane_u8(<8 x i8> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %src, ptr %src.addr, align 8
# |   %0 = load <8 x i8>, ptr %src.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 2
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i16 @test_vduph_lane_s16(<4 x i16> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %src, ptr %src.addr, align 8
# |   %0 = load <4 x i16>, ptr %src.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 2
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i16 @test_vduph_lane_u16(<4 x i16> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %src, ptr %src.addr, align 8
# |   %0 = load <4 x i16>, ptr %src.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 2
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_vdups_lane_s32(<2 x i32> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %src, ptr %src.addr, align 8
# |   %0 = load <2 x i32>, ptr %src.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_vdups_lane_u32(<2 x i32> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %src, ptr %src.addr, align 8
# |   %0 = load <2 x i32>, ptr %src.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define float @test_vdups_lane_f32(<2 x float> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   store <2 x float> %src, ptr %src.addr, align 8
# |   %0 = load <2 x float>, ptr %src.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <2 x float>, ptr %__s0, align 8
# |   %vdups_lane = extractelement <2 x float> %1, i32 0
# |   store float %vdups_lane, ptr %ref.tmp, align 4
# |   %2 = load float, ptr %ref.tmp, align 4
# |   store float %2, ptr %__ret, align 4
# |   %3 = load float, ptr %__ret, align 4
# |   store float %3, ptr %tmp, align 4
# |   %4 = load float, ptr %tmp, align 4
# |   ret float %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i64 @test_vdupd_lane_s64(<1 x i64> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <1 x i64> %src, ptr %src.addr, align 8
# |   %0 = load <1 x i64>, ptr %src.addr, align 8
# |   store <1 x i64> %0, ptr %__s0, align 8
# |   %1 = load <1 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x i64> %1, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i64 @test_vdupd_lane_u64(<1 x i64> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <1 x i64> %src, ptr %src.addr, align 8
# |   %0 = load <1 x i64>, ptr %src.addr, align 8
# |   store <1 x i64> %0, ptr %__s0, align 8
# |   %1 = load <1 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x i64> %1, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define double @test_vdupd_lane_f64(<1 x double> noundef %src) #0 {
# | entry:
# |   %src.addr = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store <1 x double> %src, ptr %src.addr, align 8
# |   %0 = load <1 x double>, ptr %src.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %__s0, align 8
# |   %vdupd_lane = extractelement <1 x double> %1, i32 0
# |   store double %vdupd_lane, ptr %ref.tmp, align 8
# |   %2 = load double, ptr %ref.tmp, align 8
# |   store double %2, ptr %__ret, align 8
# |   %3 = load double, ptr %__ret, align 8
# |   store double %3, ptr %tmp, align 8
# |   %4 = load double, ptr %tmp, align 8
# |   ret double %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055574c93415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055574c9310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055574c93489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab8ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab8ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab8ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab8ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055574c8c9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055574c8c9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055574c8aeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055574c55e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055574c55ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fab8ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab8ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab8ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055574c55dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c (796 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d97cd5a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d97cd570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d97cd5a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa402449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4024a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa402449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa402431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d97ccefe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d97ccefc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d97ccd4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d97c9840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d97c983dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa402432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4024330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4024330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d97c983cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c (797 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, a
# | ...
# `---data was truncated (10240/81515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b30bc415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556b30bc10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556b30bc489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feaf9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feaf9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feaf9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feaf9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b30b59e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556b30b59c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556b30b3eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556b307ee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556b307eddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feaf9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feaf9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feaf9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b307edcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c (798 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7874fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e7874fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e7874fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7022733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f702278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7022733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f702271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e787492e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e787492c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e787477b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e7871270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e787126dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f702271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f702271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f702271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e787126cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c (799 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_s16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_u16_u32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_qcvtn_u16_s32_x2(<vscale x 4 x i32> %zn.coerce0, <vscale x 4 x i32> %zn.coerce1) #0 {
# | entry:
# |   %zn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zn, align 16
# |   %zn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zn1, ptr %zn.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtun.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtun.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005584da1ba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005584da1b70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005584da1ba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d6cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d6cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d6cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d6cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584da14fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005584da14fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005584da134b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005584d9de40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005584d9de3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2d6cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d6cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d6cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584d9de3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c (800 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale 
# | ...
# `---data was truncated (10240/79853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1afd5f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d1afd5c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d1afd5f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae34049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae340a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae34049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae34031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1afcf4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d1afcf4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d1afcd9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d1af9890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d1af988dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fae34032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae340330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae340330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1af988cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c (801 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = loa
# | ...
# `---data was truncated (10240/33443) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f1e6f115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562f1e6ee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562f1e6f189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae53c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae53ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae53c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae53c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f1e686e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562f1e686c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562f1e66bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562f1e31b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562f1e31add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fae53c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae53c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae53c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f1e31acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c (802 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c309bbe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c309bbb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c309bbe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6915733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f691578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6915733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f691571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c309b53e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c309b53c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c309b38b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c3097e80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c3097e7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f691571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f691571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f691571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3097e7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c (803 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd67b9015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cd67b8d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cd67b9089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe073249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0732a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe073249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe073231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd67b25e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cd67b25c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cd67b0ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cd677ba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cd677b9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe073232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0732330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0732330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd677b9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c (804 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_ext_v_f16mf4_f16mf2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf4_f16m1(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf4_f16m2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf4_f16m4(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf4_f16m8(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf2_f16m1(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf2_f16m2(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf2_f16m4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf2_f16m8(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16m1_f16m2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m1_f16m4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m1_f16m8(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m2_f16m4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m2_f16m8(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline n
# | ...
# `---data was truncated (10240/83088) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ebd078715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ebd07840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ebd078789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac5b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac5b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac5b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac5b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebd071ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ebd071cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ebd0701b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ebd03b10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ebd03b0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fac5b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac5b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac5b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebd03b0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c (805 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/223367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056023530015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005602352fd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056023530089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa1d4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1d44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa1d4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa1d4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560235295e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560235295c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056023527ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560234f2a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560234f29dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa1d4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1d44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1d44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560234f29cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c (806 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vect
# | ...
# `---data was truncated (10240/113765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055926476115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055926475e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055926476189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efcd7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efcd74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efcd7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efcd7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592646f6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005592646f6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005592646dbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055926438b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055926438add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efcd7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efcd74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efcd74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055926438acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c (807 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056314a79b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056314a7980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056314a79b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f170c01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f170c0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f170c01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f170c003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056314a730e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056314a730c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056314a715b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056314a3c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056314a3c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f170c004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f170c0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f170c0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056314a3c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c (808 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale 
# | ...
# `---data was truncated (10240/179177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056535c62a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056535c6270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056535c62a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33bec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33bec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33bec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33bec03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056535c5bfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056535c5bfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056535c5a4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056535c2540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056535c253dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f33bec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33bec050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33bec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056535c253cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c (809 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret voi
# | ...
# `---data was truncated (10240/102304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4c637415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d4c63710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d4c637489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb3db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb3db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb3db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb3db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4c6309e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d4c6309c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d4c62eeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d4c5f9e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d4c5f9ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdb3db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb3db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb3db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4c5f9dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/poly128.c (810 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/poly128.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon  -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vldrq_p128(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %__ret = alloca i128, align 16
# |   %ref.tmp = alloca i128, align 16
# |   %tmp = alloca i128, align 16
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i128, ptr %0, align 16
# |   store i128 %1, ptr %ref.tmp, align 16
# |   %2 = load i128, ptr %ref.tmp, align 16
# |   store i128 %2, ptr %__ret, align 16
# |   %3 = load i128, ptr %__ret, align 16
# |   store i128 %3, ptr %tmp, align 16
# |   %4 = load i128, ptr %tmp, align 16
# |   ret i128 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_ld_st_p128(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %__s1 = alloca i128, align 16
# |   %__ret = alloca i128, align 16
# |   %ref.tmp = alloca i128, align 16
# |   %tmp = alloca i128, align 16
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i128, ptr %0, align 16
# |   store i128 %1, ptr %ref.tmp, align 16
# |   %2 = load i128, ptr %ref.tmp, align 16
# |   store i128 %2, ptr %__ret, align 16
# |   %3 = load i128, ptr %__ret, align 16
# |   store i128 %3, ptr %tmp, align 16
# |   %4 = load i128, ptr %tmp, align 16
# |   store i128 %4, ptr %__s1, align 16
# |   %5 = load ptr, ptr %ptr.addr, align 8
# |   %add.ptr = getelementptr inbounds i128, ptr %5, i64 1
# |   %6 = load i128, ptr %__s1, align 16
# |   store i128 %6, ptr %add.ptr, align 16
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vmull_p64(i64 noundef %a, i64 noundef %b) #1 {
# | entry:
# |   %__p0.addr.i = alloca i64, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca i128, align 16
# |   %ref.tmp.i = alloca i128, align 16
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__p0.addr.i, align 8
# |   store i64 %1, ptr %__p1.addr.i, align 8
# |   %2 = load i64, ptr %__p0.addr.i, align 8
# |   %3 = load i64, ptr %__p1.addr.i, align 8
# |   %vmull_p64.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %2, i64 %3)
# |   %vmull_p641.i = bitcast <16 x i8> %vmull_p64.i to i128
# |   store i128 %vmull_p641.i, ptr %ref.tmp.i, align 16
# |   %4 = load i128, ptr %ref.tmp.i, align 16
# |   store i128 %4, ptr %__ret.i, align 16
# |   %5 = load i128, ptr %__ret.i, align 16
# |   ret i128 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vmull_high_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
# | entry:
# |   %__p0.addr.i3 = alloca <2 x i64>, align 16
# |   %__ret.i4 = alloca <1 x i64>, align 8
# |   %__p0.addr.i1 = alloca <2 x i64>, align 16
# |   %__ret.i2 = alloca <1 x i64>, align 8
# |   %__p0.addr.i.i = alloca i64, align 8
# |   %__p1.addr.i.i = alloca i64, align 8
# |   %__ret.i.i = alloca i128, align 16
# |   %ref.tmp.i.i = alloca i128, align 16
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %ref.tmp.i = alloca <1 x i64>, align 8
# |   %ref.tmp1.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %2, ptr %__p0.addr.i3, align 16
# |   %3 = load <2 x i64>, ptr %__p0.addr.i3, align 16
# |   %4 = load <2 x i64>, ptr %__p0.addr.i3, align 16
# |   %shuffle.i5 = shufflevector <2 x i64> %3, <2 x i64> %4, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i5, ptr %__ret.i4, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i4, align 8
# |   store <1 x i64> %5, ptr %ref.tmp.i, align 8
# |   %6 = load i64, ptr %ref.tmp.i, align 8
# |   %7 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   store <2 x i64> %7, ptr %__p0.addr.i1, align 16
# |   %8 = load <2 x i64>, ptr %__p0.addr.i1, align 16
# |   %9 = load <2 x i64>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <2 x i64> %8, <2 x i64> %9, <1 x i32> <i32 1>
# |   store <1 x i64> %shuffle.i, ptr %__ret.i2, align 8
# |   %10 = load <1 x i64>, ptr %__ret.i2, align 8
# |   store <1 x i64> %10, ptr %ref.tmp1.i, align 8
# |   %11 = load i64, ptr %ref.tmp1.i, align 8
# |   store i64 %6, ptr %__p0.addr.i.i, align 8
# |   store i64 %11, ptr %__p1.addr.i.i, align 8
# |   %12 = load i64, ptr %__p0.addr.i.i, align 8
# |   %13 = load i64, ptr %__p1.addr.i.i, align 8
# |   %vmull_p64.i.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %12, i64 %13)
# |   %vmull_p641.i.i = bitcast <16 x i8> %vmull_p64.i.i to i128
# |   store i128 %vmull_p641.i.i, ptr %ref.tmp.i.i, align 16
# |   %14 = load i128, ptr %ref.tmp.i.i, align 16
# |   store i128 %14, ptr %__ret.i.i, align 16
# |   %15 = load i128, ptr %__ret.i.i, align 16
# |   store i128 %15, ptr %__ret.i, align 16
# |   %16 = load i128, ptr %__ret.i, align 16
# |   ret i128 %16
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %a.ad
# | ...
# `---data was truncated (10240/19795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000557fc43d315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557fc43d00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557fc43d389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1739049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17390a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1739049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1739031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fc4368e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557fc4368c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557fc434db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557fc3ffd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557fc3ffcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1739032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17390330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17390330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fc3ffccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c (811 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e9db9e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562e9db9b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562e9db9e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f641c61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f641c6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f641c61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f641c603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e9db33e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562e9db33c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562e9db18b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562e9d7c80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562e9d7c7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f641c604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f641c6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f641c6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e9d7c7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c (812 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055792be7a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055792be770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055792be7a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9894933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f989498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9894933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f989491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055792be0fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055792be0fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055792bdf4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055792baa40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055792baa3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f989491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f989491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f989491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055792baa3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c (813 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 
# | ...
# `---data was truncated (10240/51193) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557a161015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005557a160d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005557a161089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe470b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe470b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe470b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe470b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557a15a5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005557a15a5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005557a158ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005557a123a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005557a1239dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe470b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe470b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe470b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557a1239cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c (814 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1   -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(<vscale x 16 x i8> %0, i32 0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(<vscale x 16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(<vscale x 16 x i8> %0, i32 0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(<vscale x 8 x i16> %0, i32 0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(<vscale x 8 x i16>, i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(<vscale x 8 x i16> %0, i32 1)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(<vscale x 4 x i32> %0, i32 0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(<vscale x 4 x i32>, i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(<vscale x 4 x i32> %0, i32 3)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_u64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(<vscale x 2 x i64> %0, i32 0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(<vscale x 2 x i64>, i32 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_lane_s64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(<vscale x 2 x i64> %0, i32 7)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8(<vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_s8(<vscale x 16 x i8> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8(<vscale x 16 x i8> %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16(<vscale x 8 x i16> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16(<vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_s16(<vscale x 8 x i16> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16(<vscale x 8 x i16> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32(<vscale x 4 x i32> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32(<vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_s32(<vscale x 4 x i32> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32(<vscale x 4 x i32> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svpmov_u64(<vscale x 2 x i64> %zn) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv2i64(<vscale x 2 x i64> %0)
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv2i64(<vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x
# | ...
# `---data was truncated (10240/11356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005559ed0bc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005559ed0b90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005559ed0bc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe341c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe341ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe341c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe341c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559ed051e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005559ed051c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005559ed036b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005559ecce60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005559ecce5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe341c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe341c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe341c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559ecce5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c (815 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005565efbf715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005565efbf40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005565efbf789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd179b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd179b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd179b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd179aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565efb8ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005565efb8cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005565efb71b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005565ef8210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005565ef820dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd179aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd179aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd179aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565ef820cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c (816 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561dac41415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561dac4110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561dac41489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b47d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b47d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b47d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b47d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561dac3a9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561dac3a9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561dac38eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561dac03e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561dac03ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6b47d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b47d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b47d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561dac03dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGenHIP/offload-pgo-sections.hip (817 of 27911)
******************** TEST 'Clang :: CodeGenHIP/offload-pgo-sections.hip' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -cuid=abc    -fprofile-instrument=clang -emit-llvm -o - -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -cuid=abc -fprofile-instrument=clang -emit-llvm -o - -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip"
# | target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p10:32:32-p11:32:32-p12:32:32-p13:32:32-p14:32:32-p15:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
# | target triple = "amdgpu-amd-amdhsa"
# | 
# | $__profc__Z6helperi = comdat any
# | 
# | $__llvm_prf_unifcnt__Z6helperi = comdat any
# | 
# | $__profc__Z6kernelPi = comdat any
# | 
# | $__llvm_prf_unifcnt__Z6kernelPi = comdat any
# | 
# | @__hip_cuid_b04fd23c98500190 = addrspace(1) global i8 0
# | @__profc__Z6helperi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", comdat, align 8
# | @__llvm_prf_unifcnt__Z6helperi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_ucnts", comdat, align 8
# | @__profd__Z6helperi = linkonce_odr protected addrspace(1) global { i64, i64, i64, i64, i64, ptr, ptr, i32, [3 x i16], i16, i32 } { i64 6265860958107916728, i64 24, i64 sub (i64 ptrtoint (ptr addrspace(1) @__profc__Z6helperi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6helperi to i64)), i64 sub (i64 ptrtoint (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6helperi to i64)), i64 0, ptr null, ptr null, i32 1, [3 x i16] zeroinitializer, i16 0, i32 0 }, section "__llvm_prf_data", comdat($__profc__Z6helperi), align 8
# | @__profc__Z6kernelPi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", comdat, align 8
# | @__llvm_prf_unifcnt__Z6kernelPi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_ucnts", comdat, align 8
# | @__profd__Z6kernelPi = linkonce_odr protected addrspace(1) global { i64, i64, i64, i64, i64, ptr, ptr, i32, [3 x i16], i16, i32 } { i64 4905896731224577586, i64 0, i64 sub (i64 ptrtoint (ptr addrspace(1) @__profc__Z6kernelPi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6kernelPi to i64)), i64 sub (i64 ptrtoint (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6kernelPi to i64)), i64 0, ptr null, ptr null, i32 1, [3 x i16] zeroinitializer, i16 0, i32 0 }, section "__llvm_prf_data", comdat($__profc__Z6kernelPi), align 8
# | @__llvm_prf_nm_b04fd23c98500190 = protected addrspace(1) constant [32 x i8] c"\16\1Ex\DA\8B\8F2\CBH\CD)H-\CAd\8C\8F2\CBN-\CAK\CD\09\C8\04\00Z\AD\08\03", section "__llvm_prf_names", align 1
# | @__start___llvm_prf_names = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_names = external hidden addrspace(1) global i8
# | @__start___llvm_prf_cnts = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_cnts = external hidden addrspace(1) global i8
# | @__start___llvm_prf_data = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_data = external hidden addrspace(1) global i8
# | @__start___llvm_prf_ucnts = external hidden addrspace(1) global i8
# | @__stop___llvm_prf_ucnts = external hidden addrspace(1) global i8
# | @__llvm_profile_raw_version = external addrspace(1) constant i64
# | @__llvm_profile_sections_b04fd23c98500190 = protected addrspace(1) constant { ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1) } { ptr addrspace(1) @__start___llvm_prf_names, ptr addrspace(1) @__stop___llvm_prf_names, ptr addrspace(1) @__start___llvm_prf_cnts, ptr addrspace(1) @__stop___llvm_prf_cnts, ptr addrspace(1) @__start___llvm_prf_data, ptr addrspace(1) @__stop___llvm_prf_data, ptr addrspace(1) @__start___llvm_prf_ucnts, ptr addrspace(1) @__stop___llvm_prf_ucnts, ptr addrspace(1) @__llvm_profile_raw_version }
# | @llvm.compiler.used = appending addrspace(1) global [6 x ptr] [ptr addrspacecast (ptr addrspace(1) @__hip_cuid_b04fd23c98500190 to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__profd__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__profd__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_profile_sections_b04fd23c98500190 to ptr)], section "llvm.metadata"
# | @llvm.used = appending addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @__llvm_prf_nm_b04fd23c98500190 to ptr)], section "llvm.metadata"
# | 
# | ; Function Attrs: convergent mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z6helperi(i32 noundef %x) #0 {
# | entry:
# |   %0 = call i32 @llvm.amdgcn.wavefrontsize()
# |   %wavesize.i16 = trunc i32 %0 to i16
# |   store i16 %wavesize.i16, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @__profd__Z6helperi, i64 66), align 2
# |   %pgo.sampled = call i32 @__llvm_profile_sampling_gpu(i32 3)
# |   %pgo.matched = icmp ne i32 %pgo.sampled, 0
# |   %x.addr = alloca i32, align 4, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store i32 %x, ptr %x.addr.ascast, align 4
# |   br i1 %pgo.matched, label %po_then, label %po_cont
# | 
# | po_cont:                                          ; preds = %po_then, %entry
# |   %1 = load i32, ptr %x.addr.ascast, align 4
# |   %add = add nsw i32 %1, 1
# |   ret i32 %add
# | 
# | po_then:                                          ; preds = %entry
# |   call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) @__profc__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to ptr), i64 1)
# |   br label %po_cont
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.instrprof.increment(ptr, i64, i32, i32) #1
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind optnone
# | define dso_local amdgpu_kernel void @_Z6kernelPi(ptr addrspace(1) noundef %p.coerce) #2 {
# | entry:
# |   %0 = call i32 @llvm.amdgcn.wavefrontsize()
# |   %wavesize.i16 = trunc i32 %0 to i16
# |   store i16 %wavesize.i16, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @__profd__Z6kernelPi, i64 66), align 2
# |   %pgo.sampled = call i32 @__llvm_profile_sampling_gpu(i32 3)
# |   %pgo.matched = icmp ne i32 %pgo.sampled, 0
# |   %p = alloca ptr, align 8, addrspace(5)
# |   %p.addr = alloca ptr, align 8, addrspace(5)
# |   %p.addr.ascast = addrspacecast ptr addrspace(5) %p.addr to ptr
# |   store ptr addrspace(1) %p.coerce, ptr addrspace(5) %p, align 8
# |   %p1 = load ptr, ptr addrspace(5) %p, align 8
# |   store ptr %p1, ptr %p.addr.ascast, align 8
# |   br i1 %pgo.matched, label %po_then, label %po_cont
# | 
# | po_cont:                                          ; preds = %po_then, %entry
# |   %1 = load ptr, ptr %p.addr.ascast, align 8
# |   %2 = load i32, ptr %1, align 4
# |   %call = call noundef i32 @_Z6helperi(i32 noundef %2) #4
# |   %3 = load ptr, ptr %p.addr.ascast, align 8
# |   store i32 %call, ptr %3, align 4
# |   ret void
# | 
# | po_then:                                          ; preds = %entry
# |   call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) @__profc__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to ptr), i64 1)
# |   br label %po_cont
# | }
# | 
# | declare i32 @__llvm_profile_sampling_gpu(i32)
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare noundef range(i32 32, 65) i32 @llvm.amdgcn.wavefrontsize() #3
# | 
# | declare void @__llvm_profile_instrument_gpu(ptr, ptr, i64)
# | 
# | attributes #0 = { convergent mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #1 = { nounwind }
# | attributes #2 = { convergent mustprogress noinline norecurse nounwind optnone "amdgpu-flat-work-group-size"="1,1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #4 = { convergent nounwind "uniform-work-group-size" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 2, !"EnableValueProfiling", i32 0}
# | !1 = !{i32 1, !"amdhsa_code_object_version", i32 600}
# | !2 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S
# |  #0 0x00005595e243315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005595e24300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005595e243389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f807e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f807e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f807e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f807e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595e23c8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005595e23c8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005595e23adb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005595e205d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005595e205cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f807e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f807e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f807e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595e205ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c (818 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align
# | ...
# `---data was truncated (10240/47596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056322062715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005632206240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056322062789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e5ba1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e5ba725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e5ba1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e5ba03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632205bce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005632205bcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005632205a1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005632202510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563220250dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7e5ba04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e5ba050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e5ba050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563220250cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c (819 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/136005) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c02152f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c02152c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c02152f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6863649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68636a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6863649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6863631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0214c4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c0214c4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c0214a9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c0211590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c021158dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6863632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68636330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68636330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c021158cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c (820 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed9f2f915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ed9f2f60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ed9f2f989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd57eb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd57eb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd57eb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd57eaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed9f28ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ed9f28ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ed9f273b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ed9ef230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ed9ef22dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd57eaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd57eaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd57eaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed9ef22cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c (821 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmerge_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/124506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561429d5615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561429d530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561429d5689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57db333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57db38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57db333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57db31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561429cebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561429cebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561429cd0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005614299800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056142997fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f57db31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57db31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57db31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056142997fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrnd.c (822 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrnd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndaq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.round.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.round.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndaq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.round.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.round.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndmq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.floor.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.floor.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.floor.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.floor.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndpq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.ceil.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.ceil.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndpq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.ceil.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.trunc.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.trunc.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.trunc.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.trunc.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndxq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.rint.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.rint.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndxq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.rint.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.rint.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndnq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.roundeven.v8f16(<8 x half> %0)
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.roundeven.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %0)
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.roundeven.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndaq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half> %0, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndaq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = call <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float> %0, <4 x i1> %3, <4 x float> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half> %0, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1
# | ...
# `---data was truncated (10240/26476) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1cd31d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e1cd31a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e1cd31d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa29b505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa29b55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa29b505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa29b4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1cd2b2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e1cd2b2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e1cd297b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e1ccf470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e1ccf46dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa29b4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa29b4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa29b4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1ccf46cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c (823 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcopy_lane_bf16_v1(<4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_322 = alloca <4 x bfloat>, align 8
# |   %__s0_322 = alloca <4 x bfloat>, align 8
# |   %__s2_322 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp3 = alloca <4 x bfloat>, align 8
# |   %tmp4 = alloca <4 x bfloat>, align 8
# |   %tmp5 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_322, align 8
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_322, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_322, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 3
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <4 x bfloat>, ptr %__s0_322, align 8
# |   store <4 x bfloat> %7, ptr %__s1, align 8
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <4 x bfloat>, ptr %__s1, align 8
# |   %vset_lane = insertelement <4 x bfloat> %9, bfloat %8, i32 1
# |   store <4 x bfloat> %vset_lane, ptr %ref.tmp3, align 8
# |   %10 = load <4 x bfloat>, ptr %ref.tmp3, align 8
# |   store <4 x bfloat> %10, ptr %__ret, align 8
# |   %11 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %11, ptr %tmp4, align 8
# |   %12 = load <4 x bfloat>, ptr %tmp4, align 8
# |   store <4 x bfloat> %12, ptr %__ret_322, align 8
# |   %13 = load <4 x bfloat>, ptr %__ret_322, align 8
# |   store <4 x bfloat> %13, ptr %tmp5, align 8
# |   %14 = load <4 x bfloat>, ptr %tmp5, align 8
# |   ret <4 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcopy_lane_bf16_v2(<4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_322 = alloca <4 x bfloat>, align 8
# |   %__s0_322 = alloca <4 x bfloat>, align 8
# |   %__s2_322 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp3 = alloca <4 x bfloat>, align 8
# |   %tmp4 = alloca <4 x bfloat>, align 8
# |   %tmp5 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_322, align 8
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_322, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_322, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 0
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <4 x bfloat>, ptr %__s0_322, align 8
# |   store <4 x bfloat> %7, ptr %__s1, align 8
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <4 x bfloat>, ptr %__s1, align 8
# |   %vset_lane = insertelement <4 x bfloat> %9, bfloat %8, i32 2
# |   store <4 x bfloat> %vset_lane, ptr %ref.tmp3, align 8
# |   %10 = load <4 x bfloat>, ptr %ref.tmp3, align 8
# |   store <4 x bfloat> %10, ptr %__ret, align 8
# |   %11 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %11, ptr %tmp4, align 8
# |   %12 = load <4 x bfloat>, ptr %tmp4, align 8
# |   store <4 x bfloat> %12, ptr %__ret_322, align 8
# |   %13 = load <4 x bfloat>, ptr %__ret_322, align 8
# |   store <4 x bfloat> %13, ptr %tmp5, align 8
# |   %14 = load <4 x bfloat>, ptr %tmp5, align 8
# |   ret <4 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcopyq_lane_bf16_v1(<8 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_298 = alloca <8 x bfloat>, align 16
# |   %__s0_298 = alloca <8 x bfloat>, align 16
# |   %__s2_298 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <8 x bfloat>, align 16
# |   %ref.tmp3 = alloca <8 x bfloat>, align 16
# |   %tmp4 = alloca <8 x bfloat>, align 16
# |   %tmp5 = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_298, align 16
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_298, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_298, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 2
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <8 x bfloat>, ptr %__s0_298, align 16
# |   store <8 x bfloat> %7, ptr %__s1, align 16
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <8 x bfloat>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x bfloat> %9, bfloat %8, i32 0
# |   store <8 x bfloat> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x bfloat>, ptr %ref.tmp3, align 16
# |   store <8 x bfloat> %10, ptr %__ret, align 16
# |   %11 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %11, ptr %tmp4, align 16
# |   %12 = load <8 x bfloat>, ptr %tmp4, align 16
# |   store <8 x bfloat> %12, ptr %__ret_298, align 16
# |   %13 = load <8 x bfloat>, ptr %__ret_298, align 16
# |   store <8 x bfloat> %13, ptr %tmp5, align 16
# |   %14 = load <8 x bfloat>, ptr %tmp5, align 16
# |   ret <8 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcopyq_lane_bf16_v2(<8 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x bfloat>, align 16
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_298 = alloca <8 x bfloat>, align 16
# |   %__s0_298 = alloca <8 x bfloat>, align 16
# |   %__s2_298 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <8 x bfloat>, align 16
# |   %ref.tmp3 = alloca <8 x bfloat>, align 16
# |   %tmp4 = alloca <8 x bfloat>, align 16
# |   %tmp5 = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %a, ptr %a.addr, align 16
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <8 x bfloat>, ptr %a.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_298, align 16
# |   %1 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s2_298, align 8
# |   %2 = load <4 x bfloat>, ptr %__s2_298, align 8
# |   store <4 x bfloat> %2, ptr %__s02, align 8
# |   %3 = load <4 x bfloat>, ptr %__s02, align 8
# |   %vget_lane = extractelement <4 x bfloat> %3, i32 0
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %4 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %4, ptr %__ret1, align 2
# |   %5 = load bfloat, ptr %__ret1, align 2
# |   store bfloat %5, ptr %tmp, align 2
# |   %6 = load bfloat, ptr %tmp, align 2
# |   store bfloat %6, ptr %__s0, align 2
# |   %7 = load <8 x bfloat>, ptr %__s0_298, align 16
# |   store <8 x bfloat> %7, ptr %__s1, align 16
# |   %8 = load bfloat, ptr %__s0, align 2
# |   %9 = load <8 x bfloat>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x bfloat> %9, bfloat %8, i32 6
# |   store <8 x bfloat> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x bfloat>, ptr %ref.tmp3, align 16
# |   store <8 x bfloat> %10, ptr %__ret, align 16
# |   %11 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %11, ptr %tmp4, align 16
# |   %12 = load <8 x bfloat>, ptr %tmp4, align 16
# |   store <8 x bfloat> %12, ptr %__ret_298, align 16
# |   %13 = load <8 x bfloat>, ptr %__ret_298, align 16
# |   store <8 x bfloat> %13, ptr %tmp5, align 16
# |   %14 = load <8 x bfloat>, ptr %tmp5, align 16
# |   ret <8 x bfloat> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcopy_laneq_bf16_v1(<4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 16
# |   %__ret_374 = alloca <4 x bfloat>, align 8
# |   %__s0_374 = alloca <4 x bfloat>, align 8
# |   %__s2_374 = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__ret1 = alloca bfloat, align 2
# |   %__s02 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp3 = alloca <4 x bfloat>, align 8
# |   %tmp4 = alloca <4 x bfloat>, align 8
# |   %tmp5 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <8 x bfloat> %b, ptr %b.add
# | ...
# `---data was truncated (10240/18871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e98777315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e9877700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e98777389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8cae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8caea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8cae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8cae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e987708e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e987708c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e9876edb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e98739d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e98739cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd8cae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8cae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8cae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e98739ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c (824 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9ea4d315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d9ea4d00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d9ea4d389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7daa849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7daa8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7daa849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7daa831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9ea468e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d9ea468c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d9ea44db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d9ea0fd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d9ea0fcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7daa832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7daa8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7daa8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9ea0fccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c (825 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i
# | ...
# `---data was truncated (10240/25624) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff63abb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ff63ab80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ff63abb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f1e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f1e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f1e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f1e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff63a50e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ff63a50c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ff63a35b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ff636e50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ff636e4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0f1e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f1e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f1e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff636e4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c (826 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e93519615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e9351930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e93519689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f757e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f757e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f757e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f757e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e93512be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e93512bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e935110b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e934dc00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e934dbfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f757e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f757e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f757e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e934dbfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c (827 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580e799915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005580e79960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005580e799989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8dd9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8dd998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8dd9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8dd991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580e792ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005580e792ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005580e7913b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005580e75c30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005580e75c2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8dd991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8dd991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8dd991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580e75c2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c (828 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv
# | ...
# `---data was truncated (10240/20082) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648df4ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005648df4a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005648df4ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d76133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d7618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d76133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d7611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648df440e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005648df440c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005648df425b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005648df0d50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005648df0d4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3d7611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d7611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d7611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648df0d4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu (829 of 27911)
******************** TEST 'Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple spirv64-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK-SPIRV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple spirv64-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK-SPIRV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
# RUN: at line 7
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -disable-O0-optnone -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -disable-O0-optnone -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu"
# | target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p10:32:32-p11:32:32-p12:32:32-p13:32:32-p14:32:32-p15:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
# | target triple = "amdgpu-amd-amdhsa"
# | 
# | %struct.S = type { ptr, ptr }
# | %struct.T = type { [2 x ptr] }
# | %struct.SS = type { ptr }
# | 
# | @__hip_cuid_ = addrspace(1) global i8 0
# | @llvm.compiler.used = appending addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @__hip_cuid_ to ptr)], section "llvm.metadata"
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel1Pi(ptr addrspace(1) noundef %x.coerce) #0 {
# | entry:
# |   %x = alloca ptr, align 8, addrspace(5)
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8
# |   %x1 = load ptr, ptr addrspace(5) %x, align 8
# |   store ptr %x1, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %0, i64 0
# |   %1 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel2Ri(ptr addrspace(1) noundef nonnull align 4 dereferenceable(4) %x.coerce) #0 {
# | entry:
# |   %x = alloca ptr, align 8, addrspace(5)
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8
# |   %x1 = load ptr, ptr addrspace(5) %x, align 8
# |   store ptr %x1, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8, !nonnull !3, !align !4
# |   %1 = load i32, ptr %0, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %0, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel3PU3AS2iPU3AS1i(ptr addrspace(2) noundef %x, ptr addrspace(1) noundef %y) #0 {
# | entry:
# |   %x.addr = alloca ptr addrspace(2), align 8, addrspace(5)
# |   %y.addr = alloca ptr addrspace(1), align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   %y.addr.ascast = addrspacecast ptr addrspace(5) %y.addr to ptr
# |   store ptr addrspace(2) %x, ptr %x.addr.ascast, align 8
# |   store ptr addrspace(1) %y, ptr %y.addr.ascast, align 8
# |   %0 = load ptr addrspace(2), ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr addrspace(2) %0, i64 0
# |   %1 = load i32, ptr addrspace(2) %arrayidx, align 4
# |   %2 = load ptr addrspace(1), ptr %y.addr.ascast, align 8
# |   %arrayidx1 = getelementptr inbounds i32, ptr addrspace(1) %2, i64 0
# |   store i32 %1, ptr addrspace(1) %arrayidx1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline nounwind
# | define dso_local void @_Z4funcPi(ptr noundef %x) #1 {
# | entry:
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr %x, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %0, i64 0
# |   %1 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel41S(ptr addrspace(4) noundef byref(%struct.S) align 8 %0) #0 {
# | entry:
# |   %s = alloca %struct.S, align 8, addrspace(5)
# |   call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 8 %s, ptr addrspace(4) align 8 %0, i64 16, i1 false)
# |   %s.ascast = addrspacecast ptr addrspace(5) %s to ptr
# |   %x = getelementptr inbounds nuw %struct.S, ptr %s.ascast, i32 0, i32 0
# |   %1 = load ptr, ptr %x, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %1, i64 0
# |   %2 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   %y = getelementptr inbounds nuw %struct.S, ptr %s.ascast, i32 0, i32 1
# |   %3 = load ptr, ptr %y, align 8
# |   %arrayidx1 = getelementptr inbounds float, ptr %3, i64 0
# |   %4 = load float, ptr %arrayidx1, align 4
# |   %add = fadd contract float %4, 1.000000e+00
# |   store float %add, ptr %arrayidx1, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) noalias writeonly captures(none), ptr addrspace(4) noalias readonly captures(none), i64, i1 immarg) #2
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel5P1S(ptr addrspace(1) noundef %s.coerce) #0 {
# | entry:
# |   %s = alloca ptr, align 8, addrspace(5)
# |   %s.addr = alloca ptr, align 8, addrspace(5)
# |   %s.addr.ascast = addrspacecast ptr addrspace(5) %s.addr to ptr
# |   store ptr addrspace(1) %s.coerce, ptr addrspace(5) %s, align 8
# |   %s1 = load ptr, ptr addrspace(5) %s, align 8
# |   store ptr %s1, ptr %s.addr.ascast, align 8
# |   %0 = load ptr, ptr %s.addr.ascast, align 8
# |   %x = getelementptr inbounds nuw %struct.S, ptr %0, i32 0, i32 0
# |   %1 = load ptr, ptr %x, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %1, i64 0
# |   %2 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   %3 = load ptr, ptr %s.addr.ascast, align 8
# |   %y = getelementptr inbounds nuw %struct.S, ptr %3, i32 0, i32 1
# |   %4 = load ptr, ptr %y, align 8
# |   %arrayidx2 = getelementptr inbounds float, ptr %4, i64 0
# |   %5 = load float, ptr %arrayidx2, align 4
# |   %add = fadd contract float %5, 1.000000e+00
# |   store float %add, ptr %arrayidx2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel61T(ptr addrspace(4) noundef byref(%struct.T) align 8 %0) #0 {
# | entry:
# |   %t = alloca %struct.T, align 8, addrspace(5)
# |   call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 8 %t, ptr addrspace(4) align 8 %0, i64 16, i1 false)
# |   %t.ascast = addrspacecast ptr addrspace(5) %t to ptr
# |   %x = getelementptr inbounds nuw %struct.T, ptr %t.ascast, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x ptr], ptr %x, i64 0, i64 0
# |   %1 = load ptr, ptr %arrayidx, align 8
# |   %arrayidx1 = getelementptr inbounds float, ptr %1, i64 0
# |   %2 = load float, ptr %arrayidx1, align 4
# |   %add = fadd contract float %2, 1.000000e+00
# |   store float %add, ptr %arrayidx1, align 4
# |   %x2 = getelementptr inbounds nuw %struct.T, ptr %t.ascast, i32 0, i32 0
# |   %arrayidx3 = getelementptr inbounds [2 x ptr], ptr %x2, i64 0, i64 1
# |   %3 = load ptr, ptr %arrayidx3, align 8
# |   %arrayidx4 = getelementptr inbounds float, ptr %3, i64 0
# |   %4 = load float, ptr %arrayidx4, align 4
# |   %add5 = fadd contract float %4, 2.000000e+00
# |   store float %add5, ptr %arrayidx4, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel7Pi(ptr addrspace(1) noalias noundef %x.coerce) #0 {
# | entry:
# |   %x = alloca ptr, align 8, addrspace(5)
# |   %x.addr = alloca ptr, align 8, addrspace(5)
# |   %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr
# |   store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8
# |   %x1 = load ptr, ptr addrspace(5) %x, align 8
# |   store ptr %x1, ptr %x.addr.ascast, align 8
# |   %0 = load ptr, ptr %x.addr.ascast, align 8
# |   %arrayidx = getelementptr inbounds i32, ptr %0, i64 0
# |   %1 = load i32, ptr %arrayidx, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %arrayidx, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: convergent mustprogress noinline norecurse nounwind
# | define dso_local amdgpu_kernel void @_Z7kernel82SS(ptr addrspace(1) %a.coerce) #0 {
# | entry:
# |   %a = alloca %struct.SS, align 8, addrspace(5)
# |   %coerce.dive = getelementptr inbounds nuw %struct.SS, ptr addrspace(5) %a, i32 0, i32 0
# |   store ptr addrspace(1) %a.coerce, ptr addrspace(5) %coerce.dive, align 8
# |   %a.ascast = addrspacecast ptr addrspace(5) %a to ptr
# |   %x = getelementptr inbounds nuw %struct.SS, ptr %a.ascast, i32 0, i32 0
# |   %0 = load ptr, ptr %x, align 8
# |   %1 = load float, ptr %0, align 4
# |   %add = fadd contract float %1, 3.000000e+00
# |   store float %add, ptr %0, align 4
# |   ret void
# | }
# | 
# | attributes #0 = { convergent mustprogress noinline norecurse nounwind "amdgpu-flat-work-group-size"="1,1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #1 = { convergent mustprogress noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"amdhsa_code_object_version", i32 600}
# | !1 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"}
# | !2 = !{!"clang version 24.0.0"}
# | !3 = !{}
# | !4 = !{i64 4}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# |  #0 0x000055f9f3ad215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f9f3acf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f9f3ad289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdcccf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdcccf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdcccf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdcccf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9f3a67e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f9f3a67c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f9f3a4cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f9f36fc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f9f36fbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdcccf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdcccf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdcccf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9f36fbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c (830 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056320bdc515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056320bdc20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056320bdc589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac63e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac63ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac63e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac63e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056320bd5ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056320bd5ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056320bd3fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056320b9ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056320b9eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fac63e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac63e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac63e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056320b9eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c (831 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bcae6815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556bcae650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556bcae6889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b10a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b10aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b10a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b10a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bcadfde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556bcadfdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556bcade2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556bcaa920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556bcaa91dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6b10a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b10a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b10a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bcaa91cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c (832 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.firstp.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.firstp.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b32(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.firstp.nxv4i1(<vscale x 4 x i1> %2, <vscale x 4 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svfirstp_b64(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op, ptr %op.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call i64 @llvm.aarch64.sve.firstp.nxv2i1(<vscale x 2 x i1> %2, <vscale x 2 x i1> %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.firstp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005600df2e915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005600df2e60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005600df2e989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7651c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7651c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7651c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7651c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600df27ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005600df27ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005600df263b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005600def130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005600def12dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7651c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7651c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7651c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600def12cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c (833 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsge_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589aab1d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005589aab1a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005589aab1d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9cf4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9cf4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9cf4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9cf4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589aaab2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005589aaab2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005589aaa97b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005589aa7470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005589aa746dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9cf4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9cf4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9cf4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589aa746cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c (834 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b23153815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b2315350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b23153889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80f8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80f818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80f8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80f811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2314cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b2314cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b2314b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b2311620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b231161dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f80f811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80f811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80f811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b231161cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c (835 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_f32m8(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_f32m8(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>
# | ...
# `---data was truncated (10240/76635) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599fd7b215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005599fd7af0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005599fd7b289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd92f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd92f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd92f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd92f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599fd747e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005599fd747c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005599fd72cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005599fd3dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005599fd3dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd92f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd92f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd92f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599fd3dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c (836 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/66036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f58447115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f58446e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f58447189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30dfe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30dfe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30dfe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30dfe03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f584406e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f584406c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f5843ebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f58409b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f58409add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f30dfe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30dfe050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30dfe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f58409acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-vector-compare-ops.c (837 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-compare-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve  -disable-O0-optnone   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @eq_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %cmp = icmp eq <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %cmp
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @eq_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @eq_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @eq_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @eq_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @eq_u8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @eq_u16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @eq_u32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @eq_u64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %b.addr, align 16
# |   %cmp = icmp eq <vscale x 2 x i64> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @eq_f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x half>, align 16
# |   %b.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %b.addr, align 16
# |   %cmp = fcmp oeq <vscale x 8 x half> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @eq_f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x float>, align 16
# |   %b.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %b.addr, align 16
# |   %cmp = fcmp oeq <vscale x 4 x float> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @eq_f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x double>, align 16
# |   %b.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %a, ptr %a.addr, align 16
# |   store <vscale x 2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %a.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %b.addr, align 16
# |   %cmp = fcmp oeq <vscale x 2 x double> %0, %1
# |   %sext = sext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @neq_bool(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i1>, align 2
# |   %b.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %a, ptr %a.addr, align 2
# |   store <vscale x 16 x i1> %b, ptr %b.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %a.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %b.addr, align 2
# |   %cmp = icmp ne <vscale x 16 x i1> %0, %1
# |   ret <vscale x 16 x i1> %cmp
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @neq_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 16 x i8>, align 16
# |   %b.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %a, ptr %a.addr, align 16
# |   store <vscale x 16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %a.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %b.addr, align 16
# |   %cmp = icmp ne <vscale x 16 x i8> %0, %1
# |   %sext = sext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @neq_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 8 x i16>, align 16
# |   %b.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %a, ptr %a.addr, align 16
# |   store <vscale x 8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %a.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %b.addr, align 16
# |   %cmp = icmp ne <vscale x 8 x i16> %0, %1
# |   %sext = sext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @neq_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 4 x i32>, align 16
# |   %b.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %a, ptr %a.addr, align 16
# |   store <vscale x 4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %a.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %b.addr, align 16
# |   %cmp = icmp ne <vscale x 4 x i32> %0, %1
# |   %sext = sext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %sext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @neq_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
# | entry:
# |   %a.addr = alloca <vscale x 2 x i64>, align 16
# |   %b.addr = alloca <vscale x 2 x i64>, align 16
# |   stor
# | ...
# `---data was truncated (10240/44453) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000056139e33615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056139e3330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056139e33689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37af049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37af0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37af049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37af031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056139e2cbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056139e2cbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056139e2b0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056139df600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056139df5fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f37af032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37af0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37af0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056139df5fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c (838 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055959aee415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055959aee10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055959aee489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5163449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51634a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5163449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5163431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055959ae79e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055959ae79c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055959ae5eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055959ab0e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055959ab0ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5163432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51634330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51634330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055959ab0dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c (839 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2_tu(<vscale
# | ...
# `---data was truncated (10240/288267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8d1c4915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a8d1c460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a8d1c4989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2411733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f241178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2411733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f241171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8d1bdee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a8d1bdec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a8d1bc3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a8d18730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a8d1872dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f241171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f241171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f241171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8d1872cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c (840 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557360cb415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557360cb10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557360cb489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35ebd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35ebd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35ebd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35ebd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557360c49e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557360c49c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557360c2eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005573608de0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005573608dddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f35ebd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35ebd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35ebd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573608ddcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c (841 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d     -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpairo.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpairo_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 =
# | ...
# `---data was truncated (10240/125488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056029a56415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056029a5610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056029a56489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1585849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15858a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1585849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1585831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056029a4f9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056029a4f9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056029a4deb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056029a18e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056029a18ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1585832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15858330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15858330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056029a18dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c (842 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vremu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vremu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055994f7be15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055994f7bb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055994f7be89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ac2b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ac2b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ac2b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ac2aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055994f753e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055994f753c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055994f738b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055994f3e80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055994f3e7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2ac2aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ac2aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ac2aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055994f3e7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c (843 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/208191) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb70b7215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eb70b6f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eb70b7289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b8ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b8caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b8ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b8ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb70b07e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eb70b07c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eb70aecb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eb7079c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eb7079bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8b8ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b8ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b8ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb7079bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c (844 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608fb80215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005608fb7ff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005608fb80289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5dfdf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5dfdf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5dfdf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5dfdf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608fb797e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005608fb797c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005608fb77cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005608fb42c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005608fb42bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5dfdf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5dfdf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5dfdf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608fb42bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/compare.c (845 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/compare.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fcmp oeq <8 x half> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = fcmp oeq <4 x float> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp eq <16 x i8> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp eq <8 x i16> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp eq <4 x i32> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp eq <16 x i8> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp eq <8 x i16> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp eq <4 x i32> %0, %1
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_f16(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fcmp oeq <8 x half> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_f32(<4 x float> noundef %a, float noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load float, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %1, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %2 = fcmp oeq <4 x float> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = icmp eq <16 x i8> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = icmp eq <8 x i16> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = icmp eq <4 x i32> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = icmp eq <16 x i8> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = icmp eq <8 x i16> %0, %.splat
# |   %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = 
# | ...
# `---data was truncated (10240/125481) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e847d1115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e847d0e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e847d1189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f612921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61292725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f612921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6129203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e847ca6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e847ca6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e847c8bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e84793b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e84793add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6129204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61292050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61292050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e84793acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c (846 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055722680d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055722680a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055722680d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91b3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91b3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91b3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91b3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572267a2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005572267a2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557226787b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005572264370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557226436dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f91b3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91b3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91b3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557226436cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c (847 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svbic_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svbic_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svbic_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svbic_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svbic_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svbic_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svbic_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svbic_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svbic_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/52880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055eca57b315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eca57b00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eca57b389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61ee849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61ee8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61ee849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61ee831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eca5748e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eca5748c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eca572db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eca53dd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eca53dcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f61ee832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61ee8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61ee8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eca53dccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c (848 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qdmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qdmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/11849) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593ed23315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005593ed2300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005593ed23389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66d1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66d138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66d1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66d131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593ed1c8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005593ed1c8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005593ed1adb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005593ece5d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005593ece5cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f66d131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66d131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66d131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593ece5ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c (849 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1down_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1down_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale 
# | ...
# `---data was truncated (10240/87191) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb519af15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fb519ac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fb519af89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb57333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb5738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb57333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb5731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb51944e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fb51944c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fb51929b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fb515d90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fb515d8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcb5731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb5731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb5731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb515d8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c (850 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i16> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i16> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_gather_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1, i64 0)
# |   %4 = zext <vscale x 4 x i16> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uh_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i16> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1uh_gather_u32base_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.a
# | ...
# `---data was truncated (10240/36974) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055b36a04715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b36a0440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b36a04789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde46a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde46aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde46a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde46a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b369fdce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b369fdcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b369fc1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b369c710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b369c70dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fde46a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde46a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde46a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b369c70cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c (851 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf6128015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cf6127d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cf6128089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1dd2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1dd2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1dd2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1dd2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf61215e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cf61215c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cf611fab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cf60eaa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cf60ea9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1dd2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1dd2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1dd2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf60ea9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c (852 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv1i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv1i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2_m(<vscale x 32 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v
# | ...
# `---data was truncated (10240/18520) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ea2af815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556ea2af50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556ea2af889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4913133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f491318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4913133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f491311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ea2a8de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556ea2a8dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556ea2a72b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556ea27220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556ea2721dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f491311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f491311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f491311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ea2721cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c (853 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_s32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64 %0, <vscale x 16 x i1> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b16(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64 %0, <vscale x 8 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b32(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64 %0, <vscale x 4 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_s64_b64(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i64 %op, ptr %op.addr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i64, ptr %op.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64 %0, <vscale x 2 x i1> %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b8(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32 %0, <vscale x 16 x i1> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b16(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32 %0, <vscale x 8 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32, <vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b32(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32 %0, <vscale x 4 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32, <vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svqdecp_n_u32_b64(i32 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i32, align 4
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store i32 %op, ptr %op.addr, align 4
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load i32, ptr %op.addr, align 4
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32 %0, <vscale x 2 x i1> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32, <vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svqdecp_n_u64_b8(i64 noundef %op, <vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %op.addr = alloca i64, align 8
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/19010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f280f0215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f280eff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f280f0289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa78221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7822725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa78221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa782203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f280e97e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f280e97c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f280e7cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f280b2c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f280b2bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa782204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7822050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7822050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f280b2bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c (854 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldnf1_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldnf1_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldnf1_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svldnf1_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ldnf1.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ldnf1.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svldnf1_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ldnf1.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ldnf1.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svldnf1_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ldnf1.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ldnf1.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svldnf1_vnum_mf8(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# | 
# | ...
# `---data was truncated (10240/22483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ffb42d015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ffb42cd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ffb42d089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8caea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8caeaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8caea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8caea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffb4265e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ffb4265c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ffb424ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ffb3efa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ffb3ef9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8caea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8caea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8caea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffb3ef9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c (855 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfvfexp32e,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexp32e0p5"}
# | !3 = !{i32 8, !"SmallDataLi
# | ...
# `---data was truncated (10240/10285) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f8668bc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f8668b90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f8668bc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0945449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09454a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0945449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0945431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f866851e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f866851c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f866836b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f8664e60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f8664e5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0945432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09454330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09454330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f8664e5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c (856 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4(<vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2(<vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1(<vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2(<vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4(<vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8(<vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2(<vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1(<vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2(<vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vslidedown_vx_f32m4(<vscale x 8 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64, i64,
# | ...
# `---data was truncated (10240/120460) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556edfbe415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556edfbe10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556edfbe489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e96933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e9698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e96933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e9691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556edfb79e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556edfb79c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556edfb5eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556edf80e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556edf80ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6e9691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e9691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e9691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556edf80dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c (857 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a34be1515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a34be120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a34be1589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f336f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f336f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f336f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f336f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a34bdaae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a34bdaac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a34bd8fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a34ba3f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a34ba3edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f336f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f336f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f336f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a34ba3ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c (858 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560783ed815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560783ed50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560783ed889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa620d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa620d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa620d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa620d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560783e6de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560783e6dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560783e52b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560783b020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560783b01dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa620d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa620d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa620d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560783b01cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c (859 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f07d21215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f07d20f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f07d21289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f26533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f2658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f26533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f2651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f07d1a7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f07d1a7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f07d18cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f07ce3c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f07ce3bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3f2651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f2651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f2651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f07ce3bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c (860 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32mf2(ptr noundef %base, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m1(ptr noundef %base, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m2(ptr noundef %base, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m4(ptr noundef %base, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_f32m8(ptr noundef %base, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m2(ptr noundef %base, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m4(ptr noundef %base, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_i32m8(ptr noundef %base, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32mf2(ptr noundef %base, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse32_v_u32m1(ptr noundef %base, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i32.p0.i64(<vscale x 2 x i32> %1, ptr %0,
# | ...
# `---data was truncated (10240/28346) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056175cb7e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056175cb7b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056175cb7e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b37c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b37c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b37c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b37c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056175cb13e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056175cb13c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056175caf8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056175c7a80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056175c7a7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8b37c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b37c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b37c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056175c7a7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c (861 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> 
# | ...
# `---data was truncated (10240/32133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0c45b915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b0c45b60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b0c45b989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7246933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f724698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7246933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f724691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0c454ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b0c454ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b0c4533b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b0c41e30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b0c41e2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f724691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f724691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f724691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0c41e2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c (862 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_u32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_u32m1x2_m(<vscale x 2 x i1> %mask,
# | ...
# `---data was truncated (10240/13544) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e237ab215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e237aaf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e237ab289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4bfa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4bfa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4bfa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4bfa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e237a47e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e237a47c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e237a2cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e2376dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e2376dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe4bfa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4bfa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4bfa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2376dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c (863 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |  
# | ...
# `---data was truncated (10240/26713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055850689515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005585068920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055850689589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e2c505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e2c55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e2c505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e2c4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055850682ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055850682ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055850680fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005585064bf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005585064bedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6e2c4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e2c4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e2c4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005585064becc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c (864 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605dcee515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005605dcee20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005605dcee589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3014133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f301418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3014133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f301411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605dce7ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005605dce7ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005605dce5fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005605dcb0f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005605dcb0edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f301411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f301411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f301411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605dcb0ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon/getset.c (865 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/getset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vget_lane_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vget_lane_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 3
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vget_lane_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vget_lane_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vget_lane_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 3
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vget_lane_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vget_lane_p8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load i8, ptr %ref.tmp, align 1
# |   store i8 %2, ptr %__ret, align 1
# |   %3 = load i8, ptr %__ret, align 1
# |   store i8 %3, ptr %tmp, align 1
# |   %4 = load i8, ptr %tmp, align 1
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vget_lane_p16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i16>, align 8
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0, align 8
# |   %1 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %1, i32 3
# |   store i16 %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i8> @test_vget_lane_mf8(<8 x i8> %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <1 x i8>, align 1
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <1 x i8>, align 1
# |   %tmp = alloca <1 x i8>, align 1
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vget_lane = extractelement <8 x i8> %1, i32 7
# |   store i8 %vget_lane, ptr %ref.tmp, align 1
# |   %2 = load <1 x i8>, ptr %ref.tmp, align 1
# |   store <1 x i8> %2, ptr %__ret, align 1
# |   %3 = load <1 x i8>, ptr %__ret, align 1
# |   store <1 x i8> %3, ptr %tmp, align 1
# |   %4 = load <1 x i8>, ptr %tmp, align 1
# |   ret <1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vget_lane_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %__ret_847 = alloca half, align 2
# |   %__s0_847 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca i16, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp1 = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   %tmp2 = alloca half, align 2
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0_847, align 8
# |   %1 = load <4 x i16>, ptr %__s0_847, align 8
# |   store <4 x i16> %1, ptr %__s0, align 8
# |   %2 = load <4 x i16>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i16> %2, i32 1
# |   store i16 %vget_lane, ptr %ref.tmp1, align 2
# |   %3 = load i16, ptr %ref.tmp1, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   store i16 %5, ptr %ref.tmp, align 2
# |   %6 = load half, ptr %ref.tmp, align 2
# |   store half %6, ptr %__ret_847, align 2
# |   %7 = load half, ptr %__ret_847, align 2
# |   store half %7, ptr %tmp2, align 2
# |   %8 = load half, ptr %tmp2, align 2
# |   %conv = fpext half %8 to float
# |   ret float %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vget_lane_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <2 x float>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x float> %1, i32 1
# |   store float %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load float, ptr %ref.tmp, align 4
# |   store float %2, ptr %__ret, align 4
# |   %3 = load float, ptr %__ret, align 4
# |   store float %3, ptr %tmp, align 4
# |   %4 = load float, ptr %tmp, align 4
# |   ret float %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vget_lane_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %__s0, align 8
# |   %vget_lane = extractelement <1 x double> %1, i32 0
# |   store double %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load double, ptr %ref.tmp, align 8
# |   store double %2, ptr %__ret, align 8
# |   %3 = load double, ptr %__ret, align 8
# |   store double %3, ptr %tmp, align 8
# |   %4 = load double, ptr %tmp, align 8
# |   ret double %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 16
# |   %__ret = alloca i8, align 1
# |   %__s0 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__s0, align
# | ...
# `---data was truncated (10240/76998) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005625d91d915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005625d91d60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005625d91d989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b91305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b9135c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b91305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b912ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625d916ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005625d916ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005625d9153b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005625d8e030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005625d8e02dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7b912eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b912ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b912ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625d8e02cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c (866 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <v
# | ...
# `---data was truncated (10240/280163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ed5e5f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557ed5e5c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557ed5e5f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1bda449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1bda4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1bda449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1bda431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ed5df4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557ed5df4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557ed5dd9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557ed5a890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557ed5a88dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1bda432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1bda4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1bda4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ed5a88cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon/perm.c (867 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/perm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -flax-vector-conversions=none           -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vzip1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vzip1q_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vzip1_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vzip1q_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %2, <8 x i16> %3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i16> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vzip1_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <2 x i32> <i32 0, i32 2>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vzip1q_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %2, <4 x i32> %3, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x i32> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vzip1q_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <2 x i64> %2, <2 x i64> %3, <2 x i32> <i32 0, i32 2>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vzip1_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vzip1q_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vzip1_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, 
# | ...
# `---data was truncated (10240/231562) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x0000561bf434915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561bf43460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561bf434989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9628d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9628d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9628d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9628d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561bf42dee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561bf42dec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561bf42c3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561bf3f730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561bf3f72dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9628d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9628d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9628d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561bf3f72cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c (868 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558fc178c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558fc17890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558fc178c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0104f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0104f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0104f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0104f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558fc1721e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558fc1721c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558fc1706b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558fc13b60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558fc13b5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0104f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0104f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0104f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558fc13b5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c (869 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b79fdd315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b79fdd00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b79fdd389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f762df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f762df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f762df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f762df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b79fd68e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b79fd68c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b79fd4db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b79f9fd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b79f9fcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f762df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f762df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f762df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b79f9fccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c (870 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2
# | ...
# `---data was truncated (10240/50524) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b21ffc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562b21ff90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562b21ffc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb0f01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb0f0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb0f01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb0f003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b21f91e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562b21f91c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562b21f76b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562b21c260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562b21c25dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feb0f004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb0f0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb0f0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b21c25cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c (871 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630c5f2915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005630c5f260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005630c5f2989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f498e305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f498e35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f498e305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f498e2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630c5ebee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005630c5ebec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005630c5ea3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005630c5b530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005630c5b52dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f498e2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f498e2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f498e2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630c5b52cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c (872 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %v
# | ...
# `---data was truncated (10240/222307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056122bbc515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056122bbc20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056122bbc589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7124d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7124d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7124d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7124d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056122bb5ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056122bb5ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056122bb3fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056122b7ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056122b7eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7124d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7124d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7124d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056122b7eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c (873 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11051) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613959b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005613959b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005613959b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40bf249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40bf2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40bf249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40bf231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056139594ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056139594cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561395931b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005613955e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005613955e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f40bf232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40bf2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40bf2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613955e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c (874 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3d994315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f3d99400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f3d994389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff20c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff20c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff20c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff20c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3d98d8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f3d98d8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f3d98bdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f3d956d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f3d956cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff20c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff20c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff20c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3d956ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c (875 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ee793b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556ee79380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556ee793b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f162b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f162b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f162b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f162b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ee78d0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556ee78d0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556ee78b5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556ee75650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556ee7564dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f162b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f162b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f162b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ee7564cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c (876 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscal
# | ...
# `---data was truncated (10240/12471) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd8fb9915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cd8fb960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cd8fb9989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f65e4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65e44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f65e4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f65e4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd8fb2ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cd8fb2ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cd8fb13b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cd8f7c30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cd8f7c2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f65e4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65e44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65e44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd8f7c2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c (877 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558af478915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558af47860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558af478989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e92f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e92f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e92f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e92eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558af471ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558af471ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558af4703b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558af43b30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558af43b2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7e92eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e92eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e92eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558af43b2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c (878 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/24990) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c2a23c415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c2a23c10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c2a23c489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7218133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f721818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7218133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f721811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2a2359e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c2a2359c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c2a233eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c2a1fee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c2a1feddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f721811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f721811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f721811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2a1fedcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c (879 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x
# | ...
# `---data was truncated (10240/164783) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc5afb315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dc5afb00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dc5afb389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad35e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad35ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad35e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad35e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc5af48e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dc5af48c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dc5af2db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dc5abdd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dc5abdcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fad35e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad35e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad35e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc5abdccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c (880 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vabs_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vabs.i = bitcast <8 x i8> %1 to <4 x half>
# |   %vabs1.i = call <4 x half> @llvm.fabs.v4f16(<4 x half> %vabs.i)
# |   store <4 x half> %vabs1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vabs.i = bitcast <16 x i8> %1 to <8 x half>
# |   %vabs1.i = call <8 x half> @llvm.fabs.v8f16(<8 x half> %vabs.i)
# |   store <8 x half> %vabs1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vceqz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oeq <4 x half> %2, zeroinitializer
# |   %vceqz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vceqz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oeq <8 x half> %2, zeroinitializer
# |   %vceqz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vceqz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oge <4 x half> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oge <8 x half> %2, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ogt <4 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgtz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ogt <8 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgtz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vclez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ole <4 x half> %2, zeroinitializer
# |   %vclez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vclez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vclezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ole <8 x half> %2, zeroinitializer
# |   %vclez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vclez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcltz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp olt <4 x half> %2, zeroinitializer
# |   %vcltz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcltz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp olt <8 x half> %2, zeroinitializer
# |   %vcltz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcltz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>,
# | ...
# `---data was truncated (10240/159327) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000560918e9715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560918e940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560918e9789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa51121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5112725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa51121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa511203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560918e2ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560918e2cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560918e11b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560918ac10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560918ac0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa511204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5112050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5112050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560918ac0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c (881 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <1 x double> @test_vfma_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__p1.addr.i = alloca <1 x double>, align 8
# |   %__p2.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %c.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %c, ptr %c.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   %2 = load <1 x double>, ptr %c.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   store <1 x double> %1, ptr %__p1.addr.i, align 8
# |   store <1 x double> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <1 x double>
# |   %7 = bitcast <8 x i8> %4 to <1 x double>
# |   %8 = bitcast <8 x i8> %5 to <1 x double>
# |   %9 = call <1 x double> @llvm.experimental.constrained.fma.v1f64(<1 x double> %7, <1 x double> %8, <1 x double> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <1 x double> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %10, ptr %__ret.i, align 8
# |   %11 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <1 x double> @test_vfma_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <2 x double>, align 16
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <2 x double> %v, ptr %v.addr, align 16
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1, align 8
# |   %2 = load <2 x double>, ptr %v.addr, align 16
# |   store <2 x double> %2, ptr %__s2, align 16
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <8 x i8> %3 to double
# |   %7 = bitcast <8 x i8> %4 to double
# |   %8 = bitcast <16 x i8> %5 to <2 x double>
# |   %extract = extractelement <2 x double> %8, i32 0
# |   %9 = call double @llvm.experimental.constrained.fma.f64(double %7, double %extract, double %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   %10 = bitcast double %9 to <1 x double>
# |   store <1 x double> %10, ptr %ref.tmp, align 8
# |   %11 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %11, ptr %__ret, align 8
# |   %12 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %12, ptr %tmp, align 8
# |   %13 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %13
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local <2 x double> @test_vfmaq_laneq_f64(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   %v.addr = alloca <2 x double>, align 16
# |   %__ret = alloca <2 x double>, align 16
# |   %__s0 = alloca <2 x double>, align 16
# |   %__s1 = alloca <2 x double>, align 16
# |   %__s2 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   store <2 x double> %v, ptr %v.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__s0, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %1, ptr %__s1, align 16
# |   %2 = load <2 x double>, ptr %v.addr, align 16
# |   store <2 x double> %2, ptr %__s2, align 16
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <16 x i8> %3 to <2 x double>
# |   %7 = bitcast <16 x i8> %4 to <2 x double>
# |   %8 = bitcast <16 x i8> %5 to <2 x double>
# |   %lane = shufflevector <2 x double> %8, <2 x double> %8, <2 x i32> <i32 1, i32 1>
# |   %9 = call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %lane, <2 x double> %7, <2 x double> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store <2 x double> %9, ptr %ref.tmp, align 16
# |   %10 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %10, ptr %__ret, align 16
# |   %11 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %11, ptr %tmp, align 16
# |   %12 = load <2 x double>, ptr %tmp, align 16
# |   ret <2 x double> %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local float @test_vfmas_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca float, align 4
# |   %c.addr = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca float, align 4
# |   %__s1 = alloca float, align 4
# |   %__s2 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store float %b, ptr %b.addr, align 4
# |   store <2 x float> %c, ptr %c.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0, align 4
# |   %1 = load float, ptr %b.addr, align 4
# |   store float %1, ptr %__s1, align 4
# |   %2 = load <2 x float>, ptr %c.addr, align 8
# |   store <2 x float> %2, ptr %__s2, align 8
# |   %3 = load float, ptr %__s0, align 4
# |   %4 = load float, ptr %__s1, align 4
# |   %5 = load <2 x float>, ptr %__s2, align 8
# |   %extract = extractelement <2 x float> %5, i32 1
# |   %6 = call float @llvm.experimental.constrained.fma.f32(float %4, float %extract, float %3, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store float %6, ptr %ref.tmp, align 4
# |   %7 = load float, ptr %ref.tmp, align 4
# |   store float %7, ptr %__ret, align 4
# |   %8 = load float, ptr %__ret, align 4
# |   store float %8, ptr %tmp, align 4
# |   %9 = load float, ptr %tmp, align 4
# |   ret float %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare <1 x double> @llvm.experimental.constrained.fma.v1f64(<1 x double>, <1 x double>, <1 x double>, metadata, metadata) #1
# | 
# | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
# | attributes #2 = { strictfp }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000558326b8915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558326b860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558326b8989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f748a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f748a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f748a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f748a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558326b1ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558326b1ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558326b03b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005583267b30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005583267b2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f748a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f748a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f748a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583267b2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c (882 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vv_u64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vx_u64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vv_u64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vx_u64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vv_u64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vx_u64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.
# | ...
# `---data was truncated (10240/18641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056057ade415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056057ade10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056057ade489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7911e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7911ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7911e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7911e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056057ad79e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056057ad79c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056057ad5eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056057aa0e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056057aa0ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7911e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7911e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7911e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056057aa0dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c (883 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svtssel_f16(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.ftssel.x.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ftssel.x.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svtssel_f32(<vscale x 4 x float> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.ftssel.x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ftssel.x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svtssel_f64(<vscale x 2 x double> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.ftssel.x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ftssel.x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055c4f361715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c4f36140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c4f361789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c88a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c88aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c88a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c88a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4f35ace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c4f35acc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c4f3591b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c4f32410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c4f3240dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4c88a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c88a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c88a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4f3240cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c (884 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, alig
# | ...
# `---data was truncated (10240/150641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624e4f8415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005624e4f810f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005624e4f8489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f674f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f674f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f674f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f674f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624e4f19e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005624e4f19c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005624e4efeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005624e4bae0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005624e4baddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f674f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f674f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f674f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624e4badcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c (885 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip2q.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip2q.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip2q.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip2q.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip2_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip2q.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip2_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip2q.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip2_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip2q.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip2_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip2q.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip2_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip2q.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip2q.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip2_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip2q.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip2q.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip2_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip2q.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip2q.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svzip2_bf16(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.zip2q.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.zip2q.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005644b969115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005644b968e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005644b969189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa319533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa31958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa319533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa31951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644b9626e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005644b9626c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005644b960bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005644b92bb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005644b92badd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa31951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa31951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa31951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644b92bacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c (886 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmerge_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr =
# | ...
# `---data was truncated (10240/124514) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651411a515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005651411a20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005651411a589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff28f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff28f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff28f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff28f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056514113ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056514113ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056514111fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000565140dcf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000565140dcedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff28f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff28f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff28f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565140dcecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c (887 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/113039) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cac67c215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cac67bf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cac67c289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5014f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5014f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5014f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5014f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cac6757e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cac6757c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cac673cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cac63ec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cac63ebdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5014f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5014f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5014f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cac63ebcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c (888 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vminu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605e858a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005605e85870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005605e858a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a10b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a10b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a10b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a10b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605e851fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005605e851fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005605e8504b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005605e81b40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005605e81b3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5a10b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a10b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a10b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605e81b3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c (889 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf2_u32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf2_u64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf2_u64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %op
# | ...
# `---data was truncated (10240/28563) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e08653d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e08653a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e08653d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff01d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff01d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff01d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff01d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0864d2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e0864d2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e0864b7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e0861670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e086166dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff01d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff01d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff01d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e086166cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c (890 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564af804115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564af803e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564af804189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf99133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf9918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf99133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf9911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564af7fd6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564af7fd6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564af7fbbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564af7c6b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564af7c6add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faf9911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf9911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf9911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564af7c6acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c (891 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16>, <vscale x 4 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16>, <vscale x 2 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %6, <vscale x 4 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 4 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv4i16.p0(<vscale x 4 x i16> %6, <vscale x 4 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i16>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i16>
# |   call void @llvm.aarch64.sve.st1.nxv2i16.p0(<vscale x 2 x i16> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1h_scatter_u32base_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %bases, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 4 x i32>, align 16
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %bases, ptr %bases.addr, align 16
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %bases.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i16>
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i16> %3, <vscale x 4 x i1> %4, <vscale x 4 x i32> %1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i16>, <vscale x 4 x i1>, <vscale x 4 x i32>, i64) #
# | ...
# `---data was truncated (10240/43213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x00005571e05f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005571e05f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005571e05f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb3c3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3c3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb3c3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb3c3e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571e058de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005571e058dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005571e0572b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005571e02220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005571e0221dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb3c3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3c3e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3c3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571e0221cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/mozilla-ms-inline-asm.c (892 of 27911)
******************** TEST 'Clang :: CodeGen/mozilla-ms-inline-asm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c"
# | target datalayout = "e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-i128:128-f64:32:64-f80:128-n8:16:32-S128"
# | target triple = "i386-apple-darwin10"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define void @invoke_copy_to_stack() #0 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define void @invoke(ptr noundef %that, i32 noundef %methodIndex, i32 noundef %paramCount, ptr noundef %params) #0 {
# | entry:
# |   %that.addr = alloca ptr, align 4
# |   %methodIndex.addr = alloca i32, align 4
# |   %paramCount.addr = alloca i32, align 4
# |   %params.addr = alloca ptr, align 4
# |   store ptr %that, ptr %that.addr, align 4
# |   store i32 %methodIndex, ptr %methodIndex.addr, align 4
# |   store i32 %paramCount, ptr %paramCount.addr, align 4
# |   store ptr %params, ptr %params.addr, align 4
# |   call void asm sideeffect inteldialect "mov edx,$1\0A\09test edx,edx\0A\09jz L__MSASMLABEL_.${:uid}__noparams\0A\09mov eax,edx\0A\09shl eax,$$3\0A\09sub esp,eax\0A\09mov ecx,esp\0A\09push $0\0A\09call ${2:P}\0A\09L__MSASMLABEL_.${:uid}__noparams:\0A\09mov ecx,$3\0A\09push ecx\0A\09mov edx,[ecx]\0A\09mov eax,$4\0A\09call dword ptr[edx + eax * $$4]\0A\09mov esp,ebp\0A\09pop ebp\0A\09ret", "=*m,*m,*m,*m,*m,~{eax},~{ebp},~{ecx},~{edx},~{flags},~{esp},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(ptr) %params.addr, ptr elementtype(i32) %paramCount.addr, ptr elementtype(void (...)) @invoke_copy_to_stack, ptr elementtype(ptr) %that.addr, ptr elementtype(i32) %methodIndex.addr) #1, !srcloc !2
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+x87" }
# | attributes #1 = { nounwind }
# | 
# | !llvm.module.flags = !{!0}
# | !llvm.ident = !{!1}
# | 
# | !0 = !{i32 1, !"NumRegisterParameters", i32 0}
# | !1 = !{!"clang version 24.0.0"}
# | !2 = !{i64 1623}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S
# |  #0 0x000055f2f110515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f2f11020f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f2f110589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d03b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d03b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d03b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d03b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2f109ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f2f109ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f2f107fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f2f0d2f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f2f0d2edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6d03b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d03b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d03b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2f0d2ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c (893 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 0, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 0, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 0, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 1, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 1, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 1, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_x_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> undef, <16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> undef, <8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> undef, <4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_x_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> undef, <16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> undef, <8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> undef, <4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |  
# | ...
# `---data was truncated (10240/15969) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c0cd4215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562c0cd3f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562c0cd4289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8919a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8919aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8919a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8919a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c0ccd7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562c0ccd7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562c0ccbcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562c0c96c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562c0c96bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8919a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8919a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8919a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c0c96bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c (894 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64>
# | ...
# `---data was truncated (10240/18217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055986e83e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055986e83b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055986e83e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc130533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc13058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc130533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc13051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055986e7d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055986e7d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055986e7b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055986e4680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055986e467dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc13051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc13051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc13051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055986e467cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve/addv.c (895 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/addv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i64 @llvm.aarch64.sve.saddv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.saddv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.saddv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.saddv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.saddv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i64 @llvm.aarch64.sve.uaddv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uaddv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uaddv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svaddv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.uaddv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.uaddv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local half @test_svaddv_f16(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call half @llvm.aarch64.sve.faddv.nxv8f16(<vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret half %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.sve.faddv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local float @test_svaddv_f32(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret float %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local double @test_svaddv_f64(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret double %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | a
# | ...
# `---data was truncated (10240/10826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# |  #0 0x00005633d210915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005633d21060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005633d210989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0579533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f057958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0579533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f057951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633d209ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005633d209ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005633d2083b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005633d1d330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005633d1d32dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f057951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f057951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f057951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633d1d32cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c (896 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmul_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f24a9815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562f24a950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562f24a9889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f153ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f153aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f153ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f153ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f24a2de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562f24a2dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562f24a12b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562f246c20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562f246c1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f153ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f153ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f153ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f246c1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c (897 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   re
# | ...
# `---data was truncated (10240/120915) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a7a77915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561a7a7760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561a7a77989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04c3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04c30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04c3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04c3031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a7a70ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561a7a70ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561a7a6f3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561a7a3a30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561a7a3a2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f04c3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04c30330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04c30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a7a3a2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c (898 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_x_i8mf8_tu(<vscale x 1 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_x_i8mf4_tu(<vscale x 2 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_x_i8mf2_tu(<vscale x 4 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_x_i8m1_tu(<vscale x 8 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_x_i8m2_tu(<vscale x 16 x i8> %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i8, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# | 
# | ...
# `---data was truncated (10240/134744) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594df80215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005594df7ff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005594df80289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff7a5905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7a595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff7a5905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff7a58ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594df797e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005594df797c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005594df77cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005594df42c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005594df42bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff7a58eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7a58ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7a58ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594df42bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c (899 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon      -disable-O0-optnone   -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vadd_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %add.i = fadd <2 x float> %2, %3
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vaddq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %add.i = fadd <4 x float> %2, %3
# |   store <4 x float> %add.i, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vsub_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %sub.i = fsub <2 x float> %2, %3
# |   store <2 x float> %sub.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vsubq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %sub.i = fsub <4 x float> %2, %3
# |   store <4 x float> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vsubq_f64(<2 x double> noundef %v1, <2 x double> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %v1.addr = alloca <2 x double>, align 16
# |   %v2.addr = alloca <2 x double>, align 16
# |   store <2 x double> %v1, ptr %v1.addr, align 16
# |   store <2 x double> %v2, ptr %v2.addr, align 16
# |   %0 = load <2 x double>, ptr %v1.addr, align 16
# |   %1 = load <2 x double>, ptr %v2.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__p1.addr.i, align 16
# |   %sub.i = fsub <2 x double> %2, %3
# |   store <2 x double> %sub.i, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmul_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %mul.i = fmul <2 x float> %2, %3
# |   store <2 x float> %mul.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmulq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %mul.i = fmul <4 x float> %2, %3
# |   store <4 x float> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vmulq_f64(<2 x double> noundef %v1, <2 x double> noundef %v2) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %v1.addr = alloca <2 x double>, align 16
# |   %v2.addr = alloca <2 x double>, align 16
# |   store <2 x double> %v1, ptr %v1.addr, align 16
# |   store <2 x double> %v2, ptr %v2.addr, align 16
# |   %0 = load <2 x double>, ptr %v1.addr, align 16
# |   %1 = load <2 x double>, ptr %v2.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x double>, ptr %__p1.addr.i, align 16
# |   %mul.i = fmul <2 x double> %2, %3
# |   store <2 x double> %mul.i, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmla_f32(<2 x float> noundef %v1, <2 x float> noundef %v2, <2 x float> noundef %v3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %v1.addr = alloca <2 x float>, align 8
# |   %v2.addr = alloca <2 x float>, align 8
# |   %v3.addr = alloca <2 x float>, align 8
# |   store <2 x float> %v1, ptr %v1.addr, align 8
# |   store <2 x float> %v2, ptr %v2.addr, align 8
# |   store <2 x float> %v3, ptr %v3.addr, align 8
# |   %0 = load <2 x float>, ptr %v1.addr, align 8
# |   %1 = load <2 x float>, ptr %v2.addr, align 8
# |   %2 = load <2 x float>, ptr %v3.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load <2 x float>, ptr %__p2.addr.i, align 8
# |   %mul.i = fmul <2 x float> %4, %5
# |   %add.i = fadd <2 x float> %3, %mul.i
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %6 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlaq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2, <4 x float> noundef %v3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v1.addr = alloca <4 x float>, align 16
# |   %v2.addr = alloca <4 x float>, align 16
# |   %v3.addr = alloca <4 x float>, align 16
# |   store <4 x float> %v1, ptr %v1.addr, align 16
# |   store <4 x float> %v2, ptr %v2.addr, align 16
# |   store <4 x float> %v3, ptr %v3.addr, align 16
# |   %0 = load <4 x float>, ptr %v1.addr, align 16
# |   %1 = load <4 x float>, ptr %v2.addr, align 16
# |   %2 = load <4 x float>, ptr %v3.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store <4 x float> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   %5 = load <4 x float>, ptr %__p2.addr.i, align 16
# |   %mul.i = fmul <4 x float> %4, %5
# |   %add.i = fadd <4 x float> %3, %mul.i
# |   store <4 x float> %add.i, ptr %__ret.i, align 16
# |   %6 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %6
# | }
# | 
# | ; F
# | ...
# `---data was truncated (10240/91378) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005607980eb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005607980e80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005607980eb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba6b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba6b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba6b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba6b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560798080e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560798080c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560798065b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560797d150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560797d14dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fba6b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba6b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba6b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560797d14cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c (900 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bee1e815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555bee1e50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555bee1e889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47cc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47cc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47cc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47cc91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bee17de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555bee17dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555bee162b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555bede120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555bede11dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f47cc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47cc91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47cc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bede11cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c (901 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566bca5f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005566bca5c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005566bca5f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1498649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14986a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1498649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1498631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566bc9f4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005566bc9f4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005566bc9d9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005566bc6890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005566bc688dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1498632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14986330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14986330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566bc688cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c (902 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmac
# | ...
# `---data was truncated (10240/179511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560089be15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005560089bb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005560089be89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c14e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c14ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c14e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c14e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556008953e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556008953c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556008938b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005560085e80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005560085e7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4c14e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c14e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c14e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560085e7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c (903 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmul_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmul_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.mul.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmul_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmul_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.mul.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmul_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmul_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmul_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmul_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmul_s8_m(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, pt
# | ...
# `---data was truncated (10240/77120) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055ec941be15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ec941bb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ec941be89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efcf4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efcf458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efcf4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efcf451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec94153e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ec94153c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ec94138b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ec93de80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ec93de7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efcf451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efcf451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efcf451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec93de7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c (904 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkpa_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055b90529b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b9052980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b90529b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f520c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f520c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f520c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f520c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b905230e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b905230c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b905215b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b904ec50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b904ec4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f520c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f520c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f520c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b904ec4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c (905 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bf719515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555bf71920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555bf719589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2757b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2757b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2757b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2757aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bf712ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555bf712ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555bf710fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555bf6dbf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555bf6dbedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2757aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2757aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2757aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bf6dbecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c (906 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32x_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32x_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32x_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32x_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32x_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32x_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32z_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32z_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrint32z_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrint32z_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# | 
# | ...
# `---data was truncated (10240/23662) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000562d386c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562d386c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562d386c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec98933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec9898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec98933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec9891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d3865ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562d3865ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562d3863fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562d382ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562d382eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fec9891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec9891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec9891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d382eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c (907 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadb_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadb_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadb_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadb_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadb_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadb_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vsc
# | ...
# `---data was truncated (10240/59603) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556515a0415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556515a010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556515a0489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03adc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03adca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03adc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03adc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556515999e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556515999c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055651597eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055651562e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055651562ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f03adc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03adc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03adc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055651562dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c (908 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vid_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vid_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vid_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vid_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vid_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vid_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vid_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vid_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vid_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vid_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vid_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vid_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vid_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vid_v_u32mf2_tu(<vscale x 1 x i32> %maske
# | ...
# `---data was truncated (10240/75397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557205c2415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557205c210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557205c2489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01a5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01a5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01a5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01a5e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557205bb9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557205bb9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557205b9eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055720584e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055720584ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f01a5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01a5e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01a5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055720584dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c (909 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 
# | ...
# `---data was truncated (10240/69943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555afc58315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555afc5800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555afc58389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7f5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7f58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7f5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7f5831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555afc518e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555afc518c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555afc4fdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555afc1ad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555afc1acdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd7f5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7f58330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7f58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555afc1accc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c (910 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vctz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vctz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vctz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vctz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | ...
# `---data was truncated (10240/40669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621ae2e615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005621ae2e30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005621ae2e689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a64049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a640a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a64049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a64031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621ae27be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005621ae27bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005621ae260b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005621adf100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005621adf0fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6a64032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a640330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a640330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621adf0fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c (911 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svbrkpb_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005583169ac15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005583169a90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005583169ac89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd934849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9348a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd934849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd934831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558316941e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558316941c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558316926b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005583165d60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005583165d5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd934832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9348330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9348330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583165d5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c (912 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind
# | ...
# `---data was truncated (10240/15211) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c78da4f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c78da4c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c78da4f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3b8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3b88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3b8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3b8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c78d9e4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c78d9e4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c78d9c9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c78d6790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c78d678dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff3b8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3b88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3b88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c78d678cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c (913 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 
# | ...
# `---data was truncated (10240/47772) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2dba5615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d2dba530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d2dba5689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9339b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9339b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9339b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9339b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2db9ebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d2db9ebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d2db9d0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d2db6800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d2db67fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9339b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9339b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9339b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2db67fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c (914 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vloxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscal
# | ...
# `---data was truncated (10240/107872) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619829e915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005619829e60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005619829e989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fc8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fc8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fc8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fc8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056198297ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056198297ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561982963b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005619826130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561982612dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3fc8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fc8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fc8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561982612cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c (915 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c059ac015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c059abd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c059ac089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f28f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f28f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f28f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f28f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c059a55e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c059a55c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c059a3ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c0596ea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c0596e9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2f28f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f28f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f28f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0596e9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c (916 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef4_s8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef4_s16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef4_s32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef4_s64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef4_u8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svundef4_u16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svundef4_u32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svundef4_u64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svundef4_f16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @test_svundef4_f32() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @test_svundef4_f64() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svundef4_mf8() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } undef
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_svundef4_bf16() local_unnamed_addr #0 {
# | entry:
# |   ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } undef
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055af367f315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055af367f00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055af367f389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fc641bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fc64725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fc641ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fc6403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af36788e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055af36788c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055af3676db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055af3641d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055af3641cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6fc6404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fc64050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fc64050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af3641ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c (917 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabdu_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/97514) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a61b84d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a61b84a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a61b84d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe045133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe04518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe045133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe04511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a61b7e2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a61b7e2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a61b7c7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a61b4770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a61b476dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe04511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe04511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe04511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a61b476cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c (918 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6e64f415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b6e64f10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b6e64f489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff55e305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff55e35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff55e305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff55e2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6e6489e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b6e6489c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b6e646eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b6e611e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b6e611ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff55e2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff55e2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff55e2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6e611dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c (919 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test
# | ...
# `---data was truncated (10240/156773) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563389dcd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563389dca0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563389dcd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8de7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8de7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8de7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8de7e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563389d62e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563389d62c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563389d47b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005633899f70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005633899f6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8de7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8de7e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8de7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633899f6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c (920 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa451f115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aa451ee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aa451f189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9d5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9d56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9d5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9d5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa45186e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aa45186c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aa4516bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aa44e1b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aa44e1add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa9d5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9d56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9d56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa44e1acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c (921 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8
# | ...
# `---data was truncated (10240/113011) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608c7cfd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005608c7cfa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005608c7cfd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64dd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64dd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64dd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64dd51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608c7c92e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005608c7c92c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005608c7c77b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005608c79270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005608c7926dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f64dd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64dd51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64dd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608c7926cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c (922 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr
# | ...
# `---data was truncated (10240/27541) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559938eb015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559938ead0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559938eb089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ae4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ae44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ae4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ae4431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559938e45e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559938e45c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559938e2ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559938ada0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559938ad9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0ae4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ae44330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ae44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559938ad9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c (923 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be6636d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055be6636a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055be6636d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9220c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9220ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9220c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9220c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be66302e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055be66302c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055be662e7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055be65f970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055be65f96dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9220c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9220c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9220c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be65f96cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c (924 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b584c6d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b584c6a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b584c6d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc563933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc56398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc563933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc56391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b584c02e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b584c02c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b584be7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b5848970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b584896dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc56391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc56391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc56391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b584896cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/ternary.c (925 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/ternary.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %b.addr, align 8
# |   %1 = load <8 x half>, ptr %c.addr, align 8
# |   %2 = load <8 x half>, ptr %a.addr, align 8
# |   %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %b.addr, align 8
# |   %1 = load <4 x float>, ptr %c.addr, align 8
# |   %2 = load <4 x float>, ptr %a.addr, align 8
# |   %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmaq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load half, ptr %c.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %0, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %a.addr, align 8
# |   %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %1, <8 x half> %.splat, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load float, ptr %c.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %0, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %a.addr, align 8
# |   %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %1, <4 x float> %.splat, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmasq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load half, ptr %c.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %0, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %1, <8 x half> %2, <8 x half> %.splat)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmasq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store float %c, ptr %c.addr, align 4
# |   %0 = load float, ptr %c.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %0, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %1, <4 x float> %2, <4 x float> %.splat)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %b.addr, align 8
# |   %1 = load <8 x half>, ptr %c.addr, align 8
# |   %2 = fneg <8 x half> %1
# |   %3 = load <8 x half>, ptr %a.addr, align 8
# |   %4 = call <8 x half> @llvm.fma.v8f16(<8 x half> %0, <8 x half> %2, <8 x half> %3)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmsq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %b.addr, align 8
# |   %1 = load <4 x float>, ptr %c.addr, align 8
# |   %2 = fneg <4 x float> %1
# |   %3 = load <4 x float>, ptr %a.addr, align 8
# |   %4 = call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %2, <4 x float> %3)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i8 noundef signext %c) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i8 %c, ptr %c.addr, align 1
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %c.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = mul <16 x i8> %0, %.splat
# |   %3 = load <16 x i8>, ptr %a.addr, align 8
# |   %4 = add <16 x i8> %2, %3
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef signext %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %c, ptr %c.addr, align 2
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load i16, ptr %c.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = mul <8 x i16> %0, %.splat
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = add <8 x i16> %2, %3
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmlaq_n_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i32 noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i32 %c, ptr %c.addr, align 4
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load i32, ptr %c.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = mul <4 x i32> %0, %.splat
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = add <4 x i32> %2, %3
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i8 noundef zeroext %c) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i8 %c, ptr %c.addr, align 1
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %c.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = mul <16 x i8> %0, %.splat
# |   %3 = load <16 x i8>, ptr %a.addr, align 8
# |   %4 = add <16 x i8> %2, %3
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, ali
# | ...
# `---data was truncated (10240/60411) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055acb6e4715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055acb6e440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055acb6e4789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd703c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd703ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd703c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd703c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055acb6ddce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055acb6ddcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055acb6dc1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055acb6a710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055acb6a70dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd703c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd703c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd703c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055acb6a70cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c (926 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d175bc915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d175bc60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d175bc989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62ae333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62ae38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62ae333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62ae31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d175b5ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d175b5ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d175b43b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d1757f30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d1757f2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f62ae31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62ae31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62ae31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1757f2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon/add.c (927 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vadd_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %add.i = add <8 x i8> %2, %3
# |   store <8 x i8> %add.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vadd_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %add.i = add <4 x i16> %2, %3
# |   store <4 x i16> %add.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vadd_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %add.i = add <2 x i32> %2, %3
# |   store <2 x i32> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vadd_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %add.i = add <1 x i64> %2, %3
# |   store <1 x i64> %add.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vadd_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %add.i = fadd <2 x float> %2, %3
# |   store <2 x float> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vadd_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %add.i = add <8 x i8> %2, %3
# |   store <8 x i8> %add.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vadd_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %add.i = add <4 x i16> %2, %3
# |   store <4 x i16> %add.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vadd_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %add.i = add <2 x i32> %2, %3
# |   store <2 x i32> %add.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vadd_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %add.i = add <1 x i64> %2, %3
# |   store <1 x i64> %add.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vaddq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %add.i = add <16 x i8> %2, %3
# |   store <16 x i8> %add.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %add.i = add <8 x i16> %2, %3
# |   store <8 x i16> %add.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vaddq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b
# | ...
# `---data was truncated (10240/221881) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x00005569e32d115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005569e32ce0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005569e32d189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1a1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1a1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1a1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1a1c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569e3266e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005569e3266c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005569e324bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005569e2efb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005569e2efadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff1a1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1a1c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1a1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569e2efacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c (928 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux-gnu -target-feature +neon   -target-feature +v8.1a -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux-gnu -target-feature +neon -target-feature +v8.1a -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrdmlah_laneq_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_790 = alloca <4 x i16>, align 8
# |   %__s0_790 = alloca <4 x i16>, align 8
# |   %__s1_790 = alloca <4 x i16>, align 8
# |   %__s2_790 = alloca <8 x i16>, align 16
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_790, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_790, align 8
# |   %2 = load <8 x i16>, ptr %v.addr, align 16
# |   store <8 x i16> %2, ptr %__s2_790, align 16
# |   %3 = load <4 x i16>, ptr %__s0_790, align 8
# |   %4 = load <4 x i16>, ptr %__s1_790, align 8
# |   %5 = load <8 x i16>, ptr %__s2_790, align 16
# |   store <8 x i16> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <8 x i16>
# |   %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   store <4 x i16> %3, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %4, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %10, ptr %__p2.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s16.i = bitcast <8 x i8> %11 to <4 x i16>
# |   %vqrdmlah_s161.i = bitcast <8 x i8> %12 to <4 x i16>
# |   %vqrdmlah_s162.i = bitcast <8 x i8> %13 to <4 x i16>
# |   %vqrdmlah_s163.i = call <4 x i16> @llvm.aarch64.neon.sqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i)
# |   %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8
# |   %14 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x i16>, ptr %__ret.i, align 8
# |   store <4 x i16> %15, ptr %__ret_790, align 8
# |   %16 = load <4 x i16>, ptr %__ret_790, align 8
# |   store <4 x i16> %16, ptr %tmp1, align 8
# |   %17 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vqrdmlah_laneq_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <4 x i32> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %v.addr = alloca <4 x i32>, align 16
# |   %__ret_788 = alloca <2 x i32>, align 8
# |   %__s0_788 = alloca <2 x i32>, align 8
# |   %__s1_788 = alloca <2 x i32>, align 8
# |   %__s2_788 = alloca <4 x i32>, align 16
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp1 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_788, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %1, ptr %__s1_788, align 8
# |   %2 = load <4 x i32>, ptr %v.addr, align 16
# |   store <4 x i32> %2, ptr %__s2_788, align 16
# |   %3 = load <2 x i32>, ptr %__s0_788, align 8
# |   %4 = load <2 x i32>, ptr %__s1_788, align 8
# |   %5 = load <4 x i32>, ptr %__s2_788, align 16
# |   store <4 x i32> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <4 x i32>
# |   %lane = shufflevector <4 x i32> %7, <4 x i32> %7, <2 x i32> <i32 3, i32 3>
# |   store <2 x i32> %lane, ptr %ref.tmp, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %4, ptr %__p1.addr.i, align 8
# |   store <2 x i32> %10, ptr %__p2.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s32.i = bitcast <8 x i8> %11 to <2 x i32>
# |   %vqrdmlah_s321.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vqrdmlah_s322.i = bitcast <8 x i8> %13 to <2 x i32>
# |   %vqrdmlah_s323.i = call <2 x i32> @llvm.aarch64.neon.sqrdmlah.v2i32(<2 x i32> %vqrdmlah_s32.i, <2 x i32> %vqrdmlah_s321.i, <2 x i32> %vqrdmlah_s322.i)
# |   %vqrdmlah_s324.i = bitcast <2 x i32> %vqrdmlah_s323.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s324.i, ptr %ref.tmp.i, align 8
# |   %14 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %14, ptr %__ret.i, align 8
# |   %15 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %15, ptr %__ret_788, align 8
# |   %16 = load <2 x i32>, ptr %__ret_788, align 8
# |   store <2 x i32> %16, ptr %tmp1, align 8
# |   %17 = load <2 x i32>, ptr %tmp1, align 8
# |   ret <2 x i32> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vqrdmlahq_laneq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__p2.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %v.addr = alloca <8 x i16>, align 16
# |   %__ret_786 = alloca <8 x i16>, align 16
# |   %__s0_786 = alloca <8 x i16>, align 16
# |   %__s1_786 = alloca <8 x i16>, align 16
# |   %__s2_786 = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x i16>, align 16
# |   %tmp1 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   store <8 x i16> %v, ptr %v.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_786, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %1, ptr %__s1_786, align 16
# |   %2 = load <8 x i16>, ptr %v.addr, align 16
# |   store <8 x i16> %2, ptr %__s2_786, align 16
# |   %3 = load <8 x i16>, ptr %__s0_786, align 16
# |   %4 = load <8 x i16>, ptr %__s1_786, align 16
# |   %5 = load <8 x i16>, ptr %__s2_786, align 16
# |   store <8 x i16> %5, ptr %__s0, align 16
# |   %6 = load <16 x i8>, ptr %__s0, align 16
# |   %7 = bitcast <16 x i8> %6 to <8 x i16>
# |   %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
# |   store <8 x i16> %lane, ptr %ref.tmp, align 16
# |   %8 = load <8 x i16>, ptr %ref.tmp, align 16
# |   store <8 x i16> %8, ptr %__ret, align 16
# |   %9 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %9, ptr %tmp, align 16
# |   %10 = load <8 x i16>, ptr %tmp, align 16
# |   store <8 x i16> %3, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %4, ptr %__p1.addr.i, align 16
# |   store <8 x i16> %10, ptr %__p2.addr.i, align 16
# |   %11 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %12 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %13 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vqrdmlahq_s16.i = bitcast <16 x i8> %11 to <8 x i16>
# |   %vqrdmlahq_s161.i = bitcast <16 x i8> %12 to <8 x i16>
# |   %vqrdmlahq_s162.i = bitcast <16 x i8> %13 to <8 x i16>
# |   %vqrdmlahq_s163.i = call <8 x i16> @llvm.aarch64.neon.sqrdmlah.v8i16(<8 x i16> %vqrdmlahq_s16.i, <8 x i16> %vqrdmlahq_s161.i, <8 x i16> %vqrdmlahq_s162.i)
# |   %vqrdmlahq_s164.i = bitcast <8 x i16> %vqrdmlahq_s163.i to <16 x i8>
# |   store <16 x i8> %vqrdmlahq_s164.i, ptr %ref.tmp.i, align 16
# |   %14 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %14, ptr %__ret.i, align 16
# |   %15 = load <8 x i16>, ptr %__ret.i, align 16
# |   store <8 x i16> %15, ptr %__ret_786, align 16
# |   %16 = load <8 x i16>, ptr %__ret_786, align 16
# |   store <8 x i16> %16, ptr %tmp1, align 16
# |   %17 = load <8 x i16>, ptr %tmp1, align 16
# |   ret <8 x i16> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vqrdmlahq_laneq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__p2.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %v.addr = alloca <4 x i32>, align 16
# |   %__ret_784 = alloca <4 x i32>, align 16
# |   %__s0_784 = alloca <4 x i32>, align 16
# |   %__s1_784 = alloca <4 x i32>, align 16
# |   %__s2_784 = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   %tmp1 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   store <4 x i32> %v, ptr %v.addr, align 16
# |   %0 = load <4
# | ...
# `---data was truncated (10240/50621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# |  #0 0x0000562af527d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562af527a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562af527d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb556905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb55695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb556905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5568ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562af5212e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562af5212c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562af51f7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562af4ea70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562af4ea6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb5568eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5568ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5568ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562af4ea6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c (929 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <v
# | ...
# `---data was truncated (10240/157769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3ee67915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b3ee6760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b3ee67989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b66333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b6638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b66333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b6631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3ee60ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b3ee60ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b3ee5f3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b3ee2a30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b3ee2a2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0b6631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b6631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b6631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3ee2a2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c (930 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fbf700a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fbf70070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fbf700a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0ea333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0ea38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0ea333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0ea31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbf6f9fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fbf6f9fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fbf6f84b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fbf6c340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fbf6c33dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa0ea31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0ea31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0ea31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbf6c33cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c (931 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7a924b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f7a92480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f7a924b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafd0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafd04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafd0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafd0431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7a91e0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f7a91e0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f7a91c5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f7a8e750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f7a8e74dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fafd0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafd04330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafd04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7a8e74cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c (932 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test
# | ...
# `---data was truncated (10240/94993) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd81b0b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fd81b080f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fd81b0b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57a8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57a838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57a8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57a831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd81aa0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fd81aa0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fd81a85b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fd817350b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fd81734dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f57a831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57a831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57a831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd81734cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c (933 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %1, <vscale x 1 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %1, <vscale x 2 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %1, <vscale x 4 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %1, <vscale x 8 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# | 
# | ...
# `---data was truncated (10240/12652) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055890f6d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055890f6d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055890f6d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f356e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f356e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f356e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f356e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055890f669e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055890f669c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055890f64eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055890f2fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055890f2fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f356e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f356e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f356e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055890f2fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c (934 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/69677) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563790f5215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563790f4f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563790f5289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6811933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f681198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6811933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f681191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563790ee7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563790ee7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563790eccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563790b7c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563790b7bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f681191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f681191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f681191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563790b7bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c (935 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056536284515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005653628420f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056536284589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad35f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad35f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad35f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad35f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653627dae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005653627dac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005653627bfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056536246f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056536246edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fad35f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad35f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad35f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056536246ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c (936 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vloxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x doubl
# | ...
# `---data was truncated (10240/91275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619b62f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005619b62f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005619b62f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c09933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c0998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c09933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c0991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619b628de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005619b628dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005619b6272b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005619b5f220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005619b5f21dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4c0991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c0991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c0991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619b5f21cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c (937 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llv
# | ...
# `---data was truncated (10240/20513) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648895df15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005648895dc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005648895df89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f892cb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f892cb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f892cb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f892caed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564889574e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564889574c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564889559b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005648892090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564889208dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f892caeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f892caef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f892caef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564889208cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c (938 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056312af3d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056312af3a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056312af3d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d08449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d084a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d08449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d08431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056312aed2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056312aed2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056312aeb7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056312ab670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056312ab66dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2d08432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d084330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d084330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056312ab66cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c (939 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpge.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpge.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %2, <vscale x 2 x i64> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpge.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %2, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %2, <vscale x 8 x i16> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphs.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %2, <vscale x 4 x i32> %1)
# |   %5 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
# |   ret <vscale x 16 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svcmple_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr,
# | ...
# `---data was truncated (10240/41923) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055f4723a515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f4723a20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f4723a589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6208449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62084a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6208449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6208431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f47233ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f47233ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f47231fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f471fcf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f471fcedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6208432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62084330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62084330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f471fcecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c (940 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580fcbb715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005580fcbb40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005580fcbb789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b1bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b1bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b1bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b1bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580fcb4ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005580fcb4cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005580fcb31b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005580fc7e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005580fc7e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1b1bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b1bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b1bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580fc7e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c (941 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# | 
# | ...
# `---data was truncated (10240/211223) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560cae00c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560cae0090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560cae00c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2880d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2880d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2880d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2880d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560cadfa1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560cadfa1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560cadf86b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560cadc360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560cadc35dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2880d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2880d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2880d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560cadc35cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c (942 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, splat (i8 5)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, splat (i16 5)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, splat (i32 18)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_s8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, zeroinitializer
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_s16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, zeroinitializer
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_s32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, zeroinitializer
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, splat (i8 3)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, splat (i16 11)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, splat (i32 7)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_u8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shl <16 x i8> %0, zeroinitializer
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_u16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shl <8 x i16> %0, zeroinitializer
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_u32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = shl <4 x i32> %0, zeroinitializer
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = ashr <16 x i8> %0, splat (i8 4)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = ashr <8 x i16> %0, splat (i16 10)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = ashr <4 x i32> %0, splat (i32 19)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_s8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = ashr <16 x i8> %0, splat (i8 7)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_s16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = ashr <8 x i16> %0, splat (i16 15)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_s32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = ashr <4 x i32> %0, splat (i32 31)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = lshr <16 x i8> %0, splat (i8 1)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = lshr <8 x i16> %0, splat (i16 10)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = lshr <4 x i32> %0, splat (i32 10)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_u8_trivial(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   ret <16 x i8> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_u16_trivial(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   ret <8 x i16> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_u32_trivial(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   ret <4 x i32> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8> %0, i32 6, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16> %0, i32 13, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinlin
# | ...
# `---data was truncated (10240/66359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055635bed315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055635bed00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055635bed389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc4aa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc4aa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc4aa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc4aa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055635be68e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055635be68c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055635be4db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055635bafd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055635bafcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbc4aa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc4aa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc4aa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055635bafccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c (943 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   ret <8 x i16> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align
# | ...
# `---data was truncated (10240/30281) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x000055db8c69215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055db8c68f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055db8c69289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1add649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1add6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1add649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1add631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db8c627e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055db8c627c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055db8c60cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055db8c2bc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055db8c2bbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1add632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1add6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1add6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db8c2bbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c (944 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588a323e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005588a323b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005588a323e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8898933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f889898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8898933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f889891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588a31d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005588a31d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005588a31b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005588a2e680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005588a2e67dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f889891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f889891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f889891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588a2e67cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c (945 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_i8mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_i8mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_i8mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i8m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i8m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i8m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i8m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_i8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_i8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_i8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_i8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_i8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_i8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_i8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_i16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_i16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_i16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_i16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_i16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_i16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x half>
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_u16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_u16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_u16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_u16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_u16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_u16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |  
# | ...
# `---data was truncated (10240/136489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f602ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560f602a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560f602ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6634f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6634f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6634f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6634f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f60240e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560f60240c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560f60225b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560f5fed50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560f5fed4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6634f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6634f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6634f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f5fed4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c (946 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dbe712415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dbe71210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dbe712489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25bc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25bc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25bc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25bc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbe70b9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dbe70b9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dbe709eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dbe6d4e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dbe6d4ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f25bc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25bc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25bc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbe6d4dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c (947 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 3, i32 31, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 immarg, i32 immarg, <vscale x 1 x i8>, <vscale x 1 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 3, i32 31, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 immarg, i32 immarg, <vscale x 2 x i8>, <vscale x 2 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 3, i32 31, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 immarg, i32 immarg, <vscale x 4 x i8>, <vscale x 4 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 3, i32 31, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 immarg, i32 immarg, <vscale x 8 x i8>, <vscale x 8 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 3, i32 31, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 immarg, i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 3, i32 31, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 immarg, i32 immarg, <vscale x 32 x i8>, <vscale x 32 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 3, i32 31, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 immarg, i32 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16mf4(<vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 3, i32 31, <vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 immarg, i32 immarg, <vscale x 1 x i16>, <vscale x 1 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16mf2(<vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 3, i32 31, <vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 immarg, i32 immarg, <vscale x 2 x i16>, <vscale x 2 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16m1(<vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 3, i32 31, <vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 immarg, i32 immarg, <vscale x 4 x i16>, <vscale x 4 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vv_se_u16m2(<vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i16.nxv8i16.i32(i32 3, i32 31, <vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function
# | ...
# `---data was truncated (10240/200802) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619280fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005619280f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005619280fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5518f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5518f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5518f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5518f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561928090e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561928090c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561928075b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561927d250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561927d24dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5518f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5518f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5518f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561927d24cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c (948 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bd31bc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559bd31b90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559bd31bc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2efd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2efd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2efd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2efd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bd3151e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559bd3151c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559bd3136b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559bd2de60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559bd2de5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd2efd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2efd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2efd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bd2de5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c (949 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ca155d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563ca155a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563ca155d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd21c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd21c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd21c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd21c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ca14f2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563ca14f2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563ca14d7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563ca11870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563ca1186dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd21c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd21c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd21c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ca1186cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/fp8-cast.c (950 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-cast.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_f8_f8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_f8_s8(<8 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_s8_f8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_s8(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_s8_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_f8_f32(<2 x float> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <2 x float>, align 8
# |   store <2 x float> %x, ptr %x.addr, align 8
# |   %0 = load <2 x float>, ptr %x.addr, align 8
# |   %1 = bitcast <2 x float> %0 to <8 x i8>
# |   ret <8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_f32_f8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <8 x i8> %0 to <2 x float>
# |   ret <2 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_f32(<4 x float> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <4 x float>, align 16
# |   store <4 x float> %x, ptr %x.addr, align 16
# |   %0 = load <4 x float>, ptr %x.addr, align 16
# |   %1 = bitcast <4 x float> %0 to <16 x i8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @testq_f32_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @testq_f8_p128(i128 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i128, align 16
# |   store i128 %x, ptr %x.addr, align 16
# |   %0 = load i128, ptr %x.addr, align 16
# |   %1 = bitcast i128 %0 to <16 x i8>
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @testq_p128_f8(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = bitcast <16 x i8> %0 to i128
# |   ret i128 %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg
# |  #0 0x000055ca83bc315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ca83bc00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ca83bc389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a48b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a48b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a48b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a48b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca83b58e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ca83b58c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ca83b3db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ca837ed0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ca837ecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1a48b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a48b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a48b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca837eccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c (951 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9bfc6f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c9bfc6c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c9bfc6f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27f3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27f32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27f3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27f3231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9bfc04e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c9bfc04c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c9bfbe9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c9bf8990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c9bf898dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f27f3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27f32330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27f32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9bf898cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c (952 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e861cdf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e861cdc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e861cdf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8fef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8fef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8fef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8fef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e861c74e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e861c74c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e861c59b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e8619090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e861908dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe8fef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8fef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8fef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e861908cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c (953 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645af97515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005645af9720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005645af97589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff180c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff180ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff180c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff180c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645af90ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005645af90ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005645af8efb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005645af59f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005645af59edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff180c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff180c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff180c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645af59ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c (954 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1    -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq1_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq1_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.uzpq1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq1_u32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.uzpq1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq1_u64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.uzpq1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq1_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svuzpq1_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x i16>, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.uzpq1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svuzpq1_s32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x i32>, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.uzpq1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svuzpq1_s64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x i64>, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.uzpq1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svuzpq1_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x half>, align 16
# |   %zm.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x half> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.uzpq1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.uzpq1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svuzpq1_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 4 x float>, align 16
# |   %zm.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %zn, ptr %zn.addr, align 16
# |   store <vscale x 4 x float> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.uzpq1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.uzpq1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svuzpq1_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 2 x double>, align 16
# |   %zm.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %zn, ptr %zn.addr, align 16
# |   store <vscale x 2 x double> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.uzpq1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.uzpq1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svuzpq1_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %zm.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %zn, ptr %zn.addr, align 16
# |   store <vscale x 8 x bfloat> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq1.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.uzpq1.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svuzpq1_mf8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zn.addr = alloca <vscale x 16 x i8>, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %zn, ptr %zn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %zn.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.uzpq1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %
# | ...
# `---data was truncated (10240/10910) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055e33551a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e3355170f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e33551a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64e2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64e2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64e2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64e2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3354afe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e3354afc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e335494b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e3351440b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e335143dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f64e2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64e2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64e2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e335143cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c (955 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/12067) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6a58bb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b6a58b80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b6a58bb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6089649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60896a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6089649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6089631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6a5850e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b6a5850c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b6a5835b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b6a54e50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b6a54e4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6089632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60896330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60896330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6a54e4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c (956 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615ea83415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005615ea8310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005615ea83489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f998e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f998e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f998e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f998e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615ea7c9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005615ea7c9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005615ea7aeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005615ea45e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005615ea45ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f998e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f998e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f998e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615ea45dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c (957 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |  
# | ...
# `---data was truncated (10240/207749) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eeb5fd515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eeb5fd20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eeb5fd589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67dda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67ddaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67dda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67dda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eeb5f6ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eeb5f6ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eeb5f4fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eeb5bff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eeb5bfedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f67dda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67dda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67dda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eeb5bfecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c (958 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset2_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %3, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset2_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %3, 0
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset2_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %3, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset2_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %3, 0
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset2_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %3, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset2_u16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %3, 0
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset2_u32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %3, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset2_u64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %3, 0
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x ha
# | ...
# `---data was truncated (10240/18235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000561dccea515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561dccea20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561dccea589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f526921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52692725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f526921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5269203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561dcce3ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561dcce3ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561dcce1fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561dccacf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561dccacedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5269204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52692050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52692050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561dccacecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c (959 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8mf8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 5, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 immarg, i32 immarg, i32 immarg, i8, i32 immarg, i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8mf4(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 6, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8mf2(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 7, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m1(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 0, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m2(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 1, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m4(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 2, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u8m8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 3, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16mf4(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 6, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 immarg, i32 immarg, i32 immarg, i16, i32 immarg, i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16mf2(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 7, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m1(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 0, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m2(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 1, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m4(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 2, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u16m8(i16 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i16, align 2
# |   %vl.addr = alloca i32, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i16, ptr %rs1.addr, align 2
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 3, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32mf2(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 7, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 immarg, i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m1(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 0, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m2(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 1, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m4(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 2, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u32m8(i32 noundef %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 3, i32 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vc_v_x_se_u8mf8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i32, align 4
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load i8, ptr %rs1.addr, align 1
# |   %1 = load i32, ptr %vl.addr, align 4
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.x.se.nxv1i8.i32.i8.i32(i32 3, i32 31, i8 %0, i32 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | ...
# `---data was truncated (10240/66298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd50b6915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cd50b660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cd50b6989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facc1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facc1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facc1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facc1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd50afee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cd50afec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cd50ae3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cd507930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cd50792dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007facc1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facc1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facc1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd50792cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c (960 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_lane_bf16_idx1(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 1)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_lane_bf16_idx3(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svmls_lane_bf16_idx7(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, <vscale x 8 x bfloat> %op3) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op3.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x bfloat> %op3, ptr %op3.addr, align 16
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %op3.addr, align 16
# |   %3 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 7)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000563e57fdb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563e57fd80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563e57fdb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb9ef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb9ef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb9ef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb9eeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e57f70e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563e57f70c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563e57f55b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563e57c050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563e57c04dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feb9eeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb9eeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb9eeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e57c04cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c (961 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce80bcc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ce80bc90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ce80bcc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f68ea049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68ea0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f68ea049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68ea031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce80b61e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ce80b61c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ce80b46b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ce807f60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ce807f5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f68ea032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68ea0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68ea0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce807f5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c (962 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | ...
# `---data was truncated (10240/120907) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dbc48cc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dbc48c90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dbc48cc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f046d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f046d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f046d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f046d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbc4861e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dbc4861c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dbc4846b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dbc44f60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dbc44f5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f046d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f046d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f046d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbc44f5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-vector_type-params-returns.c (963 of 27911)
******************** TEST 'Clang :: CodeGen/arm-vector_type-params-returns.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DSVE_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DSVE_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x half> @test_ret_v8f16(<8 x half> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x half> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <4 x float> @test_ret_v4f32(<4 x float> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x float> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <2 x double> @test_ret_v2f64(<2 x double> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <2 x double> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x bfloat> @test_ret_v8bf16(<8 x bfloat> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x bfloat> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <16 x i8> @test_ret_v16s8(<16 x i8> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <16 x i8> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x i16> @test_ret_v8s16(<8 x i16> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x i16> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <4 x i32> @test_ret_v32s4(<4 x i32> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x i32> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <2 x i64> @test_ret_v64s2(<2 x i64> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <2 x i64> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <16 x i8> @test_ret_v16u8(<16 x i8> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <16 x i8> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <8 x i16> @test_ret_v8u16(<8 x i16> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <8 x i16> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <4 x i32> @test_ret_v32u4(<4 x i32> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x i32> %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16)
# | define dso_local noundef <2 x i64> @test_ret_v64u2(<2 x i64> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <2 x i64> %v
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | !llvm.errno.tbaa = !{!4}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{!5, !6, i64 0}
# | !5 = !{!"__libc_errno", !6, i64 0}
# | !6 = !{!"int", !7, i64 0}
# | !7 = !{!"omnipotent char", !8, i64 0}
# | !8 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055f431e7315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f431e700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f431e7389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f517c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f517c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f517c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f517c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f431e08e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f431e08c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f431dedb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f431a9d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f431a9cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f517c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f517c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f517c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f431a9ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c (964 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a265fb515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a265fb20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a265fb589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2bd7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2bd718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2bd7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2bd711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a265f4ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a265f4ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a265f2fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a265bdf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a265bdedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2bd711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2bd711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2bd711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a265bdecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon/bf16-getset.c (965 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/bf16-getset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_vduph_lane_bf16(<4 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret = alloca bfloat, align 2
# |   %__s0 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0, align 8
# |   %1 = load <4 x bfloat>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x bfloat> %1, i32 1
# |   store bfloat %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %2, ptr %__ret, align 2
# |   %3 = load bfloat, ptr %__ret, align 2
# |   store bfloat %3, ptr %tmp, align 2
# |   %4 = load bfloat, ptr %tmp, align 2
# |   ret bfloat %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_vduph_laneq_bf16(<8 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret = alloca bfloat, align 2
# |   %__s0 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca bfloat, align 2
# |   %tmp = alloca bfloat, align 2
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0, align 16
# |   %1 = load <8 x bfloat>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <8 x bfloat> %1, i32 7
# |   store bfloat %vgetq_lane, ptr %ref.tmp, align 2
# |   %2 = load bfloat, ptr %ref.tmp, align 2
# |   store bfloat %2, ptr %__ret, align 2
# |   %3 = load bfloat, ptr %__ret, align 2
# |   store bfloat %3, ptr %tmp, align 2
# |   %4 = load bfloat, ptr %tmp, align 2
# |   ret bfloat %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vdup_lane_bf16(<4 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret_48 = alloca <4 x bfloat>, align 8
# |   %__s0_48 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   %tmp1 = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_48, align 8
# |   %1 = load <4 x bfloat>, ptr %__s0_48, align 8
# |   store <4 x bfloat> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x bfloat>
# |   %lane = shufflevector <4 x bfloat> %3, <4 x bfloat> %3, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
# |   store <4 x bfloat> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x bfloat> %4, ptr %__ret, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %5, ptr %tmp, align 8
# |   %6 = load <4 x bfloat>, ptr %tmp, align 8
# |   store <4 x bfloat> %6, ptr %__ret_48, align 8
# |   %7 = load <4 x bfloat>, ptr %__ret_48, align 8
# |   store <4 x bfloat> %7, ptr %tmp1, align 8
# |   %8 = load <4 x bfloat>, ptr %tmp1, align 8
# |   ret <4 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vdupq_lane_bf16(<4 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret_46 = alloca <8 x bfloat>, align 16
# |   %__s0_46 = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x bfloat>, align 16
# |   %tmp1 = alloca <8 x bfloat>, align 16
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %0, ptr %__s0_46, align 8
# |   %1 = load <4 x bfloat>, ptr %__s0_46, align 8
# |   store <4 x bfloat> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x bfloat>
# |   %lane = shufflevector <4 x bfloat> %3, <4 x bfloat> %3, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
# |   store <8 x bfloat> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <8 x bfloat> %4, ptr %__ret, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %5, ptr %tmp, align 16
# |   %6 = load <8 x bfloat>, ptr %tmp, align 16
# |   store <8 x bfloat> %6, ptr %__ret_46, align 16
# |   %7 = load <8 x bfloat>, ptr %__ret_46, align 16
# |   store <8 x bfloat> %7, ptr %tmp1, align 16
# |   %8 = load <8 x bfloat>, ptr %tmp1, align 16
# |   ret <8 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vdup_laneq_bf16(<8 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret_52 = alloca <4 x bfloat>, align 8
# |   %__s0_52 = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   %tmp1 = alloca <4 x bfloat>, align 8
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_52, align 16
# |   %1 = load <8 x bfloat>, ptr %__s0_52, align 16
# |   store <8 x bfloat> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x bfloat>
# |   %lane = shufflevector <8 x bfloat> %3, <8 x bfloat> %3, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
# |   store <4 x bfloat> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x bfloat> %4, ptr %__ret, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %5, ptr %tmp, align 8
# |   %6 = load <4 x bfloat>, ptr %tmp, align 8
# |   store <4 x bfloat> %6, ptr %__ret_52, align 8
# |   %7 = load <4 x bfloat>, ptr %__ret_52, align 8
# |   store <4 x bfloat> %7, ptr %tmp1, align 8
# |   %8 = load <4 x bfloat>, ptr %tmp1, align 8
# |   ret <4 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vdupq_laneq_bf16(<8 x bfloat> noundef %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret_50 = alloca <8 x bfloat>, align 16
# |   %__s0_50 = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x bfloat>, align 16
# |   %tmp1 = alloca <8 x bfloat>, align 16
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %0, ptr %__s0_50, align 16
# |   %1 = load <8 x bfloat>, ptr %__s0_50, align 16
# |   store <8 x bfloat> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x bfloat>
# |   %lane = shufflevector <8 x bfloat> %3, <8 x bfloat> %3, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
# |   store <8 x bfloat> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <8 x bfloat> %4, ptr %__ret, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %5, ptr %tmp, align 16
# |   %6 = load <8 x bfloat>, ptr %tmp, align 16
# |   store <8 x bfloat> %6, ptr %__ret_50, align 16
# |   %7 = load <8 x bfloat>, ptr %__ret_50, align 16
# |   store <8 x bfloat> %7, ptr %tmp1, align 16
# |   %8 = load <8 x bfloat>, ptr %tmp1, align 16
# |   ret <8 x bfloat> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vdup_n_bf16(bfloat noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca bfloat, align 2
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %.compoundliteral.i = alloca <4 x bfloat>, align 8
# |   %v.addr = alloca bfloat, align 2
# |   store bfloat %v, ptr %v.addr, align 2
# |   %0 = load bfloat, ptr %v.addr, align 2
# |   store bfloat %0, ptr %__p0.addr.i, align 2
# |   %1 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit.i = insertelement <4 x bfloat> poison, bfloat %1, i32 0
# |   %2 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit1.i = insertelement <4 x bfloat> %vecinit.i, bfloat %2, i32 1
# |   %3 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit2.i = insertelement <4 x bfloat> %vecinit1.i, bfloat %3, i32 2
# |   %4 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit3.i = insertelement <4 x bfloat> %vecinit2.i, bfloat %4, i32 3
# |   store <4 x bfloat> %vecinit3.i, ptr %.compoundliteral.i, align 8
# |   %5 = load <4 x bfloat>, ptr %.compoundliteral.i, align 8
# |   store <4 x bfloat> %5, ptr %__ret.i, align 8
# |   %6 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vdupq_n_bf16(bfloat noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca bfloat, align 2
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %.compoundliteral.i = alloca <8 x bfloat>, align 16
# |   %v.addr = alloca bfloat, align 2
# |   store bfloat %v, ptr %v.addr, align 2
# |   %0 = load bfloat, ptr %v.addr, align 2
# |   store bfloat %0, ptr %__p0.addr.i, align 2
# |   %1 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit.i = insertelement <8 x bfloat> poison, bfloat %1, i32 0
# |   %2 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit1.i = insertelement <8 x bfloat> %vecinit.i, bfloat %2, i32 1
# |   %3 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit2.i = insertelement <8 x bfloat> %vecinit1.i, bfloat %3, i32 2
# |   %4 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit3.i = insertelement <8 x bfloat> %vecinit2.i, bfloat %4, i32 3
# |   %5 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit4.i = insertelement <8 x bfloat> %vecinit3.i, bfloat %5, i32 4
# |   %6 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit5.i = insertelement <8 x bfloat> %vecinit4.i, bfloat %6, i32 5
# |   %7 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit6.i = insertelement <8 x bfloat> %vecinit5.i, bfloat %7, i32 6
# |   %8 = load bfloat, ptr %__p0.addr.i, align 2
# |   %vecinit7.i = insertelement <8 x bfloat> %vecinit6.i, bfloat %8, i32 7
# |   store <8 x bfloat> %vecinit7.i, ptr %.compoundliteral.i, align 16
# |   %9 = load <8 x bfloat>, ptr %.compoundliteral.i, align 16
# |   store <8 x bfloat> %9, ptr %__ret.i, align 16
# |   %10 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %10
# | }
# | 
# | ; Function Attrs: noinline noun
# | ...
# `---data was truncated (10240/13833) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000561c307be15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561c307bb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561c307be89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5c3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5c318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5c3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5c311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c30753e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561c30753c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561c30738b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561c303e80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561c303e7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb5c311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5c311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5c311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c303e7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c (966 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/15718) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c373e4915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c373e460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c373e4989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc488649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4886a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc488649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc488631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c373ddee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c373ddec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c373dc3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c373a730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c373a72dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc488632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4886330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4886330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c373a72cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c (967 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, a
# | ...
# `---data was truncated (10240/30276) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056241531215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056241530f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056241531289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3cdd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3cdd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3cdd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3cdd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624152a7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005624152a7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056241528cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562414f3c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562414f3bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3cdd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3cdd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3cdd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562414f3bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c (968 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce6464915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ce646460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ce6464989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9322b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9322b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9322b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9322b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce645dee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ce645dec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ce645c3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ce642730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ce64272dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9322b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9322b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9322b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce64272cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c (969 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a41f2f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562a41f2c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562a41f2f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc21c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc21c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc21c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc21c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a41ec4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562a41ec4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562a41ea9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562a41b590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562a41b58dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efc21c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc21c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc21c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a41b58cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c (970 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmax_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.smax.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.smax.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmax_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.smax.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.smax.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmax_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.smax.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smax.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmax_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.smax.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.smax.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmax_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.umax.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.umax.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmax_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.umax.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.umax.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmax_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.umax.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.umax.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmax_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale
# | ...
# `---data was truncated (10240/74195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005589f426f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005589f426c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005589f426f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6648e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6648ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6648e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6648e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589f4204e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005589f4204c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005589f41e9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005589f3e990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005589f3e98dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6648e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6648e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6648e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589f3e98cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c (971 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563ffb2315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005563ffb200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005563ffb2389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9a3505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9a355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9a3505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9a34ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563ffab8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005563ffab8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005563ffa9db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005563ff74d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005563ff74cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa9a34eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9a34ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9a34ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563ff74ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c (972 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c30c61615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c30c6130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c30c61689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e58649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e586a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e58649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e58631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c30c5abe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c30c5abc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c30c590b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c30c2400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c30c23fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1e58632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e586330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e586330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c30c23fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c (973 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc510e915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dc510e60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dc510e989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d0a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d0a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d0a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d0a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc5107ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dc5107ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dc51063b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dc50d130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dc50d12dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5d0a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d0a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d0a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc50d12cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c (974 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfvfexp32e,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexp32e0p5"}
# | !3 = !{i32 8, !"Sma
# | ...
# `---data was truncated (10240/10293) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4d265d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d4d265a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d4d265d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb283b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb283b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb283b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb283b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4d25f2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d4d25f2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d4d25d7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d4d22870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d4d2286dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb283b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb283b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb283b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4d2286cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c (975 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/94371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b89ea3d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b89ea3a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b89ea3d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe206533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe20658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe206533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe20651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b89e9d2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b89e9d2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b89e9b7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b89e6670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b89e666dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe20651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe20651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe20651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b89e666cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c (976 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 nou
# | ...
# `---data was truncated (10240/78890) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055718866f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055718866c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055718866f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e29133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e2918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e29133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e2911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557188604e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557188604c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005571885e9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005571882990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557188298dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5e2911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e2911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e2911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557188298cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c (977 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562de591415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562de59110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562de591489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1779533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f177958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1779533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f177951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562de58a9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562de58a9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562de588eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562de553e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562de553ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f177951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f177951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f177951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562de553dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c (978 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load
# | ...
# `---data was truncated (10240/410391) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfa6f3c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dfa6f390f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dfa6f3c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa1f4d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1f4d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa1f4d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa1f4ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfa6ed1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dfa6ed1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dfa6eb6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dfa6b660b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dfa6b65dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa1f4ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1f4cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1f4cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfa6b65cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c (979 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_vnum_u64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i32>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i32> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64base_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i64) #3
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64base_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %bases.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %bases, ptr %bases.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %bases.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1, i64 0)
# |   %4 = zext <vscale x 2 x i32> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_s64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1>, ptr, <vscale x 2 x i64>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_s64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64offset_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64offset_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %offsets) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %offsets.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %offsets, ptr %offsets.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %offsets.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(<vscale x 2 x i1> %3, ptr %1, <vscale x 2 x i64> %2)
# |   %5 = zext <vscale x 2 x i32> %4 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1uw_gather_u64base_offset_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %bases, i64 noundef %offset) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/18766) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000557afda3a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557afda370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557afda3a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b0b505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b0b55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b0b505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b0b4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557afd9cfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557afd9cfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557afd9b4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557afd6640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557afd663dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0b0b4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b0b4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b0b4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557afd663cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c (980 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x half> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x float> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svreinterpret_s8_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x double> %0 to <vscale x 16 x i8>
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   ret <vscale x 8 x i16> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_s64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   ret <vscale x 8 x i16> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x i32> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_u64(<vscale x 2 x i64> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x i64> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_f16(<vscale x 8 x half> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x half> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_f32(<vscale x 4 x float> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 4 x float> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svreinterpret_s16_f64(<vscale x 2 x double> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 2 x double> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_s8(<vscale x 16 x i8> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 16 x i8> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_s16(<vscale x 8 x i16> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svreinterpret_s32_s32(<vscale x 4 x i32> %op) #0 {
# | entry:
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   ret <vscale x 4 x i32>
# | ...
# `---data was truncated (10240/58597) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005613eb68915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005613eb6860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005613eb68989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f293ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f293caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f293ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f293ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613eb61ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005613eb61ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005613eb603b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005613eb2b30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005613eb2b2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f293ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f293ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f293ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613eb2b2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c (981 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate3_s8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %1, 1
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %2, 2
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate3_s16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %1, 1
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %2, 2
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate3_s32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vscale x 4 x i32> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, <vscale x 4 x i32> %1, 1
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %2, 2
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate3_s64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1, <vscale x 2 x i64> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   %x2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   store <vscale x 2 x i64> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, <vscale x 2 x i64> %1, 1
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %2, 2
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate3_u8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, <vscale x 16 x i8> %1, 1
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %2, 2
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate3_u16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, <vscale x 8 x i16> %1, 1
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %2, 2
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate3_u32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vscale x 4 x i32> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, <vscale x 4 x i32> %1, 1
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %2, 2
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate3_u64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1, <vscale x 2 x i64> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   %x2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   store <vscale x 2 x i64> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, <vscale x 2 x i64> %1, 1
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %2, 2
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @test_svcreate3_f16(<vscale x 8 x half> %x0, <vscale x 8 x half> %x1, <vscale x 8 x half> %x2) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x half>, align 16
# |   %x1.addr = alloca <vscale x 8 x half>, align 16
# |   %x2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x half> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x half> %x2, ptr %x2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x half>, ptr %x2.addr, align 16
# |   %3 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } poison, <vsc
# | ...
# `---data was truncated (10240/15704) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055681f37b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055681f3780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055681f37b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5f4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5f40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5f4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5f4031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055681f310e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055681f310c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055681f2f5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055681efa50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055681efa4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc5f4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5f40330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5f40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055681efa4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c (982 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_u32mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_u32m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_u32m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_u32m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_u32m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> p
# | ...
# `---data was truncated (10240/24606) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056014e01315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056014e0100f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056014e01389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42cd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42cd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42cd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42cd31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056014dfa8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056014dfa8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056014df8db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056014dc3d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056014dc3cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f42cd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42cd31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42cd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056014dc3ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c (983 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_u16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_u16mf2x4_m(<vscale x 2 x i1> %mask, ptr nound
# | ...
# `---data was truncated (10240/13515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a43ddd215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a43ddcf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a43ddd289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51aea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51aeaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51aea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51aea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a43dd67e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a43dd67c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a43dd4cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a43d9fc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a43d9fbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f51aea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51aea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51aea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a43d9fbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c (984 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf2_i32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16m1_i32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/43507) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555a75e415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005555a75e10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005555a75e489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72cde1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72cde725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72cde1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72cde03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555a7579e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005555a7579c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005555a755eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005555a720e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005555a720ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f72cde04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72cde050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72cde050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555a720dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c (985 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_u16mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_u16m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_u16m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = allo
# | ...
# `---data was truncated (10240/23031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056504f67d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056504f67a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056504f67d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff991333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff99138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff991333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff99131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056504f612e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056504f612c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056504f5f7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056504f2a70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056504f2a6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff99131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff99131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff99131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056504f2a6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon-misc-constrained.c (986 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-misc-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndaq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrnda.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrnda1.i = call <2 x double> @llvm.round.v2f64(<2 x double> %vrnda.i)
# |   store <2 x double> %vrnda1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndpq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndp.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrndp1.i = call <2 x double> @llvm.ceil.v2f64(<2 x double> %vrndp.i)
# |   store <2 x double> %vrndp1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vsqrtq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %vsqrt.i = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %2)
# |   store <4 x float> %vsqrt.i, ptr %ref.tmp.i, align 16
# |   %3 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %3, ptr %__ret.i, align 16
# |   %4 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcvt_f16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <4 x float>
# |   %3 = fptrunc <4 x float> %2 to <4 x half>
# |   store <4 x half> %3, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcvt_high_f16_f32(<4 x half> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <4 x half>, align 8
# |   %__p1.addr.i2 = alloca <4 x half>, align 8
# |   %__ret.i3 = alloca <8 x half>, align 16
# |   %__p0.addr.i.i = alloca <4 x float>, align 16
# |   %__ret.i.i = alloca <4 x half>, align 8
# |   %ref.tmp.i.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x float>, align 16
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x float>, ptr %__p1.addr.i, align 16
# |   store <4 x float> %3, ptr %__p0.addr.i.i, align 16
# |   %4 = load <16 x i8>, ptr %__p0.addr.i.i, align 16
# |   %5 = bitcast <16 x i8> %4 to <4 x float>
# |   %6 = fptrunc <4 x float> %5 to <4 x half>
# |   store <4 x half> %6, ptr %ref.tmp.i.i, align 8
# |   %7 = load <4 x half>, ptr %ref.tmp.i.i, align 8
# |   store <4 x half> %7, ptr %__ret.i.i, align 8
# |   %8 = load <4 x half>, ptr %__ret.i.i, align 8
# |   store <4 x half> %2, ptr %__p0.addr.i1, align 8
# |   store <4 x half> %8, ptr %__p1.addr.i2, align 8
# |   %9 = load <4 x half>, ptr %__p0.addr.i1, align 8
# |   %10 = load <4 x half>, ptr %__p1.addr.i2, align 8
# |   %shuffle.i = shufflevector <4 x half> %9, <4 x half> %10, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x half> %shuffle.i, ptr %__ret.i3, align 16
# |   %11 = load <8 x half>, ptr %__ret.i3, align 16
# |   store <8 x half> %11, ptr %__ret.i, align 16
# |   %12 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvt_f32_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fpext <4 x half> %2 to <4 x float>
# |   store <4 x float> %3, ptr %ref.tmp.i, align 16
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %4, ptr %__ret.i, align 16
# |   %5 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcvt_high_f32_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i1 = alloca <8 x half>, align 16
# |   %__ret.i2 = alloca <4 x half>, align 8
# |   %__p0.addr.i.i = alloca <4 x half>, align 8
# |   %__ret.i.i = alloca <4 x float>, align 16
# |   %ref.tmp.i.i = alloca <16 x i8>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p0.addr.i1, align 16
# |   %2 = load <8 x half>, ptr %__p0.addr.i1, align 16
# |   %3 = load <8 x half>, ptr %__p0.addr.i1, align 16
# |   %shuffle.i = shufflevector <8 x half> %2, <8 x half> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x half> %shuffle.i, ptr %__ret.i2, align 8
# |   %4 = load <4 x half>, ptr %__ret.i2, align 8
# |   store <4 x half> %4, ptr %__p0.addr.i.i, align 8
# |   %5 = load <8 x i8>, ptr %__p0.addr.i.i, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %7 = fpext <4 x half> %6 to <4 x float>
# |   store <4 x float> %7, ptr %ref.tmp.i.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i.i, align 16
# |   store <4 x float> %8, ptr %__ret.i.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i.i, align 16
# |   store <4 x float> %9, ptr %__ret.i, align 16
# |   %10 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %10
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x double> @llvm.round.v2f64(<2 x double>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x double> @llvm.ceil.v2f64(<2 x double>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055f6f6d4115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f6f6d3e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f6f6d4189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd18e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd18e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd18e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd18e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6f6cd6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f6f6cd6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f6f6cbbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f6f696b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f6f696add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd18e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd18e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd18e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6f696acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c (987 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558eac9fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558eac9fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558eac9fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd361133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd36118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd361133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd36111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558eac992e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558eac992c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558eac977b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558eac6270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558eac626dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd36111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd36111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd36111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558eac626cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c (988 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f7d9e215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562f7d9df0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562f7d9e289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f370d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f370d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f370d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f370d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f7d977e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562f7d977c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562f7d95cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562f7d60c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562f7d60bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f370d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f370d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f370d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f7d60bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c (989 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b68cfa215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b68cf9f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b68cfa289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8975449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89754a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8975449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8975431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b68cf37e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b68cf37c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b68cf1cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b68cbcc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b68cbcbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8975432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89754330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89754330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b68cbcbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c (990 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1b562015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d1b561d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d1b562089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1dce1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1dce725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1dce1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1dce03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1b55b5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d1b55b5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d1b559ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d1b524a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d1b5249dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc1dce04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1dce050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1dce050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1b5249cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c (991 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056387eb7415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056387eb710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056387eb7489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd97381bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9738725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd97381ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd973803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056387eb09e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056387eb09c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056387eaeeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056387e79e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056387e79ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd973804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9738050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9738050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056387e79dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c (992 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgtu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567f6ecc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005567f6ec90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005567f6ecc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d2d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d2d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d2d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d2d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567f6e61e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005567f6e61c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005567f6e46b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005567f6af60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005567f6af5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7d2d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d2d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d2d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567f6af5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c (993 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <
# | ...
# `---data was truncated (10240/112825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1c620a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c1c62070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c1c620a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4151d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4151d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4151d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4151d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1c619fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c1c619fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c1c6184b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c1c5e340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c1c5e33dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4151d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4151d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4151d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1c5e33cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c (994 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   s
# | ...
# `---data was truncated (10240/223359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559732e8015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559732e7d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559732e8089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce4a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce4a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce4a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce4a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559732e15e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559732e15c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559732dfab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559732aaa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559732aa9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fce4a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce4a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce4a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559732aa9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c (995 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea2f82a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ea2f8270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ea2f82a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb37333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb3738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb37333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb3731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea2f7bfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ea2f7bfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ea2f7a4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ea2f4540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ea2f453dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdb3731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb3731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb3731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea2f453cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c (996 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2632f615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e2632f30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e2632f689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18fa933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18fa98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18fa933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18fa91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e26328be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e26328bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e263270b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e262f200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e262f1fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f18fa91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18fa91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18fa91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e262f1fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c (997 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a7a32215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557a7a31f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557a7a32289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c9e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c9e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c9e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c9e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a7a2b7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557a7a2b7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557a7a29cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557a79f4c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557a79f4bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6c9e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c9e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c9e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a79f4bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c (998 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; F
# | ...
# `---data was truncated (10240/102296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595d274b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005595d27480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005595d274b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdddaa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdddaaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdddaa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdddaa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595d26e0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005595d26e0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005595d26c5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005595d23750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005595d2374dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdddaa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdddaa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdddaa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595d2374cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c (999 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eaa5af215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eaa5aef0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eaa5af289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcad7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcad74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcad7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcad7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eaa5a87e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eaa5a87c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eaa5a6cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eaa571c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eaa571bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcad7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcad74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcad74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eaa571bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c (1000 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ub_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ub_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1ub_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1ub_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1ub_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4
# | ...
# `---data was truncated (10240/27977) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000056490f82e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056490f82b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056490f82e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fc5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fc52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fc5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fc5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056490f7c3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056490f7c3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056490f7a8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056490f4580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056490f457dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4fc5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fc52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fc52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056490f457cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c (1001 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557fb3d2015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557fb3d1d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557fb3d2089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87c101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87c10725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87c101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87c1003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fb3cb5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557fb3cb5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557fb3c9ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557fb394a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557fb3949dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f87c1004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87c10050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87c10050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fb3949cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c (1002 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bee78bb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bee78b80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bee78bb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f249b81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f249b8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f249b81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f249b803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bee7850e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bee7850c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bee7835b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bee74e50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bee74e4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f249b804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f249b8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f249b8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bee74e4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c (1003 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallbac
# | ...
# `---data was truncated (10240/66028) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ccbdc9815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ccbdc950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ccbdc9889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f249e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f249e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f249e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f249e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccbdc2de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ccbdc2dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ccbdc12b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ccbd8c20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ccbd8c1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f249e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f249e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f249e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccbd8c1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c (1004 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vloxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vloxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double>, ptr 
# | ...
# `---data was truncated (10240/91267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594ae11715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005594ae1140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005594ae11789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba19705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba1975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba19705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba196ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594ae0ace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005594ae0acc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005594ae091b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005594add410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005594add40dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fba196eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba196ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba196ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594add40cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c (1005 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9cdd3515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b9cdd320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b9cdd3589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb3cb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3cb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb3cb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb3cb71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9cdccae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b9cdccac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b9cdcafb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b9cd95f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b9cd95edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb3cb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3cb71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3cb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9cd95ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c (1006 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/69669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4ab5dc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e4ab5d90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e4ab5dc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd692933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd69298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd692933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd69291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4ab571e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e4ab571c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e4ab556b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e4ab2060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e4ab205dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd69291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd69291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd69291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4ab205cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c (1007 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/64950) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055924397615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005592439730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055924397689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2634705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f263475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2634705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26346ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055924390be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055924390bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005592438f0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005592435a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055924359fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f26346eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26346ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26346ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055924359fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c (1008 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %
# | ...
# `---data was truncated (10240/291999) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055634bdeb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055634bde80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055634bdeb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9651b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9651b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9651b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9651b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055634bd80e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055634bd80c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055634bd65b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055634ba150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055634ba14dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9651b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9651b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9651b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055634ba14cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c (1009 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vect
# | ...
# `---data was truncated (10240/31946) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9b30e615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c9b30e30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c9b30e689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f321a81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f321a8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f321a81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f321a803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9b307be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c9b307bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c9b3060b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c9b2d100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c9b2d0fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f321a804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f321a8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f321a8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9b2d0fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c (1010 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005634a6cbd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005634a6cba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005634a6cbd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc518249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5182a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc518249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc518231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634a6c52e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005634a6c52c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005634a6c37b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005634a68e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005634a68e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc518232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5182330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5182330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005634a68e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c (1011 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintx_f16_z(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintx_f32_z(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintx_f64_z(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintx_f16_m(<vscale x 8 x half> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x half>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %3, <vscale x 8 x half> %2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintx_f32_m(<vscale x 4 x float> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x float>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %3, <vscale x 4 x float> %2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintx_f64_m(<vscale x 2 x double> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x double>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %3, <vscale x 2 x double> %2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svrintx_f16_x(<vscale x 16 x i1> %pg, <vscale x 8 x half> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x half> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.frintx.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> %2, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svrintx_f32_x(<vscale x 16 x i1> %pg, <vscale x 4 x float> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x float> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> %2, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svrintx_f64_x(<vscale x 16 x i1> %pg, <vscale x 2 x double> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x double> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x double>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.frintx.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> %2, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055812a68515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055812a6820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055812a68589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5234733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f523478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5234733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f523471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055812a61ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055812a61ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055812a5ffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055812a2af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055812a2aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f523471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f523471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f523471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055812a2aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c (1012 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, p
# | ...
# `---data was truncated (10240/14521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c948f2f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c948f2c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c948f2f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34c1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34c1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34c1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34c1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c948ec4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c948ec4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c948ea9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c948b590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c948b58dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f34c1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34c1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34c1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c948b58cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c (1013 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ad610c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562ad61090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562ad610c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd556a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd556aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd556a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd556a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ad60a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562ad60a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562ad6086b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562ad5d360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562ad5d35dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd556a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd556a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd556a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ad5d35cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c (1014 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056152b7f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056152b7f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056152b7f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b29e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b29ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b29e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b29e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056152b78de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056152b78dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056152b772b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056152b4220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056152b421dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9b29e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b29e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b29e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056152b421cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c (1015 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsle_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f65c87d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f65c87a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f65c87d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f861c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f861c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f861c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f861c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f65c812e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f65c812c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f65c7f7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f65c4a70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f65c4a6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f861c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f861c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f861c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f65c4a6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c (1016 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2
# | ...
# `---data was truncated (10240/151911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5c63dc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d5c63d90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d5c63dc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca69649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca696a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca69649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca69631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5c6371e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d5c6371c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d5c6356b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d5c60060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d5c6005dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fca69632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca696330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca696330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5c6005cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c (1017 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb5959015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eb5958d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eb5959089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f128b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f128b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f128b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f128b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb59525e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eb59525c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eb5950ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eb591ba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eb591b9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f128b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f128b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f128b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb591b9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c (1018 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16   -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svclamp_single_s8_x2(<vscale x 16 x i8> %op1.coerce0, <vscale x 16 x i8> %op1.coerce1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op1.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 16 x i8>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sclamp.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5, <vscale x 16 x i8> %6)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sclamp.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svclamp_single_s16_x2(<vscale x 8 x i16> %op1.coerce0, <vscale x 8 x i16> %op1.coerce1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %op1.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   %op3.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %op1.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %op1, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   store <vscale x 8 x i16> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 8 x i16>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sclamp.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5, <vscale x 8 x i16> %6)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sclamp.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svclamp_single_s32_x2(<vscale x 4 x i32> %op1.coerce0, <vscale x 4 x i32> %op1.coerce1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %op1.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   %op3.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %op1.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %op1, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   store <vscale x 4 x i32> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 4 x i32>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sclamp.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5, <vscale x 4 x i32> %6)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sclamp.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svclamp_single_s64_x2(<vscale x 2 x i64> %op1.coerce0, <vscale x 2 x i64> %op1.coerce1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %op1.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   %op3.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %op1.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %op1, align 16
# |   %op11 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %op1, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   store <vscale x 2 x i64> %op3, ptr %op3.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %op1.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %6 = load <vscale x 2 x i64>, ptr %op3.addr, align 16
# |   %7 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sclamp.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5, <vscale x 2 x i64> %6)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sclamp.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svclamp_single_s8_x4(<vscale x 16 x i8> %op1.coerce0, <vscale x 16 x i8> %op1.coerce1, <vscale x 16 x i8> %op1.coerce2, <vscale x 16 x i8> %op1.coerce3, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3) #0 {
# | entry:
# |   %op1 = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op1.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   %op3.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %op1.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %op1.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %op1.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %op1.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %op1, align 16
# |   %op11 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %op11, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   store <vscale x 16 x i8> %op3, ptr %op3.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %op1.addr, align 16
# |   %5 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 1
# |   %7 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, 2
# |   %8 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vsc
# | ...
# `---data was truncated (10240/62547) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x00005597662db15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005597662d80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005597662db89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba07e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba07e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba07e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba07e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559766270e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559766270c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559766255b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559765f050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559765f04dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fba07e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba07e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba07e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559765f04cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c (1019 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056068750915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005606875060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056068750989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff26ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff26eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff26ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff26ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056068749ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056068749ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560687483b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005606871330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560687132dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff26ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff26ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff26ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560687132cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c (1020 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vle.mask.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.mask.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vle.mask.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.mask.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vle.mask.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.mask.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vle.mask.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.mask.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vle.mask.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.mask.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vle.mask.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.mask.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vle.mask.nxv4i16.p0.i64(<vscale x 4 x i16> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.mask.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vle.mask.nxv8i16.p0.i64(<vscale x 8 x i16> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.mask.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinli
# | ...
# `---data was truncated (10240/17403) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec9983415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ec998310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ec9983489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5457f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5457f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5457f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5457f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec997c9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ec997c9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ec997aeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ec9945e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ec9945ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5457f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5457f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5457f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec9945dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c (1021 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svcreate2_b(<vscale x 16 x i1> %x0, <vscale x 16 x i1> %x1) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i1>, align 2
# |   %x1.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %x0, ptr %x0.addr, align 2
# |   store <vscale x 16 x i1> %x1, ptr %x1.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %x0.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %x1.addr, align 2
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %0, 0
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %1, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005592ae82315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005592ae8200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005592ae82389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31f3105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31f315c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31f3105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31f30ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592ae7b8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005592ae7b8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005592ae79db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005592ae44d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005592ae44cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f31f30eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31f30ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31f30ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592ae44ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c (1022 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568488f115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005568488ee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005568488f189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9c2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9c28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9c2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9c2831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556848886e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556848886c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055684886bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055684851b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055684851add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc9c2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9c28330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9c28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055684851acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c (1023 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583944bc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005583944b90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005583944bc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa763f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa763f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa763f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa763f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558394451e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558394451c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558394436b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005583940e60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005583940e5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa763f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa763f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa763f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583940e5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/AArch64/neon/widen.c (1024 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/widen.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmovl_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vmovl.i = sext <8 x i8> %1 to <8 x i16>
# |   store <8 x i16> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmovl_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x i16>
# |   %vmovl.i = sext <4 x i16> %2 to <4 x i32>
# |   store <4 x i32> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %3, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vmovl_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x i32>
# |   %vmovl.i = sext <2 x i32> %2 to <2 x i64>
# |   store <2 x i64> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmovl_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vmovl.i = zext <8 x i8> %1 to <8 x i16>
# |   store <8 x i16> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmovl_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x i16>
# |   %vmovl.i = zext <4 x i16> %2 to <4 x i32>
# |   store <4 x i32> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %3, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vmovl_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <2 x i32>
# |   %vmovl.i = zext <2 x i32> %2 to <2 x i64>
# |   store <2 x i64> %vmovl.i, ptr %ref.tmp.i, align 16
# |   %3 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vmovl_high_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i1 = alloca <8 x i8>, align 8
# |   %__p0_561.addr.i = alloca <16 x i8>, align 16
# |   %__ret_561.i = alloca <8 x i16>, align 16
# |   %__a1_561.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %__s0.i = alloca <8 x i8>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0_561.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0_561.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p0.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <8 x i8> %shuffle.i, ptr %__ret.i1, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i1, align 8
# |   store <8 x i8> %4, ptr %__a1_561.i, align 8
# |   %5 = load <8 x i8>, ptr %__a1_561.i, align 8
# |   store <8 x i8> %5, ptr %__s0.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i, align 8
# |   %7 = sext <8 x i8> %6 to <8 x i16>
# |   store <8 x i16> %7, ptr %ref.tmp1.i, align 16
# |   %8 = load <8 x i16>, ptr %ref.tmp1.i, align 16
# |   store <8 x i16> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x i16>, ptr %__ret.i, align 16
# |   store <8 x i16> %9, ptr %tmp.i, align 16
# |   %10 = load <8 x i16>, ptr %tmp.i, align 16
# |   store <8 x i16> %10, ptr %ref.tmp.i, align 16
# |   %11 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %11, ptr %__ret_561.i, align 16
# |   %12 = load <8 x i16>, ptr %__ret_561.i, align 16
# |   ret <8 x i16> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vmovl_high_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i1 = alloca <4 x i16>, align 8
# |   %__p0_567.addr.i = alloca <8 x i16>, align 16
# |   %__ret_567.i = alloca <4 x i32>, align 16
# |   %__a1_567.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %__s0.i = alloca <4 x i16>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0_567.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0_567.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p0.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <8 x i16> %2, <8 x i16> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
# |   store <4 x i16> %shuffle.i, ptr %__ret.i1, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i1, align 8
# |   store <4 x i16> %4, ptr %__a1_567.i, align 8
# |   %5 = load <4 x i16>, ptr %__a1_567.i, align 8
# |   store <4 x i16> %5, ptr %__s0.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %8 = sext <4 x i16> %7 to <4 x i32>
# |   store <4 x i32> %8, ptr %ref.tmp1.i, align 16
# |   %9 = load <4 x i32>, ptr %ref.tmp1.i, align 16
# |   store <4 x i32> %9, ptr %__ret.i, align 16
# |   %10 = load <4 x i32>, ptr %__ret.i, align 16
# |   store <4 x i32> %10, ptr %tmp.i, align 16
# |   %11 = load <4 x i32>, ptr %tmp.i, align 16
# |   store <4 x i32> %11, ptr %ref.tmp.i, align 16
# |   %12 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %12, ptr %__ret_567.i, align 16
# |   %13 = load <4 x i32>, ptr %__ret_567.i, align 16
# |   ret <4 x i32> %13
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vmovl_high_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i1 = alloca <2 x i32>, align 8
# |   %__p0_564.addr.i = alloca <4 x i32>, align 16
# |   %__ret_564.i = alloca <2 x i64>, align 16
# |   %__a1_564.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %__s0.i = alloca <2 x i32>, align 8
# |   %ref.tmp1.i = alloca <16 x i8>, align 16
# |   %tmp.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0_564.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0_564.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p0.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %shuffle.i = shufflevector <4 x i32> %2, <4 x i32> %3, <2 x i32> <i32 2, i32 3>
# |   store <2 x i32> %shuffle.i, ptr %__ret.i1, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i1, align 8
# |   store <2 x i32> %4, ptr %__a1_564.i, align 8
# |   %5 = load <2 x i32>, ptr %__a1_564.i, align 8
# |   store <2 x i32> %5, ptr %__s0.i, align 8
# |   %6 = load <8 x i8>, ptr %__s0.i, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %8 = sext <2 x i32> %7 to <2 x i64>
# |   store <2 x i64> %8, ptr %ref.tmp1.i, align 16
# |   %9 = load <2 x i64>, ptr %ref.tmp1.i, align 16
# |   store <2 x i64> %9, ptr %__ret.i, align 16
# |   %10 = load <2 x i64>, ptr %__ret.i, align 16
# |   store <2 x i64> %10, ptr %tmp.i, align 16
# |   %11 = load <2 x i64>, ptr %tmp.i, align 16
# |   store <2 x i64> %11, ptr %ref.tmp.i, align 16
# |   %12 = load <2 
# | ...
# `---data was truncated (10240/16529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056365b2cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056365b2c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056365b2cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbecd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbecd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbecd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbecd91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056365b260e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056365b260c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056365b245b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056365aef50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056365aef4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbecd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbecd91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbecd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056365aef4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c (1025 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willret
# | ...
# `---data was truncated (10240/365423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640e78ba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005640e78b70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005640e78ba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06a1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06a10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06a1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06a1031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640e784fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005640e784fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005640e7834b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005640e74e40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005640e74e3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f06a1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06a10330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06a10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640e74e3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c (1026 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/135997) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ec5f2a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562ec5f270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562ec5f2a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b88d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b88d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b88d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b88d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ec5ebfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562ec5ebfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562ec5ea4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562ec5b540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562ec5b53dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6b88d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b88d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b88d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ec5b53cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c (1027 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601597e915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005601597e60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005601597e989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2dad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2dad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2dad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2dad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056015977ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056015977ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560159763b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005601594130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560159412dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa2dad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2dad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2dad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560159412cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c (1028 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %o
# | ...
# `---data was truncated (10240/223855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf3b14315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cf3b1400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cf3b14389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa1fe449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1fe4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa1fe449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa1fe431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf3b0d8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cf3b0d8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cf3b0bdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cf3ad6d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cf3ad6cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa1fe432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1fe4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1fe4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf3ad6ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c (1029 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 0, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 0, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 1, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 1, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 2, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot180_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 2, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 3, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 3, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 1, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %
# | ...
# `---data was truncated (10240/20326) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd9127d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fd9127a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fd9127d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5cf6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5cf678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5cf6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5cf671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd91212e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fd91212c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fd911f7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fd90ea70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fd90ea6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5cf671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5cf671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5cf671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd90ea6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c (1030 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 
# | ...
# `---data was truncated (10240/18225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb65c2b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fb65c280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fb65c2b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a87e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a87ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a87e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a87e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb65bc0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fb65bc0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fb65ba5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fb658550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fb65854dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9a87e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a87e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a87e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb65854cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c (1031 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i1
# | ...
# `---data was truncated (10240/182173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7297ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f7297a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f7297ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5abcb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5abcb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5abcb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5abcb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f729740e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f729740c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f729725b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f7293d50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f7293d4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5abcb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5abcb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5abcb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7293d4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c (1032 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/306025) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639f8b2e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005639f8b2b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005639f8b2e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69cab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69cab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69cab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69caaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639f8ac3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005639f8ac3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005639f8aa8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005639f87580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005639f8757dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f69caaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69caaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69caaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639f8757cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c (1033 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/135345) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055635818315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005563581800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055635818389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d76705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d7675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d76705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d766ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556358118e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556358118c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005563580fdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556357dad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556357dacdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4d766eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d766ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d766ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556357daccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c (1034 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592ca4d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005592ca4d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005592ca4d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b11933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b1198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b11933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b1191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592ca469e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005592ca469c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005592ca44eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005592ca0fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005592ca0fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5b1191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b1191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b1191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592ca0fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c (1035 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vandn_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <v
# | ...
# `---data was truncated (10240/98125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b93942815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b9394250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b93942889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b82933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b8298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b82933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b8291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9393bde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b9393bdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b9393a2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b9390520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b939051dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3b8291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b8291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b8291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b939051cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c (1036 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd
# | ...
# `---data was truncated (10240/58460) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581fdd4115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005581fdd3e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005581fdd4189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ccc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ccc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ccc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ccc631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581fdcd6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005581fdcd6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005581fdcbbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005581fd96b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005581fd96add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0ccc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ccc6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ccc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581fd96acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c (1037 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, 
# | ...
# `---data was truncated (10240/142319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571db9fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005571db9f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005571db9fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ba4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ba478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ba4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ba471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571db990e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005571db990c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005571db975b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005571db6250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005571db624dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6ba471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ba471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ba471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571db624cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c (1038 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632feae515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005632feae20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005632feae589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95fa533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95fa58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95fa533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95fa51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632fea7ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005632fea7ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005632fea5fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005632fe70f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005632fe70edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f95fa51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95fa51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95fa51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632fe70ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/predicates.c (1039 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/predicates.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp16q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.vctp16(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp16q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %3)
# |   %5 = and <8 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp32q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp32q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %3)
# |   %5 = and <4 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp64q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <2 x i1> @llvm.arm.mve.vctp64(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.vctp64(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp64q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <2 x i1> @llvm.arm.mve.vctp64(i32 %3)
# |   %5 = and <2 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp8q(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %0)
# |   %2 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %1)
# |   %3 = trunc i32 %2 to i16
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.vctp8(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp8q_m(i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %4 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %3)
# |   %5 = and <16 x i1> %2, %4
# |   %6 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %5)
# |   %7 = trunc i32 %6 to i16
# |   ret i16 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vpnot(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = xor i16 %0, -1
# |   ret i16 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vpselq_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x half>, ptr %a.addr, align 8
# |   %4 = load <8 x half>, ptr %b.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x half> %3, <8 x half> %4
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vpselq_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x float>, ptr %a.addr, align 8
# |   %4 = load <4 x float>, ptr %b.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x float> %3, <4 x float> %4
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vpselq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x i16> %3, <8 x i16> %4
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vpselq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x i32> %3, <4 x i32> %4
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vpselq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <2 x i64>, ptr %a.addr, align 8
# |   %4 = bitcast <2 x i64> %3 to <4 x i32>
# |   %5 = load <2 x i64>, ptr %b.addr, align 8
# |   %6 = bitcast <2 x i64> %5 to <4 x i32>
# |   %7 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %6
# |   %8 = bitcast <4 x i32> %7 to <2 x i64>
# |   ret <2 x i64> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vpselq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, ali
# | ...
# `---data was truncated (10240/13928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x0000559cac7b015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559cac7ad0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559cac7b089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6226d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6226d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6226d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6226d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559cac745e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559cac745c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559cac72ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559cac3da0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559cac3d9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6226d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6226d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6226d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559cac3d9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c (1040 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noun
# | ...
# `---data was truncated (10240/17567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6dce0415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a6dce010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a6dce0489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2445d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2445d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2445d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2445d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6dcd99e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a6dcd99c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a6dcd7eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a6dca2e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a6dca2ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2445d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2445d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2445d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6dca2dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c (1041 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005574e4cf015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005574e4ced0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005574e4cf089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f392bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f392bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f392bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f392bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005574e4c85e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005574e4c85c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005574e4c6ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005574e491a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005574e4919dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f392bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f392bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f392bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005574e4919cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c (1042 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558968faf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558968fac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558968faf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88aba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88abaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88aba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88aba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558968f44e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558968f44c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558968f29b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558968bd90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558968bd8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f88aba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88aba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88aba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558968bd8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c (1043 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/226585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055857affe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055857affb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055857affe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5674449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56744a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5674449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5674431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055857af93e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055857af93c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055857af78b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055857ac280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055857ac27dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5674432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56744330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56744330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055857ac27cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c (1044 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.
# | ...
# `---data was truncated (10240/128424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561242bab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561242ba80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561242bab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b4d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b4d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b4d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b4d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561242b40e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561242b40c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561242b25b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005612427d50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005612427d4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3b4d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b4d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b4d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612427d4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c (1045 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591a3fc915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005591a3fc60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005591a3fc989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5cd9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5cd918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5cd9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5cd911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591a3f5ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005591a3f5ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005591a3f43b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005591a3bf30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005591a3bf2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5cd911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5cd911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5cd911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591a3bf2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c (1046 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |  
# | ...
# `---data was truncated (10240/81507) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559df825615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559df82530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559df825689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f2a705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f2a75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f2a705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f2a6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559df81ebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559df81ebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559df81d0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559df7e800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559df7e7fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1f2a6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f2a6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f2a6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559df7e7fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c (1047 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align
# | ...
# `---data was truncated (10240/151245) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb9eab915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eb9eab60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eb9eab989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e63449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e634a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e63449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e63431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb9ea4ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eb9ea4ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eb9ea33b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eb9e6e30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eb9e6e2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5e63432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e634330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e634330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb9e6e2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c (1048 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vfmad_lane_f64(double noundef %a, double noundef %b, <1 x double> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca double, align 8
# |   %c.addr = alloca <1 x double>, align 8
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca double, align 8
# |   %__s1 = alloca double, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   store <1 x double> %c, ptr %c.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0, align 8
# |   %1 = load double, ptr %b.addr, align 8
# |   store double %1, ptr %__s1, align 8
# |   %2 = load <1 x double>, ptr %c.addr, align 8
# |   store <1 x double> %2, ptr %__s2, align 8
# |   %3 = load double, ptr %__s0, align 8
# |   %4 = load double, ptr %__s1, align 8
# |   %5 = load <1 x double>, ptr %__s2, align 8
# |   %extract = extractelement <1 x double> %5, i32 0
# |   %6 = call double @llvm.fma.f64(double %4, double %extract, double %3)
# |   store double %6, ptr %ref.tmp, align 8
# |   %7 = load double, ptr %ref.tmp, align 8
# |   store double %7, ptr %__ret, align 8
# |   %8 = load double, ptr %__ret, align 8
# |   store double %8, ptr %tmp, align 8
# |   %9 = load double, ptr %tmp, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare double @llvm.fma.f64(double, double, double) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vfmad_laneq_f64(double noundef %a, double noundef %b, <2 x double> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca double, align 8
# |   %b.addr = alloca double, align 8
# |   %c.addr = alloca <2 x double>, align 16
# |   %__ret = alloca double, align 8
# |   %__s0 = alloca double, align 8
# |   %__s1 = alloca double, align 8
# |   %__s2 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca double, align 8
# |   %tmp = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   store <2 x double> %c, ptr %c.addr, align 16
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__s0, align 8
# |   %1 = load double, ptr %b.addr, align 8
# |   store double %1, ptr %__s1, align 8
# |   %2 = load <2 x double>, ptr %c.addr, align 16
# |   store <2 x double> %2, ptr %__s2, align 16
# |   %3 = load double, ptr %__s0, align 8
# |   %4 = load double, ptr %__s1, align 8
# |   %5 = load <2 x double>, ptr %__s2, align 16
# |   %extract = extractelement <2 x double> %5, i32 1
# |   %6 = call double @llvm.fma.f64(double %4, double %extract, double %3)
# |   store double %6, ptr %ref.tmp, align 8
# |   %7 = load double, ptr %ref.tmp, align 8
# |   store double %7, ptr %__ret, align 8
# |   %8 = load double, ptr %__ret, align 8
# |   store double %8, ptr %tmp, align 8
# |   %9 = load double, ptr %tmp, align 8
# |   ret double %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vfmss_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca float, align 4
# |   %c.addr = alloca <2 x float>, align 8
# |   %__ret_443 = alloca float, align 4
# |   %__s0_443 = alloca float, align 4
# |   %__s1_443 = alloca float, align 4
# |   %__s2_443 = alloca <2 x float>, align 8
# |   %__ret = alloca float, align 4
# |   %__s0 = alloca float, align 4
# |   %__s1 = alloca float, align 4
# |   %__s2 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca float, align 4
# |   %tmp = alloca float, align 4
# |   %tmp1 = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   store float %b, ptr %b.addr, align 4
# |   store <2 x float> %c, ptr %c.addr, align 8
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__s0_443, align 4
# |   %1 = load float, ptr %b.addr, align 4
# |   store float %1, ptr %__s1_443, align 4
# |   %2 = load <2 x float>, ptr %c.addr, align 8
# |   store <2 x float> %2, ptr %__s2_443, align 8
# |   %3 = load float, ptr %__s0_443, align 4
# |   store float %3, ptr %__s0, align 4
# |   %4 = load float, ptr %__s1_443, align 4
# |   %fneg = fneg float %4
# |   store float %fneg, ptr %__s1, align 4
# |   %5 = load <2 x float>, ptr %__s2_443, align 8
# |   store <2 x float> %5, ptr %__s2, align 8
# |   %6 = load float, ptr %__s0, align 4
# |   %7 = load float, ptr %__s1, align 4
# |   %8 = load <2 x float>, ptr %__s2, align 8
# |   %extract = extractelement <2 x float> %8, i32 1
# |   %9 = call float @llvm.fma.f32(float %7, float %extract, float %6)
# |   store float %9, ptr %ref.tmp, align 4
# |   %10 = load float, ptr %ref.tmp, align 4
# |   store float %10, ptr %__ret, align 4
# |   %11 = load float, ptr %__ret, align 4
# |   store float %11, ptr %tmp, align 4
# |   %12 = load float, ptr %tmp, align 4
# |   store float %12, ptr %__ret_443, align 4
# |   %13 = load float, ptr %__ret_443, align 4
# |   store float %13, ptr %tmp1, align 4
# |   %14 = load float, ptr %tmp1, align 4
# |   ret float %14
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare float @llvm.fma.f32(float, float, float) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %v, ptr %v.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1, align 8
# |   %2 = load <1 x double>, ptr %v.addr, align 8
# |   store <1 x double> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <1 x double>
# |   %lane = shufflevector <1 x double> %6, <1 x double> %6, <1 x i32> zeroinitializer
# |   %fmla = bitcast <8 x i8> %4 to <1 x double>
# |   %fmla1 = bitcast <8 x i8> %3 to <1 x double>
# |   %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1)
# |   store <1 x double> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %7, ptr %__ret, align 8
# |   %8 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %8, ptr %tmp, align 8
# |   %9 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfms_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <1 x double>, align 8
# |   %__ret_449 = alloca <1 x double>, align 8
# |   %__s0_449 = alloca <1 x double>, align 8
# |   %__s1_449 = alloca <1 x double>, align 8
# |   %__s2_449 = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   %tmp3 = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %v, ptr %v.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0_449, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1_449, align 8
# |   %2 = load <1 x double>, ptr %v.addr, align 8
# |   store <1 x double> %2, ptr %__s2_449, align 8
# |   %3 = load <1 x double>, ptr %__s0_449, align 8
# |   store <1 x double> %3, ptr %__s0, align 8
# |   %4 = load <1 x double>, ptr %__s1_449, align 8
# |   %fneg = fneg <1 x double> %4
# |   store <1 x double> %fneg, ptr %__s1, align 8
# |   %5 = load <1 x double>, ptr %__s2_449, align 8
# |   store <1 x double> %5, ptr %__s2, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = load <8 x i8>, ptr %__s1, align 8
# |   %8 = load <8 x i8>, ptr %__s2, align 8
# |   %9 = bitcast <8 x i8> %8 to <1 x double>
# |   %lane = shufflevector <1 x double> %9, <1 x double> %9, <1 x i32> zeroinitializer
# |   %fmla = bitcast <8 x i8> %7 to <1 x double>
# |   %fmla1 = bitcast <8 x i8> %6 to <1 x double>
# |   %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1)
# |   store <1 x double> %fmla2, ptr %ref.tmp, align 8
# |   %10 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %10, ptr %__ret, align 8
# |   %11 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %11, ptr %tmp, align 8
# |   %12 = load <1 x double>, ptr %tmp, align 8
# |   store <1 x double> %12, ptr %__ret_449, align 8
# |   %13 = load <1 x double>, ptr %__ret_449, align 8
# |   store <1 x double> %13, ptr %tmp3, align 8
# |   %14 = load <1 x double>, ptr %tmp3, align 8
# |   ret <1 x double> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfms_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <2 x double>, align 16
# |   %__ret_460 = alloca <1 x double>, align 8
# |   %__s0_460 = alloca <1 x double>, align 8
# |   %__s1_460 = alloca <1 x double>, align 8
# |   %__s2_460 = alloca <2 x double>, align 16
# |   %__ret = alloca <1 x double>, align 8
# |   %_
# | ...
# `---data was truncated (10240/12799) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055b7e30ac15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b7e30a90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b7e30ac89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f372da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f372daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f372da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f372da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7e3041e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b7e3041c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b7e3026b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b7e2cd60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b7e2cd5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f372da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f372da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f372da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7e2cd5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c (1049 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_x_i8mf8(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_x_i8mf4(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_x_i8mf2(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_x_i8m1(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_x_i8m2(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_x_i8m4(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i64(<vscale x 32 x i8> poison, i8 %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i64(<vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vmv_v_v_i8m8(<vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vmv_v_x_i8m8(i8 noundef signext %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i8 %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i8, ptr %src.addr, align 1
# |   %1 = load
# | ...
# `---data was truncated (10240/121927) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639cd7a115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005639cd79e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005639cd7a189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8299d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8299d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8299d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8299d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639cd736e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005639cd736c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005639cd71bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005639cd3cb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005639cd3cadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8299d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8299d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8299d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639cd3cacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c (1050 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset4_s8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %5, 1
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svset4_s16(<vscale x 8 x i16> %tuple.coerce0, <vscale x 8 x i16> %tuple.coerce1, <vscale x 8 x i16> %tuple.coerce2, <vscale x 8 x i16> %tuple.coerce3, <vscale x 8 x i16> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %tuple.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %x.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %1, <vscale x 8 x i16> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %2, <vscale x 8 x i16> %tuple.coerce3, 3
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 8 x i16> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 8 x i16>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %5, 3
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svset4_s32(<vscale x 4 x i32> %tuple.coerce0, <vscale x 4 x i32> %tuple.coerce1, <vscale x 4 x i32> %tuple.coerce2, <vscale x 4 x i32> %tuple.coerce3, <vscale x 4 x i32> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %tuple.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %x.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %1, <vscale x 4 x i32> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %2, <vscale x 4 x i32> %tuple.coerce3, 3
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 4 x i32> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 4 x i32>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %5, 1
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svset4_s64(<vscale x 2 x i64> %tuple.coerce0, <vscale x 2 x i64> %tuple.coerce1, <vscale x 2 x i64> %tuple.coerce2, <vscale x 2 x i64> %tuple.coerce3, <vscale x 2 x i64> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %tuple.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %x.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, <vscale x 2 x i64> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %2, <vscale x 2 x i64> %tuple.coerce3, 3
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 2 x i64> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 2 x i64>, ptr %x.addr, align 16
# |   %6 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %5, 1
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svset4_u8(<vscale x 16 x i8> %tuple.coerce0, <vscale x 16 x i8> %tuple.coerce1, <vscale x 16 x i8> %tuple.coerce2, <vscale x 16 x i8> %tuple.coerce3, <vscale x 16 x i8> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %tuple.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %x.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %1, <vscale x 16 x i8> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %2, <vscale x 16 x i8> %tuple.coerce3, 3
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %3, ptr %tuple, align 16
# |   %tuple1 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %tuple1, ptr %tuple.addr, align 16
# |   store <vscale x 16 x i8> %x, ptr %x.addr, align 16
# |   %4 = load { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %tuple.addr, align 16
# |   %5 = load <vscale x 16 x i8>, ptr %x.addr, align 16
# | ...
# `---data was truncated (10240/34217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e1d3e1715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e1d3e140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e1d3e1789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6da5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6da5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6da5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6da5c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1d3dace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e1d3dacc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e1d3d91b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e1d3a410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e1d3a40dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6da5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6da5c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6da5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1d3a40cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c (1051 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vmlalb(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlal.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vmlal1.i = call <8 x half> @llvm.aarch64.neon.fp8.fmlalb.v8f16(<8 x half> %vmlal.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %vmlal1.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vmlalt(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <8 x half>, align 16
# |   %vd.addr = alloca <8 x half>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <8 x half> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <8 x half>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlal.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vmlal1.i = call <8 x half> @llvm.aarch64.neon.fp8.fmlalt.v8f16(<8 x half> %vmlal.i, <16 x i8> %5, <16 x i8> %6)
# |   store <8 x half> %vmlal1.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlallbb(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbb.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlallbt(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbt.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlalltb(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltb.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmlalltt(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %vd.addr = alloca <4 x float>, align 16
# |   %vn.addr = alloca <16 x i8>, align 16
# |   %vm.addr = alloca <16 x i8>, align 16
# |   %fpm.addr = alloca i64, align 8
# |   store <4 x float> %vd, ptr %vd.addr, align 16
# |   store <16 x i8> %vn, ptr %vn.addr, align 16
# |   store <16 x i8> %vm, ptr %vm.addr, align 16
# |   store i64 %fpm, ptr %fpm.addr, align 8
# |   %0 = load <4 x float>, ptr %vd.addr, align 16
# |   %1 = load <16 x i8>, ptr %vn.addr, align 16
# |   %2 = load <16 x i8>, ptr %vm.addr, align 16
# |   %3 = load i64, ptr %fpm.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 
# | ...
# `---data was truncated (10240/35980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x00005579e271815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005579e27150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005579e271889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3015e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3015ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3015e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3015e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579e26ade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005579e26adc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005579e2692b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005579e23420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005579e2341dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3015e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3015e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3015e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579e2341cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c (1052 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e0ff3815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556e0ff350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556e0ff3889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ae5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ae5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ae5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ae5b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e0fecde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556e0fecdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556e0feb2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556e0fb620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556e0fb61dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8ae5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ae5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ae5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e0fb61cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c (1053 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_s8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.zip1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_s16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.zip1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_s32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.zip1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_s64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.zip1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svzip1_u8(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svzip1_u16(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svzip1_u32(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svzip1_u64(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svzip1_f16(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 16
# |   %op2.addr = alloca <vscale x 8 x half>, align 16
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 8 x half> @llvm.aarch64.sve.zip1.nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.zip1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svzip1_f32(<vscale x 4 x float> %op1, <vscale x 4 x float> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 16
# |   %op2.addr = alloca <vscale x 4 x float>, align 16
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x float> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 4 x float>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 4 x float> @llvm.aarch64.sve.zip1.nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.zip1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svzip1_f64(<vscale x 2 x double> %op1, <vscale x 2 x double> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 16
# |   %op2.addr = alloca <vscale x 2 x double>, align 16
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x double> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 2 x double>, ptr %op1.addr, align 16
# |   %1 = load <vscale x 2 x double>, ptr %op2.addr, align 16
# |   %2 = call <vscale x 2 x double> @llvm.aarch64.sve.zip1.nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.zip1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip1_b8(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.zip1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svzip1_b16(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.zip1.b16(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1)
# |   ret <vscale x 16 x i1> %2
# | ...
# `---data was truncated (10240/13404) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005562a4c8515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005562a4c820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005562a4c8589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f960b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f960b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f960b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f960b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562a4c1ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005562a4c1ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005562a4bffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005562a48af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005562a48aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f960b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f960b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f960b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562a48aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c (1054 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.bf16.nxv
# | ...
# `---data was truncated (10240/51702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a871b3315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a871b300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a871b3389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9ea21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9ea2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9ea21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9ea203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a871ac8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a871ac8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a871aadb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a87175d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a87175cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe9ea204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9ea2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9ea2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a87175ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c (1055 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 
# | ...
# `---data was truncated (10240/215949) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612df9aa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005612df9a70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005612df9aa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0aff733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0aff78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0aff733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0aff71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612df93fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005612df93fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005612df924b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005612df5d40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005612df5d3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0aff71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0aff71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0aff71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612df5d3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c (1056 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bce11f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bce11f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bce11f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd435105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd43515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd435105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4350ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bce118de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bce118dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bce1172b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bce0e220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bce0e21dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd4350eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4350ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4350ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bce0e21cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c (1057 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1c10c015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d1c10bd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d1c10c089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcce3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcce378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcce3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcce371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1c1055e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d1c1055c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d1c103ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d1c0cea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d1c0ce9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcce371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcce371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcce371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1c0ce9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c (1058 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b744d2b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b744d280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b744d2b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe0d6049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0d60a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe0d6049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0d6031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b744cc0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b744cc0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b744ca5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b7449550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b744954dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe0d6032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0d60330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0d60330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b744954cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c (1059 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x
# | ...
# `---data was truncated (10240/112817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8ae95e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c8ae95b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c8ae95e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcdef905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcdef95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcdef905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcdef8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8ae8f3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c8ae8f3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c8ae8d8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c8ae5880b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c8ae587dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcdef8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcdef8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcdef8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8ae587cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c (1060 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/113039) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056156da6715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056156da640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056156da6789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f82333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f8238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f82333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f8231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056156d9fce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056156d9fcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056156d9e1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056156d6910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056156d690dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3f8231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f8231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f8231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056156d690cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c (1061 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vzext_vf2_u16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vzext_vf2_u16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vzext_vf2_u16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vzext_vf2_u16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vzext_vf2_u16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vzext_vf2_u16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf2_u32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf2_u32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf2_u32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf2_u32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf2_u32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf2_u64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf2_u64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>,
# | ...
# `---data was truncated (10240/28571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b905de615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b905de30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b905de689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fec649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fec6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fec649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fec631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b905d7be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b905d7bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b905d60b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b905a100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b905a0fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4fec632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fec6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fec6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b905a0fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c (1062 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = l
# | ...
# `---data was truncated (10240/23247) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055755869a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005575586970f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055755869a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe75c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe75c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe75c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe75c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055755862fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055755862fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557558614b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005575582c40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005575582c3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe75c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe75c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe75c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575582c3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c (1063 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 31)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.cntb(i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_1() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_2() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_3() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_4() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 4)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_5() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_6() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_7() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_8() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 8)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_9() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 9)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_10() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 10)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_11() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 11)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_12() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 12)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_13() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 13)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_14() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 29)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_15() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 30)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svcntb_pat_16() #0 {
# | entry:
# |   %0 = call i64 @llvm.aarch64.sve.cntb(i32 31)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x0000561c5131815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561c513150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561c5131889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdad3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdad3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdad3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdad3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c512ade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561c512adc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561c51292b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561c50f420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561c50f41dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdad3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdad3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdad3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c50f41cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c (1064 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563368d5815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563368d550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563368d5889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f11f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f11f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f11f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f11eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563368cede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563368cedc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563368cd2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005633689820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563368981dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4f11eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f11eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f11eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563368981cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c (1065 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056412346215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056412345f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056412346289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b18b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b18b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b18b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b18b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641233f7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005641233f7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005641233dcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056412308c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056412308bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5b18b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b18b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b18b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056412308bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c (1066 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local target("aarch64.svcount") @test_svpfalse_c() #0 {
# | entry:
# |   ret target("aarch64.svcount") zeroinitializer
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055969b3f715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055969b3f40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055969b3f789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ec0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ec08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ec0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ec0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055969b38ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055969b38cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055969b371b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055969b0210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055969b020dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8ec0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ec08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ec08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055969b020cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c (1067 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llv
# | ...
# `---data was truncated (10240/101576) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b5de7e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558b5de7b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558b5de7e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a2d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a2d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a2d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a2d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b5de13e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558b5de13c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558b5ddf8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558b5daa80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558b5daa7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1a2d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a2d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a2d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b5daa7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c (1068 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv
# | ...
# `---data was truncated (10240/53548) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ea884615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559ea88430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559ea884689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c6ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c6ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c6ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c6ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ea87dbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559ea87dbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559ea87c0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559ea84700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559ea846fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4c6ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c6ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c6ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ea846fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c (1069 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate4_s8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2, <vscale x 16 x i8> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   %x4.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   store <vscale x 16 x i8> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %1, 1
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, <vscale x 16 x i8> %2, 2
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %3, 3
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate4_s16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2, <vscale x 8 x i16> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   %x4.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   store <vscale x 8 x i16> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %3, 3
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate4_s32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2, <vscale x 4 x i32> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   %x4.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vscale x 4 x i32> %x2, ptr %x2.addr, align 16
# |   store <vscale x 4 x i32> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 4 x i32>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 4 x i32>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %0, 0
# |   %5 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %4, <vscale x 4 x i32> %1, 1
# |   %6 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %5, <vscale x 4 x i32> %2, 2
# |   %7 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %6, <vscale x 4 x i32> %3, 3
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svcreate4_s64(<vscale x 2 x i64> %x0, <vscale x 2 x i64> %x1, <vscale x 2 x i64> %x2, <vscale x 2 x i64> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 2 x i64>, align 16
# |   %x1.addr = alloca <vscale x 2 x i64>, align 16
# |   %x2.addr = alloca <vscale x 2 x i64>, align 16
# |   %x4.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %x0, ptr %x0.addr, align 16
# |   store <vscale x 2 x i64> %x1, ptr %x1.addr, align 16
# |   store <vscale x 2 x i64> %x2, ptr %x2.addr, align 16
# |   store <vscale x 2 x i64> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 2 x i64>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 2 x i64>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %0, 0
# |   %5 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %4, <vscale x 2 x i64> %1, 1
# |   %6 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %5, <vscale x 2 x i64> %2, 2
# |   %7 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %6, <vscale x 2 x i64> %3, 3
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svcreate4_u8(<vscale x 16 x i8> %x0, <vscale x 16 x i8> %x1, <vscale x 16 x i8> %x2, <vscale x 16 x i8> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 16 x i8>, align 16
# |   %x1.addr = alloca <vscale x 16 x i8>, align 16
# |   %x2.addr = alloca <vscale x 16 x i8>, align 16
# |   %x4.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %x0, ptr %x0.addr, align 16
# |   store <vscale x 16 x i8> %x1, ptr %x1.addr, align 16
# |   store <vscale x 16 x i8> %x2, ptr %x2.addr, align 16
# |   store <vscale x 16 x i8> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 16 x i8>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 16 x i8>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %0, 0
# |   %5 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %4, <vscale x 16 x i8> %1, 1
# |   %6 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %5, <vscale x 16 x i8> %2, 2
# |   %7 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %6, <vscale x 16 x i8> %3, 3
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svcreate4_u16(<vscale x 8 x i16> %x0, <vscale x 8 x i16> %x1, <vscale x 8 x i16> %x2, <vscale x 8 x i16> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 8 x i16>, align 16
# |   %x1.addr = alloca <vscale x 8 x i16>, align 16
# |   %x2.addr = alloca <vscale x 8 x i16>, align 16
# |   %x4.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %x0, ptr %x0.addr, align 16
# |   store <vscale x 8 x i16> %x1, ptr %x1.addr, align 16
# |   store <vscale x 8 x i16> %x2, ptr %x2.addr, align 16
# |   store <vscale x 8 x i16> %x4, ptr %x4.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %x0.addr, align 16
# |   %1 = load <vscale x 8 x i16>, ptr %x1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %x2.addr, align 16
# |   %3 = load <vscale x 8 x i16>, ptr %x4.addr, align 16
# |   %4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %0, 0
# |   %5 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %4, <vscale x 8 x i16> %1, 1
# |   %6 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %5, <vscale x 8 x i16> %2, 2
# |   %7 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %6, <vscale x 8 x i16> %3, 3
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %7
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svcreate4_u32(<vscale x 4 x i32> %x0, <vscale x 4 x i32> %x1, <vscale x 4 x i32> %x2, <vscale x 4 x i32> %x4) #0 {
# | entry:
# |   %x0.addr = alloca <vscale x 4 x i32>, align 16
# |   %x1.addr = alloca <vscale x 4 x i32>, align 16
# |   %x2.addr = alloca <vscale x 4 x i32>, align 16
# |   %x4.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %x0, ptr %x0.addr, align 16
# |   store <vscale x 4 x i32> %x1, ptr %x1.addr, align 16
# |   store <vs
# | ...
# `---data was truncated (10240/21212) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000558a0d64415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558a0d6410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558a0d64489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdde5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdde54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdde5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdde5431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a0d5d9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558a0d5d9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558a0d5beb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558a0d26e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558a0d26ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdde5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdde54330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdde54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a0d26dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c (1070 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055729e98d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055729e98a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055729e98d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f7e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f7e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f7e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f7e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055729e922e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055729e922c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055729e907b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055729e5b70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055729e5b6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9f7e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f7e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f7e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055729e5b6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c (1071 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8f70f715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a8f70f40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a8f70f789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe474d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe474d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe474d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe474d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8f708ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a8f708cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a8f7071b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a8f6d210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a8f6d20dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe474d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe474d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe474d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8f6d20cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c (1072 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree no
# | ...
# `---data was truncated (10240/13023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567f3c8515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005567f3c820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005567f3c8589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f049b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f049b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f049b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f049b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567f3c1ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005567f3c1ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005567f3bffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005567f38af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005567f38aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f049b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f049b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f049b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567f38aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c (1073 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc1d69715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cc1d6940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cc1d69789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe15ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe15ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe15ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe15ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc1d62ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cc1d62cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cc1d611b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cc1d2c10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cc1d2c0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe15ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe15ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe15ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc1d2c0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon/rounding.c (1074 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/rounding.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrnd_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndz.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndz1.i = call <2 x float> @llvm.trunc.v2f32(<2 x float> %vrndz.i)
# |   store <2 x float> %vrndz1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndz.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndz1.i = call <4 x float> @llvm.trunc.v4f32(<4 x float> %vrndz.i)
# |   store <4 x float> %vrndz1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrnd_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndz.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrndz1.i = call <1 x double> @llvm.trunc.v1f64(<1 x double> %vrndz.i)
# |   store <1 x double> %vrndz1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndz.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrndz1.i = call <2 x double> @llvm.trunc.v2f64(<2 x double> %vrndz.i)
# |   store <2 x double> %vrndz1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndn_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndn.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndn1.i = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %vrndn.i)
# |   store <2 x float> %vrndn1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndn.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndn1.i = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %vrndn.i)
# |   store <4 x float> %vrndn1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrndn_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndn.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrndn1.i = call <1 x double> @llvm.roundeven.v1f64(<1 x double> %vrndn.i)
# |   store <1 x double> %vrndn1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndnq_f64(<2 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndn.i = bitcast <16 x i8> %1 to <2 x double>
# |   %vrndn1.i = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %vrndn.i)
# |   store <2 x double> %vrndn1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vrndns_f32(float noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__ret.i = alloca float, align 4
# |   %ref.tmp.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__p0.addr.i, align 4
# |   %1 = load float, ptr %__p0.addr.i, align 4
# |   %vrndn.i = call float @llvm.roundeven.f32(float %1)
# |   store float %vrndn.i, ptr %ref.tmp.i, align 4
# |   %2 = load float, ptr %ref.tmp.i, align 4
# |   store float %2, ptr %__ret.i, align 4
# |   %3 = load float, ptr %__ret.i, align 4
# |   ret float %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndm_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndm.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndm1.i = call <2 x float> @llvm.floor.v2f32(<2 x float> %vrndm.i)
# |   store <2 x float> %vrndm1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vrndm.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndm1.i = call <4 x float> @llvm.floor.v4f32(<4 x float> %vrndm.i)
# |   store <4 x float> %vrndm1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vrndm_f64(<1 x double> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndm.i = bitcast <8 x i8> %1 to <1 x double>
# |   %vrndm1.i = call <1 x double> @llvm.floor.v1f64(<1 x double> %vrndm.i)
# |   store <1 x double> %vrndm1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vrndmq_f64(<2 x double> noundef %a
# | ...
# `---data was truncated (10240/29785) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056331b1d215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056331b1cf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056331b1d289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbea2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbea24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbea2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbea2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056331b167e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056331b167c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056331b14cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056331adfc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056331adfbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbea2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbea24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbea24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056331adfbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c (1075 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_u8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b048ffb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b048ff80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b048ffb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd0c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd0c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd0c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd0c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b048f90e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b048f90c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b048f75b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b048c250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b048c24dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdd0c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd0c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd0c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b048c24cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c (1076 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559dd827a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559dd82770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559dd827a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f096f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f096f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f096f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f096f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559dd820fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559dd820fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559dd81f4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559dd7ea40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559dd7ea3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f096f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f096f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f096f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559dd7ea3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c (1077 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.mask.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | de
# | ...
# `---data was truncated (10240/12091) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559740dde15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559740ddb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559740dde89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f798b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f798b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f798b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f798b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559740d73e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559740d73c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559740d58b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559740a080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559740a07dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f798b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f798b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f798b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559740a07cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c (1078 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1ub_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite)
# | declare <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1>, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 8 x i8> %3 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 4 x i8> %3 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1ub_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %2, ptr %1)
# |   %4 = zext <vscale x 2 x i8> %3 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.nxv4i8.p0(<vscale x 4 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 4 x i8> %5 to <vscale x 4 x i32>
# |   ret <vscale x 4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svldff1ub_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.nxv2i8.p0(<vscale x 2 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 2 x i8> %5 to <vscale x 2 x i64>
# |   ret <vscale x 2 x i64> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svldff1ub_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %5 = call <vscale x 8 x i8> @llvm.aarch64.sve.ldff1.nxv8i8.p0(<vscale x 8 x i1> %3, ptr %4)
# |   %6 = zext <vscale x 8 x i8> %5 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svldff1ub_vnum_u32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = getelementptr <vscale x 4 x
# | ...
# `---data was truncated (10240/28299) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055e1f54a515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e1f54a20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e1f54a589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02a0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02a0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02a0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02a0e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1f543ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e1f543ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e1f541fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e1f50cf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e1f50cedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f02a0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02a0e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02a0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1f50cecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/thinlto_embed_bitcode.ll (1079 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto_embed_bitcode.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc
# |  #0 0x0000563935b2415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563935b210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563935b2489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50b8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50b86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50b8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50b8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563935ab9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563935ab9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563935a9eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056393574e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056393574ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f50b8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50b86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50b86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056393574dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c (1080 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5c08bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f5c08ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f5c08bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f972aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f972aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f972aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f972aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5c0852e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f5c0852c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f5c0837b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f5c04e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f5c04e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f972aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f972aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f972aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5c04e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c (1081 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i8 @test_vsqaddb_u8() #0 {
# | entry:
# |   %__p0.addr.i = alloca i8, align 1
# |   %__p1.addr.i = alloca i8, align 1
# |   %__ret.i = alloca i8, align 1
# |   %ref.tmp.i = alloca i8, align 1
# |   store i8 1, ptr %__p0.addr.i, align 1
# |   store i8 -1, ptr %__p1.addr.i, align 1
# |   %0 = load i8, ptr %__p0.addr.i, align 1
# |   %1 = load i8, ptr %__p1.addr.i, align 1
# |   %2 = insertelement <8 x i8> poison, i8 %0, i64 0
# |   %3 = insertelement <8 x i8> poison, i8 %1, i64 0
# |   %vsqaddb_u8.i = call <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8> %2, <8 x i8> %3)
# |   %4 = extractelement <8 x i8> %vsqaddb_u8.i, i64 0
# |   store i8 %4, ptr %ref.tmp.i, align 1
# |   %5 = load i8, ptr %ref.tmp.i, align 1
# |   store i8 %5, ptr %__ret.i, align 1
# |   %6 = load i8, ptr %__ret.i, align 1
# |   ret i8 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vsqaddh_u16() #0 {
# | entry:
# |   %__p0.addr.i = alloca i16, align 2
# |   %__p1.addr.i = alloca i16, align 2
# |   %__ret.i = alloca i16, align 2
# |   %ref.tmp.i = alloca i16, align 2
# |   store i16 1, ptr %__p0.addr.i, align 2
# |   store i16 -1, ptr %__p1.addr.i, align 2
# |   %0 = load i16, ptr %__p0.addr.i, align 2
# |   %1 = load i16, ptr %__p1.addr.i, align 2
# |   %2 = insertelement <4 x i16> poison, i16 %0, i64 0
# |   %3 = insertelement <4 x i16> poison, i16 %1, i64 0
# |   %vsqaddh_u16.i = call <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16> %2, <4 x i16> %3)
# |   %4 = extractelement <4 x i16> %vsqaddh_u16.i, i64 0
# |   store i16 %4, ptr %ref.tmp.i, align 2
# |   %5 = load i16, ptr %ref.tmp.i, align 2
# |   store i16 %5, ptr %__ret.i, align 2
# |   %6 = load i16, ptr %__ret.i, align 2
# |   ret i16 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vsqadds_u32() #0 {
# | entry:
# |   %__p0.addr.i = alloca i32, align 4
# |   %__p1.addr.i = alloca i32, align 4
# |   %__ret.i = alloca i32, align 4
# |   %ref.tmp.i = alloca i32, align 4
# |   store i32 1, ptr %__p0.addr.i, align 4
# |   store i32 -1, ptr %__p1.addr.i, align 4
# |   %0 = load i32, ptr %__p0.addr.i, align 4
# |   %1 = load i32, ptr %__p1.addr.i, align 4
# |   %vsqadds_u32.i = call i32 @llvm.aarch64.neon.usqadd.i32(i32 %0, i32 %1)
# |   store i32 %vsqadds_u32.i, ptr %ref.tmp.i, align 4
# |   %2 = load i32, ptr %ref.tmp.i, align 4
# |   store i32 %2, ptr %__ret.i, align 4
# |   %3 = load i32, ptr %__ret.i, align 4
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_vsqaddd_u64() #0 {
# | entry:
# |   %__p0.addr.i = alloca i64, align 8
# |   %__p1.addr.i = alloca i64, align 8
# |   %__ret.i = alloca i64, align 8
# |   %ref.tmp.i = alloca i64, align 8
# |   store i64 1, ptr %__p0.addr.i, align 8
# |   store i64 -1, ptr %__p1.addr.i, align 8
# |   %0 = load i64, ptr %__p0.addr.i, align 8
# |   %1 = load i64, ptr %__p1.addr.i, align 8
# |   %vsqaddd_u64.i = call i64 @llvm.aarch64.neon.usqadd.i64(i64 %0, i64 %1)
# |   store i64 %vsqaddd_u64.i, ptr %ref.tmp.i, align 8
# |   %2 = load i64, ptr %ref.tmp.i, align 8
# |   store i64 %2, ptr %__ret.i, align 8
# |   %3 = load i64, ptr %__ret.i, align 8
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8>, <8 x i8>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16>, <4 x i16>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.neon.usqadd.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.aarch64.neon.usqadd.i64(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce
# |  #0 0x0000557bf34d015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557bf34cd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557bf34d089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5534249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55342a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5534249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5534231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557bf3465e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557bf3465c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557bf344ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557bf30fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557bf30f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5534232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55342330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55342330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557bf30f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c (1082 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float>, ha
# | ...
# `---data was truncated (10240/90685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c46062615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c4606230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c46062689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d0061bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d006725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d0061ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d00603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4605bbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c4605bbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c4605a0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c4602500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c46024fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1d00604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d006050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d006050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c46024fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c (1083 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   
# | ...
# `---data was truncated (10240/135119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0b36ff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c0b36fc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c0b36ff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4067449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40674a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4067449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4067431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0b3694e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c0b3694c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c0b3679b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c0b33290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c0b3328dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4067432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40674330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40674330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0b3328cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c (1084 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca11fe215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ca11fdf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ca11fe289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55aac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55aaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55aac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55aac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca11f77e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ca11f77c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ca11f5cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ca11c0c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ca11c0bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f55aac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55aac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55aac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca11c0bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c (1085 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/60334) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f9c77215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559f9c76f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559f9c77289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feeade49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feeadea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feeade49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feeade31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f9c707e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559f9c707c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559f9c6ecb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559f9c39c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559f9c39bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feeade32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feeade330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feeade330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f9c39bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c (1086 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef
# | ...
# `---data was truncated (10240/78336) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aba513b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aba51380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aba513b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f072be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f072bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f072be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f072be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aba50d0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aba50d0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aba50b5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aba4d650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aba4d64dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f072be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f072be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f072be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aba4d64cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c (1087 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x
# | ...
# `---data was truncated (10240/208199) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055575000715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005557500040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055575000789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9deb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9deb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9deb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9deb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055574ff9ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055574ff9cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055574ff81b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055574fc310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055574fc30dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd9deb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9deb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9deb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055574fc30cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c (1088 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 
# | ...
# `---data was truncated (10240/118164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ebe278d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ebe278a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ebe278d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc9b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc9b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc9b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc9b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebe2722e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ebe2722c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ebe2707b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ebe23b70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ebe23b6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdc9b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc9b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc9b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebe23b6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c (1089 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svreinterpret_svbool_svcnt(target("aarch64.svcount") %cnt) #0 {
# | entry:
# |   %cnt.addr = alloca target("aarch64.svcount"), align 2
# |   store target("aarch64.svcount") %cnt, ptr %cnt.addr, align 2
# |   %0 = load target("aarch64.svcount"), ptr %cnt.addr, align 2
# |   %1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.from.svcount(target("aarch64.svcount") %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.from.svcount(target("aarch64.svcount")) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local target("aarch64.svcount") @test_svreinterpret_svcnt_svbool(<vscale x 16 x i1> %pg) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = call target("aarch64.svcount") @llvm.aarch64.sve.convert.to.svcount(<vscale x 16 x i1> %0)
# |   ret target("aarch64.svcount") %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("aarch64.svcount") @llvm.aarch64.sve.convert.to.svcount(<vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x0000555c4be8815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555c4be850f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555c4be8889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4956049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49560a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4956049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4956031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c4be1de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555c4be1dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555c4be02b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555c4bab20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555c4bab1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4956032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49560330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49560330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c4bab1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c (1090 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b16_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b32_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b64_s32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilels.nxv16i1.i32(i32 %0, i32 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilels.nxv16i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b16_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilels.nxv8i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilels.nxv8i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b32_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilels.nxv4i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilels.nxv4i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b64_u32(i32 noundef %op1, i32 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i32, align 4
# |   %op2.addr = alloca i32, align 4
# |   store i32 %op1, ptr %op1.addr, align 4
# |   store i32 %op2, ptr %op2.addr, align 4
# |   %0 = load i32, ptr %op1.addr, align 4
# |   %1 = load i32, ptr %op2.addr, align 4
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilels.nxv2i1.i32(i32 %0, i32 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilels.nxv2i1.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i64(i64 %0, i64 %1)
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svwhilele_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 {
# | entry:
# |   %op1.addr = alloca i64, align 8
# |   %op2.addr = alloca i64, align 8
# |   store i64 %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   %0 = load i64, ptr %op1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/13340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000557276bac15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557276ba90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557276bac89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ab4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ab4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ab4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ab4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557276b41e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557276b41c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557276b26b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005572767d60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005572767d5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2ab4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ab4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ab4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572767d5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c (1091 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb42e7c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fb42e790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fb42e7c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c42933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c4298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c42933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c4291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb42e11e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fb42e11c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fb42df6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fb42aa60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fb42aa5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6c4291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c4291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c4291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb42aa5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c (1092 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a524bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561a524ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561a524bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0444f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0444f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0444f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0444f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a52452e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561a52452c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561a52437b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561a520e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561a520e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0444f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0444f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0444f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a520e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c (1093 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a887d015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560a887cd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560a887d089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce21133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce2118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce21133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce2111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a88765e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560a88765c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560a8874ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560a883fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560a883f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fce2111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce2111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce2111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a883f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c (1094 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vluxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscal
# | ...
# `---data was truncated (10240/107872) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2f251515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a2f25120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a2f251589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5cf9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5cf9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5cf9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5cf9b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2f24aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a2f24aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a2f248fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a2f213f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a2f213edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5cf9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5cf9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5cf9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2f213ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c (1095 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_
# | ...
# `---data was truncated (10240/63061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005654e548315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005654e54800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005654e548389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f635f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f635f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f635f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f635f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654e5418e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005654e5418c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005654e53fdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005654e50ad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005654e50acdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f635f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f635f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f635f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654e50accc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c (1096 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmacc_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmacc_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmacc_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmacc_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmacc_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale
# | ...
# `---data was truncated (10240/79489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560f4cd315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005560f4cd00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005560f4cd389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9335c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9335ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9335c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9335c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560f4c68e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005560f4c68c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005560f4c4db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005560f48fd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005560f48fcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9335c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9335c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9335c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560f48fccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c (1097 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1up_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1up_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.add
# | ...
# `---data was truncated (10240/86739) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a306e715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555a306e40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555a306e789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1bd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1bd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1bd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1bd51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a3067ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555a3067cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555a30661b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555a303110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555a30310dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd1bd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1bd51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1bd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a30310cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c (1098 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055642ba5d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055642ba5a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055642ba5d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fabd5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fabd5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fabd5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fabd5f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055642b9f2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055642b9f2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055642b9d7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055642b6870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055642b686dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fabd5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fabd5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fabd5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055642b686cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c (1099 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# | 
# | ...
# `---data was truncated (10240/86100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557376c7e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557376c7b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557376c7e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9f3a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9f3a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9f3a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9f3a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557376c13e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557376c13c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557376bf8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005573768a80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005573768a7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa9f3a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9f3a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9f3a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573768a7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c (1100 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> 
# | ...
# `---data was truncated (10240/157173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055682e80c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055682e8090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055682e80c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdef9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdef998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdef9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdef991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055682e7a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055682e7a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055682e786b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055682e4360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055682e435dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdef991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdef991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdef991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055682e435cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c (1101 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653bba3715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005653bba340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005653bba3789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e2d61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e2d6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e2d61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e2d603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653bb9cce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005653bb9ccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005653bb9b1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005653bb6610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005653bb660dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7e2d604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e2d6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e2d6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653bb660cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c (1102 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svrshl_single_s8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.srshl.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.srshl.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svrshl_single_s16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.srshl.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.srshl.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 4 x i32>, <vscale x 4 x i32> } @test_svrshl_single_s32_x2(<vscale x 4 x i32> %zdn.coerce0, <vscale x 4 x i32> %zdn.coerce1, <vscale x 4 x i32> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zdn.addr = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16
# |   %zm.addr = alloca <vscale x 4 x i32>, align 16
# |   %0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } poison, <vscale x 4 x i32> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %0, <vscale x 4 x i32> %zdn.coerce1, 1
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn, align 16
# |   store { <vscale x 4 x i32>, <vscale x 4 x i32> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 4 x i32> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 4 x i32>, <vscale x 4 x i32> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 0
# |   %4 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %2, 1
# |   %5 = load <vscale x 4 x i32>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.srshl.single.x2.nxv4i32(<vscale x 4 x i32> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %5)
# |   ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.srshl.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 2 x i64>, <vscale x 2 x i64> } @test_svrshl_single_s64_x2(<vscale x 2 x i64> %zdn.coerce0, <vscale x 2 x i64> %zdn.coerce1, <vscale x 2 x i64> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zdn.addr = alloca { <vscale x 2 x i64>, <vscale x 2 x i64> }, align 16
# |   %zm.addr = alloca <vscale x 2 x i64>, align 16
# |   %0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } poison, <vscale x 2 x i64> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %0, <vscale x 2 x i64> %zdn.coerce1, 1
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn, align 16
# |   store { <vscale x 2 x i64>, <vscale x 2 x i64> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 2 x i64> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 2 x i64>, <vscale x 2 x i64> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 0
# |   %4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %2, 1
# |   %5 = load <vscale x 2 x i64>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.single.x2.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %5)
# |   ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i8>, <vscale x 16 x i8> } @test_svrshl_single_u8_x2(<vscale x 16 x i8> %zdn.coerce0, <vscale x 16 x i8> %zdn.coerce1, <vscale x 16 x i8> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zdn.addr = alloca { <vscale x 16 x i8>, <vscale x 16 x i8> }, align 16
# |   %zm.addr = alloca <vscale x 16 x i8>, align 16
# |   %0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %0, <vscale x 16 x i8> %zdn.coerce1, 1
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn, align 16
# |   store { <vscale x 16 x i8>, <vscale x 16 x i8> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 16 x i8> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 16 x i8>, <vscale x 16 x i8> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 0
# |   %4 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %2, 1
# |   %5 = load <vscale x 16 x i8>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.urshl.single.x2.nxv16i8(<vscale x 16 x i8> %3, <vscale x 16 x i8> %4, <vscale x 16 x i8> %5)
# |   ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.urshl.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 8 x i16>, <vscale x 8 x i16> } @test_svrshl_single_u16_x2(<vscale x 8 x i16> %zdn.coerce0, <vscale x 8 x i16> %zdn.coerce1, <vscale x 8 x i16> %zm) #0 {
# | entry:
# |   %zdn = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zdn.addr = alloca { <vscale x 8 x i16>, <vscale x 8 x i16> }, align 16
# |   %zm.addr = alloca <vscale x 8 x i16>, align 16
# |   %0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %zdn.coerce0, 0
# |   %1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %0, <vscale x 8 x i16> %zdn.coerce1, 1
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %1, ptr %zdn, align 16
# |   %zdn1 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn, align 16
# |   store { <vscale x 8 x i16>, <vscale x 8 x i16> } %zdn1, ptr %zdn.addr, align 16
# |   store <vscale x 8 x i16> %zm, ptr %zm.addr, align 16
# |   %2 = load { <vscale x 8 x i16>, <vscale x 8 x i16> }, ptr %zdn.addr, align 16
# |   %3 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 0
# |   %4 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %2, 1
# |   %5 = load <vscale x 8 x i16>, ptr %zm.addr, align 16
# |   %6 = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.urshl.single.x2.nxv8i16(<vscale x 8 x i16> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %5)
# |   ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <vscale x 8 x i16>, <vscale x 8 x i16> 
# | ...
# `---data was truncated (10240/93119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim
# |  #0 0x000055ab5cda315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ab5cda00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ab5cda389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb796333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb79638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb796333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb79631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab5cd38e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ab5cd38c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ab5cd1db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ab5c9cd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ab5c9ccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb79631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb79631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb79631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab5c9cccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c (1103 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmin_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.smin.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.smin.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmin_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.smin.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.smin.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmin_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.smin.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.smin.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmin_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale x 2 x i64> %1, <vscale x 2 x i64> zeroinitializer
# |   %5 = call <vscale x 2 x i64> @llvm.aarch64.sve.smin.nxv2i64(<vscale x 2 x i1> %3, <vscale x 2 x i64> %4, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.smin.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svmin_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 16
# |   %op2.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 16
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 16 x i8>, ptr %op2.addr, align 16
# |   %3 = select <vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> zeroinitializer
# |   %4 = call <vscale x 16 x i8> @llvm.aarch64.sve.umin.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %3, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.umin.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svmin_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x i16>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x i16> %1, <vscale x 8 x i16> zeroinitializer
# |   %5 = call <vscale x 8 x i16> @llvm.aarch64.sve.umin.nxv8i16(<vscale x 8 x i1> %3, <vscale x 8 x i16> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.umin.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svmin_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 4 x i32>, align 16
# |   %op2.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op1, ptr %op1.addr, align 16
# |   store <vscale x 4 x i32> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 4 x i32>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 4 x i1> %3, <vscale x 4 x i32> %1, <vscale x 4 x i32> zeroinitializer
# |   %5 = call <vscale x 4 x i32> @llvm.aarch64.sve.umin.nxv4i32(<vscale x 4 x i1> %3, <vscale x 4 x i32> %4, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.umin.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svmin_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 2 x i64>, align 16
# |   %op2.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 16
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 2 x i64>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 2 x i1> %3, <vscale
# | ...
# `---data was truncated (10240/74195) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x000055963add615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055963add30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055963add689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7335249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73352a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7335249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7335231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055963ad6be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055963ad6bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055963ad50b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055963aa000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055963a9ffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7335232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73352330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73352330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055963a9ffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c (1104 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 =
# | ...
# `---data was truncated (10240/39218) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f7b0d615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561f7b0d30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561f7b0d689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff7a6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7a64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff7a6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff7a6431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f7b06be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561f7b06bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561f7b050b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561f7ad000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561f7acffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff7a6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7a64330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7a64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f7acffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c (1105 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4c1d4115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b4c1d3e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b4c1d4189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6bad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6bad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6bad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6bad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4c1cd6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b4c1cd6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b4c1cbbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b4c196b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b4c196add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa6bad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6bad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6bad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4c196acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c (1106 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c5ecca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556c5ecc70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556c5ecca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9542a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9542a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9542a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9542a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c5ec5fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556c5ec5fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556c5ec44b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556c5e8f40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556c5e8f3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9542a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9542a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9542a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c5e8f3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c (1107 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, al
# | ...
# `---data was truncated (10240/72135) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d55832215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d55831f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d55832289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c76c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c76ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c76c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c76c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5582b7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d5582b7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d55829cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d557f4c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d557f4bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1c76c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c76c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c76c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d557f4bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c (1108 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llv
# | ...
# `---data was truncated (10240/59779) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cca100e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cca100b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cca100e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8dfd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8dfd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8dfd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8dfced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cca0fa3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cca0fa3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cca0f88b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cca0c380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cca0c37dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd8dfceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8dfcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8dfcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cca0c37cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c (1109 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vandn.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vandn_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/98117) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b722ea715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b722ea40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b722ea789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffab6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffab6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffab6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffab6e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b722e3ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b722e3cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b722e21b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b722ad10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b722ad0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ffab6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffab6e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffab6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b722ad0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c (1110 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056045d26d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056045d26a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056045d26d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f223c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f223c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f223c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f223c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056045d202e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056045d202c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056045d1e7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056045ce970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056045ce96dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f223c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f223c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f223c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056045ce96cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c (1111 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c  -check-prefix=RV32ZBKC
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmul_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.clmul.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmulh_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.clmulh.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.clmul.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.clmulh.i32(i32, i32) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkc" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbkc1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562be031f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562be031c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562be031f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6cd3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6cd3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6cd3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6cd3e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562be02b4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562be02b4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562be0299b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562bdff490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562bdff48dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6cd3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6cd3e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6cd3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bdff48cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c (1112 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.a
# | ...
# `---data was truncated (10240/174713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562125c0c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562125c090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562125c0c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5da449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5da4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5da449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5da431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562125ba1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562125ba1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562125b86b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005621258360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562125835dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb5da432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5da4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5da4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562125835cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c (1113 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559316bb315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559316bb00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559316bb389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90a0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90a0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90a0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90a0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559316b48e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559316b48c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559316b2db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005593167dd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005593167dcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f90a0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90a0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90a0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593167dccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/X86/bfloat16-convert-half.c (1114 of 27911)
******************** TEST 'Clang :: CodeGen/X86/bfloat16-convert-half.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm    /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_convert_from_bf16_to_fp16(bfloat noundef %a) #0 {
# | entry:
# |   %a.addr = alloca bfloat, align 2
# |   store bfloat %a, ptr %a.addr, align 2
# |   %0 = load bfloat, ptr %a.addr, align 2
# |   %fpext = fpext bfloat %0 to float
# |   %fptrunc = fptrunc float %fpext to half
# |   ret half %fptrunc
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_convert_from_fp16_to_bf16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   %fpext = fpext half %0 to float
# |   %fptrunc = fptrunc float %fpext to bfloat
# |   ret bfloat %fptrunc
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056304874015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056304873d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056304874089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c3c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c3c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c3c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c3c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630486d5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005630486d5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005630486bab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056304836a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563048369dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8c3c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c3c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c3c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563048369cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c (1115 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsll_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/176535) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c2c41d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562c2c41a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562c2c41d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f835b105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f835b15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f835b105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f835b0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c2c3b2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562c2c3b2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562c2c397b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562c2c0470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562c2c046dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f835b0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f835b0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f835b0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c2c046cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c (1116 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/135337) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631e01ea15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005631e01e70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005631e01ea89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89a2505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89a255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89a2505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89a24ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631e017fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005631e017fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005631e0164b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005631dfe140b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005631dfe13dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f89a24eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89a24ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89a24ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631dfe13cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c (1117 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/66036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b7411c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560b741190f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560b7411c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83bcf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83bcf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83bcf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83bcf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b740b1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560b740b1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560b74096b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560b73d460b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560b73d45dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f83bcf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83bcf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83bcf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b73d45cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c (1118 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c28de6515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c28de620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c28de6589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6929049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69290a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6929049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6929031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c28ddfae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c28ddfac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c28dddfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c28da8f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c28da8edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6929032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69290330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69290330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c28da8ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c (1119 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575d27a115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005575d279e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005575d27a189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe15b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe15b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe15b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe15b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575d2736e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005575d2736c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005575d271bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005575d23cb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005575d23cadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe15b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe15b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe15b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575d23cacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c (1120 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_t
# | ...
# `---data was truncated (10240/128436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d69d07715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d69d0740f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d69d07789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5649e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5649ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5649e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5649e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d69d00ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d69d00cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d69cff1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d69cca10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d69cca0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5649e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5649e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5649e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d69cca0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c (1121 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056493e36015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056493e35d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056493e36089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62e9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62e92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62e9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62e9231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056493e2f5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056493e2f5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056493e2dab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056493df8a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056493df89dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f62e9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62e92330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62e92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056493df89cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c (1122 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b55f3d915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b55f3d60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b55f3d989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b9ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b9eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b9ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b9ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b55f36ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b55f36ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b55f353b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b55f0030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b55f002dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2b9ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b9ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b9ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b55f002cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c (1123 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599271a415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005599271a10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005599271a489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa7b8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa7b838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa7b8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa7b831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559927139e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559927139c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055992711eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559926dce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559926dcddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa7b831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa7b831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa7b831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559926dcdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c (1124 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i8, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i16, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vs
# | ...
# `---data was truncated (10240/210427) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b7f0b315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562b7f0b00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562b7f0b389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f077e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f077e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f077e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f077e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b7f048e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562b7f048c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562b7f02db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562b7ecdd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562b7ecdcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f077e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f077e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f077e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b7ecdccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c (1125 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, al
# | ...
# `---data was truncated (10240/223137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca3a9a815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ca3a9a50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ca3a9a889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4110f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4110f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4110f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4110f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca3a93de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ca3a93dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ca3a922b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ca3a5d20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ca3a5d1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4110f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4110f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4110f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca3a5d1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c (1126 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   s
# | ...
# `---data was truncated (10240/223359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0e6ba915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b0e6ba60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b0e6ba989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef37505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef3755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef37505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef374ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0e6b3ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b0e6b3ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b0e6b23b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b0e67d30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b0e67d2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fef374eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef374ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef374ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0e67d2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c (1127 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i6
# | ...
# `---data was truncated (10240/67158) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb37dc415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eb37dc10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eb37dc489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fadf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fadf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fadf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fadf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb37d59e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eb37d59c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eb37d3eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eb379ee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eb379eddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9fadf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fadf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fadf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb379edcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c (1128 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32
# | ...
# `---data was truncated (10240/123655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005565c177315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005565c17700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005565c177389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9060e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9060ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9060e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9060e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005565c1708e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005565c1708c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005565c16edb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005565c139d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005565c139cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9060e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9060e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9060e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005565c139ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c (1129 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dab8a3615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dab8a330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dab8a3689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa1d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa1d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa1d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa1d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dab89cbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dab89cbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dab89b0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dab86600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dab865fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faa1d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa1d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa1d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dab865fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c (1130 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ca182c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564ca18290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564ca182c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff530305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff53035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff530305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5302ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ca17c1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564ca17c1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564ca17a6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564ca14560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564ca1455dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff5302eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5302ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5302ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ca1455cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c (1131 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vset_v_i8m1_i8m2(<vscale x 16 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 16 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_i8m1_i8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_i8m2_i8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8>, <vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_i8m1_i8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_i8m2_i8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8>, <vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_i8m4_i8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 32 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 32 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> %0, <vscale x 32 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8>, <vscale x 32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vset_v_u8m1_u8m2(<vscale x 16 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 16 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_u8m1_u8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vset_v_u8m2_u8m4(<vscale x 32 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 32 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_u8m1_u8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_u8m2_u8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 16 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, ptr %dest.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 64 x i8> @llvm.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> %0, <vscale x 16 x i8> %1, i64 0)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vset_v_u8m4_u8m8(<vscale x 64 x i8> %dest, i64 noundef %index, <vscale x 32 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 64 x i8> %dest, p
# | ...
# `---data was truncated (10240/54546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb65d4e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cb65d4b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cb65d4e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc83533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc8358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc83533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc8351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb65ce3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cb65ce3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cb65cc8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cb659780b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cb65977dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbc8351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc8351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc8351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb65977cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c (1132 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/113019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055836bf6b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055836bf680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055836bf6b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5ba849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5ba8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5ba849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5ba831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055836bf00e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055836bf00c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055836bee5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055836bb950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055836bb94dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa5ba832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5ba8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5ba8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055836bb94cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c (1133 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bb5fa115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562bb5f9e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562bb5fa189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f737f01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f737f0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f737f01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f737f003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bb5f36e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562bb5f36c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562bb5f1bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562bb5bcb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562bb5bcadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f737f004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f737f0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f737f0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bb5bcacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c (1134 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055619f8f715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055619f8f40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055619f8f789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83a8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83a838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83a8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83a831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055619f88ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055619f88cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055619f871b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055619f5210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055619f520dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f83a831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83a831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83a831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055619f520cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c (1135 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0
# | ...
# `---data was truncated (10240/10425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a00208d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a00208a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a00208d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f899641bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89964725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f899641ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8996403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a002022e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a002022c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a002007b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a001cb70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a001cb6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8996404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89964050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89964050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a001cb6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c (1136 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 
# | ...
# `---data was truncated (10240/98445) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ed972415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556ed97210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556ed972489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe94b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe94b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe94b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe94b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ed96b9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556ed96b9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556ed969eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556ed934e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556ed934ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe94b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe94b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe94b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ed934dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c (1137 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/110284) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c10d2bc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c10d2b90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c10d2bc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa1f601bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1f60725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa1f601ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa1f6003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c10d251e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c10d251c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c10d236b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c10cee60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c10cee5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa1f6004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1f60050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1f60050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c10cee5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c (1138 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmv_v_f_f16mf4_tu(<vscale x 1 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmv_v_f_f16mf2_tu(<vscale x 2 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmv_v_f_f16m1_tu(<vscale x 4 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmv_v_f_f16m2_tu(<vscale x 8 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmv_v_f_f16m4_tu(<vscale x 16 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmv_v_f_f16m8_tu(<vscale x 32 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmv_v_f_f32mf2_tu(<vscale x 1 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmv_v_f_f32m1_tu(<vscale x 2 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmv_v_f_f32m2_tu(<vscale x 4 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfmv_v_f_f32m4_tu(<vscale x 8 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfmv_v_f_f32m8_tu(<vscale x 16 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x flo
# | ...
# `---data was truncated (10240/29327) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005569fdaa915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005569fdaa60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005569fdaa989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04e7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04e758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04e7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04e751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569fda3ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005569fda3ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005569fda23b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005569fd6d30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005569fd6d2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f04e751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04e751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04e751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569fd6d2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c (1139 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a15e07a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a15e0770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a15e07a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fabb6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fabb6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fabb6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fabb6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a15e00fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a15e00fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a15dff4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a15dca40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a15dca3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fabb6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fabb6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fabb6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a15dca3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c (1140 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f
# | ...
# `---data was truncated (10240/165246) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee3c9ca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ee3c9c70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ee3c9ca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18f2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18f2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18f2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18f2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee3c95fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ee3c95fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ee3c944b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ee3c5f40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ee3c5f3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f18f2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18f2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18f2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee3c5f3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c (1141 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558599d3315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558599d300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558599d3389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31f8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31f878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31f8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31f871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558599cc8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558599cc8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558599cadb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055859995d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055859995cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f31f871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31f871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31f871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055859995ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGenCXX/attr-musttail.cpp (1142 of 27911)
******************** TEST 'Clang :: CodeGenCXX/attr-musttail.cpp' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o -
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %class.Foo = type { i8 }
# | %class.HasTrivialDestructor = type { i8 }
# | %struct.Data = type { ptr }
# | %struct.HasNonTrivialCopyConstructor = type { i8 }
# | %struct.HasNonTrivialCopyConstructor2 = type { i8 }
# | %struct.LargeWithCopyConstructor = type { [32 x i8] }
# | %class.anon = type { i8 }
# | 
# | $_Z12TemplateFuncIiET_S0_ = comdat any
# | 
# | $_Z6Func10IiEii = comdat any
# | 
# | $_Z6Func12IiET_S0_ = comdat any
# | 
# | @pmf = global { i64, i64 } zeroinitializer, align 8
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func1i(i32 noundef %x) #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %tobool = icmp ne i32 %0, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %entry
# |   %1 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z3Bari(i32 noundef %1)
# |   ret i32 %call
# | 
# | 2:                                                ; No predecessors!
# |   store i32 undef, ptr %retval, align 4
# |   br label %return
# | 
# | if.else:                                          ; preds = %entry
# |   %3 = load i32, ptr %x.addr, align 4
# |   %call1 = musttail call noundef i32 @_Z3Bazi(i32 noundef %3)
# |   ret i32 %call1
# | 
# | 4:                                                ; No predecessors!
# |   store i32 undef, ptr %retval, align 4
# |   br label %return
# | 
# | return:                                           ; preds = %4, %2
# |   %5 = load i32, ptr %retval, align 4
# |   ret i32 %5
# | }
# | 
# | declare noundef i32 @_Z3Bari(i32 noundef) #1
# | 
# | declare noundef i32 @_Z3Bazi(i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func2i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @_Z3Bari(i32 noundef %0)
# |   %call1 = musttail call noundef i32 @_Z3Bari(i32 noundef %call)
# |   ret i32 %call1
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_ZN3Foo8TailFromEi(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_ZN3Foo14MemberFunctionEi(ptr noundef nonnull align 1 dereferenceable(1) %this1, i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | declare noundef i32 @_ZN3Foo14MemberFunctionEi(ptr noundef nonnull align 1 dereferenceable(1), i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func3i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | declare noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func4i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %foo = alloca %class.Foo, align 1
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_ZN3Foo9TailFrom2Ei(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load { i64, i64 }, ptr @pmf, align 8
# |   %memptr.adj = extractvalue { i64, i64 } %0, 1
# |   %1 = getelementptr inbounds i8, ptr %this1, i64 %memptr.adj
# |   %memptr.ptr = extractvalue { i64, i64 } %0, 0
# |   %2 = and i64 %memptr.ptr, 1
# |   %memptr.isvirtual = icmp ne i64 %2, 0
# |   br i1 %memptr.isvirtual, label %memptr.virtual, label %memptr.nonvirtual
# | 
# | memptr.virtual:                                   ; preds = %entry
# |   %vtable = load ptr, ptr %1, align 8
# |   %3 = sub i64 %memptr.ptr, 1
# |   %4 = getelementptr i8, ptr %vtable, i64 %3, !nosanitize !1
# |   %memptr.virtualfn = load ptr, ptr %4, align 8, !nosanitize !1
# |   br label %memptr.end
# | 
# | memptr.nonvirtual:                                ; preds = %entry
# |   %memptr.nonvirtualfn = inttoptr i64 %memptr.ptr to ptr
# |   br label %memptr.end
# | 
# | memptr.end:                                       ; preds = %memptr.nonvirtual, %memptr.virtual
# |   %5 = phi ptr [ %memptr.virtualfn, %memptr.virtual ], [ %memptr.nonvirtualfn, %memptr.nonvirtual ]
# |   %6 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 %5(ptr noundef nonnull align 1 dereferenceable(1) %1, i32 noundef %6)
# |   ret i32 %call
# | 
# | 7:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_ZN3Foo9TailFrom3Ei(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   %x.addr = alloca i32, align 4
# |   store ptr %this, ptr %this.addr, align 8
# |   store i32 %x, ptr %x.addr, align 4
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %0 = load { i64, i64 }, ptr @pmf, align 8
# |   %memptr.adj = extractvalue { i64, i64 } %0, 1
# |   %1 = getelementptr inbounds i8, ptr %this1, i64 %memptr.adj
# |   %memptr.ptr = extractvalue { i64, i64 } %0, 0
# |   %2 = and i64 %memptr.ptr, 1
# |   %memptr.isvirtual = icmp ne i64 %2, 0
# |   br i1 %memptr.isvirtual, label %memptr.virtual, label %memptr.nonvirtual
# | 
# | memptr.virtual:                                   ; preds = %entry
# |   %vtable = load ptr, ptr %1, align 8
# |   %3 = sub i64 %memptr.ptr, 1
# |   %4 = getelementptr i8, ptr %vtable, i64 %3, !nosanitize !1
# |   %memptr.virtualfn = load ptr, ptr %4, align 8, !nosanitize !1
# |   br label %memptr.end
# | 
# | memptr.nonvirtual:                                ; preds = %entry
# |   %memptr.nonvirtualfn = inttoptr i64 %memptr.ptr to ptr
# |   br label %memptr.end
# | 
# | memptr.end:                                       ; preds = %memptr.nonvirtual, %memptr.virtual
# |   %5 = phi ptr [ %memptr.virtualfn, %memptr.virtual ], [ %memptr.nonvirtualfn, %memptr.nonvirtual ]
# |   %6 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 %5(ptr noundef nonnull align 1 dereferenceable(1) %1, i32 noundef %6)
# |   ret i32 %call
# | 
# | 7:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local void @_Z5Func5v() #0 {
# | entry:
# |   musttail call void @_Z11ReturnsVoidv()
# |   ret void
# | 
# | 0:                                                ; No predecessors!
# |   ret void
# | }
# | 
# | declare void @_Z11ReturnsVoidv() #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func6i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %foo = alloca %class.HasTrivialDestructor, align 1
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z10ReturnsInti(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | declare noundef i32 @_Z10ReturnsInti(i32 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func7P4Data(ptr noundef %data) #0 {
# | entry:
# |   %data.addr = alloca ptr, align 8
# |   store ptr %data, ptr %data.addr, align 8
# |   %0 = load ptr, ptr %data.addr, align 8
# |   %fptr = getelementptr inbounds nuw %struct.Data, ptr %0, i32 0, i32 0
# |   %1 = load ptr, ptr %fptr, align 8
# |   %2 = load ptr, ptr %data.addr, align 8
# |   %call = musttail call noundef i32 %1(ptr noundef %2)
# |   ret i32 %call
# | 
# | 3:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z5Func9i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z12TemplateFuncIiET_S0_(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define linkonce_odr noundef i32 @_Z12TemplateFuncIiET_S0_(i32 noundef %0) #0 comdat {
# | entry:
# |   %.addr = alloca i32, align 4
# |   store i32 %0, ptr %.addr, align 4
# |   ret i32 5
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z6Func11i(i32 noundef %x) #0 {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = call noundef i32 @_Z6Func10IiEii(i32 noundef %0)
# |   ret i32 %call
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define linkonce_odr noundef i32 @_Z6Func10IiEii(i32 noundef %x) #0 comdat {
# | entry:
# |   %x.addr = alloca i32, align 4
# |   %t = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %call = musttail call noundef i32 @_Z3Bari(i32 noundef %0)
# |   ret i32 %call
# | 
# | 1:                                                ; No predecessors!
# |   ret i32 undef
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind optnone
# | define dso_local noundef i32 @_Z6Func13i(i32 noundef %x) #0 {
# | entry:
# |   %x.ad
# | ...
# `---data was truncated (10240/18685) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify
# |  #0 0x000056138b68c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056138b6890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056138b68c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdefe533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdefe58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdefe533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdefe51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056138b621e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056138b621c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056138b606b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056138b2b60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056138b2b5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdefe51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdefe51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdefe51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056138b2b5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c (1143 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2e
# | ...
# `---data was truncated (10240/253148) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a304a4a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a304a470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a304a4a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3656d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3656d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3656d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3656d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3049dfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a3049dfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a3049c4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a3046740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a304673dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3656d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3656d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3656d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a304673cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c (1144 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055798852d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055798852a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055798852d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5be8a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5be8a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5be8a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5be8a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579884c2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005579884c2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005579884a7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005579881570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557988156dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5be8a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5be8a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5be8a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557988156cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c (1145 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmadc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmadc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmadc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmadc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmadc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   
# | ...
# `---data was truncated (10240/169917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056222ffa315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056222ffa00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056222ffa389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe50fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe50fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe50fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe50fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056222ff38e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056222ff38c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056222ff1db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056222fbcd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056222fbccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe50fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe50fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe50fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056222fbcccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c (1146 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vsc
# | ...
# `---data was truncated (10240/121179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eba802215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eba801f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eba802289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0b8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0b8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0b8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0b8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eba7fb7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eba7fb7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eba7f9cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eba7c4c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eba7c4bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa0b8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0b8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0b8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eba7c4bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c (1147 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsm
# | ...
# `---data was truncated (10240/99585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562fb711115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562fb710e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562fb711189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd369733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd36978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd369733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd36971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fb70a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562fb70a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562fb708bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562fb6d3b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562fb6d3add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd36971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd36971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd36971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fb6d3acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c (1148 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bf373315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562bf37300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562bf373389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff1ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff1eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff1ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff1ea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bf36c8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562bf36c8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562bf36adb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562bf335d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562bf335cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007eff1ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff1ea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff1ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bf335ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c (1149 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store <vscal
# | ...
# `---data was truncated (10240/142024) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a602de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555a602db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555a602de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f927ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f927ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f927ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f927ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a60273e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555a60273c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555a60258b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555a5ff080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555a5ff07dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f927ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f927ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f927ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a5ff07cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c (1150 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrol.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrol_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = al
# | ...
# `---data was truncated (10240/97675) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0b943015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c0b942d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c0b943089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75ff133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75ff18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75ff133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75ff11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0b93c5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c0b93c5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c0b93aab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c0b905a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c0b9059dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f75ff11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75ff11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75ff11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0b9059cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c (1151 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5ed69e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c5ed69b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c5ed69e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ae6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ae6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ae6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ae6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5ed633e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c5ed633c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c5ed618b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c5ed2c80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c5ed2c7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5ae6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ae6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ae6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5ed2c7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c (1152 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2_tu(target("riscv.vector.
# | ...
# `---data was truncated (10240/295525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606b4f4715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005606b4f440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005606b4f4789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f008e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f008e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f008e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f008e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606b4edce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005606b4edcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005606b4ec1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005606b4b710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005606b4b70dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f008e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f008e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f008e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606b4b70cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c (1153 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c25abe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561c25abb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561c25abe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a35933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a3598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a35933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a3591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c25a53e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561c25a53c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561c25a38b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561c256e80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561c256e7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9a3591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a3591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a3591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c256e7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c (1154 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_u8mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_u8m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557044d6f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557044d6c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557044d6f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc208a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc208aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc208a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc208a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557044d04e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557044d04c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557044ce9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005570449990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557044998dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc208a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc208a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc208a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557044998cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c (1155 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %6
# | }
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/34633) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644e55ec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005644e55e90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005644e55ec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7866733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f786678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7866733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f786671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644e5581e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005644e5581c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005644e5566b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005644e52160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005644e5215dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f786671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f786671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f786671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644e5215cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c (1156 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <
# | ...
# `---data was truncated (10240/101483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e704c6715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e704c640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e704c6789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2871c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2871c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2871c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2871c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e704bfce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e704bfcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e704be1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e7048910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e704890dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2871c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2871c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2871c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e704890cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c (1157 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055953108915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005595310860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055953108989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e2a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e2a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e2a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e2a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055953101ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055953101ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559531003b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559530cb30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559530cb2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0e2a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e2a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e2a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559530cb2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c (1158 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("risc
# | ...
# `---data was truncated (10240/11912) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ce8ab415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555ce8ab10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555ce8ab489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f246ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f246eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f246ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f246ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ce8a49e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555ce8a49c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555ce8a2eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555ce86de0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555ce86dddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f246ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f246ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f246ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ce86ddcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c (1159 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556be245215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556be244f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556be245289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd3b8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3b838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd3b8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3b831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556be23e7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556be23e7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556be23ccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556be207c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556be207bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd3b831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3b831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3b831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556be207bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c (1160 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i1
# | ...
# `---data was truncated (10240/95001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de75c3215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055de75c2f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055de75c3289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc28505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc2855c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc28505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc284ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de75bc7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055de75bc7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055de75bacb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055de7585c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055de7585bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efc284eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc284ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc284ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de7585bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c (1161 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %bas
# | ...
# `---data was truncated (10240/60209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056399a8db15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056399a8d80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056399a8db89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb87133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb8718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb87133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb8711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056399a870e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056399a870c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056399a855b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056399a5050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056399a504dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ffb8711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb8711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb8711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056399a504cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c (1162 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e9d13f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555e9d13c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555e9d13f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34dad05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34dad5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34dad05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34daced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e9d0d4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555e9d0d4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555e9d0b9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555e9cd690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555e9cd68dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f34daceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34dacef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34dacef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e9cd68cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c (1163 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64ff_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e6c05f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563e6c05c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563e6c05f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe91505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe9155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe91505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe914ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e6bff4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563e6bff4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563e6bfd9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563e6bc890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563e6bc88dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbe914eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe914ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe914ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e6bc88cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c (1164 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b78fb6c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b78fb690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b78fb6c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc22f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc22f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc22f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc22eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b78fb01e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b78fb01c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b78fae6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b78f7960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b78f795dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdc22eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc22eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc22eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b78f795cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c (1165 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @
# | ...
# `---data was truncated (10240/18570) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a655a4b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a655a480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a655a4b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f616aa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f616aa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f616aa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f616aa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6559e0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a6559e0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a6559c5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a6556750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a655674dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f616aa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f616aa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f616aa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a655674cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c (1166 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560740df515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560740df20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560740df589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e58249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e582a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e58249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e58231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560740d8ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560740d8ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560740d6fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560740a1f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560740a1edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5e58232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e582330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e582330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560740a1ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c (1167 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055911739e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055911739b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055911739e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7552f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7552f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7552f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7552f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559117333e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559117333c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559117318b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559116fc80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559116fc7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7552f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7552f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7552f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559116fc7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c (1168 of 27911)
******************** TEST 'Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-arm-none-eabi    -target-feature +neon -target-feature +bf16 -mfloat-abi soft    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi soft -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %4 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %5 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <8 x bfloat>, align 8
# |   %__p2.addr.i = alloca <8 x bfloat>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <8 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 8
# |   store <4 x float> %r, ptr %r.addr, align 8
# |   store <8 x bfloat> %a, ptr %a.addr, align 8
# |   store <8 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %r.addr, align 8
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 8
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   store <8 x bfloat> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %4 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %5 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_lane_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <4 x bfloat>, align 8
# |   %__ret_810 = alloca <2 x float>, align 8
# |   %__s0_810 = alloca <2 x float>, align 8
# |   %__s1_810 = alloca <4 x bfloat>, align 8
# |   %__s2_810 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   %tmp2 = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x bfloat> %a, ptr %a.addr, align 8
# |   store <4 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0_810, align 8
# |   %1 = load <4 x bfloat>, ptr %a.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s1_810, align 8
# |   %2 = load <4 x bfloat>, ptr %b.addr, align 8
# |   store <4 x bfloat> %2, ptr %__s2_810, align 8
# |   %3 = load <2 x float>, ptr %__s0_810, align 8
# |   %4 = load <4 x bfloat>, ptr %__s1_810, align 8
# |   %5 = load <2 x float>, ptr %__s2_810, align 8
# |   store <2 x float> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x float>
# |   %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer
# |   store <2 x float> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x float>, ptr %ref.tmp1, align 8
# |   store <2 x float> %8, ptr %__ret, align 8
# |   %9 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %9, ptr %tmp, align 8
# |   %10 = load <2 x float>, ptr %tmp, align 8
# |   store <2 x float> %10, ptr %ref.tmp, align 8
# |   %11 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <2 x float> %3, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %4, ptr %__p1.addr.i, align 8
# |   store <4 x bfloat> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <8 x i8> %12 to <2 x float>
# |   %vbfdot1.i = bitcast <8 x i8> %13 to <4 x bfloat>
# |   %vbfdot2.i = bitcast <8 x i8> %14 to <4 x bfloat>
# |   %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i)
# |   store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %16, ptr %__ret_810, align 8
# |   %17 = load <2 x float>, ptr %__ret_810, align 8
# |   store <2 x float> %17, ptr %tmp2, align 8
# |   %18 = load <2 x float>, ptr %tmp2, align 8
# |   ret <2 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vbfdotq_laneq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <8 x bfloat>, align 8
# |   %__p2.addr.i = alloca <8 x bfloat>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %r.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <8 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 8
# |   %__ret_812 = alloca <4 x float>, align 8
# |   %__s0_812 = alloca <4 x float>, align 8
# |   %__s1_812 = alloca <8 x bfloat>, align 8
# |   %__s2_812 = alloca <8 x bfloat>, align 8
# |   %ref.tmp = alloca <4 x float>, align 8
# |   %__ret = alloca <4 x float>, align 8
# |   %__s0 = alloca <4 x float>, align 8
# |   %ref.tmp1 = alloca <16 x i8>, align 8
# |   %tmp = alloca <4 x float>, align 8
# |   %tmp2 = alloca <4 x float>, align 8
# |   store <4 x float> %r, ptr %r.addr, align 8
# |   store <8 x bfloat> %a, ptr %a.addr, align 8
# |   store <8 x bfloat> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %r.addr, align 8
# |   store <4 x float> %0, ptr %__s0_812, align 8
# |   %1 = load <8 x bfloat>, ptr %a.addr, align 8
# |   store <8 x bfloat> %1, ptr %__s1_812, align 8
# |   %2 = load <8 x bfloat>, ptr %b.addr, align 8
# |   store <8 x bfloat> %2, ptr %__s2_812, align 8
# |   %3 = load <4 x float>, ptr %__s0_812, align 8
# |   %4 = load <8 x bfloat>, ptr %__s1_812, align 8
# |   %5 = load <4 x float>, ptr %__s2_812, align 8
# |   store <4 x float> %5, ptr %__s0, align 8
# |   %6 = load <16 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <16 x i8> %6 to <4 x float>
# |   %lane = shufflevector <4 x float> %7, <4 x float> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x float> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <4 x float>, ptr %ref.tmp1, align 8
# |   store <4 x float> %8, ptr %__ret, align 8
# |   %9 = load <4 x float>, ptr %__ret, align 8
# |   store <4 x float> %9, ptr %tmp, align 8
# |   %10 = load <4 x float>, ptr %tmp, align 8
# |   store <4 x float> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x float> %3, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %4, ptr %__p1.addr.i, align 8
# |   store <8 x bfloat> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vbfdot.i = bitcast <16 x i8> %12 to <4 x float>
# |   %vbfdot1.i = bitcast <16 x i8> %13 to <8 x bfloat>
# |   %vbfdot2.i = bitcast <16 x i8> %14 to <8 x bfloat>
# |   %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i)
# |   store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8
# |   %15 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %15, ptr %__ret.i, align 8
# |   %16 = load <4 x float>, ptr %__ret.i, align 8
# |   store <4 x float> %16, ptr %__ret_812, align 8
# |   %17 = load <4 x float>, ptr %__ret_812, align 8
# |   store <4 x float> %17, ptr %tmp2, align 8
# |   %18 = load <4 x float>, ptr %tmp2, align 8
# |   ret <4 x float> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vbfdot_laneq_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__p2.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x bfloat>, align 8
# |   %b.addr = alloca <8 x bfloat>, align 8
# |   %__ret_814 = alloca <2 x float>, al
# | ...
# `---data was truncated (10240/54174) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000556a03fed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556a03fea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556a03fed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b15b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b15b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b15b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b15b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a03f82e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556a03f82c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556a03f67b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556a03c170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556a03c16dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3b15b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b15b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b15b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a03c16cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c (1169 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vv_u64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhu_vx_u64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vv_u64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhu_vx_u64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vv_u64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhu_vx_u64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhu_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.i6
# | ...
# `---data was truncated (10240/18619) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e33544c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e3354490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e33544c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f384f705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f384f75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f384f705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f384f6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3353e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e3353e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e3353c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e3350760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e335075dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f384f6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f384f6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f384f6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e335075cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c (1170 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005597ab00015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005597aaffd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005597ab00089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e2db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e2db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e2db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e2db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005597aaf95e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005597aaf95c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005597aaf7ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005597aac2a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005597aac29dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9e2db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e2db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e2db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597aac29cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c (1171 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651e137715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005651e13740f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005651e137789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a07933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a0798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a07933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a0791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651e130ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005651e130cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005651e12f1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005651e0fa10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005651e0fa0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4a0791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a0791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a0791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651e0fa0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c (1172 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclipu_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclipu_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclipu_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclipu_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclipu_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale
# | ...
# `---data was truncated (10240/70021) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1e0cf515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e1e0cf20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e1e0cf589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2165849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21658a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2165849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2165831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1e0c8ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e1e0c8ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e1e0c6fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e1e091f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e1e091edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2165832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21658330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21658330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1e091ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c (1173 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005635acc8a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005635acc870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005635acc8a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fbb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fbb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fbb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fbb51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635acc1fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005635acc1fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005635acc04b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005635ac8b40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005635ac8b3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3fbb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fbb51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fbb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635ac8b3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c (1174 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1rq_mf8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1rq_s8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1rq_s16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1rq.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1rq.nxv8i16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1rq_s32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1rq.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1rq.nxv4i32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1rq_s64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1rq.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1rq.nxv2i64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svld1rq_u8(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8.p0(<vscale x 16 x i1> %0, ptr %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svld1rq_u16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1rq.nxv8i16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svld1rq_u32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1rq.nxv4i32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svld1rq_u64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1rq.nxv2i64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x half> @test_svld1rq_f16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x half> @llvm.aarch64.sve.ld1rq.nxv8f16.p0(<vscale x 8 x i1> %2, ptr %1)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.aarch64.sve.ld1rq.nxv8f16.p0(<vscale x 8 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_svld1rq_f32(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1rq.nxv4f32.p0(<vscale x 4 x i1> %2, ptr %1)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.ld1rq.nxv4f32.p0(<vscale x 4 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x double> @test_svld1rq_f64(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1rq.nxv2f64.p0(<vscale x 2 x i1> %2, ptr %1)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.aarch64.sve.ld1rq.nxv2f64.p0(<vscale x 2 x i1>, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svld1rq_bf16(<vscale x 16 x i1> %pg, ptr noundef %base) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr 
# | ...
# `---data was truncated (10240/11267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000559713c6015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559713c5d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559713c6089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28fbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28fbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28fbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28fbd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559713bf5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559713bf5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559713bdab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055971388a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559713889dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f28fbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28fbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28fbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559713889cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c (1175 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso
# | ...
# `---data was truncated (10240/148012) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558240da015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558240d9d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558240da089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4765849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47658a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4765849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4765831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558240d35e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558240d35c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558240d1ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005582409ca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005582409c9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4765832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47658330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47658330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582409c9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c (1176 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de58e3d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055de58e3a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055de58e3d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2736f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2736f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2736f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2736f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de58dd2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055de58dd2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055de58db7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055de58a670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055de58a66dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2736f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2736f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2736f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de58a66cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c (1177 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/136005) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643e67b015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005643e67ad0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005643e67b089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1171505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f117155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1171505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11714ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005643e6745e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005643e6745c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005643e672ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005643e63da0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005643e63d9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f11714eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11714ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11714ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005643e63d9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c (1178 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x
# | ...
# `---data was truncated (10240/208199) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602659c615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005602659c30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005602659c689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff77e41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff77e4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff77e41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff77e403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056026595be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056026595bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560265940b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005602655f00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005602655efdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff77e404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff77e4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff77e4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602655efcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c (1179 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vand_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba1438615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ba143830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ba1438689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdde0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdde02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdde0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdde0231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba1431be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ba1431bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ba14300b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ba13fb00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ba13fafdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdde0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdde02330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdde02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba13fafcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c (1180 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595d4fbd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005595d4fba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005595d4fbd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6cbe105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6cbe15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6cbe105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6cbe0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595d4f52e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005595d4f52c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005595d4f37b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005595d4be70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005595d4be6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6cbe0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6cbe0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6cbe0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595d4be6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c (1181 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_ext_v_f16mf4_f16mf2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.insert.nxv2f16.nxv1f16(<vscale x 2 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf4_f16m1(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv1f16(<vscale x 4 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf4_f16m2(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv1f16(<vscale x 8 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf4_f16m4(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv1f16(<vscale x 16 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf4_f16m8(<vscale x 1 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half> poison, <vscale x 1 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv1f16(<vscale x 32 x half>, <vscale x 1 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_ext_v_f16mf2_f16m1(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.insert.nxv4f16.nxv2f16(<vscale x 4 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16mf2_f16m2(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16mf2_f16m4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv2f16(<vscale x 16 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16mf2_f16m8(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half> poison, <vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv2f16(<vscale x 32 x half>, <vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_ext_v_f16m1_f16m2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m1_f16m4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m1_f16m8(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> poison, <vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_ext_v_f16m2_f16m4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlmul_ext_v_f16m2_f16m8(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> poison, <vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind 
# | ...
# `---data was truncated (10240/83080) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e40642a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e4064270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e40642a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b56249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b562a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b56249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b56231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4063bfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e4063bfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e4063a4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e4060540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e406053dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8b56232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b562330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b562330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e406053cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c (1182 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d3c9f915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562d3c9f60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562d3c9f989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8adb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8adb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8adb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8adb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d3c98ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562d3c98ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562d3c973b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562d3c6230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562d3c622dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8adb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8adb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8adb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d3c622cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon-dot-product.c (1183 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-dot-product.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %c.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   store <16 x i8> %c, ptr %c.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   %2 = load <16 x i8>, ptr %c.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %c.addr = alloca <16 x i8>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   store <16 x i8> %c, ptr %c.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   %2 = load <16 x i8>, ptr %c.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_831 = alloca <2 x i32>, align 8
# |   %__s0_831 = alloca <2 x i32>, align 8
# |   %__s1_831 = alloca <8 x i8>, align 8
# |   %__s2_831 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_831, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_831, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_831, align 8
# |   %3 = load <2 x i32>, ptr %__s0_831, align 8
# |   %4 = load <8 x i8>, ptr %__s1_831, align 8
# |   %5 = load <2 x i32>, ptr %__s2_831, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> <i32 1, i32 1>
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_831, align 8
# |   %17 = load <2 x i32>, ptr %__ret_831, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_827 = alloca <4 x i32>, align 16
# |   %__s0_827 = alloca <4 x i32>, align 16
# |   %__s1_827 = alloca <16 x i8>, align 16
# |   %__s2_827 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x i32>, align 16
# |   %tmp2 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__s0_827, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %1, ptr %__s1_827, align 16
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_827, align 8
# |   %3 = load <4 x i32>, ptr %__s0_827, align 16
# |   %4 = load <16 x i8>, ptr %__s1_827, align 16
# |   %5 = load <2 x i32>, ptr %__s2_827, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__
# | ...
# `---data was truncated (10240/29862) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# |  #0 0x000055c31dabf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c31dabc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c31dabf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e58e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e58ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e58e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e58e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c31da54e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c31da54c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c31da39b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c31d6e90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c31d6e8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3e58e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e58e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e58e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c31d6e8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGenCXX/ctor-globalopt.cpp (1184 of 27911)
******************** TEST 'Clang :: CodeGenCXX/ctor-globalopt.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp -O2
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.B = type <{ ptr, i32, [4 x i8], %struct.A.base, [4 x i8] }>
# | %struct.A.base = type <{ ptr, i32 }>
# | 
# | @b = local_unnamed_addr global %struct.B <{ ptr getelementptr inbounds inrange(-24, 8) (i8, ptr @_ZTV1B, i64 24), i32 0, [4 x i8] zeroinitializer, %struct.A.base <{ ptr getelementptr inbounds inrange(-24, 8) (i8, ptr @_ZTV1B, i64 56), i32 0 }>, [4 x i8] zeroinitializer }>, align 8
# | @_ZTV1B = external constant { [4 x ptr], [4 x ptr] }, align 8
# | @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer
# | 
# | !llvm.ident = !{!0}
# | !llvm.errno.tbaa = !{!1}
# | 
# | !0 = !{!"clang version 24.0.0"}
# | !1 = !{!2, !3, i64 0}
# | !2 = !{!"__libc_errno", !3, i64 0}
# | !3 = !{!"int", !4, i64 0}
# | !4 = !{!"omnipotent char", !5, i64 0}
# | !5 = !{!"Simple C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# |  #0 0x000056393524315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005639352400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056393524389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2547f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2547f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2547f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2547f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639351d8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005639351d8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005639351bdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563934e6d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563934e6cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2547f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2547f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2547f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563934e6ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c (1185 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e35fa8d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e35fa8a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e35fa8d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6686049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66860a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6686049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6686031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e35fa22e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e35fa22c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e35fa07b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e35f6b70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e35f6b6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6686032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66860330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66860330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e35f6b6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c (1186 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipe_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipe_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @
# | ...
# `---data was truncated (10240/35774) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566db3a515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005566db3a20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005566db3a589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82fbb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82fbb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82fbb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82fbaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566db33ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005566db33ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005566db31fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005566dafcf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005566dafcedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f82fbaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82fbaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82fbaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566dafcecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c (1187 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, <vscale x 1 x i64> %
# | ...
# `---data was truncated (10240/215941) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e49c4115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556e49c3e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556e49c4189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fef14d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fef14d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fef14d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fef14d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e49bd6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556e49bd6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556e49bbbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556e4986b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556e4986add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fef14d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fef14d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fef14d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e4986acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c (1188 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005597f278b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005597f27880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005597f278b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f86e3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86e30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f86e3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f86e3031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005597f2720e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005597f2720c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005597f2705b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005597f23b50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005597f23b4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f86e3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86e30330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86e30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597f23b4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c (1189 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1a389515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b1a38920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b1a389589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f924fe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f924fe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f924fe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f924fe03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1a382ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b1a382ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b1a380fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b1a34bf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b1a34bedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f924fe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f924fe050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f924fe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1a34becc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vclz.c (1190 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %0, i1 false)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %0, i1 false)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %0, i1 false)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %0, i1 false)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %0, i1 false)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %0, i1 false)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclsq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = call <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8> %0)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclsq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclsq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclsq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclsq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.cls.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.cls.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclsq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = call <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.clz.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.clz.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.clz.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x 
# | ...
# `---data was truncated (10240/18674) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056217ad3915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056217ad360f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056217ad3989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13d2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13d26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13d2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13d2631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056217accee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056217accec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056217acb3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056217a9630b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056217a962dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f13d2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13d26330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13d26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056217a962cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c (1191 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_i16m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_u16mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_u16mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline n
# | ...
# `---data was truncated (10240/28559) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560898a0f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560898a0c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560898a0f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbdadd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbdadd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbdadd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbdadd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608989a4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005608989a4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560898989b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005608986390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560898638dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbdadd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbdadd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbdadd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560898638cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c (1192 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# | ...
# `---data was truncated (10240/29304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632b2f3315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005632b2f300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005632b2f3389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f91b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f91b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f91b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f91b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632b2ec8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005632b2ec8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005632b2eadb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005632b2b5d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005632b2b5cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0f91b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f91b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f91b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632b2b5ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c (1193 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563dc33a715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563dc33a40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563dc33a789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff860249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8602a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff860249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff860231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563dc333ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563dc333cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563dc3321b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563dc2fd10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563dc2fd0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff860232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8602330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8602330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563dc2fd0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c (1194 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; 
# | ...
# `---data was truncated (10240/100289) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630f7e7215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005630f7e6f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005630f7e7289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24d2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24d2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24d2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24d2b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630f7e07e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005630f7e07c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005630f7decb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005630f7a9c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005630f7a9bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f24d2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24d2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24d2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630f7a9bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c (1195 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560911fcd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560911fca0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560911fcd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b93b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b93b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b93b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b93b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560911f62e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560911f62c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560911f47b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560911bf70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560911bf6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4b93b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b93b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b93b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560911bf6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c (1196 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560e0c3a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005560e0c370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005560e0c3a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71daf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71daf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71daf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71daf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560e0bcfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005560e0bcfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005560e0bb4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005560e08640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005560e0863dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f71daf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71daf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71daf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560e0863cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c (1197 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: noca
# | ...
# `---data was truncated (10240/40803) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6d786d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d6d786a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d6d786d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5de3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5de3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5de3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5de3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6d7802e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d6d7802c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d6d77e7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d6d74970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d6d7496dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5de3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5de3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5de3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6d7496cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c (1198 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b489ae715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b489ae40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b489ae789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd15f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd15f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd15f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd15f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b489a7ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b489a7cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b489a61b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b4897110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b489710dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd15f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd15f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd15f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b489710cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c (1199 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, ali
# | ...
# `---data was truncated (10240/58334) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a3ef2715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556a3ef240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556a3ef2789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff810e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff810ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff810e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff810e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a3eebce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556a3eebcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556a3eea1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556a3eb510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556a3eb50dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff810e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff810e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff810e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a3eb50cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c (1200 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f6f69b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556f6f6980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556f6f69b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4adad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4adad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4adad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4adad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f6f630e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556f6f630c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556f6f615b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556f6f2c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556f6f2c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4adad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4adad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4adad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f6f2c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c (1201 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local vo
# | ...
# `---data was truncated (10240/26928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b8e5a115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558b8e59e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558b8e5a189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb72c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb72c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb72c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb72c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b8e536e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558b8e536c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558b8e51bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558b8e1cb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558b8e1cadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ffb72c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb72c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb72c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b8e1cacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c (1202 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3a40fe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b3a40fb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b3a40fe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4137249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41372a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4137249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4137231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3a4093e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b3a4093c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b3a4078b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b3a3d280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b3a3d27dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4137232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41372330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41372330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3a3d27cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-neon-vld.c (1203 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-vld.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon      -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vld1_f16_x2(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float16x4x2_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr %0)
# |   store { <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false)
# |   %1 = load %struct.float16x4x2_t, ptr %retval, align 8
# |   ret %struct.float16x4x2_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x3_t @test_vld1_f16_x3(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float16x4x3_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float16x4x3_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr %0)
# |   store { <4 x half>, <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 24, i1 false)
# |   %1 = load %struct.float16x4x3_t, ptr %retval, align 8
# |   ret %struct.float16x4x3_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x4_t @test_vld1_f16_x4(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float16x4x4_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float16x4x4_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr %0)
# |   store { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 32, i1 false)
# |   %1 = load %struct.float16x4x4_t, ptr %retval, align 8
# |   ret %struct.float16x4x4_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float32x2x2_t @test_vld1_f32_x2(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float32x2x2_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float32x2x2_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr %0)
# |   store { <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false)
# |   %1 = load %struct.float32x2x2_t, ptr %retval, align 8
# |   ret %struct.float32x2x2_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float32x2x3_t @test_vld1_f32_x3(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float32x2x3_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float32x2x3_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr %0)
# |   store { <2 x float>, <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 24, i1 false)
# |   %1 = load %struct.float32x2x3_t, ptr %retval, align 8
# |   ret %struct.float32x2x3_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float32x2x4_t @test_vld1_f32_x4(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.float32x2x4_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.float32x2x4_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr %0)
# |   store { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 32, i1 false)
# |   %1 = load %struct.float32x2x4_t, ptr %retval, align 8
# |   ret %struct.float32x2x4_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.poly16x4x2_t @test_vld1_p16_x2(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.poly16x4x2_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.poly16x4x2_t, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %vld1xN = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr %0)
# |   store { <4 x i16>, <4 x i16> } %vld1xN, ptr %__ret, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false)
# |   %1 = load %struct.poly16x4x2_t, ptr %retval, align 8
# |   ret %struct.poly16x4x2_t %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.poly16x4x3_t @test_vld1_p16_x3(ptr noundef %a) #0 {
# | entry:
# |   %retval = alloca %struct.poly16x4x3_t, align 8
# |   %a.addr = alloca ptr, align 8
# |   %__ret = alloca %struct.poly16
# | ...
# `---data was truncated (10240/109928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636ecd0915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005636ecd060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005636ecd0989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc5b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc5b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc5b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc5b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636ecc9ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005636ecc9ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005636ecc83b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005636ec9330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005636ec932dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcc5b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc5b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc5b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636ec932cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c (1204 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vloxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x
# | ...
# `---data was truncated (10240/107864) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615f78ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005615f78a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005615f78ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6699a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6699aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6699a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6699a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615f7840e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005615f7840c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005615f7825b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005615f74d50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005615f74d4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6699a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6699a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6699a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615f74d4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c (1205 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vle16_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/71947) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642607f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005642607f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005642607f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda0e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda0e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda0e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda0e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056426078de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056426078dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564260772b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005642604220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564260421dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fda0e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda0e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda0e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564260421cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c (1206 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %sr
# | ...
# `---data was truncated (10240/288111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e21703b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e2170380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e21703b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd615533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd61558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd615533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd61551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e216fd0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e216fd0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e216fb5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e216c650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e216c64dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd61551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd61551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd61551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e216c64cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon-fp16fml.c (1207 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-fp16fml.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.2a -target-feature +neon -target-feature +fp16fml  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.2a -target-feature +neon -target-feature +fp16fml -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlal_low_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlal_low.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlal_low1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlal_low2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlal_low3.i = call <2 x float> @llvm.aarch64.neon.fmlal.v2f32.v4f16(<2 x float> %vfmlal_low.i, <4 x half> %vfmlal_low1.i, <4 x half> %vfmlal_low2.i)
# |   store <2 x float> %vfmlal_low3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlsl_low_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlsl_low.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlsl_low1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlsl_low2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlsl_low3.i = call <2 x float> @llvm.aarch64.neon.fmlsl.v2f32.v4f16(<2 x float> %vfmlsl_low.i, <4 x half> %vfmlsl_low1.i, <4 x half> %vfmlsl_low2.i)
# |   store <2 x float> %vfmlsl_low3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlal_high_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlal_high.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlal_high1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlal_high2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlal_high3.i = call <2 x float> @llvm.aarch64.neon.fmlal2.v2f32.v4f16(<2 x float> %vfmlal_high.i, <4 x half> %vfmlal_high1.i, <4 x half> %vfmlal_high2.i)
# |   store <2 x float> %vfmlal_high3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfmlsl_high_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vfmlsl_high.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vfmlsl_high1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vfmlsl_high2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vfmlsl_high3.i = call <2 x float> @llvm.aarch64.neon.fmlsl2.v2f32.v4f16(<2 x float> %vfmlsl_high.i, <4 x half> %vfmlsl_high1.i, <4 x half> %vfmlsl_high2.i)
# |   store <2 x float> %vfmlsl_high3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmlalq_low_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vfmlal_low.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vfmlal_low1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vfmlal_low2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vfmlal_low3.i = call <4 x float> @llvm.aarch64.neon.fmlal.v4f32.v8f16(<4 x float> %vfmlal_low.i, <8 x half> %vfmlal_low1.i, <8 x half> %vfmlal_low2.i)
# |   store <4 x float> %vfmlal_low3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmlslq_low_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vfmlsl_low.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vfmlsl_low1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vfmlsl_low2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vfmlsl_low3.i = call <4 x float> @llvm.aarch64.neon.fmlsl.v4f32.v8f16(<4 x float> %vfmlsl_low.i, <8 x half> %vfmlsl_low1.i, <8 x half> %vfmlsl_low2.i)
# |   store <4 x float> %vfmlsl_low3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmlalq_high_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = allo
# | ...
# `---data was truncated (10240/162735) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000557e70fd915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557e70fd60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557e70fd989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3bed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3bed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3bed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3bed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e70f6ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557e70f6ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557e70f53b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557e70c030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557e70c02dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc3bed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3bed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3bed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e70c02cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c (1208 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e80bcb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556e80bc80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556e80bcb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa381d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa381d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa381d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa381d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e80b60e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556e80b60c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556e80b45b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556e807f50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556e807f4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa381d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa381d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa381d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e807f4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c (1209 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/424835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620596a915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005620596a60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005620596a989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33dd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33dd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33dd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33dd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056205963ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056205963ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562059623b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005620592d30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005620592d2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f33dd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33dd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33dd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620592d2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c (1210 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsltu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsltu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bfb46d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559bfb46a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559bfb46d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69f0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69f0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69f0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69f0e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bfb402e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559bfb402c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559bfb3e7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559bfb0970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559bfb096dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f69f0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69f0e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69f0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bfb096cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c (1211 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipe_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipe_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1
# | ...
# `---data was truncated (10240/35782) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a626cfa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a626cf70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a626cfa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5de6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5de6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5de6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5de6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a626c8fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a626c8fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a626c74b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a6269240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a626923dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5de6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5de6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5de6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a626923cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c (1212 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7102d315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a7102d00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a7102d389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35f1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35f118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35f1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35f111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a710268e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a710268c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a71024db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a70fefd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a70fefcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f35f111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35f111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35f111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a70fefccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c (1213 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604ada1315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005604ada100f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005604ada1389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf0de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf0dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf0de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf0de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604ad9a8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005604ad9a8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005604ad98db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005604ad63d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005604ad63cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faf0de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf0de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf0de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604ad63ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c (1214 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/61929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba053e215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ba053df0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ba053e289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f85e8e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f85e8e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f85e8e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f85e8e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba05377e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ba05377c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ba0535cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ba0500c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ba0500bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f85e8e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f85e8e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f85e8e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba0500bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c (1215 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561b997f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005561b997c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005561b997f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2696333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f269638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2696333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f269631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561b9914e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005561b9914c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005561b98f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005561b95a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005561b95a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f269631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f269631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f269631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561b95a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c (1216 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, pt
# | ...
# `---data was truncated (10240/79679) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559fc058a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559fc05870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559fc058a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f110ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f110ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f110ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f110ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fc051fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559fc051fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559fc0504b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559fc01b40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559fc01b3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f110ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f110ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f110ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fc01b3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c (1217 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8
# | ...
# `---data was truncated (10240/414525) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc25db815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dc25db50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dc25db889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f449b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f449b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f449b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f449b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc25d4de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dc25d4dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dc25d32b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dc259e20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dc259e1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f449b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f449b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f449b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc259e1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c (1218 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a6f9b415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563a6f9b10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563a6f9b489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15a1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15a18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15a1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15a1831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a6f949e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563a6f949c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563a6f92eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563a6f5de0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563a6f5dddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f15a1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15a18330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15a18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a6f5ddcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c (1219 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9b791b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f9b79180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f9b791b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1d2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1d22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1d2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1d2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9b78b0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f9b78b0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f9b7895b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f9b75450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f9b7544dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff1d2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1d22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1d22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9b7544cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c (1220 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8
# | ...
# `---data was truncated (10240/96911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056328390c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005632839090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056328390c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdcc2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdcc2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdcc2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdcc2a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632838a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005632838a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563283886b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005632835360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563283535dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdcc2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdcc2a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdcc2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563283535cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c (1221 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e759e4015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e759e3d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e759e4089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce50a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce50aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce50a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce50a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e759dd5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e759dd5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e759dbab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e759a6a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e759a69dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fce50a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce50a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce50a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e759a69cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c (1222 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a83aad915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a83aad60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a83aad989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe338649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3386a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe338649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe338631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a83aa6ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a83aa6ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a83aa53b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a83a7030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a83a702dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe338632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3386330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3386330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a83a702cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c (1223 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a231c315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559a231c00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559a231c389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46ae933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46ae98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46ae933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46ae91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a23158e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559a23158c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559a2313db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559a22ded0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559a22decdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f46ae91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46ae91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46ae91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a22deccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c (1224 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16
# | ...
# `---data was truncated (10240/129182) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a8393615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557a839330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557a8393689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a3f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a3f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a3f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a3f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a838cbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557a838cbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557a838b0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557a835600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557a8355fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2a3f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a3f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a3f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a8355fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c (1225 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583a71db15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005583a71d80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005583a71db89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc55d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc55d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc55d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc55d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583a7170e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005583a7170c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005583a7155b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005583a6e050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005583a6e04dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbc55d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc55d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc55d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583a6e04cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c (1226 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2791c315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a2791c00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a2791c389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f77305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f7735c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f77305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f772ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a279158e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a279158c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a27913db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a278ded0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a278decdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3f772eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f772ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f772ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a278deccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c (1227 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = e
# | ...
# `---data was truncated (10240/100513) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570f28d615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005570f28d30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005570f28d689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7a9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7a94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7a9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7a9431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570f286be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005570f286bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005570f2850b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005570f25000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005570f24ffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd7a9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7a94330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7a94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570f24ffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c (1228 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a717dfd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a717dfa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a717dfd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff233849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2338a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff233849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff233831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a717d92e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a717d92c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a717d77b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a717a270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a717a26dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff233832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2338330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2338330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a717a26cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c (1229 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561438d4c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561438d490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561438d4c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f50333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f5038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f50333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f5031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561438ce1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561438ce1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561438cc6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005614389760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561438975dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9f5031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f5031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f5031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561438975cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c (1230 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x
# | ...
# `---data was truncated (10240/15615) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e99abd315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e99abd00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e99abd389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27df733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27df78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27df733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27df71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e99ab68e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e99ab68c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e99ab4db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e99a7fd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e99a7fcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f27df71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27df71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27df71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e99a7fccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c (1231 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   
# | ...
# `---data was truncated (10240/25616) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba3cc6515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ba3cc620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ba3cc6589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42a2f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42a2f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42a2f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42a2eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba3cbfae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ba3cbfac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ba3cbdfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ba3c88f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ba3c88edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f42a2eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42a2eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42a2eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba3c88ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c (1232 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.ad
# | ...
# `---data was truncated (10240/306619) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056185a36315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056185a3600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056185a36389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8df1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8df10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8df1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8df1031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056185a2f8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056185a2f8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056185a2ddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561859f8d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561859f8cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8df1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8df10330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8df10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561859f8ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGenCoroutines/pr65054.cpp (1233 of 27911)
******************** TEST 'Clang :: CodeGenCoroutines/pr65054.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20       -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp -o - -disable-O0-optnone       | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes='sroa,mem2reg,simplifycfg' -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.MyTask = type { %"struct.std::coroutine_handle" }
# | %"struct.std::coroutine_handle" = type { ptr }
# | %"struct.std::suspend_always" = type { i8 }
# | %struct.Awaiter = type { ptr }
# | %"struct.std::coroutine_handle.0" = type { %"struct.std::coroutine_handle" }
# | 
# | $_ZN6MyTask12promise_type17get_return_objectEv = comdat any
# | 
# | $_ZN6MyTask12promise_type15initial_suspendEv = comdat any
# | 
# | $_ZNSt14suspend_always11await_readyEv = comdat any
# | 
# | $_ZNSt14suspend_always13await_suspendESt16coroutine_handleIvE = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_addressEPv = comdat any
# | 
# | $_ZNSt14suspend_always12await_resumeEv = comdat any
# | 
# | $_ZN6MyTask12promise_type15await_transformERKi = comdat any
# | 
# | $_ZN7Awaiter11await_readyEv = comdat any
# | 
# | $_ZNKSt16coroutine_handleIvE7addressEv = comdat any
# | 
# | $_ZN7Awaiter12await_resumeEv = comdat any
# | 
# | $_ZN6MyTask12promise_type13final_suspendEv = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_promiseERS1_ = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEEC1Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEEC2Ev = comdat any
# | 
# | $_ZNSt16coroutine_handleIvEC2Ev = comdat any
# | 
# | @g_array = global [32 x i32] zeroinitializer, align 16
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local ptr @_Z6FooBarv() #0 {
# | entry:
# |   %retval = alloca %struct.MyTask, align 8
# |   %undef.agg.tmp = alloca %"struct.std::suspend_always", align 1
# |   %undef.agg.tmp19 = alloca %"struct.std::suspend_always", align 1
# |   %call = call noalias noundef nonnull ptr @_Znwm(i64 noundef 64) #6
# |   store ptr @_Z6FooBarv.resume, ptr %call, align 8
# |   %0 = select i1 true, ptr @_Z6FooBarv.destroy, ptr @_Z6FooBarv.cleanup
# |   %destroy.addr = getelementptr inbounds i8, ptr %call, i64 8
# |   store ptr %0, ptr %destroy.addr, align 8
# |   %ref.tmp.reload.addr = getelementptr inbounds i8, ptr %call, i64 18
# |   %__range1.reload.addr = getelementptr inbounds i8, ptr %call, i64 24
# |   %__begin1.reload.addr = getelementptr inbounds i8, ptr %call, i64 32
# |   %__end1.reload.addr = getelementptr inbounds i8, ptr %call, i64 40
# |   %x.reload.addr = getelementptr inbounds i8, ptr %call, i64 48
# |   %ref.tmp4.reload.addr = getelementptr inbounds i8, ptr %call, i64 56
# |   %ref.tmp18.reload.addr = getelementptr inbounds i8, ptr %call, i64 19
# |   %__promise.reload.addr = getelementptr inbounds i8, ptr %call, i64 16
# |   %call1 = call ptr @_ZN6MyTask12promise_type17get_return_objectEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr)
# |   %coerce.dive = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %coerce.dive2 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive, i32 0, i32 0
# |   store ptr %call1, ptr %coerce.dive2, align 8
# |   call void @_ZN6MyTask12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr)
# |   %call3 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp.reload.addr) #7
# |   br i1 %call3, label %init.ready, label %CoroSave
# | 
# | CoroSave:                                         ; preds = %entry
# |   %index.addr39 = getelementptr inbounds i8, ptr %call, i64 17
# |   store i8 0, ptr %index.addr39, align 1
# |   call void @_Z6FooBarv.__await_suspend_wrapper__init(ptr %ref.tmp.reload.addr, ptr %call) #7
# |   br label %AfterCoroEnd
# | 
# | init.ready:                                       ; preds = %entry
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp.reload.addr) #7
# |   store ptr @g_array, ptr %__range1.reload.addr, align 8
# |   store ptr @g_array, ptr %__begin1.reload.addr, align 8
# |   store ptr getelementptr inbounds nuw (i8, ptr @g_array, i64 128), ptr %__end1.reload.addr, align 8
# |   br label %for.cond
# | 
# | for.cond:                                         ; preds = %for.inc, %init.ready
# |   %1 = load ptr, ptr %__begin1.reload.addr, align 8
# |   %2 = load ptr, ptr %__end1.reload.addr, align 8
# |   %cmp = icmp ne ptr %1, %2
# |   br i1 %cmp, label %for.body, label %coro.final
# | 
# | for.body:                                         ; preds = %for.cond
# |   %3 = load ptr, ptr %__begin1.reload.addr, align 8
# |   store ptr %3, ptr %x.reload.addr, align 8
# |   %4 = load ptr, ptr %x.reload.addr, align 8, !nonnull !1, !align !2
# |   %call5 = call ptr @_ZN6MyTask12promise_type15await_transformERKi(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr, ptr noundef nonnull align 4 dereferenceable(4) %4)
# |   %coerce.dive6 = getelementptr inbounds nuw %struct.Awaiter, ptr %ref.tmp4.reload.addr, i32 0, i32 0
# |   store ptr %call5, ptr %coerce.dive6, align 8
# |   %call7 = call noundef zeroext i1 @_ZN7Awaiter11await_readyEv(ptr noundef nonnull align 8 dereferenceable(8) %ref.tmp4.reload.addr)
# |   br i1 %call7, label %await.ready, label %CoroSave27
# | 
# | CoroSave27:                                       ; preds = %for.body
# |   %index.addr40 = getelementptr inbounds i8, ptr %call, i64 17
# |   store i8 1, ptr %index.addr40, align 1
# |   %5 = call ptr @_Z6FooBarv.__await_suspend_wrapper__await(ptr %ref.tmp4.reload.addr, ptr %call)
# |   %6 = getelementptr inbounds { ptr, ptr }, ptr %5, i32 0, i32 0
# |   %7 = load ptr, ptr %6, align 8
# |   call void %7(ptr %5)
# |   br label %AfterCoroEnd
# | 
# | await.ready:                                      ; preds = %for.body
# |   call void @_ZN7Awaiter12await_resumeEv(ptr noundef nonnull align 8 dereferenceable(8) %ref.tmp4.reload.addr)
# |   %cond = icmp eq i32 0, 0
# |   %cond26 = icmp eq i32 0, 0
# |   br i1 %cond26, label %for.inc, label %coro.final
# | 
# | for.inc:                                          ; preds = %await.ready
# |   %8 = load ptr, ptr %__begin1.reload.addr, align 8
# |   %incdec.ptr = getelementptr inbounds nuw i32, ptr %8, i32 1
# |   store ptr %incdec.ptr, ptr %__begin1.reload.addr, align 8
# |   br label %for.cond
# | 
# | coro.final:                                       ; preds = %await.ready, %for.cond
# |   call void @_ZN6MyTask12promise_type13final_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr) #7
# |   %call20 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp18.reload.addr) #7
# |   br i1 %call20, label %final.ready, label %CoroSave31
# | 
# | CoroSave31:                                       ; preds = %coro.final
# |   store ptr null, ptr %call, align 8
# |   call void @_Z6FooBarv.__await_suspend_wrapper__final(ptr %ref.tmp18.reload.addr, ptr %call) #7
# |   br label %AfterCoroEnd
# | 
# | final.ready:                                      ; preds = %coro.final
# |   call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp18.reload.addr) #7
# |   %9 = icmp ne ptr %call, null
# |   br i1 %9, label %coro.free, label %AfterCoroEnd
# | 
# | coro.free:                                        ; preds = %final.ready
# |   call void @_ZdlPvm(ptr noundef %call, i64 noundef 64) #7
# |   br label %AfterCoroEnd
# | 
# | AfterCoroEnd:                                     ; preds = %coro.free, %final.ready, %CoroSave27, %CoroSave31, %CoroSave
# |   %coerce.dive24 = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %coerce.dive25 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive24, i32 0, i32 0
# |   %10 = load ptr, ptr %coerce.dive25, align 8
# |   ret ptr %10
# | }
# | 
# | ; Function Attrs: nobuiltin allocsize(0)
# | declare noundef nonnull ptr @_Znwm(i64 noundef) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define linkonce_odr ptr @_ZN6MyTask12promise_type17get_return_objectEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 {
# | entry:
# |   %retval = alloca %struct.MyTask, align 8
# |   %this.addr = alloca ptr, align 8
# |   %ref.tmp = alloca %"struct.std::coroutine_handle.0", align 8
# |   store ptr %this, ptr %this.addr, align 8
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   %h = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %call = call ptr @_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_promiseERS1_(ptr noundef nonnull align 1 dereferenceable(1) %this1)
# |   %coerce.dive = getelementptr inbounds nuw %"struct.std::coroutine_handle.0", ptr %ref.tmp, i32 0, i32 0
# |   %coerce.dive2 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive, i32 0, i32 0
# |   store ptr %call, ptr %coerce.dive2, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %h, ptr align 8 %ref.tmp, i64 8, i1 false)
# |   %coerce.dive3 = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0
# |   %coerce.dive4 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive3, i32 0, i32 0
# |   %0 = load ptr, ptr %coerce.dive4, align 8
# |   ret ptr %0
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define linkonce_odr void @_ZN6MyTask12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   store ptr %this, ptr %this.addr, align 8
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define linkonce_odr noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 {
# | entry:
# |   %this.addr = alloca ptr, align 8
# |   store ptr %this, ptr %this.addr, align 8
# |   %this1 = load ptr, ptr %this.addr, align 8
# |   ret i1 false
# | }
# | 
# | ; Function Attrs: alwaysinline mustprogress nounwind
# | define internal void @_Z6FooBarv.__await_suspend_wrapper__init(ptr noundef nonnull %0, ptr noundef %1) #2 {
# | entry:
# |   %.addr = alloca ptr, align 8
# |   %.addr1 = alloca ptr, align 8
# |   %agg.tmp = alloca %"struct.std::coroutine_handle", align 8
# |   %ref.tmp = alloca %"struct.std::coroutine_handle.0", align 8
# |   store ptr %0, ptr %.addr, align 8
# |   store ptr %1, ptr %.addr1, align 8
# |   %2 = load ptr, ptr %.addr, align 8
# |   %3 = load ptr, ptr %.addr1, align 8
# |   %call = call ptr @_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_addressEPv(ptr noundef %3) #7
# |   
# | ...
# `---data was truncated (10240/37953) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=sroa,mem2reg,simplifycfg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=sroa,mem2reg,simplifycfg -S
# |  #0 0x000055bba4a5615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bba4a530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bba4a5689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3dcfe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3dcfea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3dcfe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3dcfe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bba49ebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bba49ebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bba49d0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bba46800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bba467fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3dcfe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3dcfe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3dcfe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bba467fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c (1234 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, i64 noundef %offset
# | ...
# `---data was truncated (10240/287213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc39e8c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bc39e890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bc39e8c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0b4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0b46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0b4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0b4631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc39e21e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bc39e21c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bc39e06b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bc39ab60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bc39ab5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa0b4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0b46330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0b46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc39ab5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c (1235 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_s16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 8 x i16> %2 to <vscale x 8 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8> %4, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8>, <vscale x 8 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_s32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8>, <vscale x 4 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_s64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8>, <vscale x 2 x i1>, ptr captures(none)) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_u16(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 8 x i16> %2 to <vscale x 8 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8> %4, <vscale x 8 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_u32(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8> %4, <vscale x 4 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_u64(<vscale x 16 x i1> %pg, ptr noundef %base, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %4 = trunc <vscale x 2 x i64> %2 to <vscale x 2 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8> %4, <vscale x 2 x i1> %3, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_s16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 8 x i16> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 8 x i16> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 8 x i16>, ptr %data.addr, align 16
# |   %4 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 8 x i8>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 8 x i16> %3 to <vscale x 8 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv8i8.p0(<vscale x 8 x i8> %6, <vscale x 8 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_s32(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 4 x i32> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 4 x i32> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %data.addr, align 16
# |   %4 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 4 x i8>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv4i8.p0(<vscale x 4 x i8> %6, <vscale x 4 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_s64(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 2 x i64> %data) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vnum.addr = alloca i64, align 8
# |   %data.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vnum, ptr %vnum.addr, align 8
# |   store <vscale x 2 x i64> %data, ptr %data.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vnum.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %data.addr, align 16
# |   %4 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %5 = getelementptr <vscale x 2 x i8>, ptr %1, i64 %2
# |   %6 = trunc <vscale x 2 x i64> %3 to <vscale x 2 x i8>
# |   call void @llvm.aarch64.sve.st1.nxv2i8.p0(<vscale x 2 x i8> %6, <vscale x 2 x i1> %4, ptr %5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local void @test_svst1b_vnum_u16(<vscale x 16 x i1> %pg, ptr noundef %base, i64 noundef %vnum, <vscale x 8 x i16> %data) #0 {
# | e
# | ...
# `---data was truncated (10240/32866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim
# |  #0 0x000055cb0fa5515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cb0fa520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cb0fa5589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5bef249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5bef2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5bef249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5bef231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb0f9eae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cb0f9eac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cb0f9cfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cb0f67f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cb0f67edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5bef232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5bef2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5bef2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb0f67ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c (1236 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsge_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsge_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564566a6515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564566a620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564566a6589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe71cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe71cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe71cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe71cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645669fae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005645669fac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005645669dfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056456668f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056456668edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe71cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe71cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe71cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056456668ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/admin.c (1237 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/admin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcreateq_f16(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <8 x half>
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcreateq_f32(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <4 x float>
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcreateq_s16(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcreateq_s32(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <4 x i32>
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcreateq_s64(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcreateq_s8(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcreateq_u16(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcreateq_u32(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <4 x i32>
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcreateq_u64(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcreateq_u8(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = insertelement <2 x i64> poison, i64 %0, i64 0
# |   %2 = load i64, ptr %b.addr, align 8
# |   %3 = insertelement <2 x i64> %1, i64 %2, i64 1
# |   %4 = bitcast <2 x i64> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vuninitializedq_polymorphic_f16(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <8 x half> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vuninitializedq_polymorphic_f32(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <4 x float> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_polymorphic_s8(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_polymorphic_s16(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_polymorphic_s32(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_polymorphic_s64(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_polymorphic_u8(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_polymorphic_u16(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_polymorphic_u32(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_polymorphic_u64(ptr noundef %funcptr) #0 {
# | entry:
# |   %funcptr.addr = alloca ptr, align 4
# |   store ptr %funcptr, ptr %funcptr.addr, align 4
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vuninitializedq_f16() #0 {
# | entry:
# |   ret <8 x half> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vuninitializedq_f32() #0 {
# | entry:
# |   ret <4 x float> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_s16() #0 {
# | entry:
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_s32() #0 {
# | entry:
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_s64() #0 {
# | entry:
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_s8() #0 {
# | entry:
# |   ret <16 x i8> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_u16() #0 {
# | entry:
# |   ret <8 x i16> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_u32() #0 {
# | entry:
# |   ret <4 x i32> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_u64() #0 {
# | entry:
# |   ret <2 x i64> undef
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_u8() #0 {
# | entry:
# |   ret <16 x i8> undef
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x000055fc7321115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fc7320e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fc7321189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbef3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbef378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbef3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbef371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc731a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fc731a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fc7318bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fc72e3b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fc72e3add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbef371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbef371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbef371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc72e3acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c (1238 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f3904015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557f3903d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557f3904089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbdc9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbdc9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbdc9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbdc9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f38fd5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557f38fd5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557f38fbab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557f38c6a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557f38c69dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbdc9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbdc9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbdc9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f38c69cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c (1239 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648c1dbd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005648c1dba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005648c1dbd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efcfb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efcfb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efcfb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efcfb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648c1d52e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005648c1d52c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005648c1d37b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005648c19e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005648c19e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efcfb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efcfb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efcfb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648c19e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c (1240 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1down_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1down_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1down_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1down_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1down_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1down_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1down_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1down_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1down_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1down_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1down_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1
# | ...
# `---data was truncated (10240/87183) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056043f8e515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056043f8e20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056043f8e589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f53eb649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53eb6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f53eb649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f53eb631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056043f87ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056043f87ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056043f85fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056043f50f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056043f50edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f53eb632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53eb6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53eb6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056043f50ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvp-intrinsics.c (1241 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvp-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +experimental-p    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +experimental-p -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_cls_32(i32 noundef %a) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   %1 = load i32, ptr %__rs1.addr.i, align 4
# |   %isneg.i = icmp slt i32 %1, 0
# |   %not.i = xor i32 %1, -1
# |   %2 = select i1 %isneg.i, i32 %not.i, i32 %1
# |   %3 = call i32 @llvm.ctlz.i32(i32 %2, i1 false)
# |   %4 = sub nuw i32 %3, 1
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_rev_32(i32 noundef %a) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   %1 = load i32, ptr %__rs1.addr.i, align 4
# |   %2 = call i32 @llvm.bitreverse.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_slx_32(i32 noundef %rd, i32 noundef %rs1, i32 noundef %shamt) #0 {
# | entry:
# |   %__rd.addr.i = alloca i32, align 4
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__shamt.addr.i = alloca i32, align 4
# |   %rd.addr = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %shamt.addr = alloca i32, align 4
# |   store i32 %rd, ptr %rd.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %shamt, ptr %shamt.addr, align 4
# |   %0 = load i32, ptr %rd.addr, align 4
# |   %1 = load i32, ptr %rs1.addr, align 4
# |   %2 = load i32, ptr %shamt.addr, align 4
# |   store i32 %0, ptr %__rd.addr.i, align 4
# |   store i32 %1, ptr %__rs1.addr.i, align 4
# |   store i32 %2, ptr %__shamt.addr.i, align 4
# |   %3 = load i32, ptr %__rd.addr.i, align 4
# |   %4 = load i32, ptr %__rs1.addr.i, align 4
# |   %5 = load i32, ptr %__shamt.addr.i, align 4
# |   %6 = call i32 @llvm.fshl.i32(i32 %3, i32 %4, i32 %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_srx_32(i32 noundef %rd, i32 noundef %rs1, i32 noundef %shamt) #0 {
# | entry:
# |   %__rd.addr.i = alloca i32, align 4
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__shamt.addr.i = alloca i32, align 4
# |   %rd.addr = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %shamt.addr = alloca i32, align 4
# |   store i32 %rd, ptr %rd.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %shamt, ptr %shamt.addr, align 4
# |   %0 = load i32, ptr %rd.addr, align 4
# |   %1 = load i32, ptr %rs1.addr, align 4
# |   %2 = load i32, ptr %shamt.addr, align 4
# |   store i32 %0, ptr %__rd.addr.i, align 4
# |   store i32 %1, ptr %__rs1.addr.i, align 4
# |   store i32 %2, ptr %__shamt.addr.i, align 4
# |   %3 = load i32, ptr %__rs1.addr.i, align 4
# |   %4 = load i32, ptr %__rd.addr.i, align 4
# |   %5 = load i32, ptr %__shamt.addr.i, align 4
# |   %6 = call i32 @llvm.fshr.i32(i32 %3, i32 %4, i32 %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_aadd_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.aadd.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_aaddu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.aaddu.u32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_asub_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.asub.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_asubu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.asubu.u32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_sadd_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.sadd.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_saddu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.uadd.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ssub_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.ssub.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ssubu_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %elt.sat.i = call i32 @llvm.usub.sat.i32(i32 %2, i32 %3)
# |   ret i32 %elt.sat.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_abs_u32(i32 noundef %a) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   %1 = load i32, ptr %__rs1.addr.i, align 4
# |   %elt.abs.i = call i32 @llvm.abs.i32(i32 %1, i1 false)
# |   ret i32 %elt.abs.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_sati_i32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.sati.i32(i32 %0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sati.i32(i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_usati_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.usati.i32(i32 %0, i32 16)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.usati.i32(i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_mulh_i32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__rs1.addr.i = alloca i32, align 4
# |   %__rs2.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__rs1.addr.i, align 4
# |   store i32 %1, ptr %__rs2.addr.i, align 4
# |   %2 = load i32, ptr %__rs1.addr.i, align 4
# |   %3 = load i32, ptr %__rs2.addr.i, align 4
# |   %4 = call i32 @llvm.smulh.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function At
# | ...
# `---data was truncated (10240/1228637) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine
# |  #0 0x000055cc2bbbb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cc2bbb80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cc2bbbb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd7e8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7e8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd7e8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd7e8f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc2bb50e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cc2bb50c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cc2bb35b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cc2b7e50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cc2b7e4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd7e8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7e8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7e8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc2b7e4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c (1242 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <
# | ...
# `---data was truncated (10240/66998) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625ae35815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005625ae3550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005625ae35889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe388133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe38818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe388133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe38811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625ae2ede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005625ae2edc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005625ae2d2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005625adf820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005625adf81dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe38811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe38811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe38811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625adf81cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c (1243 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b35fca815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b35fca50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b35fca889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f115c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f115c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f115c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f115c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b35fc3de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b35fc3dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b35fc22b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b35f8d20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b35f8d1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f115c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f115c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f115c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b35f8d1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c (1244 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_u16mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_u16m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_u16m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = allo
# | ...
# `---data was truncated (10240/23031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d618a2915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d618a260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d618a2989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c0281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c028725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c0281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c02803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6189bee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d6189bec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d6189a3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d6186530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d618652dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2c02804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c028050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c028050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d618652cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c (1245 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/12688) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce80ee215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ce80edf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ce80ee289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1785b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1785b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1785b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1785aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce80e77e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ce80e77c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ce80e5cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ce80b0c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ce80b0bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1785aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1785aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1785aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce80b0bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c (1246 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1606b215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b1606af0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b1606b289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21fcf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21fcf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21fcf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21fcf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b160647e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b160647c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b16062cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b1602dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b1602dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f21fcf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21fcf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21fcf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1602dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c (1247 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv
# | ...
# `---data was truncated (10240/25519) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561aea4615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005561aea430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005561aea4689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa002c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa002ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa002c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa002c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561ae9dbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005561ae9dbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005561ae9c0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005561ae6700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005561ae66fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa002c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa002c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa002c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561ae66fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c (1248 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ea6bc015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557ea6bbd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557ea6bc089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2d8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2d84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2d8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2d8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ea6b55e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557ea6b55c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557ea6b3ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557ea67ea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557ea67e9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb2d8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2d84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2d84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ea67e9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c (1249 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entr
# | ...
# `---data was truncated (10240/18361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056504519b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005650451980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056504519b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3362933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f336298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3362933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f336291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565045130e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565045130c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565045115b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000565044dc50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000565044dc4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f336291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f336291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f336291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565044dc4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c (1250 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 3, i32 0, i32 0, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 9, i32 0, i32 0, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0, i32 1, i32 1, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 3, i32 0, i32 0, i32 1, i32 1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 10, i32 0, i32 0, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 6, i32 0, i32 0, i32 1, i32 1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 10, i32 0, i32 0, i32 1, i32 1, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 13, i32 0, i32 0, i32 0, i32 0, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 7, i32 0, i32 0, i32 1, i32 1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 15, i32 0, i32 0, i32 1, i32 1, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_m_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 6, i32 0, i32 0, i32 0, i32 0, i32 1, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_m_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 
# | ...
# `---data was truncated (10240/73182) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c8a49d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561c8a49a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561c8a49d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6cbeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6cbeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6cbeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6cbeb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c8a432e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561c8a432c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561c8a417b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561c8a0c70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561c8a0c6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6cbeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6cbeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6cbeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c8a0c6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vldr.c (1251 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vldr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_base_wb_s32(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 8
# |   %2 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32> %1, i32 80)
# |   %3 = extractvalue { <4 x i32>, <4 x i32> } %2, 1
# |   store <4 x i32> %3, ptr %0, align 8
# |   %4 = extractvalue { <4 x i32>, <4 x i32> } %2, 0
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_base_wb_f32(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 8
# |   %2 = call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32> %1, i32 64)
# |   %3 = extractvalue { <4 x float>, <4 x i32> } %2, 1
# |   store <4 x i32> %3, ptr %0, align 8
# |   %4 = extractvalue { <4 x float>, <4 x i32> } %2, 0
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_wb_z_u64(ptr noundef %addr, i16 noundef zeroext %p) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %1 = load <2 x i64>, ptr %0, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64> %1, i32 656, <2 x i1> %4)
# |   %6 = extractvalue { <2 x i64>, <2 x i64> } %5, 1
# |   store <2 x i64> %6, ptr %0, align 8
# |   %7 = extractvalue { <2 x i64>, <2 x i64> } %5, 0
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64>, i32, <2 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a66b3915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558a66b360f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558a66b3989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74ae61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74ae6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74ae61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74ae603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a66acee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558a66acec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558a66ab3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558a667630b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558a66762dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f74ae604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74ae6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74ae6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a66762cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c (1252 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vle16_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64
# | ...
# `---data was truncated (10240/71955) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603794ed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005603794ea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005603794ed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa044449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0444a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa044449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa044431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560379482e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560379482c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560379467b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005603791170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560379116dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa044432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0444330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0444330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560379116cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c (1253 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056245781715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005624578140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056245781789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c0ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c0eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c0ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c0ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624577ace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005624577acc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562457791b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005624574410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562457440dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6c0ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c0ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c0ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562457440cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c (1254 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.riscv.vlse.nx
# | ...
# `---data was truncated (10240/83629) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602717b215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005602717af0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005602717b289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13e5e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13e5e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13e5e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13e5e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560271747e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560271747c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056027172cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005602713dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005602713dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f13e5e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13e5e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13e5e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602713dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c (1255 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599dc20615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005599dc2030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005599dc20689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfabc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfabca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfabc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfabc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599dc19be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005599dc19bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005599dc180b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005599dbe300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005599dbe2fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcfabc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfabc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfabc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599dbe2fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c (1256 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/222315) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7813fe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c7813fb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c7813fe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f41cd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41cd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f41cd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f41cd71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c781393e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c781393c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c781378b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c7810280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c781027dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f41cd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41cd71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41cd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c781027cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c (1257 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca targe
# | ...
# `---data was truncated (10240/53556) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f9a55115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557f9a54e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557f9a55189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7175049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71750a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7175049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7175031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f9a4e6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557f9a4e6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557f9a4cbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557f9a17b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557f9a17add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7175032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71750330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71750330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f9a17acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c (1258 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1aab4715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b1aab440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b1aab4789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd179c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd179ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd179c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd179c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1aaadce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b1aaadcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b1aaac1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b1aa7710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b1aa770dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd179c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd179c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd179c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1aa770cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c (1259 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/113757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055564246915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005556424660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055564246989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b2561bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b256725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b2561ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b25603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556423fee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005556423fec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005556423e3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005556420930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555642092dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0b25604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b256050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b256050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555642092cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c (1260 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056486c6d115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056486c6ce0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056486c6d189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb7e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb7e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb7e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb7e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056486c666e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056486c666c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056486c64bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056486c2fb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056486c2fadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feb7e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb7e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb7e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056486c2facc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/neon-3v.c (1261 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-3v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vand_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %and.i = and <8 x i8> %2, %3
# |   store <8 x i8> %and.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vandq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %and.i = and <16 x i8> %2, %3
# |   store <16 x i8> %and.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vand_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %and.i = and <4 x i16> %2, %3
# |   store <4 x i16> %and.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   %3 = load <8 x i16>, ptr %__p1.addr.i, align 16
# |   %and.i = and <8 x i16> %2, %3
# |   store <8 x i16> %and.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vand_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %and.i = and <2 x i32> %2, %3
# |   store <2 x i32> %and.i, ptr %__ret.i, align 8
# |   %4 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vandq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   %3 = load <4 x i32>, ptr %__p1.addr.i, align 16
# |   %and.i = and <4 x i32> %2, %3
# |   store <4 x i32> %and.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vand_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %and.i = and <1 x i64> %2, %3
# |   store <1 x i64> %and.i, ptr %__ret.i, align 8
# |   %4 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vandq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %and.i = and <2 x i64> %2, %3
# |   store <2 x i64> %and.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vand_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %and.i = and <8 x i8> %2, %3
# |   store <8 x i8> %and.i, ptr %__ret.i, align 8
# |   %4 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   %b.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   store <16 x i8> %b, ptr %b.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   %1 = load <16 x i8>, ptr %b.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %and.i = and <16 x i8> %2, %3
# |   store <16 x i8> %and.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vand_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %and.i = and <4 x i16> %2, %3
# |   store <4 x i16> %and.i, ptr %__ret.i, align 8
# |   %4 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vandq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, al
# | ...
# `---data was truncated (10240/70553) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bf039a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559bf03970f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559bf039a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ce4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ce40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ce4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ce4031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bf032fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559bf032fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559bf0314b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559beffc40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559beffc3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4ce4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ce40330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ce40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559beffc3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c (1262 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ba0b7d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560ba0b7a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560ba0b7d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0aaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0aaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0aaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0aaf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ba0b12e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560ba0b12c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560ba0af7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560ba07a70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560ba07a6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc0aaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0aaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0aaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ba07a6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c (1263 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc0605e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dc0605b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dc0605e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafd1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafd138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafd1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafd131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc05ff3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dc05ff3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dc05fd8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dc05c880b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dc05c87dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fafd131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafd131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafd131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc05c87cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c (1264 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557edfe0215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557edfdff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557edfe0289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5f5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5f50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5f5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5f5031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557edfd97e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557edfd97c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557edfd7cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557edfa2c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557edfa2bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff5f5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5f50330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5f50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557edfa2bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/AArch64/poly64.c (1265 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/poly64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -flax-vector-conversions=none  -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -flax-vector-conversions=none -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vceq_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <1 x i64>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %cmp.i = icmp eq <1 x i64> %2, %3
# |   %sext.i = sext <1 x i1> %cmp.i to <1 x i64>
# |   store <1 x i64> %sext.i, ptr %ref.tmp.i, align 8
# |   %4 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %4, ptr %__ret.i, align 8
# |   %5 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vceqq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <2 x i64>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   %3 = load <2 x i64>, ptr %__p1.addr.i, align 16
# |   %cmp.i = icmp eq <2 x i64> %2, %3
# |   %sext.i = sext <2 x i1> %cmp.i to <2 x i64>
# |   store <2 x i64> %sext.i, ptr %ref.tmp.i, align 16
# |   %4 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %4, ptr %__ret.i, align 16
# |   %5 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vtst_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <8 x i8> %2 to <1 x i64>
# |   %5 = bitcast <8 x i8> %3 to <1 x i64>
# |   %6 = and <1 x i64> %4, %5
# |   %7 = icmp ne <1 x i64> %6, zeroinitializer
# |   %vtst.i = sext <1 x i1> %7 to <1 x i64>
# |   store <1 x i64> %vtst.i, ptr %ref.tmp.i, align 8
# |   %8 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %8, ptr %__ret.i, align 8
# |   %9 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vtstq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 16
# |   %__p1.addr.i = alloca <2 x i64>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <2 x i64>
# |   %5 = bitcast <16 x i8> %3 to <2 x i64>
# |   %6 = and <2 x i64> %4, %5
# |   %7 = icmp ne <2 x i64> %6, zeroinitializer
# |   %vtst.i = sext <2 x i1> %7 to <2 x i64>
# |   store <2 x i64> %vtst.i, ptr %ref.tmp.i, align 16
# |   %8 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %8, ptr %__ret.i, align 16
# |   %9 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vcopy_lane_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret_913 = alloca <1 x i64>, align 8
# |   %__s0_913 = alloca <1 x i64>, align 8
# |   %__s2_913 = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s0 = alloca i64, align 8
# |   %__ret1 = alloca i64, align 8
# |   %__s02 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp3 = alloca <1 x i64>, align 8
# |   %tmp4 = alloca <1 x i64>, align 8
# |   %tmp5 = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__s0_913, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %1, ptr %__s2_913, align 8
# |   %2 = load <1 x i64>, ptr %__s2_913, align 8
# |   store <1 x i64> %2, ptr %__s02, align 8
# |   %3 = load <1 x i64>, ptr %__s02, align 8
# |   %vget_lane = extractelement <1 x i64> %3, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %4 = load i64, ptr %ref.tmp, align 8
# |   store i64 %4, ptr %__ret1, align 8
# |   %5 = load i64, ptr %__ret1, align 8
# |   store i64 %5, ptr %tmp, align 8
# |   %6 = load i64, ptr %tmp, align 8
# |   store i64 %6, ptr %__s0, align 8
# |   %7 = load <1 x i64>, ptr %__s0_913, align 8
# |   store <1 x i64> %7, ptr %__s1, align 8
# |   %8 = load i64, ptr %__s0, align 8
# |   %9 = load <1 x i64>, ptr %__s1, align 8
# |   %vset_lane = insertelement <1 x i64> %9, i64 %8, i32 0
# |   store <1 x i64> %vset_lane, ptr %ref.tmp3, align 8
# |   %10 = load <1 x i64>, ptr %ref.tmp3, align 8
# |   store <1 x i64> %10, ptr %__ret, align 8
# |   %11 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %11, ptr %tmp4, align 8
# |   %12 = load <1 x i64>, ptr %tmp4, align 8
# |   store <1 x i64> %12, ptr %__ret_913, align 8
# |   %13 = load <1 x i64>, ptr %__ret_913, align 8
# |   store <1 x i64> %13, ptr %tmp5, align 8
# |   %14 = load <1 x i64>, ptr %tmp5, align 8
# |   ret <1 x i64> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcopyq_lane_p64(<2 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret_909 = alloca <2 x i64>, align 16
# |   %__s0_909 = alloca <2 x i64>, align 16
# |   %__s2_909 = alloca <1 x i64>, align 8
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s0 = alloca i64, align 8
# |   %__ret1 = alloca i64, align 8
# |   %__s02 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp3 = alloca <2 x i64>, align 16
# |   %tmp4 = alloca <2 x i64>, align 16
# |   %tmp5 = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__s0_909, align 16
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %1, ptr %__s2_909, align 8
# |   %2 = load <1 x i64>, ptr %__s2_909, align 8
# |   store <1 x i64> %2, ptr %__s02, align 8
# |   %3 = load <1 x i64>, ptr %__s02, align 8
# |   %vget_lane = extractelement <1 x i64> %3, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %4 = load i64, ptr %ref.tmp, align 8
# |   store i64 %4, ptr %__ret1, align 8
# |   %5 = load i64, ptr %__ret1, align 8
# |   store i64 %5, ptr %tmp, align 8
# |   %6 = load i64, ptr %tmp, align 8
# |   store i64 %6, ptr %__s0, align 8
# |   %7 = load <2 x i64>, ptr %__s0_909, align 16
# |   store <2 x i64> %7, ptr %__s1, align 16
# |   %8 = load i64, ptr %__s0, align 8
# |   %9 = load <2 x i64>, ptr %__s1, align 16
# |   %vset_lane = insertelement <2 x i64> %9, i64 %8, i32 1
# |   store <2 x i64> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <2 x i64>, ptr %ref.tmp3, align 16
# |   store <2 x i64> %10, ptr %__ret, align 16
# |   %11 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %11, ptr %tmp4, align 16
# |   %12 = load <2 x i64>, ptr %tmp4, align 16
# |   store <2 x i64> %12, ptr %__ret_909, align 16
# |   %13 = load <2 x i64>, ptr %__ret_909, align 16
# |   store <2 x i64> %13, ptr %tmp5, align 16
# |   %14 = load <2 x i64>, ptr %tmp5, align 16
# |   ret <2 x i64> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcopyq_laneq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret_915 = alloca <2 x i64>, align 16
# |   %__s0_915 = alloca <2 x i64>, align 16
# |   %__s2_915 = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s0 = alloca i64, align 8
# |   %__ret1 = alloca i64, align 8
# |   %__s02 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp3 = alloca <2 x i64>, align 16
# |   %tmp4 = alloca <2 x i64>, align 16
# |   %tmp5 = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   store <2 x i64> %0, ptr %__s0_915, align 16
# |   %1 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %1, ptr %__s2_915, align 16
# |   %2 = load <2 x i64>, ptr %__s2_915, align 16
# |   store <2 x i64> %2, ptr %__s02, align 16
# |   %3 = load <2 x i64>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <2 x i64> %3, i32 1
# |   store i64 %vgetq_lane, ptr %ref.tmp, align 8
# |   %4 = load i64, ptr %ref.tmp, align 8
# |   store i64 %4, ptr %__ret1, align 8
# |   %5 = 
# | ...
# `---data was truncated (10240/22456) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055c26cb5015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c26cb4d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c26cb5089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21adf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21adf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21adf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21adf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c26cae5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c26cae5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c26cacab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c26c77a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c26c779dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f21adf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21adf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21adf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c26c779cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c (1266 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/129190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564ea37815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005564ea3750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005564ea37889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6027649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60276a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6027649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6027631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564ea30de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005564ea30dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005564ea2f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005564e9fa20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005564e9fa1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6027632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60276330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60276330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564e9fa1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c (1267 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 1
# | ...
# `---data was truncated (10240/227763) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055818ba8215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055818ba7f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055818ba8289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8454f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8454f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8454f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8454f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055818ba17e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055818ba17c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055818b9fcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055818b6ac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055818b6abdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8454f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8454f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8454f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055818b6abcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c (1268 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005616b6de715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005616b6de40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005616b6de789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc966133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc96618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc966133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc96611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616b6d7ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005616b6d7cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005616b6d61b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005616b6a110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005616b6a10dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc96611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc96611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc96611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616b6a10cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c (1269 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055833253b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005583325380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055833253b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff7c105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff7c15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff7c105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff7c0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583324d0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005583324d0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005583324b5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005583321650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558332164dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007eff7c0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff7c0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff7c0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558332164cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c (1270 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d29993515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d2999320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d29993589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1dca249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1dca2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1dca249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1dca231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2998cae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d2998cac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d2998afb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d29955f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d29955edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1dca232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1dca2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1dca2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d29955ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c (1271 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tupl
# | ...
# `---data was truncated (10240/88444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577f313a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005577f31370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005577f313a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb390249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb3902a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb390249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb390231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577f30cfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005577f30cfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005577f30b4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005577f2d640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005577f2d63dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb390232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb3902330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb3902330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577f2d63cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c (1272 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db8afae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055db8afab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055db8afae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d60133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d6018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d60133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d6011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db8af43e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055db8af43c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055db8af28b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055db8abd80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055db8abd7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6d6011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d6011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d6011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db8abd7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c (1273 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a33a43515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a33a4320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a33a43589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde41333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde4138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde41333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde4131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a33a3cae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a33a3cac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a33a3afb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a33a05f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a33a05edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fde4131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde4131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde4131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a33a05ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c (1274 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfadd_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscal
# | ...
# `---data was truncated (10240/29510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605e14c915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005605e14c60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005605e14c989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f351c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f351c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f351c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f351c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605e145ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005605e145ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005605e1443b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005605e10f30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005605e10f2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f351c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f351c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f351c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605e10f2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c (1275 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb68f4d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fb68f4a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fb68f4d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f742e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f742e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f742e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f742e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb68ee2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fb68ee2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fb68ec7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fb68b770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fb68b76dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f742e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f742e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f742e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb68b76cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c (1276 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 
# | ...
# `---data was truncated (10240/26572) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055610262215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055610261f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055610262289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc849449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8494a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc849449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc849431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561025b7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005561025b7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055610259cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055610224c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055610224bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc849432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8494330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8494330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055610224bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c (1277 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.
# | ...
# `---data was truncated (10240/78690) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfd12c315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dfd12c00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dfd12c389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1315133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f131518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1315133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f131511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfd1258e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dfd1258c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dfd123db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dfd0eed0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dfd0eecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f131511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f131511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f131511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfd0eeccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c (1278 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eff405515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eff40520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eff405589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1314f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1314f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1314f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1314f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eff3feae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eff3feac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eff3fcfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eff3c7f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eff3c7edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1314f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1314f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1314f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eff3c7ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c (1279 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4_tu(<vscale x 16 x half> %maske
# | ...
# `---data was truncated (10240/157777) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a51fca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564a51fc70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564a51fca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f4e105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f4e15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f4e105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f4e0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a51f5fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564a51f5fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564a51f44b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564a51bf40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564a51bf3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5f4e0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f4e0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f4e0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a51bf3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c (1280 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8
# | ...
# `---data was truncated (10240/80508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ded89715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556ded8940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556ded89789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f980a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f980a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f980a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f980a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ded82ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556ded82cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556ded811b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556ded4c10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556ded4c0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f980a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f980a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f980a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ded4c0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c (1281 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/151903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f4aca415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562f4aca10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562f4aca489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f547c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f547c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f547c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f547c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f4ac39e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562f4ac39c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562f4ac1eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562f4a8ce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562f4a8cddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f547c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f547c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f547c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f4a8cdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c (1282 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055571abea15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055571abe70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055571abea89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe977333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe97738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe977333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe97731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055571ab7fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055571ab7fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055571ab64b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055571a8140b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055571a813dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe97731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe97731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe97731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055571a813cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c (1283 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x f
# | ...
# `---data was truncated (10240/70110) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644da38d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005644da38a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005644da38d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1bb6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1bb6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1bb6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1bb6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644da322e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005644da322c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005644da307b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005644d9fb70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005644d9fb6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1bb6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1bb6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1bb6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644d9fb6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c (1284 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willret
# | ...
# `---data was truncated (10240/15203) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618a21c215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005618a21bf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005618a21c289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a46849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a468a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a46849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a46831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618a2157e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005618a2157c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005618a213cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005618a1dec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005618a1debdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6a46832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a468330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a468330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618a1debcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c (1285 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vclz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vclz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vclz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vclz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(
# | ...
# `---data was truncated (10240/40661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ddc845915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ddc84560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ddc845989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e1e61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e1e6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e1e61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e1e603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddc83eee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ddc83eec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ddc83d3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ddc80830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ddc8082dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1e1e604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e1e6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e1e6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddc8082cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c (1286 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ...
# `---data was truncated (10240/64958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f1f112415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f1f11210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f1f112489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72dcf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72dcf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72dcf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72dcf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1f10b9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f1f10b9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f1f109eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f1f0d4e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f1f0d4ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f72dcf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72dcf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72dcf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f1f0d4dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c (1287 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.bf16.nxv8bf16.i6
# | ...
# `---data was truncated (10240/51694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c33e2ad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c33e2aa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c33e2ad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4825333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f482538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4825333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f482531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c33e242e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c33e242c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c33e227b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c33ded70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c33ded6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f482531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f482531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f482531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c33ded6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c (1288 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005654651ad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005654651aa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005654651ad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc309c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc309c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc309c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc309c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565465142e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565465142c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565465127b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000565464dd70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000565464dd6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc309c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc309c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc309c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565464dd6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c (1289 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> %1, <vsc
# | ...
# `---data was truncated (10240/12290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba219ae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ba219ab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ba219ae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4a5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4a5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4a5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4a5d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba21943e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ba21943c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ba21928b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ba215d80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ba215d7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe4a5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4a5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4a5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba215d7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c (1290 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571e620515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005571e62020f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005571e620589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb92fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb92fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb92fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb92fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571e619ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005571e619ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005571e617fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005571e5e2f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005571e5e2edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb92fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb92fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb92fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571e5e2ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c (1291 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# | 
# | ...
# `---data was truncated (10240/225655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc95e0b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fc95e080f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fc95e0b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e32249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e322a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e32249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e32231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc95da0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fc95da0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fc95d85b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fc95a350b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fc95a34dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4e32232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e322330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e322330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc95a34cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c (1292 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i
# | ...
# `---data was truncated (10240/14325) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564df542915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564df54260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564df542989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcacbb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcacbb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcacbb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcacbaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564df53bee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564df53bec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564df53a3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564df50530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564df5052dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcacbaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcacbaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcacbaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564df5052cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c (1293 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e373ca515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e373ca20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e373ca589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5267649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52676a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5267649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5267631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e373c3ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e373c3ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e373c1fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e3738cf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e3738cedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5267632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52676330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52676330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3738cecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c (1294 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055647942e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055647942b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055647942e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f9e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f9e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f9e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f9e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564793c3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005564793c3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005564793a8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005564790580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556479057dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9f9e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f9e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f9e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556479057cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c (1295 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf2_u32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16m1_u32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 
# | ...
# `---data was truncated (10240/43617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c896f2215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c896f1f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c896f2289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48b0505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48b055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48b0505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48b04ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c896eb7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c896eb7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c896e9cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c896b4c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c896b4bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f48b04eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48b04ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48b04ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c896b4bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c (1296 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale 
# | ...
# `---data was truncated (10240/150951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2265b515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f2265b20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f2265b589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06e2505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06e255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06e2505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06e24ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f22654ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f22654ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f22652fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f2261df0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f2261dedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f06e24eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06e24ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06e24ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2261decc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c (1297 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vabs_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vabs_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i
# | ...
# `---data was truncated (10240/41094) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589959eb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005589959e80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005589959eb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbd7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbd74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbd7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbd7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558995980e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558995980c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558995965b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005589956150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558995614dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcbd7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbd74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbd74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558995614cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c (1298 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055778e4fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055778e4f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055778e4fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb19f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb19f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb19f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb19f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055778e490e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055778e490c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055778e475b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055778e1250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055778e124dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbb19f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb19f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb19f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055778e124cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c (1299 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c9856215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555c9855f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555c9856289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e96333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e9638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e96333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e9631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c984f7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555c984f7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555c984dcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555c9818c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555c9818bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8e9631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e9631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e9631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c9818bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c (1300 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %o
# | ...
# `---data was truncated (10240/29054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f989a0e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f989a0b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f989a0e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57c6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57c62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57c6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57c6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9899a3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f9899a3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f989988b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f9896380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f989637dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f57c6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57c62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57c62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f989637cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c (1301 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/12433) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5d578515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b5d57820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b5d578589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f31533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f3158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f31533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f3151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5d571ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b5d571ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b5d56ffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b5d53af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b5d53aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0f3151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f3151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f3151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5d53aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c (1302 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { ta
# | ...
# `---data was truncated (10240/27858) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7ce4a215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d7ce49f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d7ce4a289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f790e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f790e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f790e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f790e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7ce437e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d7ce437c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d7ce41cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d7ce0cc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d7ce0cbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f790e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f790e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f790e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7ce0cbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c (1303 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssubu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vsca
# | ...
# `---data was truncated (10240/98171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd01ac215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bd01abf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bd01ac289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd92e705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd92e75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd92e705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd92e6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd01a57e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bd01a57c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bd01a3cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bd016ec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bd016ebdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd92e6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd92e6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd92e6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd016ebcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c (1304 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055995c35a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055995c3570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055995c35a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35a5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35a538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35a5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35a531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055995c2efe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055995c2efc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055995c2d4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055995bf840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055995bf83dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f35a531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35a531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35a531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055995bf83cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c (1305 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/129190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc40cdd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dc40cda0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dc40cdd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f14e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f14ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f14e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f14e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc40c72e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dc40c72c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dc40c57b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dc409070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dc40906dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5f14e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f14e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f14e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc40906cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c (1306 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vandn_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vandn.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vandn_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vandn.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vandn_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vandn.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vandn_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vandn.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vandn_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   
# | ...
# `---data was truncated (10240/223129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d50d3915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563d50d360f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563d50d3989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbac3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbac3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbac3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbac3c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d50ccee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563d50ccec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563d50cb3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563d509630b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563d50962dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbac3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbac3c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbac3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d50962cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c (1307 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 
# | ...
# `---data was truncated (10240/12015) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056065728e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056065728b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056065728e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83f3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83f3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83f3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83f3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560657223e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560657223c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560657208b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560656eb80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560656eb7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f83f3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83f3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83f3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560656eb7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c (1308 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdiv_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6caa0715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e6caa040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e6caa0789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e55b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e55b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e55b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e55b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6ca99ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e6ca99cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e6ca981b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e6ca6310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e6ca630dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0e55b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e55b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e55b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6ca630cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c (1309 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8mf8(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 3, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 immarg, <vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8mf4(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i16.nxv2i8.nxv2i8.i32(i32 3, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i16.nxv2i8.nxv2i8.i32(i32 immarg, <vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8mf2(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i16.nxv4i8.nxv4i8.i32(i32 3, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i16.nxv4i8.nxv4i8.i32(i32 immarg, <vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8m1(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i16.nxv8i8.nxv8i8.i32(i32 3, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i16.nxv8i8.nxv8i8.i32(i32 immarg, <vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8m2(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i16.nxv16i8.nxv16i8.i32(i32 3, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i16.nxv16i8.nxv16i8.i32(i32 immarg, <vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u8m4(<vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv32i16.nxv32i8.nxv32i8.i32(i32 3, <vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv32i16.nxv32i8.nxv32i8.i32(i32 immarg, <vscale x 32 x i16>, <vscale x 32 x i8>, <vscale x 32 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u16mf4(<vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i32.nxv1i16.nxv1i16.i32(i32 3, <vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i32.nxv1i16.nxv1i16.i32(i32 immarg, <vscale x 1 x i32>, <vscale x 1 x i16>, <vscale x 1 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u16mf2(<vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i32.nxv2i16.nxv2i16.i32(i32 3, <vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i32.nxv2i16.nxv2i16.i32(i32 immarg, <vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvw_se_u16m1(<vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void
# | ...
# `---data was truncated (10240/179328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9bf3cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c9bf3cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c9bf3cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f818b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f818b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f818b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f818b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9bf364e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c9bf364c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c9bf349b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c9beff90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c9beff8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f818b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f818b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f818b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9beff8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c (1310 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsub_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @
# | ...
# `---data was truncated (10240/61058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c0a3f615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558c0a3f30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558c0a3f689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa039533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa03958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa039533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa03951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c0a38be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558c0a38bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558c0a370b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558c0a0200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558c0a01fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa03951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa03951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa03951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c0a01fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c (1311 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhsu_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %
# | ...
# `---data was truncated (10240/66087) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563e98bf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005563e98bc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005563e98bf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd65cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd65cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd65cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd65cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563e9854e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005563e9854c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005563e9839b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005563e94e90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005563e94e8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd65cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd65cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd65cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563e94e8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c (1312 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055591406a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005559140670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055591406a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8371e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8371ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8371e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8371e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555913fffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555913fffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555913fe4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555913c940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555913c93dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8371e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8371e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8371e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555913c93cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c (1313 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c  -check-prefix=RV64ZKNH
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sig0(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sig0(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sig1(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sig1(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sum0(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sum0(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @sha512sum1(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.sha512sum1(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sig0(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sig1(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sum0(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @sha256sum1(i32 noundef signext %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sig0(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sig1(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sum0(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.sha512sum1(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum1(i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknh" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zknh1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a475ed215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a475ecf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a475ed289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad89b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad89b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad89b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad89b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a475e67e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a475e67c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a475e4cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a475afc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a475afbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fad89b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad89b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad89b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a475afbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c (1314 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556808e2b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556808e280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556808e2b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12c7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12c738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12c7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12c731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556808dc0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556808dc0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556808da5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556808a550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556808a54dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f12c731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12c731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12c731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556808a54cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c (1315 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bfeb0df15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bfeb0dc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bfeb0df89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8bb1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8bb1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8bb1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8bb1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfeb074e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bfeb074c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bfeb059b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bfead090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bfead08dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8bb1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8bb1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8bb1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfead08cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c (1316 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i6
# | ...
# `---data was truncated (10240/25511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558eacc9b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558eacc980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558eacc9b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff80f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff80f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff80f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff80f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558eacc30e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558eacc30c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558eacc15b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558eac8c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558eac8c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff80f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff80f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff80f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558eac8c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c (1317 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4_tu(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8_tu(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1_tu(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2_tu(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, pt
# | ...
# `---data was truncated (10240/73955) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563043a3e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563043a3b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563043a3e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f400ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f400ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f400ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f400ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630439d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005630439d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005630439b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005630436680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563043667dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f400ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f400ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f400ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563043667cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c (1318 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_u64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_u64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vs
# | ...
# `---data was truncated (10240/23775) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613f834115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005613f833e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005613f834189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f6f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f6f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f6f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f6f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613f82d6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005613f82d6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005613f82bbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005613f7f6b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005613f7f6add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5f6f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f6f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f6f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613f7f6acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c (1319 of 27911)
******************** TEST 'Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature +fullfp16  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "armv8.2a-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vabs_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vabs.i = bitcast <8 x i8> %1 to <4 x half>
# |   %vabs1.i = call <4 x half> @llvm.fabs.v4f16(<4 x half> %vabs.i)
# |   store <4 x half> %vabs1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vabs.i = bitcast <16 x i8> %1 to <8 x half>
# |   %vabs1.i = call <8 x half> @llvm.fabs.v8f16(<8 x half> %vabs.i)
# |   store <8 x half> %vabs1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vceqz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oeq <4 x half> %2, zeroinitializer
# |   %vceqz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vceqz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oeq <8 x half> %2, zeroinitializer
# |   %vceqz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vceqz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp oge <4 x half> %2, zeroinitializer
# |   %vcgez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp oge <8 x half> %2, zeroinitializer
# |   %vcgez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ogt <4 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcgtz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ogt <8 x half> %2, zeroinitializer
# |   %vcgtz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcgtz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vclez_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp ole <4 x half> %2, zeroinitializer
# |   %vclez.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vclez.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vclezq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp ole <8 x half> %2, zeroinitializer
# |   %vclez.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vclez.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vcltz_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %2 = bitcast <8 x i8> %1 to <4 x half>
# |   %3 = fcmp olt <4 x half> %2, zeroinitializer
# |   %vcltz.i = sext <4 x i1> %3 to <4 x i16>
# |   store <4 x i16> %vcltz.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %2 = bitcast <16 x i8> %1 to <8 x half>
# |   %3 = fcmp olt <8 x half> %2, zeroinitializer
# |   %vcltz.i = sext <8 x i1> %3 to <8 x i16>
# |   store <8 x i16> %vcltz.i, ptr %ref.tmp.i, align 16
# |   %4 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %4, ptr %__ret.i, align 16
# |   %5 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloc
# | ...
# `---data was truncated (10240/122004) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000556e7466a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556e746670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556e7466a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa19a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa19a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa19a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa19a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e745ffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556e745ffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556e745e4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556e742940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556e74293dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa19a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa19a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa19a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e74293cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c (1320 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/24982) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638b4fa715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005638b4fa40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005638b4fa789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff84cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff84cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff84cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff84cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638b4f3ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005638b4f3cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005638b4f21b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005638b4bd10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005638b4bd0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff84cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff84cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff84cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638b4bd0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/cx-complex-range.c (1321 of 27911)
******************** TEST 'Clang :: CodeGen/cx-complex-range.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown  -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @divf(<2 x float> noundef %a.coerce, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b = alloca { float, float }, align 4
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %call = call <2 x float> @__divsc3(float noundef %a.real, float noundef %a.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %coerce.real, ptr %retval.realp, align 4
# |   store float %coerce.imag, ptr %retval.imagp, align 4
# |   %0 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %0
# | }
# | 
# | declare <2 x float> @__divsc3(float, float, float, float)
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignf(ptr noundef %a, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %b = alloca { float, float }, align 4
# |   %a.addr = alloca ptr, align 8
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %call = call <2 x float> @__divsc3(float noundef %.real, float noundef %.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   %.realp1 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   store float %coerce.real, ptr %.realp1, align 4
# |   store float %coerce.imag, ptr %.imagp2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @mulf(<2 x float> noundef %a.coerce, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b = alloca { float, float }, align 4
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %mul_ac = fmul float %a.real, %b.real
# |   %mul_bd = fmul float %a.imag, %b.imag
# |   %mul_ad = fmul float %a.real, %b.imag
# |   %mul_bc = fmul float %a.imag, %b.real
# |   %mul_r = fsub float %mul_ac, %mul_bd
# |   %mul_i = fadd float %mul_ad, %mul_bc
# |   %isnan_cmp = fcmp uno float %mul_r, %mul_r
# |   br i1 %isnan_cmp, label %complex_mul_imag_nan, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_imag_nan:                             ; preds = %entry
# |   %isnan_cmp1 = fcmp uno float %mul_i, %mul_i
# |   br i1 %isnan_cmp1, label %complex_mul_libcall, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_libcall:                              ; preds = %complex_mul_imag_nan
# |   %call = call <2 x float> @__mulsc3(float noundef %a.real, float noundef %a.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   br label %complex_mul_cont
# | 
# | complex_mul_cont:                                 ; preds = %complex_mul_libcall, %complex_mul_imag_nan, %entry
# |   %real_mul_phi = phi float [ %mul_r, %entry ], [ %mul_r, %complex_mul_imag_nan ], [ %coerce.real, %complex_mul_libcall ]
# |   %imag_mul_phi = phi float [ %mul_i, %entry ], [ %mul_i, %complex_mul_imag_nan ], [ %coerce.imag, %complex_mul_libcall ]
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %real_mul_phi, ptr %retval.realp, align 4
# |   store float %imag_mul_phi, ptr %retval.imagp, align 4
# |   %0 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %0
# | }
# | 
# | declare <2 x float> @__mulsc3(float, float, float, float)
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mulassignf(ptr noundef %a, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %b = alloca { float, float }, align 4
# |   %a.addr = alloca ptr, align 8
# |   %coerce = alloca { float, float }, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %mul_ac = fmul float %.real, %b.real
# |   %mul_bd = fmul float %.imag, %b.imag
# |   %mul_ad = fmul float %.real, %b.imag
# |   %mul_bc = fmul float %.imag, %b.real
# |   %mul_r = fsub float %mul_ac, %mul_bd
# |   %mul_i = fadd float %mul_ad, %mul_bc
# |   %isnan_cmp = fcmp uno float %mul_r, %mul_r
# |   br i1 %isnan_cmp, label %complex_mul_imag_nan, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_imag_nan:                             ; preds = %entry
# |   %isnan_cmp1 = fcmp uno float %mul_i, %mul_i
# |   br i1 %isnan_cmp1, label %complex_mul_libcall, label %complex_mul_cont, !prof !2
# | 
# | complex_mul_libcall:                              ; preds = %complex_mul_imag_nan
# |   %call = call <2 x float> @__mulsc3(float noundef %.real, float noundef %.imag, float noundef %b.real, float noundef %b.imag) #2
# |   store <2 x float> %call, ptr %coerce, align 4
# |   %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0
# |   %coerce.real = load float, ptr %coerce.realp, align 4
# |   %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1
# |   %coerce.imag = load float, ptr %coerce.imagp, align 4
# |   br label %complex_mul_cont
# | 
# | complex_mul_cont:                                 ; preds = %complex_mul_libcall, %complex_mul_imag_nan, %entry
# |   %real_mul_phi = phi float [ %mul_r, %entry ], [ %mul_r, %complex_mul_imag_nan ], [ %coerce.real, %complex_mul_libcall ]
# |   %imag_mul_phi = phi float [ %mul_i, %entry ], [ %mul_i, %complex_mul_imag_nan ], [ %coerce.imag, %complex_mul_libcall ]
# |   %.realp2 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0
# |   %.imagp3 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1
# |   store float %real_mul_phi, ptr %.realp2, align 4
# |   store float %imag_mul_phi, ptr %.imagp3, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local { double, double } @divd(double noundef %a.coerce0, double noundef %a.coerce1, double noundef %b.coerce0, double noundef %b.coerce1) #1 {
# | entry:
# |   %retval = alloca { double, double }, align 8
# |   %a = alloca { double, double }, align 8
# |   %b = alloca { double, double }, align 8
# |   %0 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   store double %a.coerce0, ptr %0, align 8
# |   %1 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   store double %a.coerce1, ptr %1, align 8
# |   %2 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0
# |   store double %b.coerce0, ptr %2, align 8
# |   %3 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1
# |   store double %b.coerce1, ptr %3, align 8
# |   %a.realp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   %a.real = load double, ptr %a.realp, align 8
# |   %a.imagp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   %a.imag = load doub
# | ...
# `---data was truncated (10240/29171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005563b6cb415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005563b6cb10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005563b6cb489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64d3d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64d3d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64d3d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64d3ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563b6c49e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005563b6c49c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005563b6c2eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005563b68de0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005563b68dddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f64d3ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64d3cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64d3cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563b68ddcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c (1322 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602281e915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005602281e60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005602281e989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe512733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe51278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe512733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe51271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056022817ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056022817ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560228163b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560227e130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560227e12dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe51271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe51271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe51271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560227e12cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c (1323 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x floa
# | ...
# `---data was truncated (10240/118156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e51e2c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560e51e290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560e51e2c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ce6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ce638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ce6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ce631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e51dc1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560e51dc1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560e51da6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560e51a560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560e51a55dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2ce631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ce631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ce631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e51a55cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c (1324 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredxor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredxor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/94379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c24fb015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563c24fad0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563c24fb089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7480a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7480aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7480a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7480a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c24f45e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563c24f45c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563c24f2ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563c24bda0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563c24bd9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7480a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7480a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7480a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c24bd9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c (1325 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558fc005515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558fc00520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558fc005589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff66db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff66db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff66db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff66db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558fbffeae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558fbffeac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558fbffcfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558fbfc7f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558fbfc7edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff66db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff66db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff66db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558fbfc7ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c (1326 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/284336) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bdf5db15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563bdf5d80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563bdf5db89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa964d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa964d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa964d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa964ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bdf570e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563bdf570c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563bdf555b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563bdf2050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563bdf204dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa964ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa964cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa964cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bdf204cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c (1327 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 
# | ...
# `---data was truncated (10240/80500) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf72c4d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bf72c4a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bf72c4d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9d3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9d34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9d3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9d3431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf72be2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bf72be2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bf72bc7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bf728770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bf72876dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff9d3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9d34330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9d34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf72876cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c (1328 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_loc
# | ...
# `---data was truncated (10240/37556) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056482e20315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056482e2000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056482e20389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf9a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf9a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf9a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf9a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056482e198e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056482e198c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056482e17db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056482de2d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056482de2cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbf9a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf9a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf9a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056482de2ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon-vcombine.c (1329 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vcombine.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vcombine_s8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %low.addr = alloca <8 x i8>, align 8
# |   %high.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %low, ptr %low.addr, align 8
# |   store <8 x i8> %high, ptr %high.addr, align 8
# |   %0 = load <8 x i8>, ptr %low.addr, align 8
# |   %1 = load <8 x i8>, ptr %high.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcombine_s16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %low.addr = alloca <4 x i16>, align 8
# |   %high.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %low, ptr %low.addr, align 8
# |   store <4 x i16> %high, ptr %high.addr, align 8
# |   %0 = load <4 x i16>, ptr %low.addr, align 8
# |   %1 = load <4 x i16>, ptr %high.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i16> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcombine_s32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %low.addr = alloca <2 x i32>, align 8
# |   %high.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %low, ptr %low.addr, align 8
# |   store <2 x i32> %high, ptr %high.addr, align 8
# |   %0 = load <2 x i32>, ptr %low.addr, align 8
# |   %1 = load <2 x i32>, ptr %high.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i32> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcombine_s64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %low.addr = alloca <1 x i64>, align 8
# |   %high.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %low, ptr %low.addr, align 8
# |   store <1 x i64> %high, ptr %high.addr, align 8
# |   %0 = load <1 x i64>, ptr %low.addr, align 8
# |   %1 = load <1 x i64>, ptr %high.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> <i32 0, i32 1>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vcombine_u8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %low.addr = alloca <8 x i8>, align 8
# |   %high.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %low, ptr %low.addr, align 8
# |   store <8 x i8> %high, ptr %high.addr, align 8
# |   %0 = load <8 x i8>, ptr %low.addr, align 8
# |   %1 = load <8 x i8>, ptr %high.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   store <16 x i8> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vcombine_u16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %low.addr = alloca <4 x i16>, align 8
# |   %high.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %low, ptr %low.addr, align 8
# |   store <4 x i16> %high, ptr %high.addr, align 8
# |   %0 = load <4 x i16>, ptr %low.addr, align 8
# |   %1 = load <4 x i16>, ptr %high.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x i16>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x i16> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcombine_u32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %low.addr = alloca <2 x i32>, align 8
# |   %high.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %low, ptr %low.addr, align 8
# |   store <2 x i32> %high, ptr %high.addr, align 8
# |   %0 = load <2 x i32>, ptr %low.addr, align 8
# |   %1 = load <2 x i32>, ptr %high.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <2 x i32>, ptr %__p0.addr.i, align 8
# |   %3 = load <2 x i32>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
# |   store <4 x i32> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcombine_u64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %low.addr = alloca <1 x i64>, align 8
# |   %high.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %low, ptr %low.addr, align 8
# |   store <1 x i64> %high, ptr %high.addr, align 8
# |   %0 = load <1 x i64>, ptr %low.addr, align 8
# |   %1 = load <1 x i64>, ptr %high.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> <i32 0, i32 1>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vcombine_p64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %low.addr = alloca <1 x i64>, align 8
# |   %high.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %low, ptr %low.addr, align 8
# |   store <1 x i64> %high, ptr %high.addr, align 8
# |   %0 = load <1 x i64>, ptr %low.addr, align 8
# |   %1 = load <1 x i64>, ptr %high.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   %3 = load <1 x i64>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> <i32 0, i32 1>
# |   store <2 x i64> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcombine_f16(<4 x half> noundef %low, <4 x half> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <8 x half>, align 16
# |   %low.addr = alloca <4 x half>, align 8
# |   %high.addr = alloca <4 x half>, align 8
# |   store <4 x half> %low, ptr %low.addr, align 8
# |   store <4 x half> %high, ptr %high.addr, align 8
# |   %0 = load <4 x half>, ptr %low.addr, align 8
# |   %1 = load <4 x half>, ptr %high.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x half>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x half> %2, <4 x half> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x half> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcombine_f32(<2 x float> noundef %low, <2 x float> noundef %high) #0 {
# | entry:
# |   %__p0.addr.
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0bd56915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f0bd5660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f0bd56989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3aaeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3aaeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3aaeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3aaeb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0bd4fee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f0bd4fec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f0bd4e3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f0bd1930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f0bd192dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3aaeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3aaeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3aaeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0bd192cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c (1330 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv
# | ...
# `---data was truncated (10240/53726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555863edb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555863ed80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555863edb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc685e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc685e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc685e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc685e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555863e70e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555863e70c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555863e55b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555863b050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555863b04dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc685e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc685e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc685e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555863b04cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/builtins-arm.c (1331 of 27911)
******************** TEST 'Clang :: CodeGen/builtins-arm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv7-unknown-unknown-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @f0() #0 {
# | entry:
# |   %0 = call ptr @llvm.thread.pointer.p0()
# |   ret ptr %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare ptr @llvm.thread.pointer.p0() #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @f1(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   %b.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   store ptr %b, ptr %b.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load ptr, ptr %b.addr, align 4
# |   call void @llvm.clear_cache.p0(ptr %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.clear_cache.p0(ptr, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vcvtrf0(float noundef %f) #0 {
# | entry:
# |   %f.addr = alloca float, align 4
# |   store float %f, ptr %f.addr, align 4
# |   %0 = load float, ptr %f.addr, align 4
# |   %vcvtr = call float @llvm.arm.vcvtr.f32(float %0)
# |   ret float %vcvtr
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtr.f32(float) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_vcvtrf1(float noundef %f) #0 {
# | entry:
# |   %f.addr = alloca float, align 4
# |   store float %f, ptr %f.addr, align 4
# |   %0 = load float, ptr %f.addr, align 4
# |   %vcvtr = call float @llvm.arm.vcvtru.f32(float %0)
# |   ret float %vcvtr
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtru.f32(float) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vcvtrd0(double noundef %d) #0 {
# | entry:
# |   %d.addr = alloca double, align 8
# |   store double %d, ptr %d.addr, align 8
# |   %0 = load double, ptr %d.addr, align 8
# |   %vcvtr = call float @llvm.arm.vcvtr.f64(double %0)
# |   %conv = fpext float %vcvtr to double
# |   ret double %conv
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtr.f64(double) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_vcvtrd1(double noundef %d) #0 {
# | entry:
# |   %d.addr = alloca double, align 8
# |   store double %d, ptr %d.addr, align 8
# |   %0 = load double, ptr %d.addr, align 8
# |   %vcvtr = call float @llvm.arm.vcvtru.f64(double %0)
# |   %conv = fpext float %vcvtr to double
# |   ret double %conv
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.vcvtru.f64(double) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_eh_return_data_regno() #0 {
# | entry:
# |   %res = alloca i32, align 4
# |   store volatile i32 0, ptr %res, align 4
# |   store volatile i32 1, ptr %res, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @nop() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.hint(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @yield() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wfe() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wfi() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @sev() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @sevl() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @dbg() #0 {
# | entry:
# |   call void @llvm.arm.dbg(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dbg(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_barrier() #0 {
# | entry:
# |   call void @llvm.arm.dmb(i32 1)
# |   call void @llvm.arm.dsb(i32 2)
# |   call void @llvm.arm.isb(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dmb(i32) #2
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dsb(i32) #2
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.isb(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rbit(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %rbit = call i32 @llvm.bitreverse.i32(i32 %0)
# |   ret i32 %rbit
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.bitreverse.i32(i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @prefetch(i32 noundef %i) #0 {
# | entry:
# |   %i.addr = alloca i32, align 4
# |   store i32 %i, ptr %i.addr, align 4
# |   call void @llvm.prefetch.p0(ptr %i.addr, i32 0, i32 3, i32 1)
# |   call void @llvm.prefetch.p0(ptr %i.addr, i32 1, i32 3, i32 1)
# |   call void @llvm.prefetch.p0(ptr %i.addr, i32 1, i32 3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg range(i32 0, 2), i32 immarg range(i32 0, 4), i32 immarg range(i32 0, 2)) #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldc(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldc(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldc(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldcl(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldcl(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldcl(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldc2(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldc2(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldc2(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @ldc2l(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.ldc2l(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.ldc2l(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stc(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stc(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stc(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stcl(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stcl(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stcl(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stc2(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stc2(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stc2(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @stc2l(ptr noundef %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 4
# |   store ptr %i, ptr %i.addr, align 4
# |   %0 = load ptr, ptr %i.addr, align 4
# |   call void @llvm.arm.stc2l(i32 1, i32 2, ptr %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.stc2l(i32 immarg, i32 immarg, ptr) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @cdp() #0 {
# | entry:
# |   call void @llvm.arm.cdp(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.cdp(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @cdp2() #0 {
# | entry:
# |   call void @llvm.arm.cdp2(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.cdp2(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @mrc() #0 {
# | entry:
# |   %0 = call i32 @llvm.arm.mrc(i32 15, i32 0, i32 13, i32 0, i32 3)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.mrc(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @mrc2() #0 {
# | entry:
# |   %0 = call i32 @llvm.arm.mrc2(i32 15, i32 0, i32 13, i32 0, i32 3)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.mrc2(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mcr(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   call void @llvm.arm.mcr(i32 15, i32 0, i32 %0, i32 13, i32 0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.mcr(i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mcr2(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   call void @llvm.arm.mcr2(i32 15, i32 0, i32 %0, i32 13, i32 0, i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.mcr2(i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_lo
# | ...
# `---data was truncated (10240/15632) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ecfa1515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563ecfa120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563ecfa1589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff35de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff35dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff35de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff35de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ecf9aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563ecf9aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563ecf98fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563ecf63f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563ecf63edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff35de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff35de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff35de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ecf63ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c (1332 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmseq_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/171389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b260dc915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b260dc60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b260dc989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62ced33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62ced8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62ced33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62ced1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b260d5ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b260d5ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b260d43b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b2609f30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b2609f2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f62ced1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62ced1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62ced1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2609f2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c (1333 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgeu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgeu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b83ed8315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b83ed800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b83ed8389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa420449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa4204a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa420449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa420431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b83ed18e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b83ed18c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b83ecfdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b83e9ad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b83e9acdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa420432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa4204330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa4204330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b83e9accc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c (1334 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-feature
# | ...
# `---data was truncated (10240/10692) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601bb8f015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005601bb8ed0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005601bb8f089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fedb7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fedb7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fedb7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fedb7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601bb885e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005601bb885c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005601bb86ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005601bb51a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005601bb519dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fedb7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fedb7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fedb7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601bb519cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c (1335 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056191477215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056191476f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056191477289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f0821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f082725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f0821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f08203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561914707e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561914707c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005619146ecb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056191439c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056191439bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3f08204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f082050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f082050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056191439bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c (1336 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056390295615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005639029530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056390295689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7354933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f735498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7354933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f735491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639028ebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005639028ebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005639028d0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005639025800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056390257fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f735491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f735491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f735491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056390257fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c (1337 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = a
# | ...
# `---data was truncated (10240/288050) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628c869615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005628c86930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005628c869689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa74e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa74e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa74e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa74e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628c862be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005628c862bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005628c8610b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005628c82c00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005628c82bfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa74e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa74e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa74e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628c82bfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c (1338 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2
# | ...
# `---data was truncated (10240/50524) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638ed2ed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005638ed2ea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005638ed2ed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe789649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7896a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe789649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe789631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638ed282e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005638ed282c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005638ed267b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005638ecf170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005638ecf16dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe789632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7896330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7896330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638ecf16cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c (1339 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578f169115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005578f168e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005578f169189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8057733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f805778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8057733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f805771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578f1626e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005578f1626c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005578f160bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005578f12bb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005578f12badd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f805771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f805771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f805771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578f12bacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c (1340 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 32 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 64 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 64 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, a
# | ...
# `---data was truncated (10240/71115) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630eed7115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005630eed6e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005630eed7189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9876f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9876f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9876f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9876f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630eed06e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005630eed06c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005630eecebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005630ee99b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005630ee99add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9876f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9876f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9876f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630ee99acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c (1341 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f32mm -target-feature +fp8  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f32mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <4 x float> @test_vmmlaq_f32_mf8(<4 x float> noundef %p0, <16 x i8> %p1, <16 x i8> %p2, i64 noundef %p3) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <16 x i8>, align 16
# |   %__p2.addr.i = alloca <16 x i8>, align 16
# |   %__p3.addr.i = alloca i64, align 8
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <4 x float>, align 16
# |   %p0.addr = alloca <4 x float>, align 16
# |   %p1.addr = alloca <16 x i8>, align 16
# |   %p2.addr = alloca <16 x i8>, align 16
# |   %p3.addr = alloca i64, align 8
# |   store <4 x float> %p0, ptr %p0.addr, align 16
# |   store <16 x i8> %p1, ptr %p1.addr, align 16
# |   store <16 x i8> %p2, ptr %p2.addr, align 16
# |   store i64 %p3, ptr %p3.addr, align 8
# |   %0 = load <4 x float>, ptr %p0.addr, align 16
# |   %1 = load <16 x i8>, ptr %p1.addr, align 16
# |   %2 = load <16 x i8>, ptr %p2.addr, align 16
# |   %3 = load i64, ptr %p3.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 16
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 16
# |   store i64 %3, ptr %__p3.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %7 = load i64, ptr %__p3.addr.i, align 8
# |   call void @llvm.aarch64.set.fpmr(i64 %7)
# |   %fmmla.i = call <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v16i8(<4 x float> %4, <16 x i8> %5, <16 x i8> %6)
# |   store <4 x float> %fmmla.i, ptr %ref.tmp.i, align 16
# |   %8 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %8, ptr %__ret.i, align 16
# |   %9 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
# | declare void @llvm.aarch64.set.fpmr(i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f8f32mm,+faminmax,+flagm,+fp-armv8,+fp8,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9a,+wfxt" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000563691b3015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563691b2d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563691b3089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4508933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f450898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4508933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f450891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563691ac5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563691ac5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563691aaab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056369175a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563691759dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f450891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f450891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f450891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563691759cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c (1342 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset2_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %4 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %3, 0
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset2_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %1, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %2 = load { <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %4 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %3, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1> } %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005644e8cee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005644e8ceb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005644e8cee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fafbac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fafbaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fafbac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fafbac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644e8c83e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005644e8c83c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005644e8c68b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005644e89180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005644e8917dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fafbac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fafbac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fafbac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644e8917cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c (1343 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.mask.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <v
# | ...
# `---data was truncated (10240/12083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1d791d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b1d791a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b1d791d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe278933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe27898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe278933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe27891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1d78b2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b1d78b2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b1d7897b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b1d75470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b1d7546dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe27891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe27891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe27891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1d7546cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c (1344 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, a
# | ...
# `---data was truncated (10240/207757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646a786c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005646a78690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005646a786c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2c661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2c66725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2c661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2c6603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646a7801e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005646a7801c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005646a77e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005646a74960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005646a7495dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc2c6604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2c66050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2c66050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646a7495cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c (1345 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8(<vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4(<vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2(<vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vrsub_vx_i16m1(<vscale x 4 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vrsub_vx_i16m2(<vscale x 8 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i16, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vrsub
# | ...
# `---data was truncated (10240/84979) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf86a3215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bf86a2f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bf86a3289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c75333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c7538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c75333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c7531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf869c7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bf869c7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bf869acb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bf8665c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bf8665bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6c7531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c7531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c7531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf8665bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c (1346 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfwcvt_rtz_x_f_v_i64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfwcvt_rtz_x_f_v_i64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm
# | ...
# `---data was truncated (10240/35597) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f4a3aa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556f4a3a70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556f4a3aa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff98c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff98c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff98c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff98c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f4a33fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556f4a33fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556f4a324b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556f49fd40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556f49fd3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff98c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff98c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff98c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f49fd3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c (1347 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056037114115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056037113e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056037114189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46e4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46e458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46e4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46e451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603710d6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005603710d6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005603710bbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560370d6b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560370d6add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f46e451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46e451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46e451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560370d6acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c (1348 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.ad
# | ...
# `---data was truncated (10240/225647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb797dc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eb797d90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eb797dc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fd7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fd7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fd7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fd7e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb79771e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eb79771c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eb79756b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eb794060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eb79405dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3fd7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fd7e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fd7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb79405cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c (1349 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i6
# | ...
# `---data was truncated (10240/90867) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055979c36515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055979c3620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055979c36589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f288da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f288daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f288da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f288da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055979c2fae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055979c2fac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055979c2dfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055979bf8f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055979bf8edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f288da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f288da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f288da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055979bf8ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c (1350 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature -fullfp16 -target-feature +v8a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature -fullfp16 -target-feature +v8a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vbsl_f16(<4 x i16> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbsl.i = bitcast <8 x i8> %3 to <4 x i16>
# |   %vbsl1.i = bitcast <8 x i8> %4 to <4 x i16>
# |   %vbsl2.i = bitcast <8 x i8> %5 to <4 x i16>
# |   %vbsl3.i = and <4 x i16> %vbsl.i, %vbsl1.i
# |   %6 = xor <4 x i16> %vbsl.i, splat (i16 -1)
# |   %vbsl4.i = and <4 x i16> %6, %vbsl2.i
# |   %vbsl5.i = or <4 x i16> %vbsl3.i, %vbsl4.i
# |   %7 = bitcast <4 x i16> %vbsl5.i to <4 x half>
# |   store <4 x half> %7, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %8, ptr %__ret.i, align 8
# |   %9 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vbslq_f16(<8 x i16> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbsl.i = bitcast <16 x i8> %3 to <8 x i16>
# |   %vbsl1.i = bitcast <16 x i8> %4 to <8 x i16>
# |   %vbsl2.i = bitcast <16 x i8> %5 to <8 x i16>
# |   %vbsl3.i = and <8 x i16> %vbsl.i, %vbsl1.i
# |   %6 = xor <8 x i16> %vbsl.i, splat (i16 -1)
# |   %vbsl4.i = and <8 x i16> %6, %vbsl2.i
# |   %vbsl5.i = or <8 x i16> %vbsl3.i, %vbsl4.i
# |   %7 = bitcast <8 x i16> %vbsl5.i to <8 x half>
# |   store <8 x half> %7, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vzip_f16(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x4x2_t, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %retval = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <8 x i8> %2 to <4 x half>
# |   %5 = bitcast <8 x i8> %3 to <4 x half>
# |   %vzip.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x half> %vzip.i, ptr %retval.i, align 8
# |   %6 = getelementptr inbounds <4 x half>, ptr %retval.i, i32 1
# |   %vzip1.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
# |   store <4 x half> %vzip1.i, ptr %6, align 8
# |   %7 = load %struct.float16x4x2_t, ptr %retval.i, align 8
# |   %8 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x4x2_t %7, 0
# |   store [2 x <4 x half>] %9, ptr %8, align 8
# |   %10 = load %struct.float16x4x2_t, ptr %retval, align 8
# |   ret %struct.float16x4x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x8x2_t @test_vzipq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x8x2_t, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %retval = alloca %struct.float16x8x2_t, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x half>
# |   %5 = bitcast <16 x i8> %3 to <8 x half>
# |   %vzip.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x half> %vzip.i, ptr %retval.i, align 16
# |   %6 = getelementptr inbounds <8 x half>, ptr %retval.i, i32 1
# |   %vzip1.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   store <8 x half> %vzip1.i, ptr %6, align 16
# |   %7 = load %struct.float16x8x2_t, ptr %retval.i, align 16
# |   %8 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x8x2_t %7, 0
# |   store [2 x <8 x half>] %9, ptr %8, align 16
# |   %10 = load %struct.float16x8x2_t, ptr %retval, align 16
# |   ret %struct.float16x8x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vuzp_f16(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x4x2_t, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %retval = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = bitcast <8 x i8> %2 to <4 x half>
# |   %5 = bitcast <8 x i8> %3 to <4 x half>
# |   %vuzp.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
# |   store <4 x half> %vuzp.i, ptr %retval.i, align 8
# |   %6 = getelementptr inbounds <4 x half>, ptr %retval.i, i32 1
# |   %vuzp1.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
# |   store <4 x half> %vuzp1.i, ptr %6, align 8
# |   %7 = load %struct.float16x4x2_t, ptr %retval.i, align 8
# |   %8 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x4x2_t %7, 0
# |   store [2 x <4 x half>] %9, ptr %8, align 8
# |   %10 = load %struct.float16x4x2_t, ptr %retval, align 8
# |   ret %struct.float16x4x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x8x2_t @test_vuzpq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %retval.i = alloca %struct.float16x8x2_t, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %retval = alloca %struct.float16x8x2_t, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %4 = bitcast <16 x i8> %2 to <8 x half>
# |   %5 = bitcast <16 x i8> %3 to <8 x half>
# |   %vuzp.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
# |   store <8 x half> %vuzp.i, ptr %retval.i, align 16
# |   %6 = getelementptr inbounds <8 x half>, ptr %retval.i, i32 1
# |   %vuzp1.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
# |   store <8 x half> %vuzp1.i, ptr %6, align 16
# |   %7 = load %struct.float16x8x2_t, ptr %retval.i, align 16
# |   %8 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %retval, i32 0, i32 0
# |   %9 = extractvalue %struct.float16x8x2_t %7, 0
# |   store [2 x <8 x half>] %9, ptr %8, align 16
# |   %10 = load %struct.float16x8x2_t, ptr %retval, align 16
# |   ret %struct.float16x8x2_t %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local %struct.float16x4x2_t @test_vtrn_f16(<4 x half> noundef %a, <4 x half> noundef 
# | ...
# `---data was truncated (10240/31986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055dc817fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dc817f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dc817fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a19733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a1978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a19733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a1971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc81791e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dc81791c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dc81776b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dc814260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dc81425dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7a1971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a1971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a1971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc81425cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c (1351 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b3dde115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562b3ddde0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562b3dde189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe377249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3772a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe377249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe377231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b3dd76e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562b3dd76c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562b3dd5bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562b3da0b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562b3da0add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe377232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3772330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3772330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b3da0acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c (1352 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrol_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrol.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrol_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrol.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrol_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrol.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrol_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrol.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrol_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/222315) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005651238d615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005651238d30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005651238d689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75f1705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75f175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75f1705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75f16ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056512386be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056512386bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565123850b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005651235000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005651234ffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f75f16eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75f16ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75f16ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005651234ffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c (1353 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618401fa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005618401f70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005618401fa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f882eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f882eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f882eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f882eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056184018fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056184018fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561840174b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056183fe240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056183fe23dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f882eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f882eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f882eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056183fe23cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c (1354 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a63fea15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556a63fe70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556a63fea89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f098e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f098e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f098e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f098e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a63f7fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556a63f7fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556a63f64b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556a63c140b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556a63c13dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f098e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f098e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f098e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a63c13cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c (1355 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/25086) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005572b0e5c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005572b0e590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005572b0e5c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e25649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e256a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e25649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e25631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572b0df1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005572b0df1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005572b0dd6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005572b0a860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005572b0a85dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4e25632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e256330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e256330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005572b0a85cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c (1356 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmadd_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmadd_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmadd_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmadd_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmadd_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |  
# | ...
# `---data was truncated (10240/207749) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d7a5e615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559d7a5e30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559d7a5e689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b94a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b94a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b94a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b94a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d7a57be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559d7a57bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559d7a560b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559d7a2100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559d7a20fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0b94a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b94a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b94a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d7a20fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c (1357 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d2462c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555d246290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555d2462c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f824c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f824c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f824c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f824c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d245c1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555d245c1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555d245a6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555d242560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555d24255dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f824c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f824c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f824c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d24255cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c (1358 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>
# | ...
# `---data was truncated (10240/51185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611621c615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005611621c30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005611621c689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2bdb649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2bdb6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2bdb649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2bdb631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056116215be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056116215bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561162140b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561161df00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561161defdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2bdb632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2bdb6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2bdb6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561161defcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c (1359 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b4af9b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563b4af980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563b4af9b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd162333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd16238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd162333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd16231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b4af30e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563b4af30c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563b4af15b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563b4abc50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563b4abc4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd16231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd16231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd16231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b4abc4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c (1360 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8524e015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b8524dd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b8524e089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc028a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc028aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc028a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc028a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b852475e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b852475c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b85245ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b85210a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b852109dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc028a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc028a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc028a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b852109cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c (1361 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i64>, i64 } @llvm.risc
# | ...
# `---data was truncated (10240/62752) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562771afc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562771af90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562771afc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f902ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f902ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f902ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f902ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562771a91e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562771a91c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562771a76b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005627717260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562771725dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f902ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f902ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f902ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562771725cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/load-store.c (1362 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/load-store.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vld1q_f16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x half>, ptr %0, align 2
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vld1q_f32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x float>, ptr %0, align 4
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_s8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_s16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_s32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 4
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_u8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_u16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %0, align 2
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_u32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %0, align 4
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vld1q_z_f16(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x half> @llvm.masked.load.v8f16.p0(ptr align 2 %0, <8 x i1> %3, <8 x half> zeroinitializer)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <8 x half> @llvm.masked.load.v8f16.p0(ptr captures(none), <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vld1q_z_f32(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr align 4 %0, <4 x i1> %3, <4 x float> zeroinitializer)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <4 x float> @llvm.masked.load.v4f32.p0(ptr captures(none), <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_s8(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 %0, <16 x i1> %3, <16 x i8> zeroinitializer)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr captures(none), <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_s16(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 2 %0, <8 x i1> %3, <8 x i16> zeroinitializer)
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr captures(none), <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_s32(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 %0, <4 x i1> %3, <4 x i32> zeroinitializer)
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr captures(none), <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_u8(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 %0, <16 x i1> %3, <16 x i8> zeroinitializer)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_u16(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 2 %0, <8 x i1> %3, <8 x i16> zeroinitializer)
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_u32(ptr noundef %base, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 %0, <4 x i1> %3, <4 x i32> zeroinitializer)
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_s8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_s16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i8>, ptr %0, align 1
# |   %2 = sext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_s32(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i8>, ptr %0, align 1
# |   %2 = sext <4 x i8> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_u8(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   store ptr %base, ptr %base.addr, align 4
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %0, align 1
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_u16(ptr noundef %base) #0 {
# | entry:
# |   %base.addr = a
# | ...
# `---data was truncated (10240/50873) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af81dd815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055af81dd50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055af81dd889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c86449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c864a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c86449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c86431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af81d6de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055af81d6dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055af81d52b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055af81a020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055af81a01dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7c86432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c864330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c864330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af81a01cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-neon-vcvtX.c (1363 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-vcvtX.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvta_s32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvta_s32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvta_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %vcvta_s32_v.i)
# |   store <2 x i32> %vcvta_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvta_u32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvta_u32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvta_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %vcvta_u32_v.i)
# |   store <2 x i32> %vcvta_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtaq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtaq_s32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtaq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %vcvtaq_s32_v.i)
# |   store <4 x i32> %vcvtaq_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtaq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtaq_u32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtaq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %vcvtaq_u32_v.i)
# |   store <4 x i32> %vcvtaq_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtn_s32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtn_s32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtn_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %vcvtn_s32_v.i)
# |   store <2 x i32> %vcvtn_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtn_u32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtn_u32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtn_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float> %vcvtn_u32_v.i)
# |   store <2 x i32> %vcvtn_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtnq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtnq_s32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtnq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %vcvtnq_s32_v.i)
# |   store <4 x i32> %vcvtnq_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtnq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtnq_u32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtnq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %vcvtnq_u32_v.i)
# |   store <4 x i32> %vcvtnq_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtp_s32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtp_s32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtp_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %vcvtp_s32_v.i)
# |   store <2 x i32> %vcvtp_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vcvtp_u32_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtp_u32_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vcvtp_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float> %vcvtp_u32_v.i)
# |   store <2 x i32> %vcvtp_u32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtpq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtpq_s32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtpq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %vcvtpq_s32_v.i)
# |   store <4 x i32> %vcvtpq_s32_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vcvtpq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vcvtpq_u32_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vcvtpq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %vcvtpq_u32_v.i)
# |   st
# | ...
# `---data was truncated (10240/16770) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000557e907ff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557e907fc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557e907ff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3beac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3beaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3beac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3beac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e90794e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557e90794c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557e90779b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557e904290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557e90428dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3beac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3beac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3beac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e90428cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c (1364 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c162ecd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c162eca0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c162ecd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42dae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42daea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42dae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42dae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c162e62e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c162e62c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c162e47b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c162af70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c162af6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f42dae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42dae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42dae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c162af6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c (1365 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.a
# | ...
# `---data was truncated (10240/86092) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a286a5a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a286a570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a286a5a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8eeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8eeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8eeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8eeb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2869efe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a2869efc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a2869d4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a2866840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a286683dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa8eeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8eeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8eeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a286683cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c (1366 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559dcc27015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559dcc26d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559dcc27089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f19333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f1938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f19333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f1931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559dcc205e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559dcc205c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559dcc1eab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559dcbe9a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559dcbe99dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6f1931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f1931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f1931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559dcbe99cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c (1367 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vv_i8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmacc_vx_i8mf8(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vv_i8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmacc_vx_i8mf4(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vv_i8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmacc_vx_i8mf2(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vv_i8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmacc_vx_i8m1(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmacc_vv_i8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, a
# | ...
# `---data was truncated (10240/207757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055badf8e315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055badf8e00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055badf8e389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f785a305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f785a35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f785a305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f785a2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055badf878e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055badf878c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055badf85db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055badf50d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055badf50cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f785a2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f785a2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f785a2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055badf50ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c (1368 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_ran
# | ...
# `---data was truncated (10240/10777) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b98284c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b9828490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b98284c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f271d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f271d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f271d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f271d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9827e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b9827e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b9827c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b9824760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b982475dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f271d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f271d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f271d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b982475cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c (1369 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0,
# | ...
# `---data was truncated (10240/29451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ccbf9bc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ccbf9b90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ccbf9bc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe68505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe6855c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe68505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe684ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ccbf951e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ccbf951c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ccbf936b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ccbf5e60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ccbf5e5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbe684eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe684ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe684ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ccbf5e5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c (1370 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | ...
# `---data was truncated (10240/120907) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b86ff4c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b86ff490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b86ff4c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9ea733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9ea78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9ea733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9ea71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b86fee1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b86fee1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b86fec6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b86fb760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b86fb75dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd9ea71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9ea71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9ea71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b86fb75cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c (1371 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c  -check-prefix=RV64ZKND
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64dsm(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64dsm(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64ds(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64ds(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64im(i64 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   %1 = load i64, ptr %__x.addr.i, align 8
# |   %2 = call i64 @llvm.riscv.aes64im(i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64dsm(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64ds(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64im(i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknd" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zknd1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056106c5e115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056106c5de0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056106c5e189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e32049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e320a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e32049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e32031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056106c576e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056106c576c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056106c55bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056106c20b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056106c20add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8e32032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e320330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e320330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056106c20acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c (1372 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600754e715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005600754e40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005600754e789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f601cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f601cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f601cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f601cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056007547ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056007547cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560075461b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005600751110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560075110dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f601cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f601cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f601cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560075110cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c (1373 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vs
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db76cf215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055db76cef0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055db76cf289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa986b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa986b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa986b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa986b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db76c87e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055db76c87c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055db76c6cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055db7691c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055db7691bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa986b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa986b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa986b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db7691bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c (1374 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3,
# | ...
# `---data was truncated (10240/15512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c859dc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558c859d90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558c859dc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2968049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29680a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2968049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2968031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c85971e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558c85971c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558c85956b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558c856060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558c85605dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2968032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29680330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29680330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c85605cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve/andv.c (1375 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/andv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svandv_s8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svandv_s16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svandv_s32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svandv_s64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i8 @test_svandv_u8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret i8 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i16 @test_svandv_u16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret i16 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i32 @test_svandv_u32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local i64 @test_svandv_u64(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret i64 %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S
# |  #0 0x00005613f26bf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005613f26bc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005613f26bf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75d6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75d64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75d6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75d6431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613f2654e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005613f2654c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005613f2639b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005613f22e90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005613f22e8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f75d6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75d64330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75d64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613f22e8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c (1376 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 3, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 immarg, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 3, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 immarg, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 3, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 immarg, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 3, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 immarg, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 3, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 immarg, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m4(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 3, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 immarg, <vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u8m8(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 64 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 64 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 3, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 3, <vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i32 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 immarg, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_vvv_se_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, i32 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i32, align 4
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i32 %vl, ptr %vl.addr, align 4
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i32, ptr %vl.addr, align 4
# |   call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i16.nxv2i16.nxv
# | ...
# `---data was truncated (10240/255166) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b5092d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564b5092a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564b5092d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73d4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73d42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73d4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73d4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b508c2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564b508c2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564b508a7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564b505570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564b50556dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f73d4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73d42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73d42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b50556cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c (1377 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsli
# | ...
# `---data was truncated (10240/14908) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056296864415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005629686410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056296864489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb378b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb378b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb378b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb378b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629685d9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005629685d9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005629685beb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056296826e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056296826ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb378b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb378b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb378b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056296826dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c (1378 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571a4a8515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005571a4a820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005571a4a8589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e2861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e286725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e2861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e28603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571a4a1ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005571a4a1ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005571a49ffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005571a46af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005571a46aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7e28604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e286050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e286050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571a46aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c (1379 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.
# | ...
# `---data was truncated (10240/101394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b19174e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b19174b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b19174e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9adae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9adaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9adae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9adae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1916e3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b1916e3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b1916c8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b1913780b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b191377dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9adae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9adae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9adae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b191377cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c (1380 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 32 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 64 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 64 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i8>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 1
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloc
# | ...
# `---data was truncated (10240/71123) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf8a5a015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cf8a59d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cf8a5a089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b68849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b688a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b68849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b68831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf8a535e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cf8a535c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cf8a51ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cf8a1ca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cf8a1c9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8b68832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b688330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b688330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf8a1c9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c (1381 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 0, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 0, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 1, <8 x half> %0)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 1, <4 x float> %0)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_s16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> %0, <8 x half> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32, <8 x i16>, <8 x half>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_m_s32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> %0, <4 x float> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32, <4 x i32>, <4 x float>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_u16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load <8 x half>, ptr %a.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(
# | ...
# `---data was truncated (10240/32505) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3cf31515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b3cf3120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b3cf31589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f522e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f522e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f522e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f522e031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3cf2aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b3cf2aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b3cf28fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b3cef3f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b3cef3edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f522e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f522e0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f522e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3cef3ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c (1382 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqr
# | ...
# `---data was truncated (10240/28170) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559aaa3315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005559aaa300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005559aaa3389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe31281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3128725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe31281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe312803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559aa9c8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005559aa9c8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005559aa9adb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005559aa65d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005559aa65cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe312804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3128050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3128050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559aa65ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c (1383 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_u16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_u16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621060af15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005621060ac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005621060af89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ba1b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ba1b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ba1b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ba1aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562106044e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562106044c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562106029b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562105cd90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562105cd8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1ba1aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ba1aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ba1aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562105cd8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c (1384 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.
# | ...
# `---data was truncated (10240/51804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608ca53115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005608ca52e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005608ca53189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48e7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48e72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48e7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48e7231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005608ca4c6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005608ca4c6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005608ca4abb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005608ca15b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005608ca15add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f48e7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48e72330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48e72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608ca15acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c (1385 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_p8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_p16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16
# |   store <8 x bfloat> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load 
# | ...
# `---data was truncated (10240/31171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056122792815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005612279250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056122792889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce78733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce7878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce78733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce7871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612278bde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005612278bdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005612278a2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005612275520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561227551dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fce7871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce7871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce7871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561227551cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c (1386 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsne_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsne_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/171381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aea02be15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aea02bb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aea02be89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9f6705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9f675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9f6705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9f66ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aea0253e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aea0253c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aea0238b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ae9fee80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ae9fee7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff9f66eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9f66ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9f66ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae9fee7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c (1387 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610361b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005610361b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005610361b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f931ec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f931ec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f931ec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f931ec03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056103614be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056103614bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561036130b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561035de00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561035ddfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f931ec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f931ec050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f931ec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561035ddfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c (1388 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %
# | ...
# `---data was truncated (10240/20631) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e627b2715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e627b240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e627b2789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56f1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56f1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56f1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56f1c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e627abce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e627abcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e627aa1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e6277510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e627750dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f56f1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56f1c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56f1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e627750cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c (1389 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vminu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vminu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d612e615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555d612e30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555d612e689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f983b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f983b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f983b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f983b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d6127be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555d6127bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555d61260b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555d60f100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555d60f0fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f983b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f983b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f983b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d60f0fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c (1390 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Functio
# | ...
# `---data was truncated (10240/13657) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d2451c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561d245190f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561d2451c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4345649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43456a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4345649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4345631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d244b1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561d244b1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561d24496b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561d241460b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561d24145dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4345632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43456330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43456330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d24145cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c (1391 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f3
# | ...
# `---data was truncated (10240/179503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611a6a2915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005611a6a260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005611a6a2989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0d2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0d20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0d2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0d2031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611a69bee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005611a69bec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005611a69a3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005611a66530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005611a6652dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb0d2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0d20330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0d20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611a6652cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c (1392 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, al
# | ...
# `---data was truncated (10240/226593) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594cd30615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005594cd3030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005594cd30689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1faee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1faeea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1faee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1faee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594cd29be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005594cd29bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005594cd280b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005594ccf300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005594ccf2fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1faee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1faee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1faee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594ccf2fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c (1393 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d0d8e715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558d0d8e40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558d0d8e789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f655c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f655c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f655c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f655c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d0d87ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558d0d87cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558d0d861b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558d0d5110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558d0d510dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f655c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f655c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f655c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d0d510cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c (1394 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_u8mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_u8m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606828d615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005606828d30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005606828d689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc8d0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8d058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc8d0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc8d051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056068286be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056068286bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560682850b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005606825000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005606824ffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc8d051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8d051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8d051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606824ffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c (1395 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local targ
# | ...
# `---data was truncated (10240/70855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056435d6ea15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056435d6e70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056435d6ea89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa39b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa39b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa39b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa39b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056435d67fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056435d67fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056435d664b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056435d3140b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056435d313dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ffa39b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa39b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa39b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056435d313cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c (1396 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vscale x 8 
# | ...
# `---data was truncated (10240/255538) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef81d5915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ef81d560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ef81d5989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e7fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e7fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e7fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e7fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef81ceee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ef81ceec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ef81cd3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ef819830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ef81982dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3e7fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e7fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e7fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef81982cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c (1397 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5d35e315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a5d35e00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a5d35e389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77bfc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77bfca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77bfc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77bfc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5d3578e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a5d3578c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a5d355db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a5d320d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a5d320cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f77bfc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77bfc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77bfc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5d320ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c (1398 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsle_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsle_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a69d8fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a69d8fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a69d8fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa45d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa45d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa45d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa45d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a69d892e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a69d892c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a69d877b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a69d5270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a69d526dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa45d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa45d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa45d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a69d526cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c (1399 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2
# | ...
# `---data was truncated (10240/32570) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b51f6ef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b51f6ec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b51f6ef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d4661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d466725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d4661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d46603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b51f684e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b51f684c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b51f669b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b51f3190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b51f318dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1d46604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d466050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d466050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b51f318cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c (1400 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056230b1d915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056230b1d60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056230b1d989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff642b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff642b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff642b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff642b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056230b16ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056230b16ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056230b153b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056230ae030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056230ae02dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff642b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff642b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff642b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056230ae02cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c (1401 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e111f615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559e111f30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559e111f689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff78f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff78f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff78f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff78f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e1118be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559e1118bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559e11170b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559e10e200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559e10e1fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff78f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff78f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff78f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e10e1fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c (1402 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f1ece4815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f1ece450f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f1ece4889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c4cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c4cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c4cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c4cc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1ecddde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f1ecdddc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f1ecdc2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f1eca720b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f1eca71dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5c4cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c4cc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c4cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f1eca71cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c (1403 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrsqrt7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrsqrt7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfrsqrt7_v_f64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double
# | ...
# `---data was truncated (10240/29119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e33511815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e3351150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e33511889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4d0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4d08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4d0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4d0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3350ade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e3350adc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e335092b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e334d420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e334d41dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff4d0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4d08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4d08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e334d41cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c (1404 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.ris
# | ...
# `---data was truncated (10240/18562) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bceecf215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bceecef0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bceecf289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58ed533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58ed58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58ed533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58ed51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bceec87e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bceec87c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bceec6cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bcee91c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bcee91bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f58ed51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58ed51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58ed51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bcee91bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c (1405 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, al
# | ...
# `---data was truncated (10240/225213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db1a1a815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055db1a1a50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055db1a1a889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4f2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4f298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4f2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4f291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db1a13de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055db1a13dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055db1a122b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055db19dd20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055db19dd1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd4f291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4f291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4f291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db19dd1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c (1406 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | ...
# `---data was truncated (10240/12457) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558748b7615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558748b730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558748b7689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbfcbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbfcbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbfcbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbfcbb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558748b0be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558748b0bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558748af0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005587487a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055874879fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbfcbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbfcbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbfcbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055874879fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c (1407 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscal
# | ...
# `---data was truncated (10240/44426) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633a563815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005633a56350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005633a563889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e43e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e43ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e43e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e43e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633a55cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005633a55cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005633a55b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005633a52620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005633a5261dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2e43e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e43e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e43e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633a5261cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c (1408 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dcadbb915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dcadbb60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dcadbb989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0290249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02902a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0290249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0290231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dcadb4ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dcadb4ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dcadb33b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dcad7e30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dcad7e2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0290232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02902330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02902330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dcad7e2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/dup.c (1409 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/dup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vdupq_n_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %0, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   ret <8 x half> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vdupq_n_f32(float noundef %a) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %0, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   ret <4 x float> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_s8(i8 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %0, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   ret <16 x i8> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_s16(i16 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %0, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   ret <8 x i16> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %0, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   ret <4 x i32> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_u8(i8 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %0, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   ret <16 x i8> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_u16(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %0, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   ret <8 x i16> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %0, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   ret <4 x i32> %.splat
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vdupq_m_n_f16(<8 x half> noundef %inactive, half noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca half, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store half %a, ptr %a.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load half, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %3, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x half> %.splat, <8 x half> %4
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vdupq_m_n_f32(<4 x float> noundef %inactive, float noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca float, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store float %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load float, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %3, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x float> %.splat, <4 x float> %4
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_s8(<16 x i8> noundef %inactive, i8 noundef signext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
# |   %3 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %3, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = select <16 x i1> %2, <16 x i8> %.splat, <16 x i8> %4
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_s16(<8 x i16> noundef %inactive, i16 noundef signext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %3, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = select <8 x i1> %2, <8 x i16> %.splat, <8 x i16> %4
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_m_n_s32(<4 x i32> noundef %inactive, i32 noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load i32, ptr %a.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %3, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = select <4 x i1> %2, <4 x i32> %.splat, <4 x i32> %4
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_u8(<16 x i8> noundef %inactive, i8 noundef zeroext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
# |   %3 = load i8, ptr %a.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %3, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %4 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %5 = select <16 x i1> %2, <16 x i8> %.splat, <16 x i8> %4
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_u16(<8 x i16> noundef %inactive, i16 noundef zeroext %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load i16, ptr %a.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %3, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = select <8 x i1> %2,
# | ...
# `---data was truncated (10240/17297) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x00005589c0f1915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005589c0f160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005589c0f1989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d00305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d0035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d00305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d002ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589c0eaee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005589c0eaec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005589c0e93b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005589c0b430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005589c0b42dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9d002eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d002ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d002ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589c0b42cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c (1410 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 
# | ...
# `---data was truncated (10240/199596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055562c74f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055562c74c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055562c74f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd691333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd69138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd691333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd69131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055562c6e4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055562c6e4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055562c6c9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055562c3790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055562c378dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd69131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd69131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd69131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055562c378cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c (1411 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tu(<vscale x 1
# | ...
# `---data was truncated (10240/295853) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581f920c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005581f92090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005581f920c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe842449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8424a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe842449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe842431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581f91a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005581f91a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005581f9186b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005581f8e360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005581f8e35dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe842432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8424330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8424330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581f8e35cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c (1412 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vs
# | ...
# `---data was truncated (10240/14201) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603c62e115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005603c62de0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005603c62e189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9ec905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9ec95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9ec905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9ec8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603c6276e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005603c6276c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005603c625bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005603c5f0b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005603c5f0add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff9ec8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9ec8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9ec8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603c5f0acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c (1413 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) 
# | ...
# `---data was truncated (10240/68437) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055637453e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055637453b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055637453e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa590d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa590d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa590d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa590d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563744d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005563744d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005563744b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005563741680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556374167dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa590d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa590d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa590d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556374167cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c (1414 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwin
# | ...
# `---data was truncated (10240/95437) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558617ac815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558617ac50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558617ac889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc4ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc4ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc4ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc4ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558617a5de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558617a5dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558617a42b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005586176f20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005586176f1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbc4ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc4ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc4ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586176f1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c (1415 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590b763915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005590b76360f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005590b763989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc61ae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc61ae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc61ae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc61ae03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590b75cee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005590b75cec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005590b75b3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005590b72630b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005590b7262dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc61ae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc61ae050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc61ae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590b7262cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c (1416 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   stor
# | ...
# `---data was truncated (10240/29518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588344f315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005588344f00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005588344f389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd277733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd27778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd277733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd27771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558834488e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558834488c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055883446db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055883411d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055883411cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd27771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd27771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd27771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055883411ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c (1417 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon   -target-feature +rcpc3 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +rcpc3 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vldap1q_lane_u64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1
# |   store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %5, ptr %__ret, align 16
# |   %6 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %6, ptr %tmp, align 16
# |   %7 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vldap1q_lane_s64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1
# |   store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %5, ptr %__ret, align 16
# |   %6 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %6, ptr %tmp, align 16
# |   %7 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vldap1q_lane_f64(ptr noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x double>, align 16
# |   %__ret = alloca <2 x double>, align 16
# |   %__s1 = alloca <2 x double>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   %0 = load <2 x double>, ptr %b.addr, align 16
# |   store <2 x double> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x double>
# |   %4 = load atomic double, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x double> %3, double %4, i32 1
# |   store <2 x double> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %5, ptr %__ret, align 16
# |   %6 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %6, ptr %tmp, align 16
# |   %7 = load <2 x double>, ptr %tmp, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vldap1q_lane_p64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__ret = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1
# |   store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16
# |   %5 = load <2 x i64>, ptr %ref.tmp, align 16
# |   store <2 x i64> %5, ptr %__ret, align 16
# |   %6 = load <2 x i64>, ptr %__ret, align 16
# |   store <2 x i64> %6, ptr %tmp, align 16
# |   %7 = load <2 x i64>, ptr %tmp, align 16
# |   ret <2 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vldap1_lane_u64(ptr noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0
# |   store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %5, ptr %__ret, align 8
# |   %6 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %6, ptr %tmp, align 8
# |   %7 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vldap1_lane_s64(ptr noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0
# |   store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %5, ptr %__ret, align 8
# |   %6 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %6, ptr %tmp, align 8
# |   %7 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vldap1_lane_f64(ptr noundef %a, <1 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   %0 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x double>
# |   %4 = load atomic double, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x double> %3, double %4, i32 0
# |   store <1 x double> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %5, ptr %__ret, align 8
# |   %6 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %6, ptr %tmp, align 8
# |   %7 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vldap1_lane_p64(ptr noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   %__ret = alloca <1 x i64>, align 8
# |   %__s1 = alloca <1 x i64>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x i64>, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__s1, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <8 x i8>, ptr %__s1, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x i64>
# |   %4 = load atomic i64, ptr %1 acquire, align 8
# |   %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0
# |   store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8
# |   %5 = load <1 x i64>, ptr %ref.tmp, align 8
# |   store <1 x i64> %5, ptr %__ret, align 8
# |   %6 = load <1 x i64>, ptr %__ret, align 8
# |   store <1 x i64> %6, ptr %tmp, align 8
# |   %7 = load <1 x i64>, ptr %tmp, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vstl1q_lane_u64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = extractelement <2 x i64> %3, i32 1
# |   store atomic i64 %4, ptr %1 release, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vstl1q_lane_s64(ptr noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca <2 x i64>, align 16
# |   %__s1 = alloca <2 x i64>, align 16
# |   store ptr %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 16
# |   %0 = load <2 x i64>, ptr %b.addr, align 16
# |   store <2 x i64> %0, ptr %__s1, align 16
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %__s1, align 16
# |   %3 = bitcast <16 x i8> %2 to <2 x i64>
# |   %4 = extractelement <2 x i64> %3, i32 1
# |   store atomic i64 %4, ptr %1 release, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vstl1q_lane_f64(ptr noundef %a, <2 x double> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca 
# | ...
# `---data was truncated (10240/14230) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000560f6cbcd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560f6cbca0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560f6cbcd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25e9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25e998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25e9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25e991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f6cb62e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560f6cb62c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560f6cb47b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560f6c7f70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560f6c7f6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f25e991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25e991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25e991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f6c7f6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c (1418 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define ds
# | ...
# `---data was truncated (10240/95215) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555685f3615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555685f330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555685f3689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e74e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e74ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e74e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e74e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555685ecbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555685ecbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555685eb0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555685b600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555685b5fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7e74e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e74e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e74e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555685b5fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c (1419 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8
# | ...
# `---data was truncated (10240/113011) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f3f32415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560f3f3210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560f3f32489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8357a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8357aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8357a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8357a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f3f2b9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560f3f2b9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560f3f29eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560f3ef4e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560f3ef4ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8357a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8357a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8357a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f3ef4dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c (1420 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581b59fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005581b59fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005581b59fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f60d2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60d20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f60d2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60d2031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581b5992e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005581b5992c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005581b5977b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005581b56270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005581b5626dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f60d2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60d20330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60d20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581b5626cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c (1421 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555fefc115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005555fefbe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005555fefc189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f48e261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48e26725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f48e261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f48e2603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555fef56e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005555fef56c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005555fef3bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005555febeb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005555febeadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f48e2604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48e26050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48e26050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555febeacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c (1422 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfdot(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_lane_0_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 0)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.aarch64.sve.bfdot.lane.v2(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_lane_3_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, <vscale x 8 x bfloat> %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca <vscale x 8 x bfloat>, align 16
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store <vscale x 8 x bfloat> %z, ptr %z.addr, align 16
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load <vscale x 8 x bfloat>, ptr %z.addr, align 16
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot.lane.v2(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i32 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x float> @test_bfdot_n_f32(<vscale x 4 x float> %x, <vscale x 8 x bfloat> %y, bfloat noundef %z) #0 {
# | entry:
# |   %x.addr = alloca <vscale x 4 x float>, align 16
# |   %y.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %z.addr = alloca bfloat, align 2
# |   store <vscale x 4 x float> %x, ptr %x.addr, align 16
# |   store <vscale x 8 x bfloat> %y, ptr %y.addr, align 16
# |   store bfloat %z, ptr %z.addr, align 2
# |   %0 = load <vscale x 4 x float>, ptr %x.addr, align 16
# |   %1 = load <vscale x 8 x bfloat>, ptr %y.addr, align 16
# |   %2 = load bfloat, ptr %z.addr, align 2
# |   %.splatinsert = insertelement <vscale x 8 x bfloat> poison, bfloat %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x bfloat> %.splatinsert, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
# |   %3 = call <vscale x 4 x float> @llvm.aarch64.sve.bfdot(<vscale x 4 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %.splat)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000562265efe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562265efb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562265efe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbad5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbad5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbad5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbad5d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562265e93e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562265e93c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562265e78b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562265b280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562265b27dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbad5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbad5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbad5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562265b27cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c (1423 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560cb362b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560cb36280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560cb362b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69dcb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69dcb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69dcb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69dcb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560cb35c0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560cb35c0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560cb35a5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560cb32550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560cb3254dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f69dcb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69dcb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69dcb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560cb3254cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c (1424 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b8908215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564b8907f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564b8908289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b54e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b54ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b54e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b54e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b89017e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564b89017c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564b88ffcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564b88cac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564b88cabdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2b54e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b54e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b54e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b88cabcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c (1425 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc  -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +lut -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +lut -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vcreate_mf8(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__promote = alloca i64, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__promote, align 8
# |   %1 = load <8 x i8>, ptr %__promote, align 8
# |   store <8 x i8> %1, ptr %__ret, align 8
# |   %2 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %2, ptr %tmp, align 8
# |   %3 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vdup_n_mf8(<1 x i8> %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i8>, align 1
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %.compoundliteral.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i8>, align 1
# |   store <1 x i8> %a, ptr %a.addr, align 1
# |   %0 = load <1 x i8>, ptr %a.addr, align 1
# |   store <1 x i8> %0, ptr %__p0.addr.i, align 1
# |   %1 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext.i = shufflevector <1 x i8> %1, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit.i = shufflevector <8 x i8> %vext.i, <8 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %2 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext1.i = shufflevector <1 x i8> %2, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit2.i = shufflevector <8 x i8> %vecinit.i, <8 x i8> %vext1.i, <8 x i32> <i32 0, i32 8, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %3 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext3.i = shufflevector <1 x i8> %3, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit4.i = shufflevector <8 x i8> %vecinit2.i, <8 x i8> %vext3.i, <8 x i32> <i32 0, i32 1, i32 8, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %4 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext5.i = shufflevector <1 x i8> %4, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit6.i = shufflevector <8 x i8> %vecinit4.i, <8 x i8> %vext5.i, <8 x i32> <i32 0, i32 1, i32 2, i32 8, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %5 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext7.i = shufflevector <1 x i8> %5, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit8.i = shufflevector <8 x i8> %vecinit6.i, <8 x i8> %vext7.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 poison, i32 poison, i32 poison>
# |   %6 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext9.i = shufflevector <1 x i8> %6, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit10.i = shufflevector <8 x i8> %vecinit8.i, <8 x i8> %vext9.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 poison, i32 poison>
# |   %7 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext11.i = shufflevector <1 x i8> %7, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit12.i = shufflevector <8 x i8> %vecinit10.i, <8 x i8> %vext11.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 poison>
# |   %8 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext13.i = shufflevector <1 x i8> %8, <1 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit14.i = shufflevector <8 x i8> %vecinit12.i, <8 x i8> %vext13.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8>
# |   store <8 x i8> %vecinit14.i, ptr %.compoundliteral.i, align 8
# |   %9 = load <8 x i8>, ptr %.compoundliteral.i, align 8
# |   store <8 x i8> %9, ptr %__ret.i, align 8
# |   %10 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vdupq_n_mf8(<1 x i8> %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i8>, align 1
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %.compoundliteral.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <1 x i8>, align 1
# |   store <1 x i8> %a, ptr %a.addr, align 1
# |   %0 = load <1 x i8>, ptr %a.addr, align 1
# |   store <1 x i8> %0, ptr %__p0.addr.i, align 1
# |   %1 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext.i = shufflevector <1 x i8> %1, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit.i = shufflevector <16 x i8> %vext.i, <16 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %2 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext1.i = shufflevector <1 x i8> %2, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit2.i = shufflevector <16 x i8> %vecinit.i, <16 x i8> %vext1.i, <16 x i32> <i32 0, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %3 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext3.i = shufflevector <1 x i8> %3, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit4.i = shufflevector <16 x i8> %vecinit2.i, <16 x i8> %vext3.i, <16 x i32> <i32 0, i32 1, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %4 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext5.i = shufflevector <1 x i8> %4, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit6.i = shufflevector <16 x i8> %vecinit4.i, <16 x i8> %vext5.i, <16 x i32> <i32 0, i32 1, i32 2, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %5 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext7.i = shufflevector <1 x i8> %5, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit8.i = shufflevector <16 x i8> %vecinit6.i, <16 x i8> %vext7.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %6 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext9.i = shufflevector <1 x i8> %6, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit10.i = shufflevector <16 x i8> %vecinit8.i, <16 x i8> %vext9.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %7 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext11.i = shufflevector <1 x i8> %7, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit12.i = shufflevector <16 x i8> %vecinit10.i, <16 x i8> %vext11.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %8 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext13.i = shufflevector <1 x i8> %8, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit14.i = shufflevector <16 x i8> %vecinit12.i, <16 x i8> %vext13.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %9 = load <1 x i8>, ptr %__p0.addr.i, align 1
# |   %vext15.i = shufflevector <1 x i8> %9, <1 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
# |   %vecinit16.i = shufflevector <16 x i8> %vecinit14.i, <16 x i8> %vext15.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison
# | ...
# `---data was truncated (10240/101594) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x0000564a2ccb415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564a2ccb10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564a2ccb489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff6ad933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6ad98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff6ad933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6ad91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a2cc49e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564a2cc49c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564a2cc2eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564a2c8de0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564a2c8dddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff6ad91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6ad91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6ad91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a2c8ddcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiply.c (1426 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiply.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o -           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfma_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %c.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store <2 x float> %c, ptr %c.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load <2 x float>, ptr %c.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <2 x float>
# |   %7 = bitcast <8 x i8> %4 to <2 x float>
# |   %8 = bitcast <8 x i8> %5 to <2 x float>
# |   %9 = call <2 x float> @llvm.fma.v2f32(<2 x float> %7, <2 x float> %8, <2 x float> %6)
# |   store <2 x float> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %10, ptr %__ret.i, align 8
# |   %11 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfma_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x double>, align 8
# |   %__p1.addr.i = alloca <1 x double>, align 8
# |   %__p2.addr.i = alloca <1 x double>, align 8
# |   %__ret.i = alloca <1 x double>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %c.addr = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %c, ptr %c.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   %2 = load <1 x double>, ptr %c.addr, align 8
# |   store <1 x double> %0, ptr %__p0.addr.i, align 8
# |   store <1 x double> %1, ptr %__p1.addr.i, align 8
# |   store <1 x double> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <1 x double>
# |   %7 = bitcast <8 x i8> %4 to <1 x double>
# |   %8 = bitcast <8 x i8> %5 to <1 x double>
# |   %9 = call <1 x double> @llvm.fma.v1f64(<1 x double> %7, <1 x double> %8, <1 x double> %6)
# |   store <1 x double> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <1 x double>, ptr %ref.tmp.i, align 8
# |   store <1 x double> %10, ptr %__ret.i, align 8
# |   %11 = load <1 x double>, ptr %__ret.i, align 8
# |   ret <1 x double> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x float>, align 16
# |   %b.addr = alloca <4 x float>, align 16
# |   %c.addr = alloca <4 x float>, align 16
# |   store <4 x float> %a, ptr %a.addr, align 16
# |   store <4 x float> %b, ptr %b.addr, align 16
# |   store <4 x float> %c, ptr %c.addr, align 16
# |   %0 = load <4 x float>, ptr %a.addr, align 16
# |   %1 = load <4 x float>, ptr %b.addr, align 16
# |   %2 = load <4 x float>, ptr %c.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store <4 x float> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <4 x float>
# |   %7 = bitcast <16 x i8> %4 to <4 x float>
# |   %8 = bitcast <16 x i8> %5 to <4 x float>
# |   %9 = call <4 x float> @llvm.fma.v4f32(<4 x float> %7, <4 x float> %8, <4 x float> %6)
# |   store <4 x float> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %10, ptr %__ret.i, align 16
# |   %11 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vfmaq_f64(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__p2.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <2 x double>, align 16
# |   %b.addr = alloca <2 x double>, align 16
# |   %c.addr = alloca <2 x double>, align 16
# |   store <2 x double> %a, ptr %a.addr, align 16
# |   store <2 x double> %b, ptr %b.addr, align 16
# |   store <2 x double> %c, ptr %c.addr, align 16
# |   %0 = load <2 x double>, ptr %a.addr, align 16
# |   %1 = load <2 x double>, ptr %b.addr, align 16
# |   %2 = load <2 x double>, ptr %c.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   store <2 x double> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <2 x double>
# |   %7 = bitcast <16 x i8> %4 to <2 x double>
# |   %8 = bitcast <16 x i8> %5 to <2 x double>
# |   %9 = call <2 x double> @llvm.fma.v2f64(<2 x double> %7, <2 x double> %8, <2 x double> %6)
# |   store <2 x double> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %10, ptr %__ret.i, align 16
# |   %11 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfma_lane_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %v.addr = alloca <2 x float>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %__s1 = alloca <2 x float>, align 8
# |   %__s2 = alloca <2 x float>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store <2 x float> %v, ptr %v.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %1, ptr %__s1, align 8
# |   %2 = load <2 x float>, ptr %v.addr, align 8
# |   store <2 x float> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <2 x float>
# |   %lane = shufflevector <2 x float> %6, <2 x float> %6, <2 x i32> <i32 1, i32 1>
# |   %fmla = bitcast <8 x i8> %4 to <2 x float>
# |   %fmla1 = bitcast <8 x i8> %3 to <2 x float>
# |   %fmla2 = call <2 x float> @llvm.fma.v2f32(<2 x float> %fmla, <2 x float> %lane, <2 x float> %fmla1)
# |   store <2 x float> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %7, ptr %__ret, align 8
# |   %8 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %8, ptr %tmp, align 8
# |   %9 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca <1 x double>, align 8
# |   %b.addr = alloca <1 x double>, align 8
# |   %v.addr = alloca <1 x double>, align 8
# |   %__ret = alloca <1 x double>, align 8
# |   %__s0 = alloca <1 x double>, align 8
# |   %__s1 = alloca <1 x double>, align 8
# |   %__s2 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <1 x double>, align 8
# |   store <1 x double> %a, ptr %a.addr, align 8
# |   store <1 x double> %b, ptr %b.addr, align 8
# |   store <1 x double> %v, ptr %v.addr, align 8
# |   %0 = load <1 x double>, ptr %a.addr, align 8
# |   store <1 x double> %0, ptr %__s0, align 8
# |   %1 = load <1 x double>, ptr %b.addr, align 8
# |   store <1 x double> %1, ptr %__s1, align 8
# |   %2 = load <1 x double>, ptr %v.addr, align 8
# |   store <1 x double> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <1 x double>
# |   %lane = shufflevector <1 x double> %6, <1 x double> %6, <1 x i32> zeroinitializer
# |   %fmla = bitcast <8 x i8> %4 to <1 x double>
# |   %fmla1 = bitcast <8 x i8> %3 to <1 x double>
# |   %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1)
# |   store <1 x double> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <1 x double>, ptr %ref.tmp, align 8
# |   store <1 x double> %7, ptr %__ret, align 8
# |   %8 = load <1 x double>, ptr %__ret, align 8
# |   store <1 x double> %8, ptr %tmp, align 8
# |   %9 = load <1 x double>, ptr %tmp, align 8
# |   ret <1 x double> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>) #1
# | 
# | ; Functio
# | ...
# `---data was truncated (10240/80179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000562da75d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562da75d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562da75d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf03f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf03f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf03f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf03f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562da7569e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562da7569c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562da754eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562da71fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562da71fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbf03f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf03f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf03f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562da71fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c (1427 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555798da115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555798d9e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555798da189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f480681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48068725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f480681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4806803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555798d36e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555798d36c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555798d1bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005557989cb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005557989cadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4806804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48068050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48068050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557989cacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c (1428 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c05f1215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564c05f0f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564c05f1289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4c70449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4c704a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4c70449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4c70431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c05ea7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564c05ea7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564c05e8cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564c05b3c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564c05b3bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4c70432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4c704330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4c704330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c05b3bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c (1429 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cbb38cd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cbb38ca0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cbb38cd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4fa933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4fa98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4fa933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4fa91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbb3862e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cbb3862c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cbb3847b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cbb34f70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cbb34f6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff4fa91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4fa91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4fa91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbb34f6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c (1430 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca 
# | ...
# `---data was truncated (10240/14311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf338b515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bf338b20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bf338b589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc22a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc22a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc22a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc22a003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf3384ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bf3384ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bf3382fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bf334df0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bf334dedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc22a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc22a0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc22a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf334decc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c (1431 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056163bb8915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056163bb860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056163bb8989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f354b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f354b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f354b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f354b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056163bb1ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056163bb1ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056163bb03b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056163b7b30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056163b7b2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f354b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f354b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f354b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056163b7b2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c (1432 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8_tu(<vscale x 32 x i16> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 nounde
# | ...
# `---data was truncated (10240/26592) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e11dbc115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e11dbbe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e11dbc189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fefee249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fefee2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fefee249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fefee231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e11db56e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e11db56c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e11db3bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e11d7eb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e11d7eadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fefee232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fefee2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fefee2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e11d7eacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c (1433 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_ran
# | ...
# `---data was truncated (10240/10878) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570da26e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005570da26b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005570da26e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff406a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff406a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff406a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff406a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570da203e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005570da203c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005570da1e8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005570d9e980b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005570d9e97dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff406a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff406a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff406a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570d9e97cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c (1434 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/12067) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055932c36415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055932c3610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055932c36489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22bdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22bdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22bdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22bdd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055932c2f9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055932c2f9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055932c2deb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055932bf8e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055932bf8ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f22bdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22bdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22bdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055932bf8dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c (1435 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_wv_i16m
# | ...
# `---data was truncated (10240/134565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561dce23f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561dce23c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561dce23f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9309933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f930998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9309933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f930991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561dce1d4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561dce1d4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561dce1b9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561dcde690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561dcde68dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f930991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f930991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f930991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561dcde68cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c (1436 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tupl
# | ...
# `---data was truncated (10240/53454) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576c521515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005576c52120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005576c521589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f89c8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f89c878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f89c8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f89c871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576c51aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005576c51aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005576c518fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005576c4e3f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005576c4e3edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f89c871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f89c871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f89c871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576c4e3ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c (1437 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 0)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_poly_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_poly_m_p8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |  
# | ...
# `---data was truncated (10240/12050) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b377b415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555b377b10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555b377b489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f52a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f52aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f52a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f52a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b37749e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555b37749c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555b3772eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555b373de0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555b373dddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4f52a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f52a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f52a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b373ddcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c (1438 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650446cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005650446c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005650446cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9243705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f924375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9243705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92436ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565044660e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565044660c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565044645b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005650442f50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005650442f4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f92436eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92436ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92436ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650442f4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c (1439 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b7f8e9115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b7f8e8e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b7f8e9189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdab3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdab34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdab3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdab3431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7f8e26e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b7f8e26c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b7f8e0bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b7f8abb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b7f8abadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdab3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdab34330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdab34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7f8abacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c (1440 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2
# | ...
# `---data was truncated (10240/32654) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560d2f5715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005560d2f540f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005560d2f5789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1b1f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1b1f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1b1f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1b1eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560d2eece2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005560d2eecc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005560d2ed1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005560d2b810b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005560d2b80dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff1b1eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1b1eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1b1eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560d2b80cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c (1441 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/225205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b9388215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563b9387f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563b9388289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78b7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78b78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78b7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78b7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b93817e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563b93817c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563b937fcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563b934ac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563b934abdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f78b7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78b78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78b78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b934abcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c (1442 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560fae73415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560fae7310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560fae73489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4d0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4d0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4d0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4d0c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560fae6c9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560fae6c9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560fae6aeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560fae35e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560fae35ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb4d0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4d0c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4d0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560fae35dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c (1443 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8
# | ...
# `---data was truncated (10240/60809) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567cd00b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005567cd0080f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005567cd00b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cd2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cd20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cd2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cd2031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567ccfa0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005567ccfa0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005567ccf85b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005567ccc350b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005567ccc34dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7cd2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cd20330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cd20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567ccc34cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c (1444 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function A
# | ...
# `---data was truncated (10240/30415) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bbe47dd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bbe47da0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bbe47dd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc423333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc42338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc423333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc42331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbe4772e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bbe4772c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bbe4757b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bbe44070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bbe4406dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc42331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc42331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc42331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbe4406cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c (1445 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c63802d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c63802a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c63802d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7db9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7db92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7db9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7db9231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c637fc2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c637fc2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c637fa7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c637c570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c637c56dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7db9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7db92330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7db92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c637c56cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c (1446 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/68429) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563847e8915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563847e860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563847e8989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50af305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50af35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50af305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50af2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563847e1ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563847e1ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563847e03b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563847ab30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563847ab2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f50af2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50af2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50af2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563847ab2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c (1447 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x 
# | ...
# `---data was truncated (10240/292007) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9758fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e9758f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e9758fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fccbba1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fccbba725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fccbba1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fccbba03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e975890e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e975890c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e975875b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e9755250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e975524dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fccbba04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fccbba050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fccbba050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e975524cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c (1448 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline noun
# | ...
# `---data was truncated (10240/121187) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9b867c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a9b86790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a9b867c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f253c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f253c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f253c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f253c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9b8611e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a9b8611c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a9b85f6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a9b82a60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a9b82a5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f253c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f253c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f253c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9b82a5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c (1449 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055582b99015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055582b98d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055582b99089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc74fa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc74fa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc74fa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc74fa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055582b925e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055582b925c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055582b90ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055582b5ba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055582b5b9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc74fa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc74fa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc74fa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055582b5b9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c (1450 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, 
# | ...
# `---data was truncated (10240/288103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3e9dfc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b3e9df90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b3e9dfc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7309f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7309f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7309f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7309eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3e9d91e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b3e9d91c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b3e9d76b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b3e9a260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b3e9a25dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7309eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7309eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7309eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3e9a25cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c (1451 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056282a05715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056282a0540f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056282a05789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12f7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12f7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12f7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12f7c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562829fece2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562829fecc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562829fd1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562829c810b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562829c80dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f12f7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12f7c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12f7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562829c80cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c (1452 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9c608915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a9c60860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a9c608989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1854733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f185478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1854733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f185471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9c601ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a9c601ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a9c6003b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a9c5cb30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a9c5cb2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f185471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f185471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f185471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9c5cb2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c (1453 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | decl
# | ...
# `---data was truncated (10240/20497) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2bafb315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a2bafb00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a2bafb389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0a1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0a1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0a1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0a1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2baf48e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a2baf48c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a2baf2db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a2babdd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a2babdcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb0a1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0a1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0a1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2babdccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c (1454 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Functio
# | ...
# `---data was truncated (10240/13657) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b79def15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561b79dec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561b79def89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4988533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f498858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4988533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f498851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b79d84e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561b79d84c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561b79d69b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561b79a190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561b79a18dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f498851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f498851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f498851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b79a18cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c (1455 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x bfloa
# | ...
# `---data was truncated (10240/12528) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca5a2d815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ca5a2d50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ca5a2d889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6270e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6270ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6270e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6270e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca5a26de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ca5a26dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ca5a252b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ca59f020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ca59f01dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6270e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6270e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6270e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca59f01cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c (1456 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrsub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrsub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrsub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrsub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrsub_vx_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrsub_vx_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vrsub_vx_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vrsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vrsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i16 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i16 %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vsc
# | ...
# `---data was truncated (10240/207075) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e36d06f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e36d06c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e36d06f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56a8f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56a8f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56a8f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56a8eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e36d004e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e36d004c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e36cfe9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e36cc990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e36cc98dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f56a8eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56a8eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56a8eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e36cc98cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c (1457 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1
# | ...
# `---data was truncated (10240/154215) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c7089615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559c708930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559c7089689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f996d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f996d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f996d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f996d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c7082be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559c7082bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559c70810b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559c704c00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559c704bfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f996d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f996d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f996d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c704bfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c (1458 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 
# | ...
# `---data was truncated (10240/26520) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632d7c4515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005632d7c420f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005632d7c4589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b18f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b18f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b18f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b18f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632d7bdae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005632d7bdac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005632d7bbfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005632d786f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005632d786edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6b18f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b18f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b18f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632d786ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c (1459 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-unknown-linux"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_8x8(<8 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   %1 = load <8 x i8>, ptr %x.addr, align 8
# |   %shuffle = shufflevector <8 x i8> %0, <8 x i8> %1, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 3, i32 2, i32 1, i32 0>
# |   ret <8 x i8> %shuffle
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_8x8_v(<8 x i8> %x, <8 x i8> noundef %p) #0 {
# | entry:
# |   %x.addr = alloca <8 x i8>, align 8
# |   %p.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %x, ptr %x.addr, align 8
# |   store <8 x i8> %p, ptr %p.addr, align 8
# |   %0 = load <8 x i8>, ptr %x.addr, align 8
# |   %1 = load <8 x i8>, ptr %p.addr, align 8
# |   %mask = and <8 x i8> %1, splat (i8 7)
# |   %shuf_idx = extractelement <8 x i8> %mask, i64 0
# |   %shuf_elt = extractelement <8 x i8> %0, i8 %shuf_idx
# |   %shuf_ins = insertelement <8 x i8> poison, i8 %shuf_elt, i64 0
# |   %shuf_idx1 = extractelement <8 x i8> %mask, i64 1
# |   %shuf_elt2 = extractelement <8 x i8> %0, i8 %shuf_idx1
# |   %shuf_ins3 = insertelement <8 x i8> %shuf_ins, i8 %shuf_elt2, i64 1
# |   %shuf_idx4 = extractelement <8 x i8> %mask, i64 2
# |   %shuf_elt5 = extractelement <8 x i8> %0, i8 %shuf_idx4
# |   %shuf_ins6 = insertelement <8 x i8> %shuf_ins3, i8 %shuf_elt5, i64 2
# |   %shuf_idx7 = extractelement <8 x i8> %mask, i64 3
# |   %shuf_elt8 = extractelement <8 x i8> %0, i8 %shuf_idx7
# |   %shuf_ins9 = insertelement <8 x i8> %shuf_ins6, i8 %shuf_elt8, i64 3
# |   %shuf_idx10 = extractelement <8 x i8> %mask, i64 4
# |   %shuf_elt11 = extractelement <8 x i8> %0, i8 %shuf_idx10
# |   %shuf_ins12 = insertelement <8 x i8> %shuf_ins9, i8 %shuf_elt11, i64 4
# |   %shuf_idx13 = extractelement <8 x i8> %mask, i64 5
# |   %shuf_elt14 = extractelement <8 x i8> %0, i8 %shuf_idx13
# |   %shuf_ins15 = insertelement <8 x i8> %shuf_ins12, i8 %shuf_elt14, i64 5
# |   %shuf_idx16 = extractelement <8 x i8> %mask, i64 6
# |   %shuf_elt17 = extractelement <8 x i8> %0, i8 %shuf_idx16
# |   %shuf_ins18 = insertelement <8 x i8> %shuf_ins15, i8 %shuf_elt17, i64 6
# |   %shuf_idx19 = extractelement <8 x i8> %mask, i64 7
# |   %shuf_elt20 = extractelement <8 x i8> %0, i8 %shuf_idx19
# |   %shuf_ins21 = insertelement <8 x i8> %shuf_ins18, i8 %shuf_elt20, i64 7
# |   ret <8 x i8> %shuf_ins21
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_8x16(<16 x i8> %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = load <16 x i8>, ptr %x.addr, align 16
# |   %shuffle = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
# |   ret <16 x i8> %shuffle
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_8x16_v(<16 x i8> %x, <16 x i8> noundef %p) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   %p.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   store <16 x i8> %p, ptr %p.addr, align 16
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = load <16 x i8>, ptr %p.addr, align 16
# |   %mask = and <16 x i8> %1, splat (i8 15)
# |   %shuf_idx = extractelement <16 x i8> %mask, i64 0
# |   %shuf_elt = extractelement <16 x i8> %0, i8 %shuf_idx
# |   %shuf_ins = insertelement <16 x i8> poison, i8 %shuf_elt, i64 0
# |   %shuf_idx1 = extractelement <16 x i8> %mask, i64 1
# |   %shuf_elt2 = extractelement <16 x i8> %0, i8 %shuf_idx1
# |   %shuf_ins3 = insertelement <16 x i8> %shuf_ins, i8 %shuf_elt2, i64 1
# |   %shuf_idx4 = extractelement <16 x i8> %mask, i64 2
# |   %shuf_elt5 = extractelement <16 x i8> %0, i8 %shuf_idx4
# |   %shuf_ins6 = insertelement <16 x i8> %shuf_ins3, i8 %shuf_elt5, i64 2
# |   %shuf_idx7 = extractelement <16 x i8> %mask, i64 3
# |   %shuf_elt8 = extractelement <16 x i8> %0, i8 %shuf_idx7
# |   %shuf_ins9 = insertelement <16 x i8> %shuf_ins6, i8 %shuf_elt8, i64 3
# |   %shuf_idx10 = extractelement <16 x i8> %mask, i64 4
# |   %shuf_elt11 = extractelement <16 x i8> %0, i8 %shuf_idx10
# |   %shuf_ins12 = insertelement <16 x i8> %shuf_ins9, i8 %shuf_elt11, i64 4
# |   %shuf_idx13 = extractelement <16 x i8> %mask, i64 5
# |   %shuf_elt14 = extractelement <16 x i8> %0, i8 %shuf_idx13
# |   %shuf_ins15 = insertelement <16 x i8> %shuf_ins12, i8 %shuf_elt14, i64 5
# |   %shuf_idx16 = extractelement <16 x i8> %mask, i64 6
# |   %shuf_elt17 = extractelement <16 x i8> %0, i8 %shuf_idx16
# |   %shuf_ins18 = insertelement <16 x i8> %shuf_ins15, i8 %shuf_elt17, i64 6
# |   %shuf_idx19 = extractelement <16 x i8> %mask, i64 7
# |   %shuf_elt20 = extractelement <16 x i8> %0, i8 %shuf_idx19
# |   %shuf_ins21 = insertelement <16 x i8> %shuf_ins18, i8 %shuf_elt20, i64 7
# |   %shuf_idx22 = extractelement <16 x i8> %mask, i64 8
# |   %shuf_elt23 = extractelement <16 x i8> %0, i8 %shuf_idx22
# |   %shuf_ins24 = insertelement <16 x i8> %shuf_ins21, i8 %shuf_elt23, i64 8
# |   %shuf_idx25 = extractelement <16 x i8> %mask, i64 9
# |   %shuf_elt26 = extractelement <16 x i8> %0, i8 %shuf_idx25
# |   %shuf_ins27 = insertelement <16 x i8> %shuf_ins24, i8 %shuf_elt26, i64 9
# |   %shuf_idx28 = extractelement <16 x i8> %mask, i64 10
# |   %shuf_elt29 = extractelement <16 x i8> %0, i8 %shuf_idx28
# |   %shuf_ins30 = insertelement <16 x i8> %shuf_ins27, i8 %shuf_elt29, i64 10
# |   %shuf_idx31 = extractelement <16 x i8> %mask, i64 11
# |   %shuf_elt32 = extractelement <16 x i8> %0, i8 %shuf_idx31
# |   %shuf_ins33 = insertelement <16 x i8> %shuf_ins30, i8 %shuf_elt32, i64 11
# |   %shuf_idx34 = extractelement <16 x i8> %mask, i64 12
# |   %shuf_elt35 = extractelement <16 x i8> %0, i8 %shuf_idx34
# |   %shuf_ins36 = insertelement <16 x i8> %shuf_ins33, i8 %shuf_elt35, i64 12
# |   %shuf_idx37 = extractelement <16 x i8> %mask, i64 13
# |   %shuf_elt38 = extractelement <16 x i8> %0, i8 %shuf_idx37
# |   %shuf_ins39 = insertelement <16 x i8> %shuf_ins36, i8 %shuf_elt38, i64 13
# |   %shuf_idx40 = extractelement <16 x i8> %mask, i64 14
# |   %shuf_elt41 = extractelement <16 x i8> %0, i8 %shuf_idx40
# |   %shuf_ins42 = insertelement <16 x i8> %shuf_ins39, i8 %shuf_elt41, i64 14
# |   %shuf_idx43 = extractelement <16 x i8> %mask, i64 15
# |   %shuf_elt44 = extractelement <16 x i8> %0, i8 %shuf_idx43
# |   %shuf_ins45 = insertelement <16 x i8> %shuf_ins42, i8 %shuf_elt44, i64 15
# |   ret <16 x i8> %shuf_ins45
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a88405615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a8840530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a88405689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff192f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff192f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff192f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff192f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a883febe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a883febc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a883fd0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a883c800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a883c7fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff192f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff192f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff192f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a883c7fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c (1460 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vx_u16m4(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/68141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1b195815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c1b19550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c1b195889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f003d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f003d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f003d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f003d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1b18ede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c1b18edc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c1b18d2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c1b15820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c1b1581dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f003d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f003d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f003d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1b1581cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c (1461 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_s16(ptr noundef %base, <8 x i16> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_s32(ptr noundef %base, <4 x i32> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_s8(ptr noundef %base, <16 x i8> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr, <16 x i8>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_u16(ptr noundef %base, <8 x i16> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_u32(ptr noundef %base, <4 x i32> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_u8(ptr noundef %base, <16 x i8> noundef %offset) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_s16(ptr noundef %base, <8 x i16> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 0, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr, <8 x i16>, i32, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_s32(ptr noundef %base, <4 x i32> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 0, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr, <4 x i32>, i32, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_s8(ptr noundef %base, <16 x i8> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 0, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr, <16 x i8>, i32, i32, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_u16(ptr noundef %base, <8 x i16> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <8 x i16> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <8 x i16>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_u32(ptr noundef %base, <4 x i32> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <4 x i32> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <4 x i32>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_u8(ptr noundef %base, <16 x i8> noundef %offset, i16 noundef zeroext %p) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 4
# |   %offset.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store ptr %base, ptr %base.addr, align 4
# |   store <16 x i8> %offset, ptr %offset.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load ptr, ptr %base.addr, align 4
# |   %1 = load <16 x i8>, ptr %offset.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vf
# | ...
# `---data was truncated (10240/117019) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfdd26215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cfdd25f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cfdd26289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb702649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7026a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb702649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb702631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfdd1f7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cfdd1f7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cfdd1dcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cfdce8c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cfdce8bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb702632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7026330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7026330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfdce8bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c (1462 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055907fc0215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055907fbff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055907fc0289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f481dd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f481dd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f481dd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f481dced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055907fb97e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055907fb97c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055907fb7cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055907f82c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055907f82bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f481dceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f481dcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f481dcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055907f82bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c (1463 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractva
# | ...
# `---data was truncated (10240/27866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b0a01c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562b0a0190f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562b0a01c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff606b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff606b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff606b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff606b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b09fb1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562b09fb1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562b09f96b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562b09c460b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562b09c45dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff606b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff606b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff606b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b09c45cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c (1464 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { targe
# | ...
# `---data was truncated (10240/68233) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056550614515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005655061420f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056550614589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d3d81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d3d8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d3d81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d3d803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005655060dae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005655060dac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005655060bfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000565505d6f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000565505d6edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4d3d804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d3d8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d3d8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565505d6ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c (1465 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_i16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8
# | ...
# `---data was truncated (10240/15457) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc1b91215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cc1b90f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cc1b91289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe88c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe88c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe88c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe88c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc1b8a7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cc1b8a7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cc1b88cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cc1b53c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cc1b53bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efe88c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe88c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe88c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc1b53bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c (1466 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32bf16.i64(<vscale x
# | ...
# `---data was truncated (10240/24328) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055961bf4415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055961bf410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055961bf4489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57f1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57f118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57f1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57f111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055961bed9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055961bed9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055961bebeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055961bb6e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055961bb6ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f57f111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57f111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57f111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055961bb6dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c (1467 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c466e615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562c466e30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562c466e689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2e2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2e28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2e2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2e2831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c4667be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562c4667bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562c46660b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562c463100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562c4630fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa2e2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2e28330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2e28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c4630fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c (1468 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>
# | ...
# `---data was truncated (10240/13290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ab779915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555ab77960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555ab779989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7b4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7b4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7b4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7b4c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ab772ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555ab772ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555ab7713b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555ab73c30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555ab73c2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb7b4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7b4c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7b4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ab73c2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c (1469 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560c972e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005560c972b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005560c972e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9cc0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9cc04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9cc0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9cc0431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560c96c3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005560c96c3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005560c96a8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005560c93580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005560c9357dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9cc0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9cc04330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9cc04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560c9357cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c (1470 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8(<vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vrgatherei16_vv_f32m2(<vscale x 4 x float> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vrgatherei16_vv_f32m4(<vscale x 8 x float> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 8 x 
# | ...
# `---data was truncated (10240/124028) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056378064215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056378063f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056378064289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c2061bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c206725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c2061ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c20603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637805d7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005637805d7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005637805bcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056378026c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056378026bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6c20604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c206050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c206050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056378026bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c (1471 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ba03ae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555ba03ab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555ba03ae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ff0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ff0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ff0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ff0e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ba0343e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555ba0343c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555ba0328b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555b9ffd80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555b9ffd7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7ff0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ff0e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ff0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b9ffd7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c (1472 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vsc
# | ...
# `---data was truncated (10240/147382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9c2e4115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d9c2e3e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d9c2e4189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9002f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9002f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9002f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9002f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9c2dd6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d9c2dd6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d9c2dbbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d9c2a6b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d9c2a6add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9002f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9002f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9002f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9c2a6acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c (1473 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f996ef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557f996ec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557f996ef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5676a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5676aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5676a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5676a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f99684e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557f99684c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557f99669b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557f993190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557f99318dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5676a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5676a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5676a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f99318cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c (1474 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale 
# | ...
# `---data was truncated (10240/179177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582708b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005582708b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005582708b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f298cc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f298cc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f298cc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f298cc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055827084be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055827084bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558270830b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005582704e00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005582704dfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f298cc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f298cc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f298cc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582704dfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c (1475 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584dc4cd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005584dc4ca0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005584dc4cd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94f7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94f758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94f7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94f751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584dc462e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005584dc462c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005584dc447b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005584dc0f70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005584dc0f6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f94f751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94f751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94f751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584dc0f6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c (1476 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local targ
# | ...
# `---data was truncated (10240/70855) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c09b2d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562c09b2a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562c09b2d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9d4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9d438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9d4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9d431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c09ac2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562c09ac2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562c09aa7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562c097570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562c09756dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc9d431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9d431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9d431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c09756cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c (1477 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056109bbb315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056109bbb00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056109bbb389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4b6905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4b695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4b6905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4b68ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056109bb48e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056109bb48c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056109bb2db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056109b7dd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056109b7dcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd4b68eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4b68ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4b68ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056109b7dccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c (1478 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x floa
# | ...
# `---data was truncated (10240/199588) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565215e4d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000565215e4a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000565215e4d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a72a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a72a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a72a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a72a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565215de2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565215de2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565215dc7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000565215a770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000565215a76dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2a72a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a72a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a72a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565215a76cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c (1479 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f7fbb115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555f7fbae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555f7fbb189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7019f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7019f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7019f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7019eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f7fb46e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555f7fb46c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555f7fb2bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555f7f7db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555f7f7dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7019eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7019eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7019eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f7f7dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c (1480 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6d915615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a6d91530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a6d915689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facc2c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facc2c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facc2c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facc2c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6d90ebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a6d90ebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a6d90d0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a6d8d800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a6d8d7fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007facc2c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facc2c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facc2c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6d8d7fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c (1481 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9890e415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d9890e10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d9890e489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba70849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba708a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba70849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba70831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d989079e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d989079c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d98905eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d988d0e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d988d0ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fba70832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba708330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba708330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d988d0dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c (1482 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056438de3d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056438de3a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056438de3d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f810ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f810cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f810ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f810ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056438ddd2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056438ddd2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056438ddb7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056438da670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056438da66dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f810ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f810ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f810ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056438da66cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c (1483 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644c4a1b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005644c4a180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005644c4a1b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4018133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f401818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4018133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f401811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644c49b0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005644c49b0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005644c4995b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005644c46450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005644c4644dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f401811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f401811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f401811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644c4644cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c (1484 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64ff_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bc837c115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bc837be0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bc837c189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc661849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6618a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc661849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc661831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bc83756e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bc83756c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bc8373bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bc833eb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bc833eadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc661832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6618330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6618330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bc833eacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c (1485 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f8f3c015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564f8f3bd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564f8f3c089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc768133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc76818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc768133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc76811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f8f355e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564f8f355c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564f8f33ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564f8efea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564f8efe9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc76811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc76811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc76811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f8efe9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c (1486 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscal
# | ...
# `---data was truncated (10240/13282) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e281e215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560e281df0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560e281e289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ca3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ca358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ca3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ca351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e28177e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560e28177c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560e2815cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560e27e0c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560e27e0bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6ca351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ca351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ca351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e27e0bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c (1487 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %v
# | ...
# `---data was truncated (10240/148843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056431a63515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056431a6320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056431a63589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff65c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff65c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff65c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff65c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056431a5cae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056431a5cac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056431a5afb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056431a25f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056431a25edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff65c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff65c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff65c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056431a25ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c (1488 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x half>, ptr %inactive.addr, align 8
# |   %6 = call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> undef)
# |   ret <4 x float> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056005d1be15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056005d1bb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056005d1be89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f570e705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f570e75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f570e705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f570e6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056005d153e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056005d153c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056005d138b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056005cde80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056005cde7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f570e6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f570e6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f570e6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056005cde7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c (1489 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i64>, i64 } @l
# | ...
# `---data was truncated (10240/62760) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bba2f615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559bba2f30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559bba2f689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71e0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71e0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71e0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71e0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bba28be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559bba28bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559bba270b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559bb9f200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559bb9f1fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f71e0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71e0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71e0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bb9f1fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c (1490 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vluxei32_v_f32m8(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(<vscale x 16 x
# | ...
# `---data was truncated (10240/107864) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576e9f9a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005576e9f970f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005576e9f9a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ae6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ae62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ae6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ae6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576e9f2fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005576e9f2fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005576e9f14b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005576e9bc40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005576e9bc3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2ae6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ae62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ae62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576e9bc3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c (1491 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> 
# | ...
# `---data was truncated (10240/68054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646cc69015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005646cc68d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005646cc69089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec45f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec45f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec45f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec45eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646cc625e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005646cc625c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005646cc60ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005646cc2ba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005646cc2b9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fec45eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec45eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec45eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646cc2b9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c (1492 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# | ...
# `---data was truncated (10240/60691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0fa75915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c0fa7560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c0fa75989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f204b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f204b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f204b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f204b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0fa6eee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c0fa6eec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c0fa6d3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c0fa3830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c0fa382dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f204b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f204b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f204b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0fa382cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c (1493 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr,
# | ...
# `---data was truncated (10240/30874) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555aaf07f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555aaf07c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555aaf07f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed6b41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed6b4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed6b41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed6b403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555aaf014e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555aaf014c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555aaeff9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555aaeca90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555aaeca8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fed6b404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed6b4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed6b4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555aaeca8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/thinlto_backend.ll (1494 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto_backend.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll
# |  #0 0x000055c33a75f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c33a75c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c33a75f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16d8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16d878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16d8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16d871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c33a6f4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c33a6f4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c33a6d9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c33a3890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c33a388dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f16d871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16d871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16d871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c33a388cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c (1495 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vasub_vv_i8
# | ...
# `---data was truncated (10240/99577) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e5aaeb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557e5aae80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557e5aaeb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3942b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3942b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3942b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3942aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e5aa80e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557e5aa80c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557e5aa65b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557e5a7150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557e5a714dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3942aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3942aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3942aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e5a714cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c (1496 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559df42fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559df42fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559df42fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5375f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5375f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5375f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5375f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559df4292e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559df4292c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559df4277b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559df3f270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559df3f26dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5375f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5375f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5375f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559df3f26cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c (1497 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x 
# | ...
# `---data was truncated (10240/134919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056221a85815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056221a8550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056221a85889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc61d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc61d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc61d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc61d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056221a7ede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056221a7edc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056221a7d2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056221a4820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056221a481dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc61d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc61d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc61d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056221a481cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm64_vdupq_n_f64.c (1498 of 27911)
******************** TEST 'Clang :: CodeGen/arm64_vdupq_n_f64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x double> @test_vdupq_n_f64(double noundef %w) #0 {
# | entry:
# |   %__p0.addr.i = alloca double, align 8
# |   %__ret.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %w.addr = alloca double, align 8
# |   store double %w, ptr %w.addr, align 8
# |   %0 = load double, ptr %w.addr, align 8
# |   store double %0, ptr %__p0.addr.i, align 8
# |   %1 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit.i = insertelement <2 x double> poison, double %1, i32 0
# |   %2 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit1.i = insertelement <2 x double> %vecinit.i, double %2, i32 1
# |   store <2 x double> %vecinit1.i, ptr %.compoundliteral.i, align 16
# |   %3 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   store <2 x double> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x float> @test_vdupq_n_f32(float noundef %w) #0 {
# | entry:
# |   %__p0.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 16
# |   %.compoundliteral.i = alloca <4 x float>, align 16
# |   %w.addr = alloca float, align 4
# |   store float %w, ptr %w.addr, align 4
# |   %0 = load float, ptr %w.addr, align 4
# |   store float %0, ptr %__p0.addr.i, align 4
# |   %1 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %1, i32 0
# |   %2 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %2, i32 1
# |   %3 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %3, i32 2
# |   %4 = load float, ptr %__p0.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %4, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16
# |   %5 = load <4 x float>, ptr %.compoundliteral.i, align 16
# |   store <4 x float> %5, ptr %__ret.i, align 16
# |   %6 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x double> @test_vdupq_lane_f64(<1 x double> noundef %V) #0 {
# | entry:
# |   %V.addr = alloca <1 x double>, align 8
# |   %__ret_379 = alloca <2 x double>, align 16
# |   %__s0_379 = alloca <1 x double>, align 8
# |   %__ret = alloca <2 x double>, align 16
# |   %__s0 = alloca <1 x double>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <2 x double>, align 16
# |   %tmp1 = alloca <2 x double>, align 16
# |   store <1 x double> %V, ptr %V.addr, align 8
# |   %0 = load <1 x double>, ptr %V.addr, align 8
# |   store <1 x double> %0, ptr %__s0_379, align 8
# |   %1 = load <1 x double>, ptr %__s0_379, align 8
# |   store <1 x double> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <1 x double>
# |   %lane = shufflevector <1 x double> %3, <1 x double> %3, <2 x i32> zeroinitializer
# |   store <2 x double> %lane, ptr %ref.tmp, align 16
# |   %4 = load <2 x double>, ptr %ref.tmp, align 16
# |   store <2 x double> %4, ptr %__ret, align 16
# |   %5 = load <2 x double>, ptr %__ret, align 16
# |   store <2 x double> %5, ptr %tmp, align 16
# |   %6 = load <2 x double>, ptr %tmp, align 16
# |   store <2 x double> %6, ptr %__ret_379, align 16
# |   %7 = load <2 x double>, ptr %__ret_379, align 16
# |   store <2 x double> %7, ptr %tmp1, align 16
# |   %8 = load <2 x double>, ptr %tmp1, align 16
# |   ret <2 x double> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <2 x double> @test_vmovq_n_f64(double noundef %w) #0 {
# | entry:
# |   %__p0.addr.i = alloca double, align 8
# |   %__ret.i = alloca <2 x double>, align 16
# |   %.compoundliteral.i = alloca <2 x double>, align 16
# |   %w.addr = alloca double, align 8
# |   store double %w, ptr %w.addr, align 8
# |   %0 = load double, ptr %w.addr, align 8
# |   store double %0, ptr %__p0.addr.i, align 8
# |   %1 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit.i = insertelement <2 x double> poison, double %1, i32 0
# |   %2 = load double, ptr %__p0.addr.i, align 8
# |   %vecinit1.i = insertelement <2 x double> %vecinit.i, double %2, i32 1
# |   store <2 x double> %vecinit1.i, ptr %.compoundliteral.i, align 16
# |   %3 = load <2 x double>, ptr %.compoundliteral.i, align 16
# |   store <2 x double> %3, ptr %__ret.i, align 16
# |   %4 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x half> @test_vmov_n_f16(ptr noundef %a1) #0 {
# | entry:
# |   %a1.addr = alloca ptr, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store ptr %a1, ptr %a1.addr, align 8
# |   %0 = load ptr, ptr %a1.addr, align 8
# |   %1 = load half, ptr %0, align 2
# |   store half %1, ptr %__s0, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <4 x half> poison, half %2, i32 0
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <4 x half> %vecinit, half %3, i32 1
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <4 x half> %vecinit1, half %4, i32 2
# |   %5 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <4 x half> %vecinit2, half %5, i32 3
# |   store <4 x half> %vecinit3, ptr %.compoundliteral, align 8
# |   %6 = load <4 x half>, ptr %.compoundliteral, align 8
# |   store <4 x half> %6, ptr %__ret, align 8
# |   %7 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %7, ptr %tmp, align 8
# |   %8 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x half> @test_vmovq_n_f16(ptr noundef %a1) #0 {
# | entry:
# |   %a1.addr = alloca ptr, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store ptr %a1, ptr %a1.addr, align 8
# |   %0 = load ptr, ptr %a1.addr, align 8
# |   %1 = load half, ptr %0, align 2
# |   store half %1, ptr %__s0, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <8 x half> poison, half %2, i32 0
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <8 x half> %vecinit, half %3, i32 1
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <8 x half> %vecinit1, half %4, i32 2
# |   %5 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <8 x half> %vecinit2, half %5, i32 3
# |   %6 = load half, ptr %__s0, align 2
# |   %vecinit4 = insertelement <8 x half> %vecinit3, half %6, i32 4
# |   %7 = load half, ptr %__s0, align 2
# |   %vecinit5 = insertelement <8 x half> %vecinit4, half %7, i32 5
# |   %8 = load half, ptr %__s0, align 2
# |   %vecinit6 = insertelement <8 x half> %vecinit5, half %8, i32 6
# |   %9 = load half, ptr %__s0, align 2
# |   %vecinit7 = insertelement <8 x half> %vecinit6, half %9, i32 7
# |   store <8 x half> %vecinit7, ptr %.compoundliteral, align 16
# |   %10 = load <8 x half>, ptr %.compoundliteral, align 16
# |   store <8 x half> %10, ptr %__ret, align 16
# |   %11 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %11, ptr %tmp, align 16
# |   %12 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %12
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055e321a6915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e321a660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e321a6989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0bfac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0bfaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0bfac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0bfac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3219fee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e3219fec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e3219e3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e3216930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e321692dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0bfac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0bfac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0bfac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e321692cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c (1499 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa042f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fa042f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fa042f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7785f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7785f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7785f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7785f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa0428de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fa0428dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fa04272b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fa03f220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fa03f21dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7785f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7785f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7785f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa03f21cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c (1500 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -target-feature +zve64d    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_bf16m8(i64 noundef %tss, <vscale x 32 x bfloat> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f16m8(i64 noundef %tss, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 %0, <vscale x 32 x half> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f32m8(i64 noundef %tss, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 %0, <vscale x 16 x float> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f64m8(i64 noundef %tss, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 %0, <vscale x 8 x double> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64, <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f8e4m3m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale
# | ...
# `---data was truncated (10240/11640) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c99fa4015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c99fa3d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c99fa4089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3153333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f315338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3153333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f315331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c99f9d5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c99f9d5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c99f9bab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c99f66a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c99f669dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f315331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f315331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f315331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c99f669cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c (1501 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulsu_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulsu_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulsu_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulsu_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulsu_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr =
# | ...
# `---data was truncated (10240/154509) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b1935415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556b193510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556b1935489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5097d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5097d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5097d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5097d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b192e9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556b192e9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556b192ceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556b18f7e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556b18f7ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5097d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5097d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5097d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b18f7dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c (1502 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/16424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b743e4615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b743e430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b743e4689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c2a61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c2a6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c2a61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c2a603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b743ddbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b743ddbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b743dc0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b743a700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b743a6fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6c2a604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c2a6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c2a6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b743a6fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c (1503 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl
# | ...
# `---data was truncated (10240/78896) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e07109a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e0710970f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e07109a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc32201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3220725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc32201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc322003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e07102fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e07102fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e071014b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e070cc40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e070cc3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc322004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3220050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3220050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e070cc3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c (1504 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   s
# | ...
# `---data was truncated (10240/223359) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae0515b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ae051580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ae0515b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea7ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea7ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea7ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea7ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae050f0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ae050f0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ae050d5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ae04d850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ae04d84dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fea7ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea7ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea7ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae04d84cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c (1505 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vctz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vctz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vctz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vctz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vctz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vctz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(
# | ...
# `---data was truncated (10240/40661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d9e2d015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557d9e2cd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557d9e2d089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facd861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facd86725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facd861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facd8603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d9e265e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557d9e265c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557d9e24ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557d9defa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557d9def9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007facd8604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facd86050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facd86050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d9def9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c (1506 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_
# | ...
# `---data was truncated (10240/68065) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563eedb0c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563eedb090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563eedb0c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95f9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95f958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95f9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95f951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563eedaa1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563eedaa1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563eeda86b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563eed7360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563eed735dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f95f951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95f951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95f951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563eed735cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c (1507 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc39d8115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dc39d7e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dc39d8189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9ec733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9ec78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9ec733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9ec71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc39d16e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dc39d16c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dc39cfbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dc399ab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dc399aadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb9ec71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9ec71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9ec71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc399aacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c (1508 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056352a71915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056352a7160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056352a71989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a3661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a366725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a3661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a36603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056352a6aee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056352a6aec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056352a693b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056352a3430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056352a342dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8a36604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a366050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a366050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056352a342cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c (1509 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmset_m_b1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1.i64(i64 %0)
# |   ret <vscale x 64 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmset_m_b2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i1> @llvm.riscv.vmset.nxv32i1.i64(i64 %0)
# |   ret <vscale x 32 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmset.nxv32i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmset_m_b4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i1> @llvm.riscv.vmset.nxv16i1.i64(i64 %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmset.nxv16i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmset_m_b8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i1> @llvm.riscv.vmset.nxv8i1.i64(i64 %0)
# |   ret <vscale x 8 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmset.nxv8i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmset_m_b16(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i1> @llvm.riscv.vmset.nxv4i1.i64(i64 %0)
# |   ret <vscale x 4 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmset.nxv4i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmset_m_b32(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i1> @llvm.riscv.vmset.nxv2i1.i64(i64 %0)
# |   ret <vscale x 2 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmset.nxv2i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmset_m_b64(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1.i64(i64 %0)
# |   ret <vscale x 1 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1.i64(i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a9963b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559a996380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559a9963b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7650c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7650ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7650c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7650c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a995d0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559a995d0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559a995b5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559a992650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559a99264dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7650c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7650c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7650c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a99264cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c (1510 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055840adde15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055840addb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055840adde89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a07d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a07d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a07d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a07d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055840ad73e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055840ad73c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055840ad58b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055840aa080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055840aa07dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2a07d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a07d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a07d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055840aa07cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c (1511 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7dba1415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e7dba110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e7dba1489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe975133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe97518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe975133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe97511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7db9a9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e7db9a9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e7db98eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e7db63e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e7db63ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe97511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe97511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe97511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7db63dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c (1512 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vle.mask.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.mask.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vle.mask.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.mask.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vle.mask.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.mask.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vle.mask.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.mask.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vle.mask.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.mask.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vle.mask.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.mask.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vle.mask.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.mask.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vle.mask.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.mask.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vle.mask.nxv16i32.p0.i64(<vscale x 16 x i32> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.mask.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; 
# | ...
# `---data was truncated (10240/14699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ff59e115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564ff59de0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564ff59e189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbb6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbb6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbb6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbb6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ff5976e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564ff5976c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564ff595bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564ff560b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564ff560add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ffbb6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbb6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbb6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ff560acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmovn.c (1513 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmovn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = shufflevector <16 x i8> %1, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   %3 = bitcast <16 x i8> %2 to <8 x i16>
# |   %4 = shufflevector <8 x i16> %0, <8 x i16> %3, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %5 = trunc <16 x i16> %4 to <16 x i8>
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = shufflevector <8 x i16> %1, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   %3 = bitcast <8 x i16> %2 to <4 x i32>
# |   %4 = shufflevector <4 x i32> %0, <4 x i32> %3, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %5 = trunc <8 x i32> %4 to <8 x i16>
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = shufflevector <16 x i8> %1, <16 x i8> poison, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
# |   %3 = bitcast <16 x i8> %2 to <8 x i16>
# |   %4 = shufflevector <8 x i16> %0, <8 x i16> %3, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %5 = trunc <16 x i16> %4 to <16 x i8>
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load <8 x i16>, ptr %a.addr, align 8
# |   %2 = shufflevector <8 x i16> %1, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
# |   %3 = bitcast <8 x i16> %2 to <4 x i32>
# |   %4 = shufflevector <4 x i32> %0, <4 x i32> %3, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %5 = trunc <8 x i32> %4 to <8 x i16>
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %4 = trunc <16 x i16> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x i32>
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %4 = trunc <8 x i32> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   %4 = trunc <16 x i16> %3 to <16 x i8>
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovntq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <4 x i32>
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
# |   %4 = trunc <8 x i32> %3 to <8 x i16>
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, a
# | ...
# `---data was truncated (10240/13410) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ffc6ad415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ffc6ad10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ffc6ad489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa71c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa71c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa71c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa71c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffc6a69e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ffc6a69c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ffc6a4eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ffc66fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ffc66fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa71c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa71c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa71c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffc66fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c (1514 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/96919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555eef0e615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555eef0e30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555eef0e689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83b6905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83b695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83b6905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83b68ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555eef07be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555eef07bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555eef060b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555eeed100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555eeed0fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f83b68eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83b68ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83b68ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555eeed0fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c (1515 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571b3a8515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005571b3a820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005571b3a8589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed05305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed0535c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed05305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed052ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571b3a1ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005571b3a1ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005571b39ffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005571b36af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005571b36aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fed052eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed052ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed052ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571b36aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c (1516 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b44a8e715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b44a8e40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b44a8e789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fc7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fc7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fc7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fc7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b44a87ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b44a87cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b44a861b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b44a5110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b44a510dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2fc7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fc7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fc7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b44a510cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c (1517 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrem.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vrem_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056491f48715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056491f4840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056491f48789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbb5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbb558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbb5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbb551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056491f41ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056491f41cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056491f401b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056491f0b10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056491f0b0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcbb551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbb551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbb551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056491f0b0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c (1518 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2,
# | ...
# `---data was truncated (10240/65194) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590f3fbc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005590f3fb90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005590f3fbc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9acaf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9acaf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9acaf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9acaeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590f3f51e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005590f3f51c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005590f3f36b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005590f3be60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005590f3be5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9acaeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9acaeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9acaeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590f3be5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c (1519 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32, i32, i32, i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32, i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_u16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 1, i32 0, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_u32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 1, i32 0, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaxq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 1, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaxq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 1, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldaxvaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <8 x i16>, ptr %b.addr, align 8
# |   %5 = load <8 x i16>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 1, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaxq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load <4 x i32>, ptr %b.addr, align 8
# |   %5 = load <4 x i32>, ptr %c.addr, align 8
# |   %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 1, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vrmlaldavhaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, al
# | ...
# `---data was truncated (10240/58468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055b51060815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b5106050f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b51060889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab05249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab052a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab05249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab05231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b51059de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b51059dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b510582b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b5102320b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b510231dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fab05232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab052330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab052330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b510231cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c (1520 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555609c7015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555609c6d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555609c7089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb4da933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4da98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb4da933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb4da91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555609c05e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555609c05c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555609beab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055560989a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555609899dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb4da91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4da91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4da91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555609899cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c (1521 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x
# | ...
# `---data was truncated (10240/123663) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056074746c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005607474690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056074746c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25e3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25e3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25e3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25e3a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560747401e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560747401c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005607473e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005607470960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560747095dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f25e3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25e3a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25e3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560747095cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c (1522 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005635098d115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005635098ce0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005635098d189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21a2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21a24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21a2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21a2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563509866e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563509866c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056350984bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005635094fb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005635094fadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f21a2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21a24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21a24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635094facc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c (1523 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsll_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsll_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsll_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsll.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsll_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsll.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsll_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsll.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsll_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 
# | ...
# `---data was truncated (10240/176543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620de77515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005620de7720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005620de77589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f17849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f178a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f17849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f17831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620de70ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005620de70ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005620de6efb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005620de39f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005620de39edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2f17832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f178330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f178330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620de39ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c (1524 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i
# | ...
# `---data was truncated (10240/306017) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627f772b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005627f77280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005627f772b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ab8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ab8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ab8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ab8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627f76c0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005627f76c0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005627f76a5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005627f73550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005627f7354dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2ab8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ab8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ab8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627f7354cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c (1525 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, <vscale x 8 x i16> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load <vscale x 8 x i16>, ptr %op2.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_n_bf16_z(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = select <vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> zeroinitializer
# |   %5 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %4, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_n_bf16_m(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x bfloat> @test_svscale_n_bf16_x(<vscale x 16 x i1> %pg, <vscale x 8 x bfloat> %op1, i16 noundef %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 16
# |   %op2.addr = alloca i16, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 16
# |   store i16 %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 16
# |   %2 = load i16, ptr %op2.addr, align 2
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %.splatinsert = insertelement <vscale x 8 x i16> poison, i16 %2, i64 0
# |   %.splat = shufflevector <vscale x 8 x i16> %.splatinsert, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
# |   %4 = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fscale.nxv8bf16(<vscale x 8 x i1> %3, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %.splat)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-bfscale" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556a1c17015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556a1c16d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556a1c17089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f53e8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53e86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f53e8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f53e8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a1c105e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556a1c105c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556a1c0eab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556a1bd9a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556a1bd99dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f53e8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53e86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53e86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a1bd99cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c (1526 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/223367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056213e07015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056213e06d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056213e07089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14b4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14b4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14b4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14b4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056213e005e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056213e005c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056213dfeab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056213dc9a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056213dc99dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f14b4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14b4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14b4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056213dc99cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c (1527 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056377ab4b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056377ab480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056377ab4b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5980b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5980b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5980b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5980b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056377aae0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056377aae0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056377aac5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056377a7750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056377a774dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5980b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5980b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5980b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056377a774cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c (1528 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = allo
# | ...
# `---data was truncated (10240/154609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca2bcea15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ca2bce70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ca2bcea89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe83941bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8394725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe83941ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe839403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca2bc7fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ca2bc7fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ca2bc64b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ca2b9140b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ca2b913dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe839404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8394050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8394050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca2b913cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c (1529 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560453c6e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560453c6b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560453c6e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56dd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56dd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56dd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56dd51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560453c03e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560453c03c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560453be8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005604538980b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560453897dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f56dd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56dd51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56dd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560453897cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c (1530 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee7e6f315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ee7e6f00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ee7e6f389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2838f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2838f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2838f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2838f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee7e688e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ee7e688c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ee7e66db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ee7e31d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ee7e31cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2838f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2838f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2838f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee7e31ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminvq.c (1531 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminvq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i8 @test_vminvq_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v16i8(i32 %1, <16 x i8> %2, i32 0)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minv.v16i8(i32, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i16 @test_vminvq_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v8i16(i32 %1, <8 x i16> %2, i32 0)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minv.v8i16(i32, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vminvq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.minv.v4i32(i32 %0, <4 x i32> %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minv.v4i32(i32, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vminvq_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v16i8(i32 %1, <16 x i8> %2, i32 1)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vminvq_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minv.v8i16(i32 %1, <8 x i16> %2, i32 1)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vminvq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.minv.v4i32(i32 %0, <4 x i32> %1, i32 1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i8 @test_vmaxvq_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v16i8(i32 %1, <16 x i8> %2, i32 0)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxv.v16i8(i32, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i16 @test_vmaxvq_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v8i16(i32 %1, <8 x i16> %2, i32 0)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxv.v8i16(i32, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmaxvq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.maxv.v4i32(i32 %0, <4 x i32> %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxv.v4i32(i32, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vmaxvq_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v16i8(i32 %1, <16 x i8> %2, i32 1)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vmaxvq_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxv.v8i16(i32 %1, <8 x i16> %2, i32 1)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmaxvq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.maxv.v4i32(i32 %0, <4 x i32> %1, i32 1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vminavq_s8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minav.v16i8(i32 %1, <16 x i8> %2)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minav.v16i8(i32, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vminavq_s16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.minav.v8i16(i32 %1, <8 x i16> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minav.v8i16(i32, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vminavq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.arm.mve.minav.v4i32(i32 %0, <4 x i32> %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.minav.v4i32(i32, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vmaxavq_s8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load i8, ptr %a.addr, align 1
# |   %1 = zext i8 %0 to i32
# |   %2 = load <16 x i8>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxav.v16i8(i32 %1, <16 x i8> %2)
# |   %4 = trunc i32 %3 to i8
# |   ret i8 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.maxav.v16i8(i32, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vmaxavq_s16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load i16, ptr %a.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = load <8 x i16>, ptr %b.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.maxav.v8i16(i32 %1, <8 x i16> %2)
# |   %4 = trunc i32 %3 to i16
# |   ret i16 
# | ...
# `---data was truncated (10240/39417) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055751f5f115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055751f5ee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055751f5f189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55a8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55a86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55a8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55a8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055751f586e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055751f586c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055751f56bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055751f21b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055751f21add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f55a8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55a86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55a86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055751f21acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c (1532 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 
# | ...
# `---data was truncated (10240/12015) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e0703415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557e070310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557e0703489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff15249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff152a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff15249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff15231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e06fc9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557e06fc9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557e06faeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557e06c5e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557e06c5ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007eff15232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff152330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff152330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e06c5dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c (1533 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_f32m1x2_tu(target("riscv
# | ...
# `---data was truncated (10240/295533) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056401d3c815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056401d3c50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056401d3c889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11cd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11cd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11cd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11cd11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056401d35de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056401d35dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056401d342b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056401cff20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056401cff1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f11cd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11cd11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11cd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056401cff1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c (1534 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_u8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583f951815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005583f95150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005583f951889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0311f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0311f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0311f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0311f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583f94ade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005583f94adc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005583f9492b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005583f91420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005583f9141dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0311f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0311f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0311f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583f9141cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c (1535 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @
# | ...
# `---data was truncated (10240/23479) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056062badf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056062badc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056062badf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f447861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44786725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f447861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4478603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056062ba74e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056062ba74c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056062ba59b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056062b7090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056062b708dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4478604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44786050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44786050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056062b708cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c (1536 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstrid
# | ...
# `---data was truncated (10240/17118) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a177f5d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a177f5a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a177f5d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f7ea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f7ea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f7ea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f7ea03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a177ef2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a177ef2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a177ed7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a177b870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a177b86dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3f7ea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f7ea050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f7ea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a177b86cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c (1537 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558dec07615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558dec0730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558dec07689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe400449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4004a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe400449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe400431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558dec00be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558dec00bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558debff0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558debca00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558debc9fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe400432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4004330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4004330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558debc9fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c (1538 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b13f5e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558b13f5b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558b13f5e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a64f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a64f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a64f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a64f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b13ef3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558b13ef3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558b13ed8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558b13b880b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558b13b87dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7a64f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a64f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a64f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b13b87cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c (1539 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b41e9215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564b41e8f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564b41e9289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e46533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e4658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e46533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e4651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b41e27e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564b41e27c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564b41e0cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564b41abc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564b41abbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8e4651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e4651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e4651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b41abbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c (1540 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ce1caa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556ce1ca70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556ce1caa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff6f1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6f138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff6f1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6f131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ce1c3fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556ce1c3fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556ce1c24b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556ce18d40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556ce18d3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff6f131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6f131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6f131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ce18d3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c (1541 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target
# | ...
# `---data was truncated (10240/10700) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c4ba6b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559c4ba680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559c4ba6b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52a3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52a3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52a3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52a3d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c4ba00e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559c4ba00c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559c4b9e5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559c4b6950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559c4b694dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f52a3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52a3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52a3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c4b694cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c (1542 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_u8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vncvt_x_x_w_i16mf4(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i32>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vncvt_x_x_w_i16mf2(<vscale x 2 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64(<vscale x 2 x i16> poison, <v
# | ...
# `---data was truncated (10240/50890) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6828cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e6828cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e6828cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7038505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f703855c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7038505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70384ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e682864e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e682864c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e682849b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e6824f90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e6824f8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f70384eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70384ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70384ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6824f8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c (1543 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb586d315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fb586d00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fb586d389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f11ab449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11ab4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f11ab449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f11ab431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb58668e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fb58668c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fb5864db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fb582fd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fb582fcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f11ab432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11ab4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11ab4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb582fccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c (1544 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfs
# | ...
# `---data was truncated (10240/65574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef3799615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ef379930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ef3799689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff116c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff116ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff116c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff116c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef3792be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ef3792bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ef37910b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ef375c00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ef375bfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff116c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff116c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff116c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef375bfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c (1545 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c15db5315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c15db500f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c15db5389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5ed249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5ed2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5ed249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5ed231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c15dae8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c15dae8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c15dacdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c15d77d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c15d77cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb5ed232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5ed2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5ed2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c15d77ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c (1546 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale 
# | ...
# `---data was truncated (10240/13048) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055699234e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055699234b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055699234e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe53d105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe53d15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe53d105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe53d0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569922e3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005569922e3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005569922c8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556991f780b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556991f77dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe53d0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe53d0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe53d0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556991f77cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c (1547 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrbit_s8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrbit_s16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrbit_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrbit_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrbit_u8_z(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %2 = call <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %0, <vscale x 16 x i8> %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrbit_u16_z(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %2 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %2, <vscale x 8 x i16> %1)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrbit_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrbit_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.rbit.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i8> @test_svrbit_s8_m(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 16 x i8>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 16 x i8>, align 16
# |   store <vscale x 16 x i8> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i8> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i8>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 16 x i8>, ptr %op.addr, align 16
# |   %3 = call <vscale x 16 x i8> @llvm.aarch64.sve.rbit.nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, <vscale x 16 x i8> %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 8 x i16> @test_svrbit_s16_m(<vscale x 8 x i16> %inactive, <vscale x 16 x i1> %pg, <vscale x 8 x i16> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 8 x i16>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 8 x i16>, align 16
# |   store <vscale x 8 x i16> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 8 x i16> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 8 x i16>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %op.addr, align 16
# |   %3 = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 8 x i16> @llvm.aarch64.sve.rbit.nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %3, <vscale x 8 x i16> %2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrbit_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x
# | ...
# `---data was truncated (10240/21349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005622b3e6d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005622b3e6a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005622b3e6d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd6bbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6bbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd6bbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6bbf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622b3e02e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005622b3e02c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005622b3de7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005622b3a970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005622b3a96dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd6bbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6bbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6bbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622b3a96cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c (1548 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local t
# | ...
# `---data was truncated (10240/36031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e8ade815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555e8ade50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555e8ade889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6ac849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6ac8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6ac849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6ac831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e8ad7de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555e8ad7dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555e8ad62b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555e8aa120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555e8aa11dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb6ac832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6ac8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6ac8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e8aa11cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c (1549 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056517791d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056517791a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056517791d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd81e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd81e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd81e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd81e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005651778b2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005651778b2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565177897b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005651775470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000565177546dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd81e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd81e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd81e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565177546cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c (1550 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vsc
# | ...
# `---data was truncated (10240/53446) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607ee9e315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005607ee9e00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005607ee9e389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ecb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ecb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ecb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ecb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607ee978e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005607ee978c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005607ee95db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005607ee60d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005607ee60cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0ecb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ecb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ecb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607ee60ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c (1551 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2e
# | ...
# `---data was truncated (10240/253148) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bfb9d115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555bfb9ce0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555bfb9d189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12bfa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12bfaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12bfa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12bfa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bfb966e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555bfb966c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555bfb94bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555bfb5fb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555bfb5fadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f12bfa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12bfa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12bfa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bfb5facc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c (1552 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16_v_f16mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16_v_f16mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16_v_f16m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16_v_f16m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16_v_f16m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16_v_f16m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_i16mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_i16mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16_v_i16m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16_v_i16m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vle16_v_i16m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16.p0.i64(<vscale x 16 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vle16_v_i16m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.p0.i64(<vscale x 32 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.p0.i64(<vscale x 32 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16_v_u16mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16_v_u16mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_v
# | ...
# `---data was truncated (10240/29273) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6cd1fe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b6cd1fb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b6cd1fe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1538e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1538ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1538e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1538e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6cd193e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b6cd193c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b6cd178b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b6cce280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b6cce27dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1538e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1538e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1538e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6cce27cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c (1553 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16.nx
# | ...
# `---data was truncated (10240/90875) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a5753715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557a575340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557a5753789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4e4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4e42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4e4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4e4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a574cce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557a574ccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557a574b1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557a571610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557a57160dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc4e4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4e42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4e42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a57160cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c (1554 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005608765a015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056087659d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005608765a089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4475705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f447575c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4475705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44756ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560876535e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560876535c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056087651ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005608761ca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005608761c9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f44756eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44756ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44756ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608761c9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c (1555 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c63039715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c6303940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c63039789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31faf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31faf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31faf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31faf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c63032ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c63032cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c630311b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c62ffc10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c62ffc0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f31faf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31faf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31faf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c62ffc0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c (1556 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055645702515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005564570220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055645702589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f2ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f2ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f2ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f2ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556456fbae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556456fbac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556456f9fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556456c4f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556456c4edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0f2ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f2ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f2ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556456c4ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c (1557 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssubu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssubu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssubu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssubu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssubu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssubu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssubu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/98179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2aebf915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f2aebf60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f2aebf989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f056ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f056baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f056ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f056ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2aeb8ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f2aeb8ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f2aeb73b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f2ae8230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f2ae822dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f056ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f056ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f056ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2ae822cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c (1558 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055860a32c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055860a3290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055860a32c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e65333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e6538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e65333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e6531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055860a2c1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055860a2c1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055860a2a6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558609f560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558609f55dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2e6531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e6531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e6531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558609f55cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c (1559 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, al
# | ...
# `---data was truncated (10240/81312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f683aa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559f683a70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559f683aa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2829f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2829f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2829f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2829eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f6833fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559f6833fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559f68324b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559f67fd40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559f67fd3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2829eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2829eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2829eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f67fd3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c (1560 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vghsh_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vghsh_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vghsh_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vghsh_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vghsh_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055833795f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055833795c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055833795f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff86a905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff86a95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff86a905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff86a8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583378f4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005583378f4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005583378d9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005583375890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558337588dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff86a8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff86a8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff86a8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558337588cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c (1561 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055add03c915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055add03c60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055add03c989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29fe733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29fe78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29fe733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29fe71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055add035ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055add035ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055add0343b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055adcfff30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055adcfff2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f29fe71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29fe71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29fe71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055adcfff2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c (1562 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4ecd0915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f4ecd060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f4ecd0989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0c9705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0c975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0c9705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0c96ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4ecc9ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f4ecc9ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f4ecc83b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f4ec9330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f4ec932dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc0c96eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0c96ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0c96ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4ec932cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c (1563 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d3c2b1715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d3c2b140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d3c2b1789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9973049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99730a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9973049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9973031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3c2aace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d3c2aacc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d3c2a91b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d3c27410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d3c2740dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9973032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99730330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99730330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3c2740cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c (1564 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nof
# | ...
# `---data was truncated (10240/11966) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3445a415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b3445a10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b3445a489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0626333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f062638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0626333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f062631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b344539e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b344539c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b34451eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b3441ce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b3441cddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f062631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f062631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f062631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3441cdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c (1565 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noin
# | ...
# `---data was truncated (10240/25042) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557acdc2215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557acdc1f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557acdc2289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12b0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12b0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12b0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12b0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557acdbb7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557acdbb7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557acdb9cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557acd84c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557acd84bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f12b0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12b0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12b0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557acd84bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c (1566 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005582e203b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005582e20380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005582e203b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a05d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a05d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a05d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a05d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005582e1fd0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005582e1fd0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005582e1fb5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005582e1c650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005582e1c64dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1a05d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a05d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a05d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582e1c64cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c (1567 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055587ceaa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055587cea70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055587ceaa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fd3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fd338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fd3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fd331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055587ce3fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055587ce3fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055587ce24b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055587cad40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055587cad3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0fd331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fd331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fd331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055587cad3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c (1568 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c5450615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563c545030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563c5450689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f54733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f5478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f54733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f5471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c5449be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563c5449bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563c54480b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563c541300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563c5412fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0f5471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f5471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f5471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c5412fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c (1569 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/96919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e617d8015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e617d7d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e617d8089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe0ea733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0ea78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe0ea733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0ea71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e617d15e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e617d15c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e617cfab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e6179aa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e6179a9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe0ea71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0ea71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0ea71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6179a9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c (1570 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/40795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e89a4c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e89a4c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e89a4c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff4e6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4e678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff4e6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff4e671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e89a45ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e89a45ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e89a43fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e89a0ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e89a0eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff4e671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4e671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4e671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e89a0eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c (1571 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584d125b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005584d12580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005584d125b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87aa849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87aa8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87aa849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87aa831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584d11f0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005584d11f0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005584d11d5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005584d0e850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005584d0e84dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f87aa832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87aa8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87aa8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584d0e84cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c (1572 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056345981e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056345981b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056345981e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e44533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e4458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e44533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e4451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005634597b3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005634597b3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563459798b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005634594480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563459447dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7e4451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e4451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e4451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563459447cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c (1573 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056224885715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005622488540f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056224885789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9931505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f993155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9931505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99314ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622487ece2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005622487ecc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005622487d1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005622484810b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562248480dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f99314eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99314ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99314ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562248480cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c (1574 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsaddu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsaddu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/98179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ac033d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562ac033a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562ac033d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23d1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23d1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23d1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23d1c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ac02d2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562ac02d2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562ac02b7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562abff670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562abff66dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f23d1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23d1c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23d1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562abff66cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c (1575 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   s
# | ...
# `---data was truncated (10240/58326) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561de2cdc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561de2cd90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561de2cdc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f889ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f889eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f889ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f889ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561de2c71e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561de2c71c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561de2c56b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561de29060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561de2905dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f889ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f889ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f889ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561de2905cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c (1576 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f8345715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563f834540f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563f8345789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c08333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c0838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c08333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c0831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f833ece2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563f833ecc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563f833d1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563f830810b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563f83080dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3c0831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c0831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c0831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f83080cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c (1577 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8ff_v_i8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8ff_v_u8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8ff_v_u8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8ff_v_u8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d209e2415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d209e210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d209e2489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb0fed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb0fed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb0fed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb0fed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d209db9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d209db9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d209d9eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d209a4e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d209a4ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb0fed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb0fed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb0fed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d209a4dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c (1578 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, p
# | ...
# `---data was truncated (10240/33198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0f561d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e0f561a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e0f561d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa956933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa95698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa956933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa95691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0f55b2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e0f55b2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e0f5597b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e0f52470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e0f5246dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa95691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa95691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa95691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0f5246cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c (1579 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055853a36b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055853a3680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055853a36b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61cc01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61cc0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61cc01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61cc003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055853a300e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055853a300c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055853a2e5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558539f950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558539f94dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f61cc004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61cc0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61cc0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558539f94cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c (1580 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055adcb68515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055adcb6820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055adcb68589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ba2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ba24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ba2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ba2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055adcb61ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055adcb61ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055adcb5ffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055adcb2af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055adcb2aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9ba2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ba24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ba24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055adcb2aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c (1581 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x 
# | ...
# `---data was truncated (10240/134919) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614a7a3815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005614a7a350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005614a7a3889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b29133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b2918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b29133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b2911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614a79cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005614a79cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005614a79b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005614a76620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005614a7661dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7b2911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b2911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b2911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614a7661cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c (1582 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_u64m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64.p0.i64(<vscale x 2 x d
# | ...
# `---data was truncated (10240/19901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559fdc90715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559fdc9040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559fdc90789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd10601bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1060725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd10601ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd106003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fdc89ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559fdc89cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559fdc881b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559fdc5310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559fdc530dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd106004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1060050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1060050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fdc530cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c (1583 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmin.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmin_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c6d7dc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564c6d7d90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564c6d7dc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0dacc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0dacca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0dacc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0dacc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c6d771e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564c6d771c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564c6d756b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564c6d4060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564c6d405dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0dacc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0dacc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0dacc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c6d405cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c (1584 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0d7ee515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d0d7ee20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d0d7ee589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc220733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc22078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc220733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc22071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0d7e7ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d0d7e7ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d0d7e5fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d0d7b0f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d0d7b0edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc22071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc22071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc22071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0d7b0ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c (1585 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557601c9f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557601c9c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557601c9f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feaca649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feaca6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feaca649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feaca631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557601c34e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557601c34c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557601c19b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005576018c90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005576018c8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feaca632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feaca6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feaca6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576018c8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c (1586 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline noun
# | ...
# `---data was truncated (10240/121187) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b055f315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562b055f00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562b055f389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99c5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99c558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99c5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99c551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b05588e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562b05588c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562b0556db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562b0521d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562b0521cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f99c551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99c551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99c551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b0521ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c (1587 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055754433a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005575443370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055754433a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f086dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f086dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f086dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f086dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575442cfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005575442cfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005575442b4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557543f640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557543f63dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f086dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f086dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f086dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557543f63cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c (1588 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9498ca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d9498c70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d9498ca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2155849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21558a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2155849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2155831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d94985fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d94985fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d949844b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d9494f40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d9494f3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2155832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21558330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21558330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9494f3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c (1589 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vs
# | ...
# `---data was truncated (10240/68517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560254bdd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560254bda0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560254bdd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14e6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14e6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14e6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14e6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560254b72e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560254b72c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560254b57b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005602548070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560254806dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f14e6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14e6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14e6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560254806cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c (1590 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_u16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_u16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d39f3915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563d39f360f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563d39f3989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b92049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b920a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b92049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b92031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d39ecee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563d39ecec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563d39eb3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563d39b630b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563d39b62dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0b92032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b920330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b920330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d39b62cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c (1591 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscal
# | ...
# `---data was truncated (10240/29510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588fce8315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005588fce800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005588fce8389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5e5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5e5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5e5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5e5d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588fce18e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005588fce18c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005588fcdfdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005588fcaad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005588fcaacdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe5e5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5e5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5e5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588fcaaccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c (1592 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dac455215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dac454f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dac455289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa1da533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1da58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa1da533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa1da51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dac44e7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dac44e7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dac44ccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dac417c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dac417bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa1da51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1da51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1da51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dac417bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c (1593 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc3e84b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dc3e8480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dc3e84b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fd0905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fd095c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fd0905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fd08ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc3e7e0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dc3e7e0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dc3e7c5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dc3e4750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dc3e474dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2fd08eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fd08ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fd08ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc3e474cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c (1594 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/205805) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a1dbbc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560a1dbb90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560a1dbbc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb511c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb511ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb511c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb511c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a1db51e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560a1db51c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560a1db36b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560a1d7e60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560a1d7e5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb511c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb511c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb511c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a1d7e5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c (1595 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv
# | ...
# `---data was truncated (10240/75133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f8b79a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559f8b7970f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559f8b79a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f038d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f038d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f038d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f038d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f8b72fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559f8b72fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559f8b714b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559f8b3c40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559f8b3c3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f038d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f038d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f038d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f8b3c3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c (1596 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vx_u16m4(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/68133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e4cfc215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555e4cfbf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555e4cfc289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f238441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23844725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f238441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2384403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e4cf57e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555e4cf57c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555e4cf3cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555e4cbec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555e4cbebdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2384404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23844050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23844050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e4cbebcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c (1597 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +f16f32dot -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +f16f32dot -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vdot_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   %1 = load <4 x half>, ptr %a.addr, align 8
# |   %2 = load <4 x half>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vdot1.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vdot2.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vdot3.i = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot.i, <4 x half> %vdot1.i, <4 x half> %vdot2.i)
# |   store <2 x float> %vdot3.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vdotq_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vdot1.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vdot2.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vdot3.i = call <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float> %vdot.i, <8 x half> %vdot1.i, <8 x half> %vdot2.i)
# |   store <4 x float> %vdot3.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vdot_lane_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> zeroinitializer
# |   %vdot = bitcast <8 x i8> %3 to <2 x float>
# |   %vdot1 = bitcast <8 x i8> %4 to <4 x half>
# |   %vdot2 = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot, <4 x half> %vdot1, <4 x half> %lane)
# |   store <2 x float> %vdot2, ptr %ref.tmp, align 8
# |   %7 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %7, ptr %__ret, align 8
# |   %8 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %8, ptr %tmp, align 8
# |   %9 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float>, <4 x half>, <4 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vdot_laneq_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <2 x float>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <2 x float>, align 8
# |   %__s0 = alloca <2 x float>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x float>, align 8
# |   store <2 x float> %r, ptr %r.addr, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <2 x float>, ptr %r.addr, align 8
# |   store <2 x float> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <16 x i8> %5 to <8 x half>
# |   %lane = shufflevector <8 x half> %6, <8 x half> %6, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   %vdot = bitcast <8 x i8> %3 to <2 x float>
# |   %vdot1 = bitcast <8 x i8> %4 to <4 x half>
# |   %vdot2 = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot, <4 x half> %vdot1, <4 x half> %lane)
# |   store <2 x float> %vdot2, ptr %ref.tmp, align 8
# |   %7 = load <2 x float>, ptr %ref.tmp, align 8
# |   store <2 x float> %7, ptr %__ret, align 8
# |   %8 = load <2 x float>, ptr %__ret, align 8
# |   store <2 x float> %8, ptr %tmp, align 8
# |   %9 = load <2 x float>, ptr %tmp, align 8
# |   ret <2 x float> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vdotq_lane_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <4 x float>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   store <4 x float> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <8 x i32> zeroinitializer
# |   %vdot = bitcast <16 x i8> %3 to <4 x float>
# |   %vdot1 = bitcast <16 x i8> %4 to <8 x half>
# |   %vdot2 = call <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float> %vdot, <8 x half> %vdot1, <8 x half> %lane)
# |   store <4 x float> %vdot2, ptr %ref.tmp, align 16
# |   %7 = load <4 x float>, ptr %ref.tmp, align 16
# |   store <4 x float> %7, ptr %__ret, align 16
# |   %8 = load <4 x float>, ptr %__ret, align 16
# |   store <4 x float> %8, ptr %tmp, align 16
# |   %9 = load <4 x float>, ptr %tmp, align 16
# |   ret <4 x float> %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vdotq_laneq_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %r.addr = alloca <4 x float>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %__ret = alloca <4 x float>, align 16
# |   %__s0 = alloca <4 x float>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <4 x float>, align 16
# |   store <4 x float> %r, ptr %r.addr, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   %0 = load <4 x float>, ptr %r.addr, align 16
# |   store <4 x float> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %1, ptr %__s1, align 16
# |   %2 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %2, ptr %__s2, align 16
# |   %3 = load <16 x i8>, ptr %__s0, align 16
# |   %4 = load <16 x i8>, ptr %__s1, align 16
# |   %5 = load <16 x i8>, ptr %__s2, align 16
# |   %6 = bitcast <16 x i8> %5 to <8 x half>
# |   %lane = shufflevector <8 x half> %6, <8 x half> %6, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   %vdot = bitcast <16 x i8> %3 to <4 x float>
# |   %vdot1 = bitcast <16 x i8> %4 to <8 x half>
# |   %vdot2 = call <4 x float> @llvm.aa
# | ...
# `---data was truncated (10240/11256) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine
# |  #0 0x000055887d39715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055887d3940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055887d39789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f17c9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17c9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f17c9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17c9c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055887d32ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055887d32cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055887d311b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055887cfc10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055887cfc0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f17c9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17c9c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17c9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055887cfc0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c (1598 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.ris
# | ...
# `---data was truncated (10240/12914) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645b38ba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005645b38b70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005645b38ba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f034c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f034c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f034c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f034c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645b384fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005645b384fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005645b3834b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005645b34e40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005645b34e3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f034c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f034c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f034c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645b34e3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulq.c (1599 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = mul <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = mul <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = mul <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmulq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = fmul <4 x float> %0, %1
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmulq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x half>, ptr %inactive.addr, align 8
# |   %6 = call <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmulq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.mul.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> undef)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.m
# | ...
# `---data was truncated (10240/21288) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055eb6ca9d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eb6ca9a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eb6ca9d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62faa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62faaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62faa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62faa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb6ca32e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eb6ca32c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eb6ca17b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eb6c6c70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eb6c6c6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f62faa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62faa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62faa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb6c6c6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c (1600 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, al
# | ...
# `---data was truncated (10240/128416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645505a715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005645505a40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005645505a789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d94e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d94ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d94e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d94e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056455053ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056455053cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564550521b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005645501d10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005645501d0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9d94e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d94e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d94e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645501d0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c (1601 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x flo
# | ...
# `---data was truncated (10240/51759) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f2a7cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555f2a7c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555f2a7cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc664933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc66498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc664933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc66491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f2a760e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555f2a760c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555f2a745b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555f2a3f50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555f2a3f4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc66491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc66491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc66491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f2a3f4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c (1602 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vset_v_bf16m1_bf16m2(<vscale x 8 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m1_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m2_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m1_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m2_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m4_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vset_v_bf16mf4_bf16mf4x2(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vset_v_bf16mf4_bf16mf4x3(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vset_v_bf16mf4_bf16mf4x4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/41651) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620cb23e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005620cb23b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005620cb23e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb467049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4670a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb467049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb467031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620cb1d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005620cb1d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005620cb1b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005620cae680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005620cae67dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb467032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4670330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4670330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620cae67cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c (1603 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c19f82915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c19f8260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c19f82989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbbc1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbbc178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbbc1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbbc171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c19f7bee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c19f7bec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c19f7a3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c19f4530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c19f452dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbbc171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbbc171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbbc171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c19f452cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c (1604 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056505ad9615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056505ad930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056505ad9689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe176449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1764a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe176449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe176431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056505ad2be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056505ad2bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056505ad10b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056505a9c00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056505a9bfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe176432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1764330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1764330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056505a9bfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c (1605 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592a40fa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005592a40f70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005592a40fa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ddba1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ddba725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ddba1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ddba03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592a408fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005592a408fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005592a4074b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005592a3d240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005592a3d23dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4ddba04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ddba050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ddba050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592a3d23cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c (1606 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_u32m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry
# | ...
# `---data was truncated (10240/14002) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5dacac15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c5daca90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c5dacac89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ed7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ed7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ed7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ed7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5dac41e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c5dac41c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c5dac26b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c5da8d60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c5da8d5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3ed7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ed7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ed7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5da8d5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm_acle_swp.c (1607 of 27911)
******************** TEST 'Clang :: CodeGen/arm_acle_swp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple thumbv7m-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple thumbv7m-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv7m-unknown-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_swp(i32 noundef %x, ptr noundef %p) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__p.addr.i = alloca ptr, align 4
# |   %__v.i = alloca i32, align 4
# |   %.atomictmp.i = alloca i32, align 4
# |   %atomic-temp.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %p.addr = alloca ptr, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store ptr %p, ptr %p.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load ptr, ptr %p.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store ptr %1, ptr %__p.addr.i, align 4
# |   %2 = load ptr, ptr %__p.addr.i, align 4
# |   %3 = load i32, ptr %__x.addr.i, align 4
# |   store i32 %3, ptr %.atomictmp.i, align 4
# |   %4 = load i32, ptr %.atomictmp.i, align 4
# |   %5 = atomicrmw volatile xchg ptr %2, i32 %4 monotonic, align 4
# |   store i32 %5, ptr %atomic-temp.i, align 4
# |   %6 = load i32, ptr %atomic-temp.i, align 4
# |   store i32 %6, ptr %__v.i, align 4
# |   %7 = load i32, ptr %__v.i, align 4
# |   ret i32 %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv7-m,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !3 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a7805515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564a780520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564a7805589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f769f905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f769f95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f769f905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f769f8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a77feae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564a77feac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564a77fcfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564a77c7f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564a77c7edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f769f8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f769f8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f769f8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a77c7ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/builtins-arm64.c (1608 of 27911)
******************** TEST 'Clang :: CodeGen/builtins-arm64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-unknown-linux"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @f0(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load ptr, ptr %b.addr, align 8
# |   call void @llvm.clear_cache.p0(ptr %0, ptr %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.clear_cache.p0(ptr, ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @tp() #0 {
# | entry:
# |   %0 = call ptr @llvm.thread.pointer.p0()
# |   ret ptr %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare ptr @llvm.thread.pointer.p0() #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rbit(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %rbit = call i32 @llvm.bitreverse.i32(i32 %0)
# |   ret i32 %rbit
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.bitreverse.i32(i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @rbitl(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %rbit = call i64 @llvm.bitreverse.i64(i64 %0)
# |   ret i64 %rbit
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.bitreverse.i64(i64) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @rbit64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %rbit = call i64 @llvm.bitreverse.i64(i64 %0)
# |   ret i64 %rbit
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @hints() #0 {
# | entry:
# |   call void @llvm.aarch64.hint(i32 0)
# |   call void @llvm.aarch64.hint(i32 1)
# |   call void @llvm.aarch64.hint(i32 2)
# |   call void @llvm.aarch64.hint(i32 3)
# |   call void @llvm.aarch64.hint(i32 4)
# |   call void @llvm.aarch64.hint(i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.aarch64.hint(i32) #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @barriers() #0 {
# | entry:
# |   call void @llvm.aarch64.dmb(i32 1)
# |   call void @llvm.aarch64.dsb(i32 2)
# |   call void @llvm.aarch64.isb(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nofree nounwind willreturn
# | declare void @llvm.aarch64.dmb(i32) #5
# | 
# | ; Function Attrs: nofree nounwind willreturn
# | declare void @llvm.aarch64.dsb(i32) #5
# | 
# | ; Function Attrs: nofree nounwind willreturn
# | declare void @llvm.aarch64.isb(i32) #5
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @prefetch() #0 {
# | entry:
# |   call void @llvm.aarch64.prefetch(ptr null, i32 1, i32 2, i32 0, i32 1)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 0, i32 0)
# |   call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 3, i32 0, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.prefetch(ptr readonly, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #6
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @range_prefetch() #0 {
# | entry:
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 1, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 1, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.range.prefetch(ptr readonly, i32 immarg, i32 immarg, i64) #6
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @range_prefetch_x() #0 {
# | entry:
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 1, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 0, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 1, i64 0)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 576460752305520640)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 576460752301326335)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -1152921504606846976)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -2305843009213693952)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -6917529027641081856)
# |   call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @read_intent_prefetch() #0 {
# | entry:
# |   call void @llvm.aarch64.prefetch.ir(ptr null)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.aarch64.prefetch.ir(ptr readonly) #6
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @jcvt(double noundef %v) #7 {
# | entry:
# |   %v.addr = alloca double, align 8
# |   store double %v, ptr %v.addr, align 8
# |   %0 = load double, ptr %v.addr, align 8
# |   %1 = call i32 @llvm.aarch64.fjcvtzs(double %0)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.fjcvtzs(double) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rsr() #0 {
# | entry:
# |   %0 = call i64 @llvm.read_volatile_register.i64(metadata !7)
# |   %1 = trunc i64 %0 to i32
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i64 @llvm.read_volatile_register.i64(metadata) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @rsr64() #0 {
# | entry:
# |   %0 = call i64 @llvm.read_volatile_register.i64(metadata !7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @rsrp() #0 {
# | entry:
# |   %0 = call i64 @llvm.read_volatile_register.i64(metadata !7)
# |   %1 = inttoptr i64 %0 to ptr
# |   ret ptr %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wsr(i32 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i32, align 4
# |   store i32 %v, ptr %v.addr, align 4
# |   %0 = load i32, ptr %v.addr, align 4
# |   %1 = zext i32 %0 to i64
# |   call void @llvm.write_register.i64(metadata !7, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nounwind
# | declare void @llvm.write_register.i64(metadata, i64) #8
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wsr64(i64 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i64, align 8
# |   store i64 %v, ptr %v.addr, align 8
# |   %0 = load i64, ptr %v.addr, align 8
# |   call void @llvm.write_register.i64(metadata !7, i64 %0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @wsrp(ptr noundef %v) #0 {
# | entry:
# |   %v.addr = alloca ptr, align 8
# |   store ptr %v, ptr %v.addr, align 8
# |   %0 = load ptr, ptr %v.addr, align 8
# |   %1 = ptrtoint ptr %0 to i64
# |   call void @llvm.write_register.i64(metadata !7, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @cls(i32 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i32, align 4
# |   store i32 %v, ptr %v.addr, align 4
# |   %0 = load i32, ptr %v.addr, align 4
# |   %cls = call i32 @llvm.aarch64.cls(i32 %0)
# |   ret i32 %cls
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.cls(i32) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clsl(i64 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i64, align 8
# |   store i64 %v, ptr %v.addr, align 8
# |   %0 = load i64, ptr %v.addr, align 8
# |   %cls = call i32 @llvm.aarch64.cls64(i64 %0)
# |   ret i32 %cls
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.cls64(i64) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clsll(i64 noundef %v) #0 {
# | entry:
# |   %v.addr = alloca i64, align 8
# |   store i64 %v, ptr %v.addr, align 8
# |   %0 = load i64, ptr %v.addr, align 8
# |   %cls = call i32 @llvm.aarch64.cls64(i64 %0)
# |   ret i32 %cls
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rndr(ptr noundef %__addr) #9 {
# | entry:
# |   %__addr.addr = alloca ptr, align 8
# |   store ptr %__addr, ptr %__addr.addr, align 8
# |   %0 = call { i64, i1 } @llvm.aarch64.rndr()
# |   %1 = extractvalue { i64, i1 } %0, 0
# |   %2 = extractvalue { i64, i1 } %0, 1
# |   %3 = load ptr, ptr %__addr.addr, align 8
# |   store i64 %1, ptr %3, align 8
# |   %4 = zext i1 %2 to i32
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { i64, i1 } @llvm.aarch64.rndr() #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @rndrrs(ptr noundef %__addr) #9 {
# | entry:
# |   %__addr.addr = alloca ptr, align 8
# |   store ptr %__addr, ptr %__addr.addr, align 8
# |   %0 = call { i64, i1 } @llvm.aarch64.rndrrs()
# |   %1 = extractvalue { i64, i1 } %0, 0
# |   %2 = extractvalue { i64, i1 } %0, 1
# |   %3 = load ptr, ptr %__addr.addr, align 8
# |   store i64 %1, ptr %3, align 8
# |   %4 = zext i1 %2 to i32
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { i64, i1 } @llvm.aarch64.rndrrs() #4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @trap() #0 {
# | entry:
# |   call void @llvm.aarch64.break(i32 42)
# |   ret void
# | }
# | 
# | ; Function Attrs: cold noreturn nounwind
# | declare void @llvm.aarch64.break(i32 immarg) #10
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @atomic_store_with_hint(ptr noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca i64, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store atomic i64 %1, ptr %0 monotonic, align 8, !mem.cache_hint !8
# |   %2 = load ptr, ptr %a.addr, align 8
# |   %3 = load i64, ptr %b.addr, a
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# .---command stderr------------
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:243:3: warning: unrecognised hint type argument to atomic hint operation (5) [-Watomic-hint-type]
# |   243 |   __builtin_arm_atomic_store_with_hint(a, b, __ATOMIC_RELAXED, 5); // Invalid Hint
# |       |   ^                                                            ~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:305:3: warning: unrecognised hint type argument to atomic hint operation (0) [-Watomic-hint-type]
# |   305 |   __builtin_arm_atomic_fetch_add_with_hint(a, b, __ATOMIC_RELAXED, HINT_STSHH_KEEP);
# |       |   ^                                                                ~~~~~~~~~~~~~~~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:306:3: warning: unrecognised hint type argument to atomic hint operation (1) [-Watomic-hint-type]
# |   306 |   __builtin_arm_atomic_fetch_sub_with_hint(a, b, __ATOMIC_RELAXED, HINT_STSHH_STRM);
# |       |   ^                                                                ~~~~~~~~~~~~~~~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:307:3: warning: unrecognised hint type argument to atomic hint operation (2) [-Watomic-hint-type]
# |   307 |   __builtin_arm_atomic_fetch_and_with_hint(a, b, __ATOMIC_RELAXED, HINT_STCPH);
# |       |   ^                                                                ~~~~~~~~~~
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:308:10: warning: unrecognised hint type argument to atomic hint operation (5) [-Watomic-hint-type]
# |   308 |   return __builtin_arm_atomic_fetch_add_with_hint(a, b, __ATOMIC_RELAXED, 5);
# |       |          ^                                                                ~
# | 5 warnings generated.
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005643636e415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005643636e10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005643636e489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0104a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0104aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0104a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0104a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564363679e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564363679c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056436365eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056436330e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056436330ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0104a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0104a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0104a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056436330dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c (1609 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_u8m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_
# | ...
# `---data was truncated (10240/23574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056529eb2315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056529eb200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056529eb2389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5250333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f525038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5250333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f525031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056529eab8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056529eab8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056529ea9db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056529e74d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056529e74cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f525031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f525031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f525031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056529e74ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c (1610 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_i16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_i16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_i16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_i16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_i16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_i16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_u16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_u16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_u16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_u16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_u16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_u16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_i16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_i16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_i16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_i16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_i16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 to <vscale x 16 x i16>
# |   ret <vscale x 16 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_vreinterpret_v_bf16m8_i16m8(<vscale x 32 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x bfloat> %0 to <vscale x 32 x i16>
# |   ret <vscale x 32 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_u16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_u16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_u16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 
# | ...
# `---data was truncated (10240/11237) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab1f15515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ab1f1520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ab1f15589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fddf5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fddf5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fddf5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fddf5b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab1f0eae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ab1f0eac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ab1f0cfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ab1ed7f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ab1ed7edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fddf5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fddf5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fddf5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab1ed7ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c (1611 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563c476d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005563c476a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005563c476d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffaaf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffaaf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffaaf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffaaf31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563c4702e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005563c4702c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005563c46e7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005563c43970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005563c4396dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ffaaf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffaaf31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffaaf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563c4396cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-neon-vst.c (1612 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-vst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +neon      -target-feature +fp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +neon -target-feature +fp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-none-linux-gnueabi"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x4x3_t = type { [3 x <4 x half>] }
# | %struct.float16x4x4_t = type { [4 x <4 x half>] }
# | %struct.float32x2x2_t = type { [2 x <2 x float>] }
# | %struct.float32x2x3_t = type { [3 x <2 x float>] }
# | %struct.float32x2x4_t = type { [4 x <2 x float>] }
# | %struct.poly16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.poly16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.poly16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.poly8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.poly8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.poly8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.int16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.int16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.int16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.int32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.int32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.int32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.int64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.int64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.int64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.int8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.int8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.int8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.uint16x4x2_t = type { [2 x <4 x i16>] }
# | %struct.uint16x4x3_t = type { [3 x <4 x i16>] }
# | %struct.uint16x4x4_t = type { [4 x <4 x i16>] }
# | %struct.uint32x2x2_t = type { [2 x <2 x i32>] }
# | %struct.uint32x2x3_t = type { [3 x <2 x i32>] }
# | %struct.uint32x2x4_t = type { [4 x <2 x i32>] }
# | %struct.uint64x1x2_t = type { [2 x <1 x i64>] }
# | %struct.uint64x1x3_t = type { [3 x <1 x i64>] }
# | %struct.uint64x1x4_t = type { [4 x <1 x i64>] }
# | %struct.uint8x8x2_t = type { [2 x <8 x i8>] }
# | %struct.uint8x8x3_t = type { [3 x <8 x i8>] }
# | %struct.uint8x8x4_t = type { [4 x <8 x i8>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | %struct.float16x8x3_t = type { [3 x <8 x half>] }
# | %struct.float16x8x4_t = type { [4 x <8 x half>] }
# | %struct.float32x4x2_t = type { [2 x <4 x float>] }
# | %struct.float32x4x3_t = type { [3 x <4 x float>] }
# | %struct.float32x4x4_t = type { [4 x <4 x float>] }
# | %struct.poly16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.poly16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.poly16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.poly8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.poly8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.poly8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.int16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.int16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.int16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.int32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.int32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.int32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.int64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.int64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.int64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.int8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.int8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.int8x16x4_t = type { [4 x <16 x i8>] }
# | %struct.uint16x8x2_t = type { [2 x <8 x i16>] }
# | %struct.uint16x8x3_t = type { [3 x <8 x i16>] }
# | %struct.uint16x8x4_t = type { [4 x <8 x i16>] }
# | %struct.uint32x4x2_t = type { [2 x <4 x i32>] }
# | %struct.uint32x4x3_t = type { [3 x <4 x i32>] }
# | %struct.uint32x4x4_t = type { [4 x <4 x i32>] }
# | %struct.uint64x2x2_t = type { [2 x <2 x i64>] }
# | %struct.uint64x2x3_t = type { [3 x <2 x i64>] }
# | %struct.uint64x2x4_t = type { [4 x <2 x i64>] }
# | %struct.uint8x16x2_t = type { [2 x <16 x i8>] }
# | %struct.uint8x16x3_t = type { [3 x <16 x i8>] }
# | %struct.uint8x16x4_t = type { [4 x <16 x i8>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16_x2(ptr noundef %a, [2 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float16x4x2_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float16x4x2_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %b, i32 0, i32 0
# |   store [2 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 16, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <4 x half>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [2 x <4 x half>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %3 = bitcast <8 x i8> %1 to <4 x i16>
# |   %4 = bitcast <8 x i8> %2 to <4 x i16>
# |   call void @llvm.arm.neon.vst1x2.p0.v4i16(ptr %0, <4 x i16> %3, <4 x i16> %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i32(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i32, i1 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x2.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16_x3(ptr noundef %a, [3 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float16x4x3_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float16x4x3_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %b, i32 0, i32 0
# |   store [3 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 24, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [3 x <4 x half>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [3 x <4 x half>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %val3 = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx4 = getelementptr inbounds [3 x <4 x half>], ptr %val3, i32 0, i32 2
# |   %3 = load <8 x i8>, ptr %arrayidx4, align 8
# |   %4 = bitcast <8 x i8> %1 to <4 x i16>
# |   %5 = bitcast <8 x i8> %2 to <4 x i16>
# |   %6 = bitcast <8 x i8> %3 to <4 x i16>
# |   call void @llvm.arm.neon.vst1x3.p0.v4i16(ptr %0, <4 x i16> %4, <4 x i16> %5, <4 x i16> %6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x3.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>, <4 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f16_x4(ptr noundef %a, [4 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float16x4x4_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float16x4x4_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %b, i32 0, i32 0
# |   store [4 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 32, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [4 x <4 x half>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [4 x <4 x half>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %val3 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx4 = getelementptr inbounds [4 x <4 x half>], ptr %val3, i32 0, i32 2
# |   %3 = load <8 x i8>, ptr %arrayidx4, align 8
# |   %val5 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx6 = getelementptr inbounds [4 x <4 x half>], ptr %val5, i32 0, i32 3
# |   %4 = load <8 x i8>, ptr %arrayidx6, align 8
# |   %5 = bitcast <8 x i8> %1 to <4 x i16>
# |   %6 = bitcast <8 x i8> %2 to <4 x i16>
# |   %7 = bitcast <8 x i8> %3 to <4 x i16>
# |   %8 = bitcast <8 x i8> %4 to <4 x i16>
# |   call void @llvm.arm.neon.vst1x4.p0.v4i16(ptr %0, <4 x i16> %5, <4 x i16> %6, <4 x i16> %7, <4 x i16> %8)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x4.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f32_x2(ptr noundef %a, [2 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %struct.float32x2x2_t, align 8
# |   %a.addr = alloca ptr, align 4
# |   %__s1 = alloca %struct.float32x2x2_t, align 8
# |   %coerce.dive = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %b, i32 0, i32 0
# |   store [2 x i64] %b.coerce, ptr %coerce.dive, align 8
# |   store ptr %a, ptr %a.addr, align 4
# |   call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 16, i1 false)
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %val = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx = getelementptr inbounds [2 x <2 x float>], ptr %val, i32 0, i32 0
# |   %1 = load <8 x i8>, ptr %arrayidx, align 8
# |   %val1 = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %__s1, i32 0, i32 0
# |   %arrayidx2 = getelementptr inbounds [2 x <2 x float>], ptr %val1, i32 0, i32 1
# |   %2 = load <8 x i8>, ptr %arrayidx2, align 8
# |   %3 = bitcast <8 x i8> %1 to <2 x float>
# |   %4 = bitcast <8 x i8> %2 to <2 x float>
# |   call void @llvm.arm.neon.vst1x2.p0.v2f32(ptr %0, <2 x float> %3, <2 x float> %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.arm.neon.vst1x2.p0.v2f32(ptr captures(none), <2 x float>, <2 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vst1_f32_x3(ptr noundef %a, [3 x i64] %b.coerce) #0 {
# | entry:
# |   %b = alloca %s
# | ...
# `---data was truncated (10240/108866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056055601615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005605560130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056055601689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc06e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc06e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc06e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc06e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560555fabe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560555fabc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560555f90b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560555c400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560555c3fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc06e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc06e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc06e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560555c3fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c (1613 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_f16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_f16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_f16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_i16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_i16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_i16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tu
# | ...
# `---data was truncated (10240/17844) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056471423a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005647142370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056471423a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f87533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f8758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f87533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f8751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647141cfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005647141cfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005647141b4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564713e640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564713e63dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1f8751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f8751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f8751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564713e63cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c (1614 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_vreinterpret_p8_mf8(<8 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vreinterpret_p64_mf8(<8 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <1 x i64>, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__ret.i, align 8
# |   %2 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vreinterpret_p16_mf8(<8 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x i16>, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_p8_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i128 @test_vreinterpretq_p128_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca i128, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load i128, ptr %__p0.addr.i, align 16
# |   store i128 %1, ptr %__ret.i, align 16
# |   %2 = load i128, ptr %__ret.i, align 16
# |   ret i128 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vreinterpretq_p64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vreinterpretq_p16_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_u8_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vreinterpretq_u32_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__ret.i, align 16
# |   %2 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vreinterpretq_u64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vreinterpretq_u16_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x i16>, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_s8_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vreinterpretq_f64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x double>, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vreinterpretq_f32_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x float>, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__ret.i, align 16
# |   %2 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vreinterpretq_f16_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__ret.i, align 16
# |   %2 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vreinterpretq_s32_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <4 x i32>, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__ret.i, align 16
# |   %2 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vreinterpretq_s64_mf8(<16 x i8> %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <2 x i64>, ptr %__p0.addr.i, align 16
# |   store <2 x i64> %1, ptr %__ret.i, align 16
# |   %2 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_mf8_p8(<16 x i8> noundef %v) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <16 x i8>, align 16
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   store <16 x i8> %1, ptr %__ret.i, align 16
# |   %2 = load <16 x i8>, ptr %__ret.i, align 16
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_vreinterpretq_mf8_p128(i128 noundef %v) #0 {
# | entry:
# |   
# | ...
# `---data was truncated (10240/32178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa
# |  #0 0x000055c4a4ada15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c4a4ad70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c4a4ada89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbe9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbe918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbe9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbe911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4a4a6fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c4a4a6fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c4a4a54b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c4a47040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c4a4703dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ffbe911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbe911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbe911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c4a4703cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c (1615 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m8(ptr noundef %base, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | 
# | ...
# `---data was truncated (10240/25279) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609746ed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005609746ea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005609746ed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1136933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f113698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1136933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f113691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560974682e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560974682c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560974667b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005609743170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560974316dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f113691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f113691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f113691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560974316cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c (1616 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649a61e515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005649a61e20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005649a61e589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe4c7f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe4c7f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe4c7f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe4c7eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649a617ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005649a617ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005649a615fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005649a5e0f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005649a5e0edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe4c7eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe4c7eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe4c7eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649a5e0ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c (1617 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6e611815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e6e61150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e6e611889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2904333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f290438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2904333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f290431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6e60ade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e6e60adc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e6e6092b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e6e5d420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e6e5d41dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f290431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f290431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f290431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6e5d41cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c (1618 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3b478315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e3b47800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e3b478389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f582a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f582a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f582a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f582a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3b4718e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e3b4718c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e3b46fdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e3b43ad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e3b43acdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f582a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f582a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f582a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3b43accc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c (1619 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8>, <16 x i8>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16>, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_s8(<16 x i8> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %0, i32 %1, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8>, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_s16(<8 x i16> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %0, i32 %1, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16>, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32>, i32, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_u8(<16 x i8> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %0, i32 %1, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_u16(<8 x i16> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %0, i32 %1, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqshlq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqshlq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqshlq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 0, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqshlq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqshlq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/79071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f18e1aa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f18e1a70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f18e1aa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01d3a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01d3a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01d3a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01d3a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f18e13fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f18e13fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f18e124b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f18ddd40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f18ddd3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f01d3a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01d3a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01d3a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f18ddd3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c (1620 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5696a115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a56969e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a5696a189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ef7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ef758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ef7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ef751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a569636e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a569636c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a56961bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a5692cb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a5692cadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5ef751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ef751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ef751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5692cacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c (1621 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64
# | ...
# `---data was truncated (10240/24373) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e15abe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555e15abb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555e15abe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76dd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76dd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76dd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76dd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e15a53e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555e15a53c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555e15a38b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555e156e80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555e156e7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f76dd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76dd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76dd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e156e7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c (1622 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0471d815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f0471d50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f0471d889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe172a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe172a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe172a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe172a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f04716de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f04716dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f047152b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f046e020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f046e01dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe172a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe172a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe172a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f046e01cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c (1623 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/235596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e3c9e515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564e3c9e20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564e3c9e589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f35f681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f35f68725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f35f681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f35f6803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e3c97ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564e3c97ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564e3c95fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564e3c60f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564e3c60edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f35f6804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f35f68050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f35f68050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e3c60ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c (1624 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/26748) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b2dd7e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560b2dd7b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560b2dd7e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71c8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71c8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71c8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71c8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b2dd13e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560b2dd13c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560b2dcf8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560b2d9a80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560b2d9a7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f71c8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71c8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71c8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b2d9a7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c (1625 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslideup_vx_f16mf4(<vscale x 1 x half> %dest, <vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslideup_vx_f16mf2(<vscale x 2 x half> %dest, <vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslideup_vx_f16m1(<vscale x 4 x half> %dest, <vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslideup_vx_f16m2(<vscale x 8 x half> %dest, <vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslideup_vx_f16m4(<vscale x 16 x half> %dest, <vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslideup_vx_f16m8(<vscale x 32 x half> %dest, <vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslideup_vx_f32mf2(<vscale x 1 x float> %dest, <vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslideup_vx_f32m1(<vscale x 2 x float> %dest, <vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %offset.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslideup_vx_f32m2(<vscale x 4 x float> %dest, <vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store <vscale x 4 x 
# | ...
# `---data was truncated (10240/142016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d76625b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d7662580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d76625b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27f1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27f1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27f1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27f1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7661f0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d7661f0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d7661d5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d765e850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d765e84dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f27f1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27f1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27f1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d765e84cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c (1626 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset4_b_0(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %5, 0
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset4_b_1(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %5, 1
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } @test_svset4_b_3(<vscale x 16 x i1> %tuple.coerce0, <vscale x 16 x i1> %tuple.coerce1, <vscale x 16 x i1> %tuple.coerce2, <vscale x 16 x i1> %tuple.coerce3, <vscale x 16 x i1> %x) #0 {
# | entry:
# |   %tuple = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %tuple.addr = alloca { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, align 2
# |   %x.addr = alloca <vscale x 16 x i1>, align 2
# |   %0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } poison, <vscale x 16 x i1> %tuple.coerce0, 0
# |   %1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %0, <vscale x 16 x i1> %tuple.coerce1, 1
# |   %2 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %1, <vscale x 16 x i1> %tuple.coerce2, 2
# |   %3 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %2, <vscale x 16 x i1> %tuple.coerce3, 3
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %3, ptr %tuple, align 2
# |   %tuple1 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple, align 2
# |   store { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %tuple1, ptr %tuple.addr, align 2
# |   store <vscale x 16 x i1> %x, ptr %x.addr, align 2
# |   %4 = load { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> }, ptr %tuple.addr, align 2
# |   %5 = load <vscale x 16 x i1>, ptr %x.addr, align 2
# |   %6 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %4, <vscale x 16 x i1> %5, 3
# |   ret { <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1> } %6
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x00005564e184415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005564e18410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005564e184489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b68849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b688a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b68849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b68831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564e17d9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005564e17d9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005564e17beb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005564e146e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005564e146ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8b68832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b688330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b688330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564e146dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c (1627 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 0
# |   %7 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret <vscale x 1 x bfloat> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2
# | ...
# `---data was truncated (10240/32198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592607d915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005592607d60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005592607d989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8750449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87504a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8750449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8750431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055926076ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055926076ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559260753b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005592604030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559260402dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8750432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87504330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87504330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559260402cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c (1628 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vror_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = al
# | ...
# `---data was truncated (10240/97675) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559dd04ec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559dd04e90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559dd04ec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8011533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f801158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8011533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f801151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559dd0481e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559dd0481c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559dd0466b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559dd01160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559dd0115dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f801151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f801151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f801151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559dd0115cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c (1629 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.t
# | ...
# `---data was truncated (10240/12089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e295e115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559e295de0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559e295e189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0c8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0c818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0c8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0c811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e29576e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559e29576c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559e2955bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559e2920b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559e2920add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff0c811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0c811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0c811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e2920acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c (1630 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620c243a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005620c24370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005620c243a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3eaed05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3eaed5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3eaed05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3eaeced507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620c23cfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005620c23cfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005620c23b4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005620c20640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005620c2063dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3eaeceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3eaecef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3eaecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620c2063cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c (1631 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056484fbee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056484fbeb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056484fbee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe966d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe966d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe966d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe966ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056484fb83e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056484fb83c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056484fb68b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056484f8180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056484f817dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe966ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe966cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe966cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056484f817cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c (1632 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_s32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_s64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_u32_z(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_u64_z(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_s32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_s64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_u32_m(<vscale x 4 x i32> %inactive, <vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 4 x i32>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 4 x i32> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 4 x i32>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %3 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %3, <vscale x 4 x i32> %2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_u64_m(<vscale x 2 x i64> %inactive, <vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %inactive.addr = alloca <vscale x 2 x i64>, align 16
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 2 x i64> %inactive, ptr %inactive.addr, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 2 x i64>, ptr %inactive.addr, align 16
# |   %1 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %2 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %1)
# |   %4 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %3, <vscale x 2 x i64> %2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_s32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 2 x i64> @test_svrevh_s64_x(<vscale x 16 x i1> %pg, <vscale x 2 x i64> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 2 x i64>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 2 x i64> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 2 x i64>, ptr %op.addr, align 16
# |   %2 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %2, <vscale x 2 x i64> %1)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 4 x i32> @test_svrevh_u32_x(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %op) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op.addr = alloca <vscale x 4 x i32>, align 16
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 4 x i32> %op, ptr %op.addr, align 16
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 4 x i32>, ptr %op.addr, align 16
# |   %2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
# |   %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %2, <vscale x 4 x i32> %1)
# |   
# | ...
# `---data was truncated (10240/11488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim
# |  #0 0x0000556a71cd015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556a71ccd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556a71cd089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff662d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff662d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff662d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff662d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a71c65e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556a71c65c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556a71c4ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556a718fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556a718f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff662d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff662d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff662d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a718f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c (1633 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %o
# | ...
# `---data was truncated (10240/70102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056303c21315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056303c2100f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056303c21389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e79c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e79c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e79c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e79c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056303c1a8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056303c1a8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056303c18db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056303be3d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056303be3cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8e79c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e79c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e79c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056303be3ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c (1634 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_i64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_u64m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(arg
# | ...
# `---data was truncated (10240/20531) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560dc2d8915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560dc2d860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560dc2d8989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02c0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02c058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02c0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02c051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560dc2d1ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560dc2d1ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560dc2d03b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560dc29b30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560dc29b2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f02c051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02c051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02c051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560dc29b2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c (1635 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32, <8 x half>, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32, <4 x float>, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 1, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot180_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 2, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot180_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 2, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 3, <8 x half> %0, <8 x half> %1, <8 x half> %2)
# |   ret <8 x half> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 3, <4 x float> %0, <4 x float> %1, <4 x float> %2)
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load <4 x float>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %c.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store <8 x half> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load <8 x half>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %c.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store <4 x float> %
# | ...
# `---data was truncated (10240/15051) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bea880615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bea88030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bea880689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f973e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f973e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f973e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f973e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bea879be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bea879bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bea8780b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bea84300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bea842fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f973e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f973e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f973e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bea842fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c (1636 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0)
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %2)
# |   %4 = call <8 x half> @llvm.minnum.v8f16(<8 x half> %1, <8 x half> %3)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0)
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2)
# |   %4 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %1, <4 x float> %3)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d50efd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562d50efa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562d50efd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b44b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b44b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b44b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b44b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d50e92e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562d50e92c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562d50e77b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562d50b270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562d50b26dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4b44b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b44b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b44b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d50b26cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c (1637 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b8c0d9215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b8c0d8f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b8c0d9289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42c4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42c418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42c4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42c411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8c0d27e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b8c0d27c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b8c0d0cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b8c09bc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b8c09bbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f42c411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42c411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42c411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b8c09bbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c (1638 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056205687b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005620568780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056205687b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff87fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff87fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff87fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff87fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562056810e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562056810c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005620567f5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005620564a50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005620564a4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff87fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff87fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff87fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620564a4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c (1639 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %v
# | ...
# `---data was truncated (10240/11349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bcccce115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bccccde0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bcccce189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ad9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ad9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ad9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ad9a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bcccc76e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bcccc76c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bcccc5bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bccc90b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bccc90add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4ad9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ad9a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ad9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bccc90acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c (1640 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056115d84d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056115d84a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056115d84d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9081c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9081ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9081c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9081c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056115d7e2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056115d7e2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056115d7c7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056115d4770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056115d476dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9081c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9081c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9081c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056115d476cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c (1641 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b1502315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557b150200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557b1502389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd659333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd65938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd659333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd65931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b14fb8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557b14fb8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557b14f9db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557b14c4d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557b14c4cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd65931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd65931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd65931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b14c4ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c (1642 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vs
# | ...
# `---data was truncated (10240/10886) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605b1f9f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005605b1f9c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005605b1f9f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2363105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f236315c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2363105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23630ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605b1f34e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005605b1f34c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005605b1f19b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005605b1bc90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005605b1bc8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f23630eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23630ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23630ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605b1bc8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c (1643 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/69542) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618e6e3215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005618e6e2f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005618e6e3289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f870801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87080725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f870801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8708003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618e6dc7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005618e6dc7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005618e6dacb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005618e6a5c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005618e6a5bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8708004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87080050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87080050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618e6a5bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c (1644 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602b3c6015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005602b3c5d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005602b3c6089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f53a6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53a6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f53a6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f53a6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602b3bf5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005602b3bf5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005602b3bdab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005602b388a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005602b3889dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f53a6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53a6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53a6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602b3889cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c (1645 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i
# | ...
# `---data was truncated (10240/125641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055856edd215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055856edcf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055856edd289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd5d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd5d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd5d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd5d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055856ed67e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055856ed67c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055856ed4cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055856e9fc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055856e9fbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcd5d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd5d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd5d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055856e9fbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c (1646 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i6
# | ...
# `---data was truncated (10240/132470) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aaea74215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aaea73f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aaea74289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d97e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d97ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d97e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d97e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aaea6d7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aaea6d7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aaea6bcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aaea36c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aaea36bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5d97e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d97e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d97e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aaea36bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c (1647 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/284336) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f610f7f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f610f7c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f610f7f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa139d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa139d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa139d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa139d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f610f14e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f610f14c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f610ef9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f610ba90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f610ba8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa139d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa139d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa139d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f610ba8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c (1648 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e84101115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e84100e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e84101189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44ddb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44ddb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44ddb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44ddb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e840fa6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e840fa6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e840f8bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e840c3b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e840c3add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f44ddb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44ddb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44ddb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e840c3acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c (1649 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | defi
# | ...
# `---data was truncated (10240/13593) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056376306815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005637630650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056376306889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f824fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f824fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f824fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f824fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563762ffde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563762ffdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563762fe2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563762c920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563762c91dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f824fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f824fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f824fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563762c91cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c (1650 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %v
# | ...
# `---data was truncated (10240/222307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e70661915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e7066160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e70661989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d9ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d9cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d9ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d9ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7065aee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e7065aec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e706593b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e7062430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e706242dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9d9ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d9ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d9ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e706242cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c (1651 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a842fbd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a842fba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a842fbd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f8e61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f8e6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f8e61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f8e603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a842f52e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a842f52c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a842f37b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a842be70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a842be6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8f8e604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f8e6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f8e6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a842be6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c (1652 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9cb6fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d9cb6fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d9cb6fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffbd8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffbd818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffbd8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffbd811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9cb692e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d9cb692c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d9cb677b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d9cb3270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d9cb326dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ffbd811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffbd811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffbd811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9cb326cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c (1653 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vxor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5b24af15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a5b24ac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a5b24af89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdefb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdefb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdefb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdefb51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5b2444e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a5b2444c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a5b2429b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a5b20d90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a5b20d8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdefb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdefb51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdefb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5b20d8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c (1654 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3c511b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e3c51180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e3c511b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2261249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22612a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2261249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2261231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3c50b0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e3c50b0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e3c5095b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e3c4d450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e3c4d44dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2261232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22612330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22612330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3c4d44cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c (1655 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_i16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_u16m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsse
# | ...
# `---data was truncated (10240/20441) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e28a12e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e28a12b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e28a12e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9416105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f941615c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9416105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94160ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e28a0c3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e28a0c3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e28a0a8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e289d580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e289d57dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f94160eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94160ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94160ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e289d57cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c (1656 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e522d315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557e522d00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557e522d389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6499f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6499f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6499f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6499f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e52268e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557e52268c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557e5224db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557e51efd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557e51efcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6499f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6499f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6499f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e51efccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c (1657 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 8 x 
# | ...
# `---data was truncated (10240/12463) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055780726015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055780725d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055780726089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08f4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08f438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08f4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08f431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578071f5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005578071f5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005578071dab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557806e8a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557806e89dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f08f431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08f431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08f431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557806e89cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c (1658 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4
# | ...
# `---data was truncated (10240/17503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce09a2c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ce09a290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ce09a2c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe65f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe65f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe65f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe65f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce099c1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ce099c1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ce099a6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ce096560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ce09655dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe65f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe65f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe65f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce09655cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c (1659 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <
# | ...
# `---data was truncated (10240/14421) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc4a1c615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cc4a1c30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cc4a1c689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f01fd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01fd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f01fd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f01fd51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc4a15be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cc4a15bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cc4a140b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cc49df00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cc49defdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f01fd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01fd51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01fd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc49defcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c (1660 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, al
# | ...
# `---data was truncated (10240/13263) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c6647615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563c664730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563c6647689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3427049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34270a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3427049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3427031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c6640be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563c6640bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563c663f0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563c660a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563c6609fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3427032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34270330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34270330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c6609fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c (1661 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f8d54c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562f8d5490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562f8d54c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa876649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8766a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa876649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa876631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f8d4e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562f8d4e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562f8d4c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562f8d1760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562f8d175dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa876632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8766330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8766330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f8d175cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c (1662 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2623ef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f2623ec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f2623ef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14c9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14c958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14c9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14c951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f262384e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f262384c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f262369b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f2620190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f262018dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f14c951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14c951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14c951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f262018cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c (1663 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsgtu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsgtu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.n
# | ...
# `---data was truncated (10240/95355) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056309b85115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056309b84e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056309b85189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb970849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9708a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb970849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb970831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056309b7e6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056309b7e6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056309b7cbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056309b47b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056309b47add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb970832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9708330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9708330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056309b47acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c (1664 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vminu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vminu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vminu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vminu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vminu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vminu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vminu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vminu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1a0f2115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a1a0f1e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a1a0f2189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2934c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2934ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2934c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2934c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1a0eb6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a1a0eb6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a1a0e9bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a1a0b4b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a1a0b4add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2934c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2934c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2934c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1a0b4acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c (1665 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_i16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_u16m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc7df4915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dc7df460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dc7df4989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f473fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f473fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f473fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f473fe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc7dedee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dc7dedec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dc7dec3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dc7db730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dc7db72dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f473fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f473fe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f473fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc7db72cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c (1666 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/40852) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056149578415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005614957810f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056149578489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c97449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c974a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c97449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c97431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561495719e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561495719c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005614956feb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005614953ae0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005614953addd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2c97432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c974330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c974330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614953adcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c (1667 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("risc
# | ...
# `---data was truncated (10240/14659) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625232c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005625232c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005625232c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feec0505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feec055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feec0505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feec04ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056252325ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056252325ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056252323fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562522eef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562522eeedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feec04eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feec04ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feec04ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562522eeecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c (1668 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei8_v_f32m4(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vsc
# | ...
# `---data was truncated (10240/121179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633e47a315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005633e47a00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005633e47a389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a80333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a8038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a80333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a8031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633e4738e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005633e4738c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005633e471db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005633e43cd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005633e43ccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8a8031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a8031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a8031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633e43cccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c (1669 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056275296c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005627529690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056275296c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4de161bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4de16725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4de161ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4de1603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562752901e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562752901c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005627528e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005627525960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562752595dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4de1604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4de16050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4de16050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562752595cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c (1670 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560fbf51115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560fbf50e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560fbf51189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e9e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e9e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e9e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e9e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560fbf4a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560fbf4a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560fbf48bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560fbf13b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560fbf13add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0e9e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e9e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e9e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560fbf13acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c (1671 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsadd_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsadd_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsadd_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsadd_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsadd_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsadd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsadd_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600a722315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005600a72200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005600a722389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3652649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36526a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3652649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3652631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600a71b8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005600a71b8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005600a719db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005600a6e4d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005600a6e4cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3652632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36526330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36526330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600a6e4ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c (1672 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3e73d015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e3e73cd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e3e73d089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d15133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d1518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d15133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d1511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3e7365e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e3e7365c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e3e734ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e3e6ffa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e3e6ff9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3d1511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d1511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d1511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3e6ff9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c (1673 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee40fbf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ee40fbc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ee40fbf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f24a7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24a778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f24a7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f24a771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee40f54e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ee40f54c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ee40f39b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ee40be90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ee40be8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f24a771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24a771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24a771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee40be8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c (1674 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple,
# | ...
# `---data was truncated (10240/27986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf4c44815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bf4c4450f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bf4c44889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f68a8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68a898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f68a8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68a891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf4c3dde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bf4c3ddc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bf4c3c2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bf4c0720b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bf4c071dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f68a891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68a891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68a891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf4c071cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c (1675 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d5858915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562d585860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562d5858989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c17649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c176a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c17649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c17631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d5851ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562d5851ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562d58503b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562d581b30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562d581b2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8c17632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c176330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c176330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d581b2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c (1676 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret voi
# | ...
# `---data was truncated (10240/102304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd0500215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cd04fff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cd0500289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e7d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e7d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e7d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e7d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd04f97e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cd04f97c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cd04f7cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cd04c2c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cd04c2bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4e7d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e7d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e7d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd04c2bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c (1677 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055768648615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005576864830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055768648689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5009533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f500958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5009533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f500951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055768641be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055768641bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557686400b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005576860b00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005576860afdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f500951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f500951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f500951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576860afcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c (1678 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>
# | ...
# `---data was truncated (10240/15607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055994efac15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055994efa90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055994efac89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93b3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93b358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93b3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93b351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055994ef41e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055994ef41c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055994ef26b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055994ebd60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055994ebd5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f93b351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93b351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93b351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055994ebd5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c (1679 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tu(<vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tu(<vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tu(<vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tum(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vd, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x double>, align 8
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_tum(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vd, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x double>, align 8
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_tum(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vd, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x double>, align 8
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_tumu(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vd, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %3 
# | ...
# `---data was truncated (10240/18303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d92692a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d9269270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d92692a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4245249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42452a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4245249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4245231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9268bfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d9268bfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d9268a4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d9265540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d926553dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4245232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42452330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42452330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d926553cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c (1680 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.add
# | ...
# `---data was truncated (10240/153913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055724d79015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055724d78d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055724d79089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f841e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f841e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f841e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f841e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055724d725e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055724d725c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055724d70ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055724d3ba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055724d3b9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f841e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f841e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f841e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055724d3b9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c (1681 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560fe1bd115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560fe1bce0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560fe1bd189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c9dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c9dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c9dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c9dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560fe1b66e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560fe1b66c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560fe1b4bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560fe17fb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560fe17fadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0c9dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c9dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c9dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560fe17facc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c (1682 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 0, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32, i32, <8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 0, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32, i32, <4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 1, <8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 1, <4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load <16 x i8>, ptr %b.addr, align
# | ...
# `---data was truncated (10240/39627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055924a1f015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055924a1ed0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055924a1f089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca07a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca07a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca07a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca07a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055924a185e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055924a185c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055924a16ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559249e1a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559249e19dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fca07a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca07a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca07a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559249e19cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c (1683 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16mf2_bf16mf4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv2bf16(<vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m1_bf16mf2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv4bf16(<vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16mf2(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf4(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16mf2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf4(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.vector.extract.nxv1bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16mf2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_trunc_v_bf16m8_bf16m4(<vscale x
# | ...
# `---data was truncated (10240/11396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622709ca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005622709c70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005622709ca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8050e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8050ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8050e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8050e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056227095fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056227095fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562270944b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005622705f40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005622705f3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8050e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8050e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8050e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622705f3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c (1684 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8ec98b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c8ec9880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c8ec98b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51c2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51c238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51c2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51c231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8ec920e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c8ec920c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c8ec905b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c8ec5b50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c8ec5b4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f51c231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51c231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51c231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8ec5b4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c (1685 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2(<vscale x 1 x double> %vs2, <vscale x 1 x double> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vs1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x double> %vs1, ptr %vs1.addr, align
# | ...
# `---data was truncated (10240/102872) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0bf1da15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a0bf1d70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a0bf1da89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e85d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e85d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e85d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e85d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0bf16fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a0bf16fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a0bf154b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a0bee040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a0bee03dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3e85d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e85d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e85d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0bee03cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c (1686 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vx_u16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind 
# | ...
# `---data was truncated (10240/68247) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9fbe6215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b9fbe5f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b9fbe6289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cfa849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cfa8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cfa849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cfa831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9fbdf7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b9fbdf7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b9fbddcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b9fba8c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b9fba8bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1cfa832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cfa8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cfa8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9fba8bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c (1687 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad7ad3515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ad7ad320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ad7ad3589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f218b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f218b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f218b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f218b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad7accae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ad7accac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ad7acafb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ad7a95f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ad7a95edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f218b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f218b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f218b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad7a95ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c (1688 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmaxu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmaxu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7dfc3d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c7dfc3a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c7dfc3d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83da449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83da4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83da449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83da431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7dfbd2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c7dfbd2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c7dfbb7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c7df8670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c7df866dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f83da432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83da4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83da4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7df866cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c (1689 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bf2f9f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555bf2f9c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555bf2f9f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbd3a105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbd3a15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbd3a105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbd3a0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bf2f34e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555bf2f34c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555bf2f19b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555bf2bc90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555bf2bc8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbd3a0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbd3a0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbd3a0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bf2bc8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c (1690 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vx_u8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhu_vv_u8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vsc
# | ...
# `---data was truncated (10240/65905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640180bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005640180ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005640180bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f65b5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f65b5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f65b5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f65b5f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564018052e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564018052c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564018037b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564017ce70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564017ce6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f65b5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65b5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65b5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564017ce6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c (1691 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback 
# | ...
# `---data was truncated (10240/15245) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa9229615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fa922930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fa9229689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6bc0a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6bc0a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6bc0a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6bc0a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa9222be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fa9222bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fa92210b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fa91ec00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fa91ebfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6bc0a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6bc0a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6bc0a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa91ebfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c (1692 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aac8ae815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aac8ae50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aac8ae889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42e0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42e0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42e0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42e0c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aac8a7de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aac8a7dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aac8a62b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aac87120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aac8711dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f42e0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42e0c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42e0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aac8711cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c (1693 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vx_u8m1_b8(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vv_u8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsltu_vx_u8m2_b4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsltu_vv_u8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8.n
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d485a515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558d485a20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558d485a589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90efa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90efaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90efa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90efa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d4853ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558d4853ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558d4851fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558d481cf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558d481cedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f90efa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90efa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90efa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d481cecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c (1694 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571cc25615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005571cc2530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005571cc25689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f014b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f014b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f014b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f014b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571cc1ebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005571cc1ebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005571cc1d0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005571cbe800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005571cbe7fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f014b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f014b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f014b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571cbe7fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c (1695 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1,
# | ...
# `---data was truncated (10240/223801) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0983a115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e09839e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e0983a189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7141e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7141ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7141e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7141e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e098336e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e098336c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e09831bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e097fcb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e097fcadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7141e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7141e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7141e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e097fcacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c (1696 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640ad4f715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005640ad4f40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005640ad4f789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe28649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe286a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe28649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe28631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005640ad48ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005640ad48cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005640ad471b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005640ad1210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005640ad120dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbe28632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe286330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe286330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640ad120cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c (1697 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind
# | ...
# `---data was truncated (10240/365431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7a8e5e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a7a8e5b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a7a8e5e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43a1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43a10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43a1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43a1031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7a8df3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a7a8df3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a7a8dd8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a7a8a880b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a7a8a87dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f43a1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43a10330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43a10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7a8a87cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c (1698 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 
# | ...
# `---data was truncated (10240/24206) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac85cec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ac85ce90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ac85cec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d3961bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d396725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d3961ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d39603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac85c81e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ac85c81c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ac85c66b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ac859160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ac85915dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4d39604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d396050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d396050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac85915cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c (1699 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vnot_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vnot_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vnot_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale 
# | ...
# `---data was truncated (10240/72501) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564583d8d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564583d8a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564583d8d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f08533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f0858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f08533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f0851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564583d22e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564583d22c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564583d07b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005645839b70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005645839b6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3f0851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f0851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f0851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005645839b6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c (1700 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0eacb215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a0eacaf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a0eacb289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5edb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5edb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5edb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5edb51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0eac47e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a0eac47c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a0eac2cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a0ea8dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a0ea8dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5edb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5edb51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5edb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0ea8dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c (1701 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055683eabe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055683eabb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055683eabe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a4c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a4c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a4c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a4c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055683ea53e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055683ea53c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055683ea38b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055683e6e80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055683e6e7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0a4c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a4c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a4c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055683e6e7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c (1702 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vget_v_bf16m8_bf16m4(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x2_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x3_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x4_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x5_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x6_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x7_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x 
# | ...
# `---data was truncated (10240/30682) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d016ecf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d016ecc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d016ecf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa18b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa18b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa18b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa18b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d016e64e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d016e64c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d016e49b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d016af90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d016af8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa18b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa18b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa18b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d016af8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-neon-directed-rounding-constrained.c (1703 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-directed-rounding-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57      -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c -o - |      /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vrndi_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndi_v.i = bitcast <8 x i8> %1 to <2 x float>
# |   %vrndi_v1.i = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %vrndi_v.i)
# |   store <2 x float> %vrndi_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vrndiq_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %vrndiq_v.i = bitcast <16 x i8> %1 to <4 x float>
# |   %vrndiq_v1.i = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %vrndiq_v.i)
# |   store <4 x float> %vrndiq_v1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs-linux"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005579c4a7f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005579c4a7c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005579c4a7f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa80d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa80d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa80d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa80d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579c4a14e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005579c4a14c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005579c49f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005579c46a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005579c46a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa80d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa80d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa80d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579c46a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c (1704 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b7883e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559b7883b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559b7883e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a8781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a878725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a8781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a87803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b787d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559b787d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559b787b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559b784680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559b78467dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2a87804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a878050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a878050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b78467cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c (1705 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560de297315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560de29700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560de297389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd20c61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd20c6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd20c61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd20c603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560de2908e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560de2908c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560de28edb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560de259d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560de259cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd20c604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd20c6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd20c6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560de259ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c (1706 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load 
# | ...
# `---data was truncated (10240/26710) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055636759315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005563675900f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055636759389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69b3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69b3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69b3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69b3d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556367528e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556367528c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055636750db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005563671bd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005563671bcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f69b3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69b3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69b3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563671bccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c (1707 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfm
# | ...
# `---data was truncated (10240/65574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e162cd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558e162ca0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558e162cd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e19333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e1938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e19333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e1931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e16262e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558e16262c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558e16247b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558e15ef70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558e15ef6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3e1931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e1931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e1931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e15ef6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c (1708 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjx_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjx_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjx_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjx_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjx_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/69669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056394be7c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056394be790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056394be7c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29d1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29d1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29d1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29d1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056394be11e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056394be11c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056394bdf6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056394baa60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056394baa5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f29d1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29d1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29d1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056394baa5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c (1709 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ea64d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564ea64d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564ea64d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84cd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84cd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84cd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84cd11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ea6469e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564ea6469c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564ea644eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564ea60fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564ea60fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f84cd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84cd11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84cd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ea60fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c (1710 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca targ
# | ...
# `---data was truncated (10240/11920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561416e7a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561416e770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561416e7a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6342249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63422a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6342249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6342231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561416e0fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561416e0fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561416df4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561416aa40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561416aa3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6342232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63422330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63422330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561416aa3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/veorq.c (1711 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/veorq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = xor <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = xor <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = xor <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_veorq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = xor <4 x i32> %1, %3
# |   %5 = bitcast <4 x i32> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_veorq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_veorq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5)
# |   %7 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x
# | ...
# `---data was truncated (10240/10901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f029ac15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555f029a90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555f029ac89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5f4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5f48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5f4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5f4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f02941e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555f02941c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555f02926b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555f025d60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555f025d5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa5f4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5f48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5f48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f025d5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c (1712 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16mf2_f16mf4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m1_f16mf4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m1_f16mf2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m2_f16mf4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m2_f16mf2(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m2_f16m1(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m4_f16mf4(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m4_f16mf2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m4_f16m1(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m4_f16m2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m8_f16mf4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m8_f16mf2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m8_f16m1(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m8_f16m2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_trunc_v_f16m8_f16m4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 im
# | ...
# `---data was truncated (10240/78242) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d2bca6715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d2bca640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d2bca6789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98d1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98d1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98d1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98d1c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2bc9fce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d2bc9fcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d2bc9e1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d2bc6910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d2bc690dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f98d1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98d1c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98d1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2bc690cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c (1713 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/94371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a3a6da15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563a3a6d70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563a3a6da89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb0f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb0f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb0f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb0f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a3a66fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563a3a66fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563a3a654b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563a3a3040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563a3a303dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feb0f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb0f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb0f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a3a303cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c (1714 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf4(ptr noundef %base, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf2(ptr noundef %base, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m1(ptr noundef %base, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m2(ptr noundef %base, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m4(ptr noundef %base, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m8(ptr noundef %base, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf4(ptr noundef %base, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf2(ptr noundef %base, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m1(ptr noundef %base, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m2(ptr noundef %base, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m4(ptr noundef %base, <vscale x 16 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m8(ptr noundef %base, <vscale x 32 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, ali
# | ...
# `---data was truncated (10240/33772) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055648f06a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055648f0670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055648f06a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9ab649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9ab6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9ab649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9ab631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055648efffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055648efffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055648efe4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055648ec940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055648ec93dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff9ab632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9ab6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9ab6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055648ec93cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c (1715 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580c3f3715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005580c3f340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005580c3f3789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f16049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f160a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f16049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f16031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580c3ecce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005580c3eccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005580c3eb1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005580c3b610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005580c3b60dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6f16032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f160330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f160330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580c3b60cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll (1716 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll
# |  #0 0x000055b5b6ce615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b5b6ce30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b5b6ce689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2f3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2f398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2f3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2f391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5b6c7be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b5b6c7bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b5b6c60b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b5b69100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b5b690fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd2f391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2f391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2f391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5b690fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c (1717 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561fdc98c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561fdc9890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561fdc98c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff1a105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff1a15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff1a105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff1a0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561fdc921e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561fdc921c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561fdc906b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561fdc5b60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561fdc5b5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007eff1a0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff1a0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff1a0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561fdc5b5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c (1718 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vror_vx_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vror_vx_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vror_vx_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vror_vx_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vror_vx_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vror_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.a
# | ...
# `---data was truncated (10240/97683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bad95b415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bad95b10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bad95b489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe83d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe83d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe83d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe83d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bad9549e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bad9549c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bad952eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bad91de0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bad91dddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe83d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe83d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe83d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bad91ddcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c (1719 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i6
# | ...
# `---data was truncated (10240/157165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f438b7b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f438b780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f438b7b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f298c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f298c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f298c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f298c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f438b10e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f438b10c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f438af5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f4387a50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f4387a4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f298c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f298c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f298c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4387a4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c (1720 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc half @test_vgetq_lane_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = extractelement <8 x half> %0, i32 2
# |   ret half %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc float @test_vgetq_lane_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = extractelement <4 x float> %0, i32 3
# |   ret float %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i16 @test_vgetq_lane_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = extractelement <8 x i16> %0, i32 4
# |   ret i16 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vgetq_lane_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = extractelement <4 x i32> %0, i32 0
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vgetq_lane_s64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = extractelement <2 x i64> %0, i32 0
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc signext i8 @test_vgetq_lane_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = extractelement <16 x i8> %0, i32 10
# |   ret i8 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vgetq_lane_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = extractelement <8 x i16> %0, i32 3
# |   ret i16 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vgetq_lane_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = extractelement <4 x i32> %0, i32 3
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vgetq_lane_u64(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = extractelement <2 x i64> %0, i32 1
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = extractelement <16 x i8> %0, i32 1
# |   ret i8 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsetq_lane_f16(half noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca <8 x half>, align 8
# |   store half %a, ptr %a.addr, align 2
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %b.addr, align 8
# |   %1 = load half, ptr %a.addr, align 2
# |   %2 = insertelement <8 x half> %0, half %1, i32 4
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsetq_lane_f32(float noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca float, align 4
# |   %b.addr = alloca <4 x float>, align 8
# |   store float %a, ptr %a.addr, align 4
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %b.addr, align 8
# |   %1 = load float, ptr %a.addr, align 4
# |   %2 = insertelement <4 x float> %0, float %1, i32 2
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsetq_lane_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %a.addr, align 1
# |   %2 = insertelement <16 x i8> %0, i8 %1, i32 12
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsetq_lane_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load i16, ptr %a.addr, align 2
# |   %2 = insertelement <8 x i16> %0, i16 %1, i32 6
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsetq_lane_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load i32, ptr %a.addr, align 4
# |   %2 = insertelement <4 x i32> %0, i32 %1, i32 2
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vsetq_lane_s64(i64 noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %b.addr, align 8
# |   %1 = load i64, ptr %a.addr, align 8
# |   %2 = insertelement <2 x i64> %0, i64 %1, i32 0
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsetq_lane_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   %b.addr = alloca <16 x i8>, align 8
# |   store i8 %a, ptr %a.addr, align 1
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = load i8, ptr %a.addr, align 1
# |   %2 = insertelement <16 x i8> %0, i8 %1, i32 2
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsetq_lane_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %b.addr = alloca <8 x i16>, align 8
# |   store i16 %a, ptr %a.addr, align 2
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = load i16, ptr %a.addr, align 2
# |   %2 = insertelement <8 x i16> %0, i16 %1, i32 7
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsetq_lane_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = load i32, ptr %a.addr, align 4
# |   %2 = insertelement <4 x i32> %0, i32 %1, i32 0
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vsetq_lane_u64(i64 noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %b.addr, align 8
# |   %1 = load i64, ptr %a.addr, align 8
# |   %2 = insertelement <2 x i64> %0, i64 %1, i32 1
# |   ret <2 x i64> %2
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>'
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<>
# |  #0 0x000055633ca3a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055633ca370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055633ca3a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e83849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e838a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e83849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e83831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055633c9cfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055633c9cfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055633c9b4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055633c6640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055633c663dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0e83832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e838330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e838330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055633c663cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c (1721 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, 
# | ...
# `---data was truncated (10240/24959) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e16df0f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e16df0c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e16df0f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fb8f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fb8f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fb8f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fb8eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e16dea4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e16dea4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e16de89b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e16db390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e16db38dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3fb8eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fb8eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fb8eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e16db38cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c (1722 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vsc
# | ...
# `---data was truncated (10240/255546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055daec56c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055daec5690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055daec56c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb064133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb06418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb064133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb06411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055daec501e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055daec501c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055daec4e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055daec1960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055daec195dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb06411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb06411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb06411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055daec195cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c (1723 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/113757) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd2a0c015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dd2a0bd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dd2a0c089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1cf049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1cf0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1cf049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1cf031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd2a055e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dd2a055c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dd2a03ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dd29cea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dd29ce9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff1cf032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1cf0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1cf0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd29ce9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c (1724 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load half, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load float, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x
# | ...
# `---data was truncated (10240/78032) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055858498815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005585849850f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055858498889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f360cb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f360cb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f360cb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f360caed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055858491de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055858491dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558584902b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005585845b20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005585845b1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f360caeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f360caef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f360caef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005585845b1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c (1725 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/306627) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f6fa8715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556f6fa840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556f6fa8789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdda2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdda2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdda2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdda2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f6fa1ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556f6fa1cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556f6fa01b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556f6f6b10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556f6f6b0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdda2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdda2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdda2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f6f6b0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/thinlto-funcattr-prop.ll (1726 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto-funcattr-prop.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-funcattr-prop.ll /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp
# executed command: split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-funcattr-prop.ll /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp
# RUN: at line 6
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc
# |  #0 0x000055bd6846715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bd684640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bd6846789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6797649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67976a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6797649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6797631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd683fce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bd683fcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bd683e1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bd680910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bd68090dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6797632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67976330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67976330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd68090cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c (1727 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558cad57f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558cad57c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558cad57f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3541c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3541c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3541c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3541c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558cad514e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558cad514c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558cad4f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558cad1a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558cad1a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3541c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3541c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3541c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558cad1a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c (1728 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb5c17115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cb5c16e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cb5c17189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31f3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31f3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31f3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31f3d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb5c106e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cb5c106c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cb5c0ebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cb5bd9b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cb5bd9add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f31f3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31f3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31f3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb5bd9acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c (1729 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d00f74315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d00f7400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d00f74389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfa7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfa7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfa7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfa7c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d00f6d8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d00f6d8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d00f6bdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d00f36d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d00f36cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcfa7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfa7c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfa7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d00f36ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c (1730 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621a1aa715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005621a1aa40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005621a1aa789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7276733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f727678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7276733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f727671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621a1a3ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005621a1a3cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005621a1a21b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005621a16d10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005621a16d0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f727671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f727671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f727671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621a16d0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/fp8-extract.c (1731 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/fp8-extract.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc        -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_var(<16 x i8> %v, i32 noundef %i) #0 {
# | entry:
# |   %v.addr = alloca <16 x i8>, align 16
# |   %i.addr = alloca i32, align 4
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   store i32 %i, ptr %i.addr, align 4
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   %1 = load i32, ptr %i.addr, align 4
# |   %vecext = extractelement <16 x i8> %0, i32 %1
# |   %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0
# |   call void @g(<1 x i8> %mfp8ext)
# |   ret void
# | }
# | 
# | declare void @g(<1 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_cst(<16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   %vecext = extractelement <16 x i8> %0, i32 3
# |   %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0
# |   call void @g(<1 x i8> %mfp8ext)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine
# |  #0 0x000055ffac80c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ffac8090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ffac80c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8bc533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8bc58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8bc533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8bc51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffac7a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ffac7a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ffac786b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ffac4360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ffac435dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa8bc51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8bc51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8bc51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffac435cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c (1732 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556cf7f5a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556cf7f570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556cf7f5a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f442ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f442ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f442ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f442ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556cf7eefe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556cf7eefc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556cf7ed4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556cf7b840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556cf7b83dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f442ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f442ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f442ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556cf7b83cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c (1733 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(<vscale x 2 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(<vscale x 8 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(<vscale x 16 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(<vscale x 32 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(<vscale x 4 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(<vscale x 8 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(<vscale x 16 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2(<vscale x 1 x double> %vs2, <vscale x 1 x double> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vs1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x double> %vs1, ptr %vs1.addr, align 8
# |   sto
# | ...
# `---data was truncated (10240/102864) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fdc27f715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fdc27f40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fdc27f789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f439db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f439db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f439db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f439db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fdc278ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fdc278cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fdc2771b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fdc24210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fdc2420dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f439db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f439db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f439db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fdc2420cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c (1734 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>,
# | ...
# `---data was truncated (10240/16521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4f4be215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d4f4bdf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d4f4be289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea6ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea6ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea6ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea6ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4f4b77e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d4f4b77c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d4f4b5cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d4f480c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d4f480bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fea6ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea6ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea6ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4f480bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c (1735 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eebb4fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eebb4f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eebb4fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7fdd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7fdd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7fdd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7fdd631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eebb490e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eebb490c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eebb475b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eebb1250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eebb124dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7fdd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7fdd6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7fdd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eebb124cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c (1736 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @ll
# | ...
# `---data was truncated (10240/20090) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563efc93815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563efc9350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563efc93889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94f5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94f518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94f5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94f511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563efc8cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563efc8cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563efc8b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563efc5620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563efc561dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f94f511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94f511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94f511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563efc561cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c (1737 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e09e79615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e09e7930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e09e79689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80d3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80d378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80d3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80d371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e09e72be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e09e72bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e09e710b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e09e3c00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e09e3bfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f80d371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80d371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80d371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e09e3bfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c (1738 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bad2e9b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bad2e980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bad2e9b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f596f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f596f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f596f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f596f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bad2e30e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bad2e30c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bad2e15b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bad2ac50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bad2ac4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f596f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f596f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f596f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bad2ac4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c (1739 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557e4c6215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005557e4c5f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005557e4c6289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f483bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f483bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f483bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f483bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557e4bf7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005557e4bf7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005557e4bdcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005557e488c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005557e488bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f483bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f483bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f483bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557e488bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c (1740 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d11331615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d1133130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d11331689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96f9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96f9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96f9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96f9e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1132abe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d1132abc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d113290b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d112f400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d112f3fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f96f9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96f9e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96f9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d112f3fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c (1741 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/77054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557fafad815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557fafad50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557fafad889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3175f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3175f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3175f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3175f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fafa6de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557fafa6dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557fafa52b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557faf7020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557faf701dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3175f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3175f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3175f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557faf701cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c (1742 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056489590e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056489590b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056489590e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9399533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f939958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9399533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f939951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648958a3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005648958a3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564895888b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005648955380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564895537dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f939951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f939951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f939951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564895537cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c (1743 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 1
# | ...
# `---data was truncated (10240/68509) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056057297615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005605729730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056057297689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b5de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b5dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b5de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b5de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056057290be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056057290bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005605728f0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005605725a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056057259fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8b5de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b5de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b5de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056057259fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c (1744 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# | ...
# `---data was truncated (10240/29304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556607d1f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556607d1c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556607d1f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007febd9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007febd9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007febd9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007febd9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556607cb4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556607cb4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556607c99b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005566079490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556607948dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007febd9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007febd9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007febd9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556607948cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c (1745 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vxor_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vxor_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vxor_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vxor_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vxor_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579fc82e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005579fc82b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005579fc82e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc187133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc18718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc187133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc18711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005579fc7c3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005579fc7c3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005579fc7a8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005579fc4580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005579fc457dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc18711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc18711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc18711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579fc457cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c (1746 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ae540c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561ae54090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561ae540c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57f9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57f978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57f9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57f971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ae53a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561ae53a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561ae5386b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561ae50360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561ae5035dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f57f971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57f971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57f971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ae5035cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c (1747 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd9d74d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bd9d74a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bd9d74d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d17c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d17ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d17c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d17c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd9d6e2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bd9d6e2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bd9d6c7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bd9d3770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bd9d376dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4d17c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d17c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d17c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd9d376cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c (1748 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vand_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc66c9715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fc66c940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fc66c9789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdf1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdf1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdf1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdf1c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc66c2ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fc66c2cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fc66c11b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fc668c10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fc668c0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efdf1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdf1c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdf1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc668c0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c (1749 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd82cc415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bd82cc10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bd82cc489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3e0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3e08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3e0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3e0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd82c59e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bd82c59c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bd82c3eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bd828ee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bd828eddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff3e0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3e08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3e08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd828edcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c (1750 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i6
# | ...
# `---data was truncated (10240/151253) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055edf603615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055edf60330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055edf603689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a21049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a210a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a21049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a21031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055edf5fcbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055edf5fcbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055edf5fb0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055edf5c600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055edf5c5fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5a21032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a210330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a210330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055edf5c5fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c (1751 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e32_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e32_v_u32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056321abba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056321abb70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056321abba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32f961bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32f96725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32f961ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32f9603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056321ab4fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056321ab4fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056321ab34b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056321a7e40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056321a7e3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f32f9604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32f96050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32f96050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056321a7e3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c (1752 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vremu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vremu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vremu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vremu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vremu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vremu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vremu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vremu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vremu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628d5b4b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005628d5b480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005628d5b4b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa925133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa92518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa925133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa92511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628d5ae0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005628d5ae0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005628d5ac5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005628d57750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005628d5774dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa92511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa92511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa92511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628d5774cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c (1753 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_x_f_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_x_f_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_x_f_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_x_f_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_x_f_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_x_f_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_xu_f_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_xu_f_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_xu_f_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_xu_f_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x
# | ...
# `---data was truncated (10240/514173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559fadf8615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559fadf830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559fadf8689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa26c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa26c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa26c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa26c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fadf1be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559fadf1bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559fadf00b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559fadbb00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559fadbafdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa26c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa26c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa26c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fadbafcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c (1754 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560561fd315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560561fd00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560561fd389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50f9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50f92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50f9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50f9231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560561f68e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560561f68c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560561f4db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560561bfd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560561bfcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f50f9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50f92330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50f92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560561bfccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c (1755 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvtu_x_x_v_u32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvtu_x_x_v_u64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvtu_x_x_v_u64
# | ...
# `---data was truncated (10240/29259) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055577295615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005557729530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055577295689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4637533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f463758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4637533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f463751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557728ebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005557728ebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005557728d0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005557725800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055577257fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f463751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f463751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f463751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055577257fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c (1756 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %binde
# | ...
# `---data was truncated (10240/99754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab60ec015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ab60ebd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ab60ec089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf83449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf834a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf83449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf83431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab60e55e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ab60e55c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ab60e3ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ab60aea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ab60ae9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faf83432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf834330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf834330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab60ae9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c (1757 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.ad
# | ...
# `---data was truncated (10240/26762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055731b37c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055731b3790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055731b37c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd85133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd8518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd85133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd8511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055731b311e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055731b311c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055731b2f6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055731afa60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055731afa5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcd8511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd8511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd8511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055731afa5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c (1758 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# | 
# | ...
# `---data was truncated (10240/225655) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1cf0ee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b1cf0eb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b1cf0ee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f9e21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f9e2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f9e21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f9e203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1cf083e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b1cf083c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b1cf068b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b1ced180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b1ced17dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0f9e204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f9e2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f9e2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1ced17cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c (1759 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c16ac6315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c16ac600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c16ac6389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0981d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0981d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0981d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0981ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c16abf8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c16abf8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c16abddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c16a88d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c16a88cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0981ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0981cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0981cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c16a88ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c (1760 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558632d5115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558632d4e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558632d5189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0dcb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0dcb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0dcb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0dcb91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558632ce6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558632ce6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558632ccbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055863297b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055863297add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0dcb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0dcb91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0dcb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055863297acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c (1761 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639716a515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005639716a20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005639716a589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1530733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f153078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1530733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f153071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056397163ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056397163ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056397161fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005639712cf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005639712cedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f153071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f153071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f153071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639712cecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c (1762 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6b43c215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a6b43bf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a6b43c289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd897b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd897b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd897b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd897b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6b4357e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a6b4357c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a6b433cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a6b3fec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a6b3febdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd897b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd897b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd897b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6b3febcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c (1763 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasubu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasubu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasubu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasubu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasubu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.ad
# | ...
# `---data was truncated (10240/225647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c496dd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555c496da0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555c496dd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd696249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6962a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd696249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd696231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c49672e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555c49672c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555c49657b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555c493070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555c49306dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd696232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6962330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6962330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c49306cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c (1764 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db9df4115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055db9df3e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055db9df4189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ff9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ff938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ff9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ff931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db9ded6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055db9ded6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055db9debbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055db9db6b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055db9db6add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1ff931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ff931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ff931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db9db6acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c (1765 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d164fc415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d164fc10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d164fc489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed7a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed7a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed7a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed7a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d164f59e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d164f59c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d164f3eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d164bee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d164beddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fed7a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed7a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed7a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d164bedcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c (1766 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d34062315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d3406200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d34062389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f09b341bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f09b34725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f09b341ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f09b3403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3405b8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d3405b8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d34059db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d34024d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d34024cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f09b3404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f09b34050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f09b34050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d34024ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c (1767 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dff057c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dff05790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dff057c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95da533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95da58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95da533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95da51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dff0511e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dff0511c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dff04f6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dff01a60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dff01a5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f95da51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95da51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95da51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dff01a5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c (1768 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575d5b3d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005575d5b3a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005575d5b3d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd6dbf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6dbf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd6dbf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6dbeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575d5ad2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005575d5ad2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005575d5ab7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005575d57670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005575d5766dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd6dbeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6dbeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6dbeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575d5766cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c (1769 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa4c9d815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fa4c9d50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fa4c9d889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5dc1705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5dc175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5dc1705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5dc16ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa4c96de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fa4c96dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fa4c952b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fa4c6020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fa4c601dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5dc16eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5dc16ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5dc16ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa4c601cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm64_vcopy.c (1770 of 27911)
******************** TEST 'Clang :: CodeGen/arm64_vcopy.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c"
# | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-apple-ios7"
# | 
# | ; Function Attrs: noinline nounwind
# | define <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <16 x i8>, align 16
# |   %a2.addr = alloca <16 x i8>, align 16
# |   %__ret_336 = alloca <16 x i8>, align 16
# |   %__s0_336 = alloca <16 x i8>, align 16
# |   %__s2_336 = alloca <16 x i8>, align 16
# |   %__ret = alloca <16 x i8>, align 16
# |   %__s0 = alloca i8, align 1
# |   %__ret1 = alloca i8, align 1
# |   %__s02 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   %__s1 = alloca <16 x i8>, align 16
# |   %ref.tmp3 = alloca <16 x i8>, align 16
# |   %tmp4 = alloca <16 x i8>, align 16
# |   %tmp5 = alloca <16 x i8>, align 16
# |   store <16 x i8> %a1, ptr %a1.addr, align 16
# |   store <16 x i8> %a2, ptr %a2.addr, align 16
# |   %0 = load <16 x i8>, ptr %a1.addr, align 16
# |   store <16 x i8> %0, ptr %__s0_336, align 16
# |   %1 = load <16 x i8>, ptr %a2.addr, align 16
# |   store <16 x i8> %1, ptr %__s2_336, align 16
# |   %2 = load <16 x i8>, ptr %__s2_336, align 16
# |   store <16 x i8> %2, ptr %__s02, align 16
# |   %3 = load <16 x i8>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <16 x i8> %3, i32 13
# |   store i8 %vgetq_lane, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret1, align 1
# |   %5 = load i8, ptr %__ret1, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   store i8 %6, ptr %__s0, align 1
# |   %7 = load <16 x i8>, ptr %__s0_336, align 16
# |   store <16 x i8> %7, ptr %__s1, align 16
# |   %8 = load i8, ptr %__s0, align 1
# |   %9 = load <16 x i8>, ptr %__s1, align 16
# |   %vset_lane = insertelement <16 x i8> %9, i8 %8, i32 3
# |   store <16 x i8> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <16 x i8>, ptr %ref.tmp3, align 16
# |   store <16 x i8> %10, ptr %__ret, align 16
# |   %11 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %11, ptr %tmp4, align 16
# |   %12 = load <16 x i8>, ptr %tmp4, align 16
# |   store <16 x i8> %12, ptr %__ret_336, align 16
# |   %13 = load <16 x i8>, ptr %__ret_336, align 16
# |   store <16 x i8> %13, ptr %tmp5, align 16
# |   %14 = load <16 x i8>, ptr %tmp5, align 16
# |   ret <16 x i8> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <16 x i8> @test_vcopyq_laneq_u8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <16 x i8>, align 16
# |   %a2.addr = alloca <16 x i8>, align 16
# |   %__ret_328 = alloca <16 x i8>, align 16
# |   %__s0_328 = alloca <16 x i8>, align 16
# |   %__s2_328 = alloca <16 x i8>, align 16
# |   %__ret = alloca <16 x i8>, align 16
# |   %__s0 = alloca i8, align 1
# |   %__ret1 = alloca i8, align 1
# |   %__s02 = alloca <16 x i8>, align 16
# |   %ref.tmp = alloca i8, align 1
# |   %tmp = alloca i8, align 1
# |   %__s1 = alloca <16 x i8>, align 16
# |   %ref.tmp3 = alloca <16 x i8>, align 16
# |   %tmp4 = alloca <16 x i8>, align 16
# |   %tmp5 = alloca <16 x i8>, align 16
# |   store <16 x i8> %a1, ptr %a1.addr, align 16
# |   store <16 x i8> %a2, ptr %a2.addr, align 16
# |   %0 = load <16 x i8>, ptr %a1.addr, align 16
# |   store <16 x i8> %0, ptr %__s0_328, align 16
# |   %1 = load <16 x i8>, ptr %a2.addr, align 16
# |   store <16 x i8> %1, ptr %__s2_328, align 16
# |   %2 = load <16 x i8>, ptr %__s2_328, align 16
# |   store <16 x i8> %2, ptr %__s02, align 16
# |   %3 = load <16 x i8>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <16 x i8> %3, i32 13
# |   store i8 %vgetq_lane, ptr %ref.tmp, align 1
# |   %4 = load i8, ptr %ref.tmp, align 1
# |   store i8 %4, ptr %__ret1, align 1
# |   %5 = load i8, ptr %__ret1, align 1
# |   store i8 %5, ptr %tmp, align 1
# |   %6 = load i8, ptr %tmp, align 1
# |   store i8 %6, ptr %__s0, align 1
# |   %7 = load <16 x i8>, ptr %__s0_328, align 16
# |   store <16 x i8> %7, ptr %__s1, align 16
# |   %8 = load i8, ptr %__s0, align 1
# |   %9 = load <16 x i8>, ptr %__s1, align 16
# |   %vset_lane = insertelement <16 x i8> %9, i8 %8, i32 3
# |   store <16 x i8> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <16 x i8>, ptr %ref.tmp3, align 16
# |   store <16 x i8> %10, ptr %__ret, align 16
# |   %11 = load <16 x i8>, ptr %__ret, align 16
# |   store <16 x i8> %11, ptr %tmp4, align 16
# |   %12 = load <16 x i8>, ptr %tmp4, align 16
# |   store <16 x i8> %12, ptr %__ret_328, align 16
# |   %13 = load <16 x i8>, ptr %__ret_328, align 16
# |   store <16 x i8> %13, ptr %tmp5, align 16
# |   %14 = load <16 x i8>, ptr %tmp5, align 16
# |   ret <16 x i8> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i16> @test_vcopyq_laneq_s16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <8 x i16>, align 16
# |   %a2.addr = alloca <8 x i16>, align 16
# |   %__ret_346 = alloca <8 x i16>, align 16
# |   %__s0_346 = alloca <8 x i16>, align 16
# |   %__s2_346 = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca i16, align 2
# |   %__ret1 = alloca i16, align 2
# |   %__s02 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   %__s1 = alloca <8 x i16>, align 16
# |   %ref.tmp3 = alloca <8 x i16>, align 16
# |   %tmp4 = alloca <8 x i16>, align 16
# |   %tmp5 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a1, ptr %a1.addr, align 16
# |   store <8 x i16> %a2, ptr %a2.addr, align 16
# |   %0 = load <8 x i16>, ptr %a1.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_346, align 16
# |   %1 = load <8 x i16>, ptr %a2.addr, align 16
# |   store <8 x i16> %1, ptr %__s2_346, align 16
# |   %2 = load <8 x i16>, ptr %__s2_346, align 16
# |   store <8 x i16> %2, ptr %__s02, align 16
# |   %3 = load <8 x i16>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <8 x i16> %3, i32 7
# |   store i16 %vgetq_lane, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret1, align 2
# |   %5 = load i16, ptr %__ret1, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   store i16 %6, ptr %__s0, align 2
# |   %7 = load <8 x i16>, ptr %__s0_346, align 16
# |   store <8 x i16> %7, ptr %__s1, align 16
# |   %8 = load i16, ptr %__s0, align 2
# |   %9 = load <8 x i16>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x i16> %9, i16 %8, i32 3
# |   store <8 x i16> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x i16>, ptr %ref.tmp3, align 16
# |   store <8 x i16> %10, ptr %__ret, align 16
# |   %11 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %11, ptr %tmp4, align 16
# |   %12 = load <8 x i16>, ptr %tmp4, align 16
# |   store <8 x i16> %12, ptr %__ret_346, align 16
# |   %13 = load <8 x i16>, ptr %__ret_346, align 16
# |   store <8 x i16> %13, ptr %tmp5, align 16
# |   %14 = load <8 x i16>, ptr %tmp5, align 16
# |   ret <8 x i16> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <8 x i16> @test_vcopyq_laneq_u16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <8 x i16>, align 16
# |   %a2.addr = alloca <8 x i16>, align 16
# |   %__ret_334 = alloca <8 x i16>, align 16
# |   %__s0_334 = alloca <8 x i16>, align 16
# |   %__s2_334 = alloca <8 x i16>, align 16
# |   %__ret = alloca <8 x i16>, align 16
# |   %__s0 = alloca i16, align 2
# |   %__ret1 = alloca i16, align 2
# |   %__s02 = alloca <8 x i16>, align 16
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   %__s1 = alloca <8 x i16>, align 16
# |   %ref.tmp3 = alloca <8 x i16>, align 16
# |   %tmp4 = alloca <8 x i16>, align 16
# |   %tmp5 = alloca <8 x i16>, align 16
# |   store <8 x i16> %a1, ptr %a1.addr, align 16
# |   store <8 x i16> %a2, ptr %a2.addr, align 16
# |   %0 = load <8 x i16>, ptr %a1.addr, align 16
# |   store <8 x i16> %0, ptr %__s0_334, align 16
# |   %1 = load <8 x i16>, ptr %a2.addr, align 16
# |   store <8 x i16> %1, ptr %__s2_334, align 16
# |   %2 = load <8 x i16>, ptr %__s2_334, align 16
# |   store <8 x i16> %2, ptr %__s02, align 16
# |   %3 = load <8 x i16>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <8 x i16> %3, i32 7
# |   store i16 %vgetq_lane, ptr %ref.tmp, align 2
# |   %4 = load i16, ptr %ref.tmp, align 2
# |   store i16 %4, ptr %__ret1, align 2
# |   %5 = load i16, ptr %__ret1, align 2
# |   store i16 %5, ptr %tmp, align 2
# |   %6 = load i16, ptr %tmp, align 2
# |   store i16 %6, ptr %__s0, align 2
# |   %7 = load <8 x i16>, ptr %__s0_334, align 16
# |   store <8 x i16> %7, ptr %__s1, align 16
# |   %8 = load i16, ptr %__s0, align 2
# |   %9 = load <8 x i16>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x i16> %9, i16 %8, i32 3
# |   store <8 x i16> %vset_lane, ptr %ref.tmp3, align 16
# |   %10 = load <8 x i16>, ptr %ref.tmp3, align 16
# |   store <8 x i16> %10, ptr %__ret, align 16
# |   %11 = load <8 x i16>, ptr %__ret, align 16
# |   store <8 x i16> %11, ptr %tmp4, align 16
# |   %12 = load <8 x i16>, ptr %tmp4, align 16
# |   store <8 x i16> %12, ptr %__ret_334, align 16
# |   %13 = load <8 x i16>, ptr %__ret_334, align 16
# |   store <8 x i16> %13, ptr %tmp5, align 16
# |   %14 = load <8 x i16>, ptr %tmp5, align 16
# |   ret <8 x i16> %14
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define <4 x i32> @test_vcopyq_laneq_s32(<4 x i32> noundef %a1, <4 x i32> noundef %a2) #0 {
# | entry:
# |   %a1.addr = alloca <4 x i32>, align 16
# |   %a2.addr = alloca <4 x i32>, align 16
# |   %__ret_340 = alloca <4 x i32>, align 16
# |   %__s0_340 = alloca <4 x i32>, align 16
# |   %__s2_340 = alloca <4 x i32>, align 16
# |   %__ret = alloca <4 x i32>, align 16
# |   %__s0 = alloca i32, align 4
# |   %__ret1 = alloca i32, align 4
# |   %__s02 = alloca <4 x i32>, align 16
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   %__s1 = alloca <4 x i32>, align 16
# |   %ref.tmp3 = alloca <4 x i32>, align 16
# |   %tmp4 = alloca <4 x i32>, align 16
# |   %tmp5 = alloca <4 x i32>, align 16
# |   store <4 x i32> %a1, ptr %a1.addr, align 16
# |   store <4 x i32> %a2, ptr %a2.addr, align 16
# |   %0 = load <4 x i32>, ptr %a1.addr, align 16
# |   store <4 x i32> %0, ptr %__s0_340, align 16
# |   %1 = load <4 x i32>, ptr %a2.addr, align 16
# |   store <4 x i32> %1, ptr %__s2_340, align 16
# |   %2 = load <4 x i32>, ptr %__s2_340, align 16
# |   store <4 x i32> %2, ptr %__s02, align 16
# |   %3 = load <4 x i32>, ptr %__s02, align 16
# |   %vgetq_lane = extractelement <4 x i32> %3, i32 3
# |   store i32 %vgetq_lane, ptr %ref.tmp, align 4
# |   %4 = load i32, ptr %ref.tmp, align 4
# |   store i32 %4, ptr %__ret1, align 4
# |   %5 = load i32, ptr %__ret1, align 4
# |   store i32 %5, ptr %tmp, align 4
# |   %6 = load i32, ptr %tmp, align 4
# |   store i32 %6, ptr %__s0, align 4
# |   %7 = load <4 x i32>
# | ...
# `---data was truncated (10240/22011) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb62fd515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fb62fd20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fb62fd589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb02b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb02b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb02b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb02b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb62f6ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fb62f6ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fb62f4fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fb62bff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fb62bfedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb02b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb02b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb02b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb62bfecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c (1771 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_sat_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x
# | ...
# `---data was truncated (10240/84802) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e446d4e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e446d4b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e446d4e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd0e01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd0e0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd0e01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd0e003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e446ce3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e446ce3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e446cc8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e4469780b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e446977dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdd0e004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd0e0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd0e0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e446977cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c (1772 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056352ca2e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056352ca2b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056352ca2e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6a601bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6a60725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6a601ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6a6003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056352c9c3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056352c9c3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056352c9a8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056352c6580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056352c657dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb6a6004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6a60050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6a60050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056352c657cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c (1773 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvt_x_x_v_i32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvt_x_x_v_i64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvt_x_x_v_i64m2(<vscale x 2 x i32> %src, i64 noundef
# | ...
# `---data was truncated (10240/29167) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a850c1315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a850c100f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a850c1389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04a1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04a18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04a1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04a1831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a850ba8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a850ba8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a850b8db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a85083d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a85083cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f04a1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04a18330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04a18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a85083ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c (1774 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x
# | ...
# `---data was truncated (10240/222925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562472f7915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562472f760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562472f7989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa93133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa9318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa93133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa9311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562472f0ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562472f0ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562472ef3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562472ba30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562472ba2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faa9311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa9311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa9311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562472ba2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c (1775 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055912c73c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055912c7390f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055912c73c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7087e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7087ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7087e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7087e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055912c6d1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055912c6d1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055912c6b6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055912c3660b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055912c365dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7087e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7087e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7087e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055912c365cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c (1776 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631946ad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005631946aa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005631946ad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6875933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f687598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6875933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f687591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563194642e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563194642c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563194627b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005631942d70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005631942d6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f687591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f687591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f687591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631942d6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon-vcmla.c (1777 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-vcmla.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64 -target-feature +neon         -target-feature +v8.3a         -target-feature +fullfp16         -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes="mem2reg,instsimplify,sroa" | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64 -target-feature +neon -target-feature +v8.3a -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcmla_f16(<4 x half> noundef %acc, <4 x half> noundef %lhs, <4 x half> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %acc.addr = alloca <4 x half>, align 8
# |   %lhs.addr = alloca <4 x half>, align 8
# |   %rhs.addr = alloca <4 x half>, align 8
# |   store <4 x half> %acc, ptr %acc.addr, align 8
# |   store <4 x half> %lhs, ptr %lhs.addr, align 8
# |   store <4 x half> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <4 x half>, ptr %acc.addr, align 8
# |   %1 = load <4 x half>, ptr %lhs.addr, align 8
# |   %2 = load <4 x half>, ptr %rhs.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vcmla_f16.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcmla_f161.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vcmla_f162.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vcmla_f163.i = call <4 x half> @llvm.aarch64.neon.vcmla.rot0.v4f16(<4 x half> %vcmla_f16.i, <4 x half> %vcmla_f161.i, <4 x half> %vcmla_f162.i)
# |   %vcmla_f164.i = bitcast <4 x half> %vcmla_f163.i to <8 x i8>
# |   store <8 x i8> %vcmla_f164.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vcmla_f32(<2 x float> noundef %acc, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %acc.addr = alloca <2 x float>, align 8
# |   %lhs.addr = alloca <2 x float>, align 8
# |   %rhs.addr = alloca <2 x float>, align 8
# |   store <2 x float> %acc, ptr %acc.addr, align 8
# |   store <2 x float> %lhs, ptr %lhs.addr, align 8
# |   store <2 x float> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <2 x float>, ptr %acc.addr, align 8
# |   %1 = load <2 x float>, ptr %lhs.addr, align 8
# |   %2 = load <2 x float>, ptr %rhs.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vcmla_f32.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vcmla_f321.i = bitcast <8 x i8> %4 to <2 x float>
# |   %vcmla_f322.i = bitcast <8 x i8> %5 to <2 x float>
# |   %vcmla_f323.i = call <2 x float> @llvm.aarch64.neon.vcmla.rot0.v2f32(<2 x float> %vcmla_f32.i, <2 x float> %vcmla_f321.i, <2 x float> %vcmla_f322.i)
# |   %vcmla_f324.i = bitcast <2 x float> %vcmla_f323.i to <8 x i8>
# |   store <8 x i8> %vcmla_f324.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vcmlaq_f16(<8 x half> noundef %acc, <8 x half> noundef %lhs, <8 x half> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <8 x half>, align 16
# |   %lhs.addr = alloca <8 x half>, align 16
# |   %rhs.addr = alloca <8 x half>, align 16
# |   store <8 x half> %acc, ptr %acc.addr, align 16
# |   store <8 x half> %lhs, ptr %lhs.addr, align 16
# |   store <8 x half> %rhs, ptr %rhs.addr, align 16
# |   %0 = load <8 x half>, ptr %acc.addr, align 16
# |   %1 = load <8 x half>, ptr %lhs.addr, align 16
# |   %2 = load <8 x half>, ptr %rhs.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vcmlaq_f16.i = bitcast <16 x i8> %3 to <8 x half>
# |   %vcmlaq_f161.i = bitcast <16 x i8> %4 to <8 x half>
# |   %vcmlaq_f162.i = bitcast <16 x i8> %5 to <8 x half>
# |   %vcmlaq_f163.i = call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %vcmlaq_f16.i, <8 x half> %vcmlaq_f161.i, <8 x half> %vcmlaq_f162.i)
# |   %vcmlaq_f164.i = bitcast <8 x half> %vcmlaq_f163.i to <16 x i8>
# |   store <16 x i8> %vcmlaq_f164.i, ptr %ref.tmp.i, align 16
# |   %6 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %6, ptr %__ret.i, align 16
# |   %7 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vcmlaq_f32(<4 x float> noundef %acc, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 16
# |   %__p1.addr.i = alloca <4 x float>, align 16
# |   %__p2.addr.i = alloca <4 x float>, align 16
# |   %__ret.i = alloca <4 x float>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <4 x float>, align 16
# |   %lhs.addr = alloca <4 x float>, align 16
# |   %rhs.addr = alloca <4 x float>, align 16
# |   store <4 x float> %acc, ptr %acc.addr, align 16
# |   store <4 x float> %lhs, ptr %lhs.addr, align 16
# |   store <4 x float> %rhs, ptr %rhs.addr, align 16
# |   %0 = load <4 x float>, ptr %acc.addr, align 16
# |   %1 = load <4 x float>, ptr %lhs.addr, align 16
# |   %2 = load <4 x float>, ptr %rhs.addr, align 16
# |   store <4 x float> %0, ptr %__p0.addr.i, align 16
# |   store <4 x float> %1, ptr %__p1.addr.i, align 16
# |   store <4 x float> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vcmlaq_f32.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vcmlaq_f321.i = bitcast <16 x i8> %4 to <4 x float>
# |   %vcmlaq_f322.i = bitcast <16 x i8> %5 to <4 x float>
# |   %vcmlaq_f323.i = call <4 x float> @llvm.aarch64.neon.vcmla.rot0.v4f32(<4 x float> %vcmlaq_f32.i, <4 x float> %vcmlaq_f321.i, <4 x float> %vcmlaq_f322.i)
# |   %vcmlaq_f324.i = bitcast <4 x float> %vcmlaq_f323.i to <16 x i8>
# |   store <16 x i8> %vcmlaq_f324.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x float>, ptr %ref.tmp.i, align 16
# |   store <4 x float> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x float>, ptr %__ret.i, align 16
# |   ret <4 x float> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x double> @test_vcmlaq_f64(<2 x double> noundef %acc, <2 x double> noundef %lhs, <2 x double> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x double>, align 16
# |   %__p1.addr.i = alloca <2 x double>, align 16
# |   %__p2.addr.i = alloca <2 x double>, align 16
# |   %__ret.i = alloca <2 x double>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %acc.addr = alloca <2 x double>, align 16
# |   %lhs.addr = alloca <2 x double>, align 16
# |   %rhs.addr = alloca <2 x double>, align 16
# |   store <2 x double> %acc, ptr %acc.addr, align 16
# |   store <2 x double> %lhs, ptr %lhs.addr, align 16
# |   store <2 x double> %rhs, ptr %rhs.addr, align 16
# |   %0 = load <2 x double>, ptr %acc.addr, align 16
# |   %1 = load <2 x double>, ptr %lhs.addr, align 16
# |   %2 = load <2 x double>, ptr %rhs.addr, align 16
# |   store <2 x double> %0, ptr %__p0.addr.i, align 16
# |   store <2 x double> %1, ptr %__p1.addr.i, align 16
# |   store <2 x double> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vcmlaq_f64.i = bitcast <16 x i8> %3 to <2 x double>
# |   %vcmlaq_f641.i = bitcast <16 x i8> %4 to <2 x double>
# |   %vcmlaq_f642.i = bitcast <16 x i8> %5 to <2 x double>
# |   %vcmlaq_f643.i = call <2 x double> @llvm.aarch64.neon.vcmla.rot0.v2f64(<2 x double> %vcmlaq_f64.i, <2 x double> %vcmlaq_f641.i, <2 x double> %vcmlaq_f642.i)
# |   %vcmlaq_f644.i = bitcast <2 x double> %vcmlaq_f643.i to <16 x i8>
# |   store <16 x i8> %vcmlaq_f644.i, ptr %ref.tmp.i, align 16
# |   %6 = load <2 x double>, ptr %ref.tmp.i, align 16
# |   store <2 x double> %6, ptr %__ret.i, align 16
# |   %7 = load <2 x double>, ptr %__ret.i, align 16
# |   ret <2 x double> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vcmla_rot90_f16(<4 x half> noundef %acc, <4 x half> noundef %lhs, <4 x half> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %acc.addr = alloca <4 x half>, align 8
# |   %lhs.addr = alloca <4 x half>, align 8
# |   %rhs.addr = alloca <4 x half>, align 8
# |   store <4 x half> %acc, ptr %acc.addr, align 8
# |   store <4 x half> %lhs, ptr %lhs.addr, align 8
# |   store <4 x half> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <4 x half>, ptr %acc.addr, align 8
# |   %1 = load <4 x half>, ptr %lhs.addr, align 8
# |   %2 = load <4 x half>, ptr %rhs.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vcmla_rot90_f16.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcmla_rot90_f161.i = bitcast <8 x i8> %4 to <4 x half>
# |   %vcmla_rot90_f162.i = bitcast <8 x i8> %5 to <4 x half>
# |   %vcmla_rot90_f163.i = call <4 x half> @llvm.aarch64.neon.vcmla.rot90.v
# | ...
# `---data was truncated (10240/166298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instsimplify,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instsimplify,sroa
# |  #0 0x00005621410de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005621410db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005621410de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f286d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f286d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f286d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f286d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562141073e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562141073c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562141058b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562140d080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562140d07dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f286d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f286d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f286d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562140d07cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c (1778 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv1
# | ...
# `---data was truncated (10240/47628) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fda872015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fda871d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fda872089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f39d7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39d758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f39d7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f39d751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fda86b5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fda86b5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fda869ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fda834a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fda8349dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f39d751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39d751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39d751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fda8349cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c (1779 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 0)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_n_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %.splat, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_n_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %.splat, i32 0, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ec19f215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559ec19ef0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559ec19f289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa4bb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa4bb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa4bb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa4baed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ec1987e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559ec1987c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559ec196cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559ec161c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559ec161bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ffa4baeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa4baef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa4baef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ec161bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c (1780 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563fcce9f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563fcce9c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563fcce9f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91c7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91c7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91c7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91c7e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563fcce34e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563fcce34c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563fcce19b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563fccac90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563fccac8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f91c7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91c7e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91c7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563fccac8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c (1781 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e19aac115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e19aabe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e19aac189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37e2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37e238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37e2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37e231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e19aa56e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e19aa56c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e19aa3bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e19a6eb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e19a6eadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f37e231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37e231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37e231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e19a6eacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c (1782 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x
# | ...
# `---data was truncated (10240/15615) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558a5347b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558a534780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558a5347b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c3f81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c3f8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c3f81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c3f803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558a53410e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558a53410c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558a533f5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558a530a50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558a530a4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5c3f804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c3f8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c3f8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558a530a4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c (1783 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/226585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056018befe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056018befb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056018befe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f726b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f726b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f726b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f726b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056018be93e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056018be93c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056018be78b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056018bb280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056018bb27dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f726b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f726b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f726b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056018bb27cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/AArch64/neon/f16-getset.c (1784 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/f16-getset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -disable-O0-optnone           -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdup_n_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <4 x half>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <4 x half> poison, half %1, i32 0
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <4 x half> %vecinit, half %2, i32 1
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <4 x half> %vecinit1, half %3, i32 2
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <4 x half> %vecinit2, half %4, i32 3
# |   store <4 x half> %vecinit3, ptr %.compoundliteral, align 8
# |   %5 = load <4 x half>, ptr %.compoundliteral, align 8
# |   store <4 x half> %5, ptr %__ret, align 8
# |   %6 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %6, ptr %tmp, align 8
# |   %7 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdupq_n_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca half, align 2
# |   %.compoundliteral = alloca <8 x half>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vecinit = insertelement <8 x half> poison, half %1, i32 0
# |   %2 = load half, ptr %__s0, align 2
# |   %vecinit1 = insertelement <8 x half> %vecinit, half %2, i32 1
# |   %3 = load half, ptr %__s0, align 2
# |   %vecinit2 = insertelement <8 x half> %vecinit1, half %3, i32 2
# |   %4 = load half, ptr %__s0, align 2
# |   %vecinit3 = insertelement <8 x half> %vecinit2, half %4, i32 3
# |   %5 = load half, ptr %__s0, align 2
# |   %vecinit4 = insertelement <8 x half> %vecinit3, half %5, i32 4
# |   %6 = load half, ptr %__s0, align 2
# |   %vecinit5 = insertelement <8 x half> %vecinit4, half %6, i32 5
# |   %7 = load half, ptr %__s0, align 2
# |   %vecinit6 = insertelement <8 x half> %vecinit5, half %7, i32 6
# |   %8 = load half, ptr %__s0, align 2
# |   %vecinit7 = insertelement <8 x half> %vecinit6, half %8, i32 7
# |   store <8 x half> %vecinit7, ptr %.compoundliteral, align 16
# |   %9 = load <8 x half>, ptr %.compoundliteral, align 16
# |   store <8 x half> %9, ptr %__ret, align 16
# |   %10 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %10, ptr %tmp, align 16
# |   %11 = load <8 x half>, ptr %tmp, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdup_lane_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %__ret_39 = alloca <4 x half>, align 8
# |   %__s0_39 = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   %tmp1 = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0_39, align 8
# |   %1 = load <4 x half>, ptr %__s0_39, align 8
# |   store <4 x half> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x half>
# |   %lane = shufflevector <4 x half> %3, <4 x half> %3, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x half> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %4, ptr %__ret, align 8
# |   %5 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %5, ptr %tmp, align 8
# |   %6 = load <4 x half>, ptr %tmp, align 8
# |   store <4 x half> %6, ptr %__ret_39, align 8
# |   %7 = load <4 x half>, ptr %__ret_39, align 8
# |   store <4 x half> %7, ptr %tmp1, align 8
# |   %8 = load <4 x half>, ptr %tmp1, align 8
# |   ret <4 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdupq_lane_f16(<4 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %__ret_20 = alloca <8 x half>, align 16
# |   %__s0_20 = alloca <4 x half>, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   %tmp1 = alloca <8 x half>, align 16
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0_20, align 8
# |   %1 = load <4 x half>, ptr %__s0_20, align 8
# |   store <4 x half> %1, ptr %__s0, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = bitcast <8 x i8> %2 to <4 x half>
# |   %lane = shufflevector <4 x half> %3, <4 x half> %3, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
# |   store <8 x half> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %4, ptr %__ret, align 16
# |   %5 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %5, ptr %tmp, align 16
# |   %6 = load <8 x half>, ptr %tmp, align 16
# |   store <8 x half> %6, ptr %__ret_20, align 16
# |   %7 = load <8 x half>, ptr %__ret_20, align 16
# |   store <8 x half> %7, ptr %tmp1, align 16
# |   %8 = load <8 x half>, ptr %tmp1, align 16
# |   ret <8 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vdup_laneq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %__ret_432 = alloca <4 x half>, align 8
# |   %__s0_432 = alloca <8 x half>, align 16
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   %tmp1 = alloca <4 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0_432, align 16
# |   %1 = load <8 x half>, ptr %__s0_432, align 16
# |   store <8 x half> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x half>
# |   %lane = shufflevector <8 x half> %3, <8 x half> %3, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
# |   store <4 x half> %lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %4, ptr %__ret, align 8
# |   %5 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %5, ptr %tmp, align 8
# |   %6 = load <4 x half>, ptr %tmp, align 8
# |   store <4 x half> %6, ptr %__ret_432, align 8
# |   %7 = load <4 x half>, ptr %__ret_432, align 8
# |   store <4 x half> %7, ptr %tmp1, align 8
# |   %8 = load <4 x half>, ptr %tmp1, align 8
# |   ret <4 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vdupq_laneq_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %__ret_408 = alloca <8 x half>, align 16
# |   %__s0_408 = alloca <8 x half>, align 16
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   %tmp1 = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0_408, align 16
# |   %1 = load <8 x half>, ptr %__s0_408, align 16
# |   store <8 x half> %1, ptr %__s0, align 16
# |   %2 = load <16 x i8>, ptr %__s0, align 16
# |   %3 = bitcast <16 x i8> %2 to <8 x half>
# |   %lane = shufflevector <8 x half> %3, <8 x half> %3, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
# |   store <8 x half> %lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x half>, ptr %ref.tmp, align 16
# |   store <8 x half> %4, ptr %__ret, align 16
# |   %5 = load <8 x half>, ptr %__ret, align 16
# |   store <8 x half> %5, ptr %tmp, align 16
# |   %6 = load <8 x half>, ptr %tmp, align 16
# |   store <8 x half> %6, ptr %__ret_408, align 16
# |   %7 = load <8 x half>, ptr %__ret_408, align 16
# |   store <8 x half> %7, ptr %tmp1, align 16
# |   %8 = load <8 x half>, ptr %tmp1, align 16
# |   ret <8 x half> %8
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vduph_lane_f16(<4 x half> noundef %vec) #0 {
# | entry:
# |   %vec.addr = alloca <4 x half>, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store <4 x half> %vec, ptr %vec.addr, align 8
# |   %0 = load <4 x half>, ptr %vec.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x half> %1, i32 3
# |   store half %vget_lane, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vduph_laneq_f16(<8 x half> noundef %vec) #0 {
# | entry:
# |   %vec.addr = alloca <8 x half>, align 16
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca <8 x half>, align 16
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store <8 x half> %vec, ptr %vec.addr, align 16
# |   %0 = load <8 x half>, ptr %vec.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %__s0, align 16
# |   %vgetq_lane = extractelement <8 x half> %1, i32 7
# |   store half %vgetq_lane, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-s
# | ...
# `---data was truncated (10240/10414) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055a8f33e815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a8f33e50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a8f33e889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed76249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed762a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed76249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed76231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8f337de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a8f337dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a8f3362b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a8f30120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a8f3011dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fed76232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed762330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed762330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8f3011cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c (1785 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0)
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %2)
# |   %4 = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %1, <8 x half> %3)
# |   ret <8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0)
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2)
# |   %4 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %1, <4 x float> %3)
# |   ret <4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055882975f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055882975c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055882975f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb9bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb9bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb9bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb9bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588296f4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005588296f4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005588296d9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005588293890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558829388dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdb9bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb9bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb9bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558829388cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c (1786 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b39ee0315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b39ee000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b39ee0389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6baf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6baf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6baf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6baf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b39ed98e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b39ed98c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b39ed7db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b39ea2d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b39ea2cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb6baf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6baf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6baf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b39ea2ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c (1787 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vaadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vaadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vaadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vaadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vaadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/225205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0315df15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a0315dc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a0315df89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f50e7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f50e7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f50e7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f50e7e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a031574e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a031574c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a031559b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a0312090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a031208dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f50e7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f50e7e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f50e7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a031208cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c (1788 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561719f8115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561719f7e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561719f8189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78ff333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78ff38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78ff333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78ff31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561719f16e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561719f16c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561719efbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561719bab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561719baadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f78ff31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78ff31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78ff31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561719baacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c (1789 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555db65cd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555db65ca0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555db65cd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ba0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ba02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ba0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ba0231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555db6562e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555db6562c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555db6547b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555db61f70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555db61f6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7ba0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ba02330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ba02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555db61f6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c (1790 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsbc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.ad
# | ...
# `---data was truncated (10240/98581) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e51fc415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563e51fc10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563e51fc489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd834333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd83438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd834333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd83431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e51f59e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563e51f59c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563e51f3eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563e51bee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563e51beddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd83431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd83431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd83431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e51bedcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c (1791 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x double>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_u64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(<vscale x 1 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_u64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(<vscale x 2 x i64> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i64>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/26996) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6f17e015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b6f17dd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b6f17e089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd03733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd0378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd03733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd0371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6f1775e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b6f1775c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b6f175ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b6f140a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b6f1409dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdd0371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd0371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd0371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6f1409cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c (1792 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredor_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredor_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align
# | ...
# `---data was truncated (10240/94149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b96e6815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556b96e650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556b96e6889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcaa3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcaa32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcaa3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcaa3231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b96dfde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556b96dfdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556b96de2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556b96a920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556b96a91dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcaa3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcaa32330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcaa32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b96a91cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c (1793 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ada826715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ada82640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ada826789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4530b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4530b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4530b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4530b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ada81fce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ada81fcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ada81e1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ada7e910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ada7e90dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4530b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4530b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4530b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ada7e90cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c (1794 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bd2a1915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562bd2a160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562bd2a1989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c63105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c6315c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c63105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c630ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bd29aee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562bd29aec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562bd2993b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562bd26430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562bd2642dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9c630eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c630ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c630ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bd2642cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c (1795 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611a637b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005611a63780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005611a637b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec04d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec04d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec04d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec04d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611a6310e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005611a6310c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005611a62f5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005611a5fa50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005611a5fa4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fec04d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec04d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec04d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611a5fa4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c (1796 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055abdd08215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055abdd07f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055abdd08289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe075d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe075d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe075d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe075d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055abdd017e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055abdd017c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055abdcffcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055abdccac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055abdccabdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe075d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe075d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe075d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055abdccabcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c (1797 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b1(ptr noundef %base, <vscale x 64 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv64i1.p0.i64(<vscale x 64 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b2(ptr noundef %base, <vscale x 32 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv32i1.p0.i64(<vscale x 32 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b4(ptr noundef %base, <vscale x 16 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv16i1.p0.i64(<vscale x 16 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b8(ptr noundef %base, <vscale x 8 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv8i1.p0.i64(<vscale x 8 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b16(ptr noundef %base, <vscale x 4 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv4i1.p0.i64(<vscale x 4 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b32(ptr noundef %base, <vscale x 2 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv2i1.p0.i64(<vscale x 2 x i1>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsm_v_b64(ptr noundef %base, <vscale x 1 x i1> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i1> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i1>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsm.nxv1i1.p0.i64(<vscale x 1 x i1>, ptr captures(none), i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8762ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c8762a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c8762ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1172249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11722a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1172249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1172231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c876240e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c876240c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c876225b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c875ed50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c875ed4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1172232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11722330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11722330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c875ed4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c (1798 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nx
# | ...
# `---data was truncated (10240/75125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dced46415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dced4610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dced46489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd749049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd7490a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd749049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd749031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dced3f9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dced3f9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dced3deb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dced08e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dced08ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd749032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd7490330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd7490330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dced08dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c (1799 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipo_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipo_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1
# | ...
# `---data was truncated (10240/35782) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562da79df15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562da79dc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562da79df89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe218333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe21838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe218333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe21831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562da7974e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562da7974c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562da7959b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562da76090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562da7608dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe21831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe21831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe21831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562da7608cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c (1800 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a26d04e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a26d04b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a26d04e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f373f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f373f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f373f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f373f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a26cfe3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a26cfe3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a26cfc8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a26cc780b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a26cc77dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f373f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f373f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f373f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a26cc77cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c (1801 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c8dcf315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560c8dcf00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560c8dcf389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd596f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd596f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd596f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd596f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c8dc88e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560c8dc88c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560c8dc6db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560c8d91d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560c8d91cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd596f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd596f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd596f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c8d91ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c (1802 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561fb800915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561fb80060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561fb800989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5db8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5db838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5db8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5db831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561fb7f9ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561fb7f9ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561fb7f83b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561fb7c330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561fb7c32dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5db831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5db831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5db831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561fb7c32cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c (1803 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmv_v_f_f16mf4(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half> poison, half %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmv_v_f_f16mf2(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half> poison, half %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmv_v_f_f16m1(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half> poison, half %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmv_v_f_f16m2(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half> poison, half %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmv_v_f_f16m4(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half> poison, half %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmv_v_f_f16m8(half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load half, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half> poison, half %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmv_v_f_f32mf2(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> poison, float %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmv_v_f_f32m1(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float> poison, float %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmv_v_f_f32m2(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float> poison, float %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfmv_v_f_f32m4(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float> poison, float %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfmv_v_f_f32m8(float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load float, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32.i64(<vscale x 16 x float> poison, float %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32.i64(<vscale x 16 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfmv_v_f_f64m1(double noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca double, align 8
# |   %vl.addr = alloca i64, align 8
# |   store double %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load double, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.i64(<vscale x 1 x double> poison, double %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.i64(<vscale x 1 x double>, double, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfmv_v_f_f64m2(double noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca double, align 8
# |   %vl.addr = alloca i64, align 8
# |   store double %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load double, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64.i64(<vscale x 2 x double> poison, double %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64.i64(<vscale x 2 x double>, double, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfmv_v_f_f64m4(double noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca double, align 8
# |   %vl.addr = alloca i64, align 8
# |   store double %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load double, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64.i64(<vscale x 4 x double> poison, double %0, i64 %1)
# |   
# | ...
# `---data was truncated (10240/30849) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cba24b415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cba24b10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cba24b489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb717049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7170a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb717049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb717031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cba2449e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cba2449c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cba242eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cba20de0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cba20dddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb717032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7170330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7170330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cba20ddcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c (1804 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloc
# | ...
# `---data was truncated (10240/27533) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056547ef8b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056547ef880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056547ef8b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd889333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd88938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd889333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd88931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056547ef20e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056547ef20c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056547ef05b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056547ebb50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056547ebb4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd88931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd88931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd88931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056547ebb4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c (1805 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4e
# | ...
# `---data was truncated (10240/216250) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e6082815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561e608250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561e6082889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9d4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9d438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9d4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9d431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e607bde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561e607bdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561e607a2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561e604520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561e60451dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb9d431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9d431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9d431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e60451cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c (1806 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmul_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmul_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmul_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vv_i16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmul_vx_i16m2(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vv_i16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmul_vx_i16m4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | def
# | ...
# `---data was truncated (10240/68073) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d3b89115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564d3b88e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564d3b89189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f390c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f390c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f390c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f390c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d3b826e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564d3b826c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564d3b80bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564d3b4bb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564d3b4badd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f390c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f390c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f390c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d3b4bacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c (1807 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llv
# | ...
# `---data was truncated (10240/101576) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606f6e0d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005606f6e0a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005606f6e0d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda91533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda9158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda91533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda9151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606f6da2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005606f6da2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005606f6d87b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005606f6a370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005606f6a36dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fda9151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda9151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda9151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606f6a36cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c (1808 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055669f25c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055669f2590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055669f25c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f934ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f934ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f934ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f934ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055669f1f1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055669f1f1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055669f1d6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055669ee860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055669ee85dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f934ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f934ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f934ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055669ee85cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c (1809 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ec38b815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561ec38b50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561ec38b889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c9ee1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c9ee725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c9ee1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c9ee03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ec384de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561ec384dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561ec3832b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561ec34e20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561ec34e1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1c9ee04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c9ee050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c9ee050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ec34e1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c (1810 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555978a2915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555978a260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555978a2989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28ca849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28ca8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28ca849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28ca831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559789bee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005559789bec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005559789a3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005559786530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555978652dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f28ca832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28ca8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28ca8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555978652cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c (1811 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vect
# | ...
# `---data was truncated (10240/108856) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c1e267215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c1e266f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c1e267289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb8eb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb8eb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb8eb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb8eaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c1e2607e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c1e2607c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c1e25ecb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c1e229c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c1e229bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbb8eaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb8eaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb8eaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c1e229bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c (1812 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv
# | ...
# `---data was truncated (10240/165238) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055844017315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005584401700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055844017389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f41f9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41f978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f41f9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f41f971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558440108e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558440108c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005584400edb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055843fd9d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055843fd9cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f41f971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41f971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41f971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055843fd9ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/distributed-thin-lto/basic.ll (1813 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/basic.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll
# |  #0 0x000055ca76fa715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ca76fa40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ca76fa789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5cf041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5cf04725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5cf041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5cf0403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca76f3ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ca76f3cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ca76f21b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ca76bd10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ca76bd0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5cf0404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5cf04050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5cf04050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca76bd0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c (1814 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dcd446415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dcd44610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dcd446489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f104cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f104cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f104cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f104cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dcd43f9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dcd43f9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dcd43deb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dcd408e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dcd408ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f104cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f104cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f104cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dcd408dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c (1815 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056161d6bb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056161d6b80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056161d6bb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ea6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ea66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ea6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ea6631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056161d650e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056161d650c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056161d635b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056161d2e50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056161d2e4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4ea6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ea66330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ea66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056161d2e4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c (1816 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056287e99d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056287e99a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056287e99d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f071c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f071c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f071c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f071c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056287e932e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056287e932c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056287e917b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056287e5c70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056287e5c6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f071c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f071c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f071c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056287e5c6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c (1817 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.
# | ...
# `---data was truncated (10240/72143) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055586513915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005558651360f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055586513989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb1d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb1d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb1d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb1d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558650cee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005558650cec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005558650b3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555864d630b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555864d62dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feb1d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb1d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb1d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555864d62cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c (1818 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractva
# | ...
# `---data was truncated (10240/27866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e0e47a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562e0e4770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562e0e47a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4294333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f429438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4294333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f429431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e0e40fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562e0e40fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562e0e3f4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562e0e0a40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562e0e0a3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f429431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f429431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f429431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e0e0a3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c (1819 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_u8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055786132315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005578613200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055786132389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca7b41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca7b4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca7b41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca7b403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578612b8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005578612b8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055786129db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557860f4d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557860f4cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fca7b404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca7b4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca7b4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557860f4ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c (1820 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646373ad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005646373aa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005646373ad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87b0e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87b0e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87b0e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87b0e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564637342e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564637342c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564637327b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564636fd70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564636fd6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f87b0e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87b0e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87b0e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564636fd6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/sve/orn.c (1821 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sve/orn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5 has no command after substitutions
# RUN: at line 6 has no command after substitutions
# RUN: at line 8 has no command after substitutions
# RUN: at line 9 has no command after substitutions
# RUN: at line 10 has no command after substitutions
# RUN: at line 12
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve  -o -                                  -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c        | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,16)
# | define dso_local <vscale x 16 x i1> @test_svorn_b_z(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2) #0 {
# | entry:
# |   %pg.addr = alloca <vscale x 16 x i1>, align 2
# |   %op1.addr = alloca <vscale x 16 x i1>, align 2
# |   %op2.addr = alloca <vscale x 16 x i1>, align 2
# |   store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 2
# |   %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %op2.addr, align 2
# |   %3 = call <vscale x 16 x i1> @llvm.aarch64.sve.orn.z.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.aarch64.sve.orn.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S
# |  #0 0x0000558b1fca515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558b1fca20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558b1fca589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6778e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6778ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6778e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6778e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b1fc3ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558b1fc3ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558b1fc1fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558b1f8cf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558b1f8cedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6778e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6778e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6778e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b1f8cecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c (1822 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i6
# | ...
# `---data was truncated (10240/47604) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eded5ff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eded5fc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eded5ff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7e2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7e2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7e2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7e2d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eded594e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eded594c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eded579b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eded2290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eded228dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc7e2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7e2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7e2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eded228cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c (1823 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b71af515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558b71af20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558b71af589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c3dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c3dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c3dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c3dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b71a8ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558b71a8ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558b71a6fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558b7171f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558b7171edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9c3dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c3dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c3dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b7171ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c (1824 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnjn_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnjn_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnjn_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnjn_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnjn_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <v
# | ...
# `---data was truncated (10240/157769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563890a9615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563890a930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563890a9689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5fa049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5fa0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5fa049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5fa031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563890a2be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563890a2bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563890a10b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005638906c00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005638906bfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc5fa032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5fa0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5fa0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638906bfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c (1825 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vcreate_bf16(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__promote = alloca i64, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__promote, align 8
# |   %1 = load <4 x bfloat>, ptr %__promote, align 8
# |   store <4 x bfloat> %1, ptr %__ret, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %2, ptr %tmp, align 8
# |   %3 = load <4 x bfloat>, ptr %tmp, align 8
# |   ret <4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vcombine_bf16(<4 x bfloat> noundef %low, <4 x bfloat> noundef %high) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x bfloat>, align 8
# |   %__p1.addr.i = alloca <4 x bfloat>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 16
# |   %low.addr = alloca <4 x bfloat>, align 8
# |   %high.addr = alloca <4 x bfloat>, align 8
# |   store <4 x bfloat> %low, ptr %low.addr, align 8
# |   store <4 x bfloat> %high, ptr %high.addr, align 8
# |   %0 = load <4 x bfloat>, ptr %low.addr, align 8
# |   %1 = load <4 x bfloat>, ptr %high.addr, align 8
# |   store <4 x bfloat> %0, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   %3 = load <4 x bfloat>, ptr %__p1.addr.i, align 8
# |   %shuffle.i = shufflevector <4 x bfloat> %2, <4 x bfloat> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
# |   store <8 x bfloat> %shuffle.i, ptr %__ret.i, align 16
# |   %4 = load <8 x bfloat>, ptr %__ret.i, align 16
# |   ret <8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x bfloat> @test_vset_lane_bf16(bfloat noundef %a, <4 x bfloat> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca bfloat, align 2
# |   %v.addr = alloca <4 x bfloat>, align 8
# |   %__ret = alloca <4 x bfloat>, align 8
# |   %__s0 = alloca bfloat, align 2
# |   %__s1 = alloca <4 x bfloat>, align 8
# |   %ref.tmp = alloca <4 x bfloat>, align 8
# |   %tmp = alloca <4 x bfloat>, align 8
# |   store bfloat %a, ptr %a.addr, align 2
# |   store <4 x bfloat> %v, ptr %v.addr, align 8
# |   %0 = load bfloat, ptr %a.addr, align 2
# |   store bfloat %0, ptr %__s0, align 2
# |   %1 = load <4 x bfloat>, ptr %v.addr, align 8
# |   store <4 x bfloat> %1, ptr %__s1, align 8
# |   %2 = load bfloat, ptr %__s0, align 2
# |   %3 = load <4 x bfloat>, ptr %__s1, align 8
# |   %vset_lane = insertelement <4 x bfloat> %3, bfloat %2, i32 1
# |   store <4 x bfloat> %vset_lane, ptr %ref.tmp, align 8
# |   %4 = load <4 x bfloat>, ptr %ref.tmp, align 8
# |   store <4 x bfloat> %4, ptr %__ret, align 8
# |   %5 = load <4 x bfloat>, ptr %__ret, align 8
# |   store <4 x bfloat> %5, ptr %tmp, align 8
# |   %6 = load <4 x bfloat>, ptr %tmp, align 8
# |   ret <4 x bfloat> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x bfloat> @test_vsetq_lane_bf16(bfloat noundef %a, <8 x bfloat> noundef %v) #0 {
# | entry:
# |   %a.addr = alloca bfloat, align 2
# |   %v.addr = alloca <8 x bfloat>, align 16
# |   %__ret = alloca <8 x bfloat>, align 16
# |   %__s0 = alloca bfloat, align 2
# |   %__s1 = alloca <8 x bfloat>, align 16
# |   %ref.tmp = alloca <8 x bfloat>, align 16
# |   %tmp = alloca <8 x bfloat>, align 16
# |   store bfloat %a, ptr %a.addr, align 2
# |   store <8 x bfloat> %v, ptr %v.addr, align 16
# |   %0 = load bfloat, ptr %a.addr, align 2
# |   store bfloat %0, ptr %__s0, align 2
# |   %1 = load <8 x bfloat>, ptr %v.addr, align 16
# |   store <8 x bfloat> %1, ptr %__s1, align 16
# |   %2 = load bfloat, ptr %__s0, align 2
# |   %3 = load <8 x bfloat>, ptr %__s1, align 16
# |   %vset_lane = insertelement <8 x bfloat> %3, bfloat %2, i32 7
# |   store <8 x bfloat> %vset_lane, ptr %ref.tmp, align 16
# |   %4 = load <8 x bfloat>, ptr %ref.tmp, align 16
# |   store <8 x bfloat> %4, ptr %__ret, align 16
# |   %5 = load <8 x bfloat>, ptr %__ret, align 16
# |   store <8 x bfloat> %5, ptr %tmp, align 16
# |   %6 = load <8 x bfloat>, ptr %tmp, align 16
# |   ret <8 x bfloat> %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x00005635ee8d215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005635ee8cf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005635ee8d289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc33d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc33d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc33d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc33d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635ee867e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005635ee867c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005635ee84cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005635ee4fc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005635ee4fbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc33d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc33d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc33d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635ee4fbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c (1826 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfabs_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfabs_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.
# | ...
# `---data was truncated (10240/30869) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e6bdfd015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e6bdfcd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e6bdfd089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2189649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21896a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2189649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2189631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6bdf65e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e6bdf65c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e6bdf4ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e6bdbfa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e6bdbf9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2189632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21896330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21896330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e6bdbf9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c (1827 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ea8e2315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559ea8e200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559ea8e2389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87fc733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87fc78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87fc733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87fc71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ea8db8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559ea8db8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559ea8d9db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559ea8a4d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559ea8a4cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f87fc71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87fc71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87fc71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ea8a4ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c (1828 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005623eb6a415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005623eb6a10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005623eb6a489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ce0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ce098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ce0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ce091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623eb639e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005623eb639c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005623eb61eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005623eb2ce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005623eb2cddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3ce091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ce091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ce091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623eb2cdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c (1829 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range
# | ...
# `---data was truncated (10240/302397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055736c9d115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055736c9ce0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055736c9d189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f384df05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f384df5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f384df05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f384deed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055736c966e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055736c966c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055736c94bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055736c5fb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055736c5fadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f384deeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f384deef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f384deef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055736c5facc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c (1830 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define d
# | ...
# `---data was truncated (10240/12208) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e0199a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557e019970f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557e0199a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c73a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c73aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c73a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c73a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e0192fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557e0192fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557e01914b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557e015c40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557e015c3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8c73a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c73a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c73a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e015c3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c (1831 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/12227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f92bdf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563f92bdc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563f92bdf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ad2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ad2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ad2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ad2f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f92b74e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563f92b74c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563f92b59b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563f928090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563f92808dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6ad2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ad2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ad2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f92808cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c (1832 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562aa26eb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562aa26e80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562aa26eb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fd1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fd1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fd1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fd1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562aa2680e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562aa2680c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562aa2665b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562aa23150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562aa2314dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9fd1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fd1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fd1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562aa2314cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c (1833 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsac_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsac_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsac_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsac_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsac_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = loa
# | ...
# `---data was truncated (10240/415311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605818e915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005605818e60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005605818e989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe0ba449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0ba4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe0ba449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0ba431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056058187ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056058187ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560581863b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005605815130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560581512dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe0ba432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0ba4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0ba4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560581512cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c (1834 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b602b6d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b602b6a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b602b6d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1152049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11520a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1152049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1152031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b602b02e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b602b02c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b602ae7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b6027970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b602796dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1152032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11520330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11520330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b602796cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c (1835 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9735f615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f9735f30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f9735f689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdeb9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdeb9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdeb9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdeb9e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f97358be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f97358bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f973570b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f9732200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f97321fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdeb9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdeb9e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdeb9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f97321fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c (1836 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load p
# | ...
# `---data was truncated (10240/28353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056244a22c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056244a2290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056244a22c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ea2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ea24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ea2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ea2431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056244a1c1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056244a1c1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056244a1a6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562449e560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562449e55dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7ea2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ea24330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ea24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562449e55cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c (1837 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c33499315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c3349900f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c33499389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff64cf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff64cf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff64cf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff64ceed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c334928e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c334928c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c33490db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c3345bd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c3345bcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff64ceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff64ceef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff64ceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3345bccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c (1838 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595fc77215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005595fc76f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005595fc77289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff849249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8492a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff849249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff849231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595fc707e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005595fc707c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005595fc6ecb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005595fc39c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005595fc39bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff849232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8492330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8492330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595fc39bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c (1839 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 1, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 1)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_n_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_n_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %.splat, i32 1, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5bc5dd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a5bc5da0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a5bc5dd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f36b7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f36b74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f36b7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f36b7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5bc572e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a5bc572c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a5bc557b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a5bc2070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a5bc206dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f36b7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f36b74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f36b74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5bc206cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c (1840 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define ds
# | ...
# `---data was truncated (10240/95215) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b036bdd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b036bda0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b036bdd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f10bcf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10bcf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f10bcf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10bcf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b036b72e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b036b72c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b036b57b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b0368070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b036806dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f10bcf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10bcf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10bcf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b036806cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c (1841 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oge half %1, 0.000000e+00
# |   %vcgez = sext i1 %2 to i16
# |   store i16 %vcgez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgtzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ogt half %1, 0.000000e+00
# |   %vcgtz = sext i1 %2 to i16
# |   store i16 %vcgtz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vclezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ole half %1, 0.000000e+00
# |   %vclez = sext i1 %2 to i16
# |   store i16 %vclez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcltzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp olt half %1, 0.000000e+00
# |   %vcltz = sext i1 %2 to i16
# |   store i16 %vcltz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = sitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = sitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = sitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = uitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = uitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = uitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcvth_s16_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s16_f16 = call i16 @llvm.fptosi.sat.i16.f16(half %1)
# |   store i16 %vcvth_s16_f16, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.fptosi.sat.i16.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vcvth_s32_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s32_f16 = call i32 @llvm.fptosi.sat.i32.f16(half %1)
# |   store i32 %vcvth_s32_f16, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.fptosi.sat.i32.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_vcvth_s64_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s64_f16 = call i64 @llvm.fptosi.sat.i64.f16(half %1)
# |   store i64 %vcvth_s64_f16, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.fptosi.sat.i64.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcvth_u16_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   st
# | ...
# `---data was truncated (10240/53064) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a1ec3515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560a1ec320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560a1ec3589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95b4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95b4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95b4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95b4c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a1ebcae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560a1ebcac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560a1ebafb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560a1e85f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560a1e85edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f95b4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95b4c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95b4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a1e85ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c (1842 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_i16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nx
# | ...
# `---data was truncated (10240/78682) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3ed07d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b3ed07a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b3ed07d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ce901bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ce90725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ce901ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ce9003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3ed012e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b3ed012c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b3ecff7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b3ecca70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b3ecca6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0ce9004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ce90050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ce90050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3ecca6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c (1843 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2_tu(<vscale x 16 x 
# | ...
# `---data was truncated (10240/156463) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c00a5315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564c00a500f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564c00a5389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f53cbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53cbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f53cbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f53cbd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c009e8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564c009e8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564c009cdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564c0067d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564c0067cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f53cbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53cbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53cbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c0067ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c (1844 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vluxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double>, ptr 
# | ...
# `---data was truncated (10240/91267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8696d015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a8696cd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a8696d089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd981e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd981ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd981e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd981e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a869665e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a869665c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a86964ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a8692fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a8692f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd981e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd981e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd981e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8692f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c (1845 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a0a70a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557a0a7070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557a0a70a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc9c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc9c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc9c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc9c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a0a69fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557a0a69fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557a0a684b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557a0a3340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557a0a333dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcc9c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc9c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc9c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a0a333cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c (1846 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd3614115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fd3613e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fd3614189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea5681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea568725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea5681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea56803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd360d6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fd360d6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fd360bbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fd35d6b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fd35d6add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fea56804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea568050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea568050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd35d6acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c (1847 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs
# | ...
# `---data was truncated (10240/15504) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a29fd3415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a29fd310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a29fd3489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc255933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc25598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc255933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc25591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a29fcc9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a29fcc9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a29fcaeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a29f95e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a29f95ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc25591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc25591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc25591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a29f95dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c (1848 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/12177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3708e115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f3708de0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f3708e189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb79533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb7958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb79533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb7951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f370876e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f370876c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f37085bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f37050b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f37050add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbb7951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb7951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb7951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f37050acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c (1849 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_u8m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %bas
# | ...
# `---data was truncated (10240/20340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056298a72415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056298a7210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056298a72489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a20e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a20ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a20e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a20e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056298a6b9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056298a6b9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056298a69eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056298a34e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056298a34ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6a20e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a20e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a20e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056298a34dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c (1850 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/116259) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626f2fd715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005626f2fd40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005626f2fd789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4bee333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4bee38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4bee333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4bee31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626f2f6ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005626f2f6cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005626f2f51b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005626f2c010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005626f2c00dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4bee31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4bee31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4bee31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626f2c00cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c (1851 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c750a1d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c750a1a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c750a1d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8794f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8794f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8794f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8794f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7509b2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c7509b2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c750997b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c7506470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c750646dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8794f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8794f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8794f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c750646cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c (1852 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dac256415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dac25610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dac256489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d23505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d2355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d23505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d234ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dac24f9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dac24f9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dac24deb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dac218e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dac218ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9d234eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d234ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d234ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dac218dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c (1853 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560af3c1415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560af3c110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560af3c1489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd21941bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2194725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd21941ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd219403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560af3ba9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560af3ba9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560af3b8eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560af383e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560af383ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd219404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2194050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2194050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560af383dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c (1854 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633048d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005633048d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005633048d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2cbbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2cbbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2cbbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2cbbd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563304869e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563304869c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056330484eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005633044fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005633044fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2cbbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2cbbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2cbbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633044fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c (1855 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_u16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_u16mf2x3_m(<vscale x 2 x i1> %mask, ptr nound
# | ...
# `---data was truncated (10240/13515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c71509815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c7150950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c71509889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9eb0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9eb038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9eb0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9eb031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c71502de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c71502dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c715012b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c714cc20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c714cc1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9eb031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9eb031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9eb031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c714cc1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c (1856 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c0bc4115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563c0bc3e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563c0bc4189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b7c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b7c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b7c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b7c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c0bbd6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563c0bbd6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563c0bbbbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563c0b86b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563c0b86add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5b7c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b7c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b7c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c0b86acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c (1857 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a479b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562a479ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562a479b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9bf0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9bf0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9bf0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9bf0e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a47946e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562a47946c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562a4792bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562a475db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562a475dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9bf0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9bf0e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9bf0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a475dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c (1858 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/13161) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c3d29315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558c3d2900f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558c3d29389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa821733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa82178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa821733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa82171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c3d228e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558c3d228c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558c3d20db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558c3cebd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558c3cebcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa82171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa82171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa82171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c3cebccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c (1859 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c57c05915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c57c0560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c57c05989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9548f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9548f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9548f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9548f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c57bfeee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c57bfeec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c57bfd3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c57bc830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c57bc82dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9548f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9548f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9548f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c57bc82cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c (1860 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a5e67015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557a5e66d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557a5e67089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d84733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d8478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d84733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d8471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a5e605e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557a5e605c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557a5e5eab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557a5e29a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557a5e299dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8d8471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d8471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d8471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a5e299cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c (1861 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function
# | ...
# `---data was truncated (10240/22375) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a70dd8315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a70dd800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a70dd8389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feff0305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feff035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feff0305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feff02ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a70dd18e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a70dd18c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a70dcfdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a70d9ad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a70d9acdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feff02eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feff02ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feff02ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a70d9accc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c (1862 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056496b32615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056496b3230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056496b32689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f419ab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f419ab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f419ab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f419aaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056496b2bbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056496b2bbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056496b2a0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056496af500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056496af4fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f419aaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f419aaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f419aaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056496af4fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c (1863 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vect
# | ...
# `---data was truncated (10240/108856) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056458995815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005645899550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056458995889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fdc049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fdc0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fdc049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fdc031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005645898ede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005645898edc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005645898d2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005645895820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564589581dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2fdc032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fdc0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fdc0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564589581cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c (1864 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/94371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e4e2a3315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e4e2a300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e4e2a3389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fac249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fac2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fac249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fac231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e4e29c8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e4e29c8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e4e29adb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e4e265d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e4e265cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4fac232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fac2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fac2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4e265ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c (1865 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrec7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrec7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrec7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrec7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrec7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrec7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |  
# | ...
# `---data was truncated (10240/28350) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558281b4515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558281b420f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558281b4589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb75133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb7518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb75133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb7511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558281adae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558281adac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558281abfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055828176f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055828176edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcb7511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb7511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb7511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055828176ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/builtin-align.c (1866 of 27911)
******************** TEST 'Clang :: CodeGen/builtin-align.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 4
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple=x86_64-unknown-unknown -DTEST_VOID_PTR    -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR    -enable-var-scope '-D$PTRTYPE=i8'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple=x86_64-unknown-unknown -DTEST_VOID_PTR -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | @aligned_true = global i8 1, align 1
# | @aligned_false = global i8 0, align 1
# | @down_1 = global i32 992, align 4
# | @down_2 = global i32 256, align 4
# | @up_1 = global i32 1024, align 4
# | @up_2 = global i32 256, align 4
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @get_type() #0 {
# | entry:
# |   ret ptr null
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local zeroext i1 @is_aligned(ptr noundef %ptr, i32 noundef %align) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %align.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %align, ptr %align.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %align.addr, align 4
# |   %alignment = zext i32 %1 to i64
# |   %mask = sub i64 %alignment, 1
# |   %src_addr = ptrtoint ptr %0 to i64
# |   %set_bits = and i64 %src_addr, %mask
# |   %is_aligned = icmp eq i64 %set_bits, 0
# |   ret i1 %is_aligned
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @align_up(ptr noundef %ptr, i32 noundef %align) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %align.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %align, ptr %align.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %align.addr, align 4
# |   %alignment = zext i32 %1 to i64
# |   %mask = sub i64 %alignment, 1
# |   %over_boundary = getelementptr inbounds i8, ptr %0, i64 %mask
# |   %inverted_mask = xor i64 %mask, -1
# |   %aligned_result = call ptr @llvm.ptrmask.p0.i64(ptr %over_boundary, i64 %inverted_mask)
# |   ret ptr %aligned_result
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare ptr @llvm.ptrmask.p0.i64(ptr, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local ptr @align_down(ptr noundef %ptr, i32 noundef %align) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %align.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %align, ptr %align.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %align.addr, align 4
# |   %alignment = zext i32 %1 to i64
# |   %mask = sub i64 %alignment, 1
# |   %inverted_mask = xor i64 %mask, -1
# |   %aligned_result = call ptr @llvm.ptrmask.p0.i64(ptr %0, i64 %inverted_mask)
# |   ret ptr %aligned_result
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000556ce025415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556ce02510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556ce025489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f235fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f235fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f235fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f235fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ce01e9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556ce01e9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556ce01ceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556cdfe7e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556cdfe7ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f235fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f235fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f235fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556cdfe7dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope '-D$PTRTYPE=i8'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope -D$PTRTYPE=i8
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c (1867 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d58bdc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560d58bd90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560d58bdc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7873f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7873f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7873f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7873f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d58b71e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560d58b71c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560d58b56b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560d588060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560d58805dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7873f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7873f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7873f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d58805cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c (1868 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr =
# | ...
# `---data was truncated (10240/14319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607dc01a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005607dc0170f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005607dc01a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31b4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31b4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31b4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31b4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607dbfafe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005607dbfafc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005607dbf94b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005607dbc440b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005607dbc43dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f31b4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31b4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31b4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607dbc43cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c (1869 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a7e2bb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561a7e2b80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561a7e2bb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e87849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e878a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e87849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e87831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a7e250e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561a7e250c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561a7e235b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561a7dee50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561a7dee4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7e87832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e878330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e878330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a7dee4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c (1870 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Functi
# | ...
# `---data was truncated (10240/116949) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a9c2d715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559a9c2d40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559a9c2d789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9145505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f914555c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9145505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91454ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a9c26ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559a9c26cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559a9c251b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559a9bf010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559a9bf00dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f91454eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91454ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91454ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a9bf00cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c (1871 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16
# | ...
# `---data was truncated (10240/69305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585518d815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005585518d50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005585518d889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea2cb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea2cb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea2cb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea2caed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055855186de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055855186dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558551852b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005585515020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558551501dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fea2caeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea2caef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea2caef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558551501cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c (1872 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, 
# | ...
# `---data was truncated (10240/62087) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b12888a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b1288870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b12888a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9a7fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9a7faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9a7fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9a7fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b12881fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b12881fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b128804b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b1284b40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b1284b3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9a7fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9a7fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9a7fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b1284b3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c (1873 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captur
# | ...
# `---data was truncated (10240/30617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056121a2a815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056121a2a50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056121a2a889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14eca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14ecaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14eca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14eca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056121a23de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056121a23dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056121a222b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561219ed20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561219ed1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f14eca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14eca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14eca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561219ed1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c (1874 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563db4f3315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563db4f300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563db4f3389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f3c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f3c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f3c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f3c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563db4ec8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563db4ec8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563db4eadb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563db4b5d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563db4b5cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5f3c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f3c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f3c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563db4b5ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c (1875 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7a7f4b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e7a7f480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e7a7f4b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f057db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f057db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f057db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f057db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7a7ee0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e7a7ee0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e7a7ec5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e7a7b750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e7a7b74dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f057db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f057db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f057db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7a7b74cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c (1876 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/175163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055913860e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055913860b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055913860e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa918c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa918ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa918c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa918c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591385a3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005591385a3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559138588b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005591382380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559138237dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa918c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa918c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa918c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559138237cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c (1877 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a5bcff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563a5bcfc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563a5bcff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e64133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e6418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e64133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e6411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a5bc94e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563a5bc94c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563a5bc79b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563a5b9290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563a5b928dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4e6411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e6411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e6411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a5b928cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c (1878 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7486b415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d7486b10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d7486b489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f957b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f957b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f957b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f957b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d748649e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d748649c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d74862eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d7482de0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d7482dddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f957b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f957b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f957b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7482ddcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c (1879 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vabd.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vabs_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vabd.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vabs_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale 
# | ...
# `---data was truncated (10240/41102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d29975515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d2997520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d29975589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42eeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42eeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42eeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42eeb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d2996eae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d2996eac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d2996cfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d29937f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d29937edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f42eeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42eeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42eeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d29937ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c (1880 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ead5e6915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ead5e660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ead5e6989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6e9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6e98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6e9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6e9831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ead5dfee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ead5dfec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ead5de3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ead5a930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ead5a92dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb6e9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6e98330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6e98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ead5a92cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c (1881 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ddd1c2d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ddd1c2a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ddd1c2d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4625105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f462515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4625105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46250ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddd1bc2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ddd1bc2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ddd1ba7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ddd18570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ddd1856dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f46250eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46250ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46250ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddd1856cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c (1882 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566f2aaf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005566f2aac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005566f2aaf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd015449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0154a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd015449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd015431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566f2a44e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005566f2a44c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005566f2a29b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005566f26d90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005566f26d8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd015432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0154330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0154330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566f26d8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c (1883 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x flo
# | ...
# `---data was truncated (10240/101584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562df70a515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562df70a20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562df70a589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6716305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f671635c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6716305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67162ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562df703ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562df703ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562df701fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562df6ccf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562df6ccedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f67162eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67162ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67162ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562df6ccecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c (1884 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556aea6515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005556aea620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005556aea6589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3dd4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3dd4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3dd4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3dd4f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556ae9fae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005556ae9fac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005556ae9dfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005556ae68f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005556ae68edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3dd4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3dd4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3dd4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556ae68ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c (1885 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565228fd015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000565228fcd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000565228fd089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe187e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe187ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe187e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe187e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565228f65e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565228f65c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565228f4ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000565228bfa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000565228bf9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe187e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe187e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe187e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565228bf9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c (1886 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fbf3b6615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fbf3b630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fbf3b6689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f04a261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04a26725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f04a261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f04a2603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbf3afbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fbf3afbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fbf3ae0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fbf37900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fbf378fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f04a2604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04a26050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04a26050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbf378fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c (1887 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ec917715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556ec91740f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556ec917789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff341b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff341b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff341b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff341aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ec910ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556ec910cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556ec90f1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556ec8da10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556ec8da0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff341aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff341aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff341aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ec8da0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c (1888 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_i16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_u16m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648d3ba115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005648d3b9e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005648d3ba189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe11461bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1146725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe11461ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe114603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648d3b36e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005648d3b36c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005648d3b1bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005648d37cb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005648d37cadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe114604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1146050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1146050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648d37cacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c (1889 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x fl
# | ...
# `---data was truncated (10240/90693) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590ddcd615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005590ddcd30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005590ddcd689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc44f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc44f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc44f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc44f91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590ddc6be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005590ddc6bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005590ddc50b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005590dd9000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005590dd8ffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc44f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc44f91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc44f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590dd8ffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c (1890 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557980c6a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557980c670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557980c6a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7e0a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7e0a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7e0a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7e0a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557980bffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557980bffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557980be4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005579808940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557980893dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc7e0a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7e0a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7e0a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557980893cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c (1891 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfadd_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfadd_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfadd_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfadd_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfadd_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055610010115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005561000fe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055610010189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f6e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f6e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f6e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f6e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556100096e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556100096c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055610007bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005560ffd2b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005560ffd2add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5f6e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f6e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f6e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560ffd2acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c (1892 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_u8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %ba
# | ...
# `---data was truncated (10240/15594) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be5401515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055be540120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055be5401589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc8f3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8f3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc8f3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc8f3d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be53faae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055be53faac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055be53f8fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055be53c3f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055be53c3edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc8f3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8f3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8f3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be53c3ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c (1893 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629272ca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005629272c70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005629272ca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f55049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f550a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f55049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f55031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056292725fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056292725fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562927244b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562926ef40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562926ef3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2f55032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f550330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f550330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562926ef3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c (1894 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056113346a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005611334670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056113346a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f268b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f268b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f268b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f268b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611333ffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005611333ffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005611333e4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005611330940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561133093dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f268b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f268b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f268b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561133093cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c (1895 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = allo
# | ...
# `---data was truncated (10240/98179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557065c8f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557065c8c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557065c8f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b2f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b2f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b2f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b2f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557065c24e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557065c24c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557065c09b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005570658b90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005570658b8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1b2f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b2f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b2f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570658b8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c (1896 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/13649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb9530015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eb952fd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eb9530089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0985133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f098518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0985133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f098511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb95295e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eb95295c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eb9527ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eb94f2a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eb94f29dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f098511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f098511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f098511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb94f29cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c (1897 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare
# | ...
# `---data was truncated (10240/20141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9914b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c9914b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c9914b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9daf849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9daf8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9daf849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9daf831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c99144be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c99144bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c991430b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c9910e00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c9910dfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9daf832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9daf8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9daf8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9910dfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c (1898 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea30cb615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ea30cb30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ea30cb689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7050e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7050ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7050e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7050e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea30c4be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ea30c4bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ea30c30b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ea308e00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ea308dfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7050e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7050e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7050e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea308dfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c (1899 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055acd2ea415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055acd2ea10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055acd2ea489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a0f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a0f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a0f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a0f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055acd2e39e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055acd2e39c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055acd2e1eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055acd2ace0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055acd2acddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3a0f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a0f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a0f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055acd2acdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c (1900 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |  
# | ...
# `---data was truncated (10240/30268) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583a510915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005583a51060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005583a510989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5e8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5e8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5e8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5e8a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583a509ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005583a509ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005583a5083b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005583a4d330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005583a4d32dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb5e8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5e8a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5e8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583a4d32cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c (1901 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_u8mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_u8mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vec
# | ...
# `---data was truncated (10240/27595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f55fd5515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f55fd520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f55fd5589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1b9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1b958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1b9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1b951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f55fceae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f55fceac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f55fccfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f55f97f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f55f97edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc1b951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1b951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1b951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f55f97ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c (1902 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmaxu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmaxu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmaxu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmaxu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmaxu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmaxu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmaxu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmaxu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650a943315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005650a94300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005650a943389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f535661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53566725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f535661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5356603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650a93c8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005650a93c8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005650a93adb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005650a905d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005650a905cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5356604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53566050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53566050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650a905ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c (1903 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_i8mf8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_i8mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_i8mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_i8m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8ff_v_i8m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x i8>, i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8ff_v_i8m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 32 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 32 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x i8>, i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8ff_v_i8m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 64 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 64 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 64 x i8>, i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8ff_v_u8mf8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i8>, i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(<vscale x 1 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8ff_v_u8mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i8>, i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(<vscale x 2 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8ff_v_u8mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i8>, i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(<vscale x 4 x i8> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i8>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i8>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8ff_v_u8m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, al
# | ...
# `---data was truncated (10240/30013) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573d003b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005573d00380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005573d003b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c84a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c84aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c84a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c84a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573cffd0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005573cffd0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005573cffb5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005573cfc650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005573cfc64dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5c84a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c84a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c84a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573cfc64cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c (1904 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0b6eb915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c0b6eb60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c0b6eb989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb90d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb90d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb90d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb90d031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0b6e4ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c0b6e4ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c0b6e33b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c0b6ae30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c0b6ae2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb90d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb90d0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb90d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0b6ae2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c (1905 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056012d31215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056012d30f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056012d31289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fa9305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fa935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fa9305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fa92ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056012d2a7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056012d2a7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056012d28cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056012cf3c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056012cf3bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9fa92eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fa92ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fa92ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056012cf3bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c (1906 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = loa
# | ...
# `---data was truncated (10240/14529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c84e3715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556c84e340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556c84e3789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2beac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2beaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2beac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2beac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c84dcce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556c84dccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556c84db1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556c84a610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556c84a60dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2beac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2beac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2beac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c84a60cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c (1907 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0ce76b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e0ce7680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e0ce76b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9cb0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9cb08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9cb0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9cb0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0ce700e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e0ce700c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e0ce6e5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e0ce3950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e0ce394dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9cb0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9cb08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9cb08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0ce394cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c (1908 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x
# | ...
# `---data was truncated (10240/68062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd400d115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cd400ce0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cd400d189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e1781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e178725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e1781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e17803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd40066e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cd40066c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cd4004bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cd3fcfb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cd3fcfadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0e17804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e178050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e178050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd3fcfacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c (1909 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_u16m1x6_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ee2e2f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563ee2e2c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563ee2e2f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe51df05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe51df5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe51df05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe51deed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ee2dc4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563ee2dc4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563ee2da9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563ee2a590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563ee2a58dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe51deeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe51deef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe51deef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ee2a58cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c (1910 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,10
# | ...
# `---data was truncated (10240/48393) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4da9c715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f4da9c40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f4da9c789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9330d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9330d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9330d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9330d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4da95ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f4da95cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f4da941b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f4da5f10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f4da5f0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9330d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9330d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9330d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4da5f0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c (1911 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba7be8515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ba7be820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ba7be8589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3440733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f344078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3440733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f344071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba7be1ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ba7be1ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ba7bdffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ba7baaf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ba7baaedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f344071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f344071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f344071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba7baaecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c (1912 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.a
# | ...
# `---data was truncated (10240/32394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bfd1ed215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bfd1ecf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bfd1ed289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2f1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2f1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2f1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2f1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfd1e67e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bfd1e67c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bfd1e4cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bfd1afc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bfd1afbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc2f1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2f1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2f1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfd1afbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c (1913 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz
# | ...
# `---data was truncated (10240/58675) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562dd689115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562dd688e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562dd689189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b7be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b7bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b7be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b7be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562dd6826e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562dd6826c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562dd680bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562dd64bb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562dd64badd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5b7be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b7be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b7be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562dd64bacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c (1914 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <v
# | ...
# `---data was truncated (10240/280163) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f2b280615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f2b28030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f2b280689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cdcf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cdcf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cdcf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cdceed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f2b279be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f2b279bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f2b2780b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f2b24300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f2b242fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7cdceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cdceef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cdceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f2b242fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c (1915 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_i16mf2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |  
# | ...
# `---data was truncated (10240/22074) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055608e30515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055608e3020f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055608e30589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2571e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2571ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2571e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2571e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055608e29ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055608e29ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055608e27fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055608df2f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055608df2edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2571e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2571e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2571e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055608df2ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c (1916 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 
# | ...
# `---data was truncated (10240/117397) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c82884415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c8288410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c82884489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f952b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f952b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f952b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f952b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8287d9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c8287d9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c8287beb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c82846e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c82846ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f952b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f952b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f952b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c82846dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c (1917 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ed52b915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556ed52b60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556ed52b989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74a5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74a598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74a5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74a591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ed524ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556ed524ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556ed5233b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556ed4ee30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556ed4ee2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f74a591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74a591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74a591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ed4ee2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c (1918 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredusum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredusum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   
# | ...
# `---data was truncated (10240/81304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595e07d615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005595e07d30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005595e07d689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5322533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f532258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5322533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f532251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595e076be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005595e076bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005595e0750b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005595e04000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005595e03ffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f532251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f532251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f532251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595e03ffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c (1919 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e1e73b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561e1e7380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561e1e73b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0cfda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0cfdaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0cfda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0cfda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e1e6d0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561e1e6d0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561e1e6b5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561e1e3650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561e1e364dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0cfda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0cfda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0cfda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e1e364cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c (1920 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559127b7615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559127b730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559127b7689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad4f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad4f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad4f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad4f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559127b0be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559127b0bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559127af0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005591277a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055912779fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fad4f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad4f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad4f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055912779fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c (1921 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa5153e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aa5153b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aa5153e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa443a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa443a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa443a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa443a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa514d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aa514d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aa514b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aa511680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aa51167dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa443a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa443a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa443a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa51167cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c (1922 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e9bed115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555e9bece0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555e9bed189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e72c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e72ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e72c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e72c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e9be66e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555e9be66c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555e9be4bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555e9bafb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555e9bafadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4e72c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e72c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e72c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e9bafacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c (1923 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 
# | ...
# `---data was truncated (10240/223863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629a1ba815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005629a1ba50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005629a1ba889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08e0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08e02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08e0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08e0231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629a1b3de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005629a1b3dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005629a1b22b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005629a17d20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005629a17d1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f08e0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08e02330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08e02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629a17d1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c (1924 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055884e83715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055884e8340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055884e83789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7208049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72080a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7208049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7208031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055884e7cce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055884e7ccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055884e7b1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055884e4610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055884e460dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7208032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72080330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72080330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055884e460cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c (1925 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i
# | ...
# `---data was truncated (10240/215478) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fdec78715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fdec7840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fdec78789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f43ce733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f43ce78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f43ce733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f43ce71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fdec71ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fdec71cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fdec701b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fdec3b10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fdec3b0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f43ce71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f43ce71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f43ce71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fdec3b0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c (1926 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055726343c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005572634390f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055726343c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29c9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29c918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29c9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29c911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572633d1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005572633d1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005572633b6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005572630660b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557263065dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f29c911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29c911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29c911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557263065cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c (1927 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c  -check-prefix=RV32ZBC
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmul_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.clmul.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmulh_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.clmulh.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clmulr_32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.clmulr.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.clmul.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.clmulh.i32(i32, i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.clmulr.i32(i32, i32) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbc,+zbkc" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbc1p0_zbkc1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8217fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a8217f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a8217fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51ea733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51ea78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51ea733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51ea71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a821790e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a821790c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a821775b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a8214250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a821424dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f51ea71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51ea71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51ea71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a821424cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c (1928 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055878df5515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055878df520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055878df5589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fc1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fc1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fc1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fc1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055878deeae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055878deeac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055878decfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055878db7f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055878db7edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9fc1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fc1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fc1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055878db7ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c (1929 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64
# | ...
# `---data was truncated (10240/14036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055660806a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005566080670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055660806a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f080ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f080aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f080ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f080ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556607fffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556607fffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556607fe4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556607c940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556607c93dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f080ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f080ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f080ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556607c93cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c (1930 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i8>
# | ...
# `---data was truncated (10240/29371) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b6966a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559b696670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559b6966a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8132d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8132d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8132d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8132d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b695ffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559b695ffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559b695e4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559b692940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559b69293dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8132d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8132d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8132d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b69293cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c (1931 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1up_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | de
# | ...
# `---data was truncated (10240/34581) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c2ea45f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c2ea45c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c2ea45f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6240333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f624038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6240333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f624031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2ea3f4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c2ea3f4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c2ea3d9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c2ea0890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c2ea088dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f624031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f624031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f624031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2ea088cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c (1932 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %binde
# | ...
# `---data was truncated (10240/94227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056499a28215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056499a27f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056499a28289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe183c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe183c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe183c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe183c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056499a217e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056499a217c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056499a1fcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564999eac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564999eabdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe183c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe183c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe183c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564999eabcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c (1933 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf2_u32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16m1_u32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>
# | ...
# `---data was truncated (10240/43625) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598a725415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005598a72510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005598a725489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f973a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f973a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f973a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f973a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598a71e9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005598a71e9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005598a71ceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005598a6e7e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005598a6e7ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f973a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f973a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f973a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598a6e7dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c (1934 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.
# | ...
# `---data was truncated (10240/101402) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559399cab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559399ca80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559399cab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8327a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8327a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8327a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8327a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559399c40e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559399c40c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559399c25b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005593998d50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005593998d4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8327a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8327a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8327a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593998d4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c (1935 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmseq_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmseq_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/171381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aedab3015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aedab2d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aedab3089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcbd8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcbd838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcbd8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcbd831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aedaac5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aedaac5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aedaaaab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aeda75a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aeda759dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcbd831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcbd831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcbd831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aeda759cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c (1936 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba3152a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ba315270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ba3152a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffacd41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffacd4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffacd41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffacd403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba314bfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ba314bfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ba314a4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ba311540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ba31153dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ffacd404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffacd4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffacd4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba31153cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp (1937 of 27911)
******************** TEST 'Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O1 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp -o - -triple=x86_64-linux-gnu | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O1 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp -o - -triple=x86_64-linux-gnu
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ab1Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %land.lhs.true, label %land.end
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %land.rhs, label %land.end
# | 
# | land.rhs:                                         ; preds = %land.lhs.true
# |   %call2 = call noundef zeroext i1 @_Z1av()
# |   br label %land.end
# | 
# | land.end:                                         ; preds = %land.rhs, %land.lhs.true, %entry
# |   %0 = phi i1 [ false, %land.lhs.true ], [ false, %entry ], [ %call2, %land.rhs ]
# |   %conv = zext i1 %0 to i64
# |   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
# |   %tobool = icmp ne i64 %expval, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.end
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %2 = load i32, ptr %1, align 4, !tbaa !11
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.end
# |   %3 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %4 = load i32, ptr %3, align 4, !tbaa !11
# |   %dec = add nsw i32 %4, -1
# |   store i32 %dec, ptr %3, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | declare noundef zeroext i1 @_Z1av() #1
# | 
# | declare noundef zeroext i1 @_Z1bv() #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.expect.i64(i64, i64) #2
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z2alRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   %call.expval = call i1 @llvm.expect.i1(i1 %call, i1 true)
# |   br i1 %call.expval, label %land.lhs.true, label %if.else
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   %call1.expval = call i1 @llvm.expect.i1(i1 %call1, i1 true)
# |   br i1 %call1.expval, label %land.lhs.true2, label %if.else
# | 
# | land.lhs.true2:                                   ; preds = %land.lhs.true
# |   %call3 = call noundef zeroext i1 @_Z1cv()
# |   %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 true)
# |   br i1 %call3.expval, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.lhs.true2
# |   %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %1 = load i32, ptr %0, align 4, !tbaa !11
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %0, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.lhs.true2, %land.lhs.true, %entry
# |   %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %3 = load i32, ptr %2, align 4, !tbaa !11
# |   %dec = add nsw i32 %3, -1
# |   store i32 %dec, ptr %2, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i1 @llvm.expect.i1(i1, i1) #2
# | 
# | declare noundef zeroext i1 @_Z1cv() #1
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ab0Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %land.lhs.true, label %land.end
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %land.rhs, label %land.end
# | 
# | land.rhs:                                         ; preds = %land.lhs.true
# |   %call2 = call noundef zeroext i1 @_Z1cv()
# |   br label %land.end
# | 
# | land.end:                                         ; preds = %land.rhs, %land.lhs.true, %entry
# |   %0 = phi i1 [ false, %land.lhs.true ], [ false, %entry ], [ %call2, %land.rhs ]
# |   %conv = zext i1 %0 to i64
# |   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 0)
# |   %tobool = icmp ne i64 %expval, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.end
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %2 = load i32, ptr %1, align 4, !tbaa !11
# |   %inc = add nsw i32 %2, 1
# |   store i32 %inc, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.end
# |   %3 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %4 = load i32, ptr %3, align 4, !tbaa !11
# |   %dec = add nsw i32 %4, -1
# |   store i32 %dec, ptr %3, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z2auRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %land.lhs.true, label %if.else
# | 
# | land.lhs.true:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %land.lhs.true2, label %if.else
# | 
# | land.lhs.true2:                                   ; preds = %land.lhs.true
# |   %call3 = call noundef zeroext i1 @_Z1cv()
# |   %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 false)
# |   br i1 %call3.expval, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %land.lhs.true2
# |   %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %1 = load i32, ptr %0, align 4, !tbaa !11
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %0, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %land.lhs.true2, %land.lhs.true, %entry
# |   %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %3 = load i32, ptr %2, align 4, !tbaa !11
# |   %dec = add nsw i32 %3, -1
# |   store i32 %dec, ptr %2, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ob1Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %lor.end, label %lor.lhs.false
# | 
# | lor.lhs.false:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %lor.end, label %lor.rhs
# | 
# | lor.rhs:                                          ; preds = %lor.lhs.false
# |   %call2 = call noundef zeroext i1 @_Z1av()
# |   br label %lor.end
# | 
# | lor.end:                                          ; preds = %lor.rhs, %lor.lhs.false, %entry
# |   %0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %call2, %lor.rhs ]
# |   %conv = zext i1 %0 to i64
# |   %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
# |   %tobool = icmp ne i64 %expval, 0
# |   br i1 %tobool, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %lor.end
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   store i32 0, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %lor.end
# |   %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %3 = load i32, ptr %2, align 4, !tbaa !11
# |   %dec = add nsw i32 %3, -1
# |   store i32 %dec, ptr %2, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z2olRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %if.then, label %lor.lhs.false
# | 
# | lor.lhs.false:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %if.then, label %lor.lhs.false2
# | 
# | lor.lhs.false2:                                   ; preds = %lor.lhs.false
# |   %call3 = call noundef zeroext i1 @_Z1cv()
# |   %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 true)
# |   br i1 %call3.expval, label %if.then, label %if.else
# | 
# | if.then:                                          ; preds = %lor.lhs.false2, %lor.lhs.false, %entry
# |   %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   store i32 0, ptr %0, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.else:                                          ; preds = %lor.lhs.false2
# |   %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10
# |   %2 = load i32, ptr %1, align 4, !tbaa !11
# |   %dec = add nsw i32 %2, -1
# |   store i32 %dec, ptr %1, align 4, !tbaa !11
# |   br label %if.end
# | 
# | if.end:                                           ; preds = %if.else, %if.then
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress nounwind
# | define dso_local void @_Z3ob0Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 {
# | entry:
# |   %i.addr = alloca ptr, align 8
# |   store ptr %i, ptr %i.addr, align 8, !tbaa !6
# |   %call = call noundef zeroext i1 @_Z1av()
# |   br i1 %call, label %lor.end, label %lor.lhs.false
# | 
# | lor.lhs.false:                                    ; preds = %entry
# |   %call1 = call noundef zeroext i1 @_Z1bv()
# |   br i1 %call1, label %lor.end, label %lor.rhs
# | 
# | lor.rhs:     
# | ...
# `---data was truncated (10240/28468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S
# |  #0 0x000055db655cc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055db655c90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055db655cc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff2d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff2d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff2d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff2d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db65561e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055db65561c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055db65546b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055db651f60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055db651f5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007eff2d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff2d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff2d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db651f5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c (1938 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611962a415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005611962a10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005611962a489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91eab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91eab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91eab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91eaaed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561196239e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561196239c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056119621eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561195ece0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561195ecddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f91eaaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91eaaef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91eaaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561195ecdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c (1939 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvt_x_x_v_i32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvt_x_x_v_i64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvt_x_x_v_i64m2(<vscale x 2 x i32> %src, i64
# | ...
# `---data was truncated (10240/29175) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626ad74b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005626ad7480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005626ad74b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa956933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa95698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa956933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa95691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626ad6e0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005626ad6e0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005626ad6c5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005626ad3750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005626ad374dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa95691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa95691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa95691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626ad374cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c (1940 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmin.
# | ...
# `---data was truncated (10240/69313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055681084b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005568108480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055681084b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff337049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3370a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff337049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff337031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568107e0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005568107e0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005568107c5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005568104750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556810474dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff337032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3370330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3370330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556810474cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c (1941 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tupl
# | ...
# `---data was truncated (10240/53454) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557387aee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557387aeb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557387aee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c72a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c72aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c72a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c72a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557387a83e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557387a83c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557387a68b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005573877180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557387717dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2c72a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c72a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c72a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557387717cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c (1942 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   
# | ...
# `---data was truncated (10240/12381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca0182415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ca018210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ca0182489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f63c8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63c8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f63c8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63c8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca017b9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ca017b9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ca0179eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ca0144e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ca0144ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f63c8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63c8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63c8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca0144dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c (1943 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1db6da15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e1db6d70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e1db6da89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b9001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b900725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b9001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b90003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1db66fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e1db66fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e1db654b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e1db3040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e1db303dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3b90004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b900050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b900050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1db303cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c (1944 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(
# | ...
# `---data was truncated (10240/179185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8f189715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e8f18940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e8f189789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdbfef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdbfef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdbfef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdbfeeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8f182ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e8f182cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e8f1811b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e8f14c10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e8f14c0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdbfeeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdbfeeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdbfeeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8f14c0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c (1945 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_xu_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_xu_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_x_f_v_i32mf2(<
# | ...
# `---data was truncated (10240/119297) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055758972615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005575897230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055758972689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab88c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab88ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab88c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab88c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575896bbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005575896bbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005575896a0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005575893500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055758934fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fab88c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab88c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab88c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055758934fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c (1946 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e72afc215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e72afbf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e72afc289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a6a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a6a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a6a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a6a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e72af57e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e72af57c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e72af3cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e72abec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e72abebdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1a6a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a6a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a6a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e72abebcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c (1947 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da3546315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055da354600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055da3546389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44afc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44afca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44afc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44afc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da353f8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055da353f8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055da353ddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055da3508d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055da3508cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f44afc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44afc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44afc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da3508ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c (1948 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_v
# | ...
# `---data was truncated (10240/216258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c4447415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555c444710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555c4447489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ec8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ec86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ec8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ec8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c44409e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555c44409c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555c443eeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555c4409e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555c4409ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3ec8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ec86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ec86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c4409dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c (1949 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wv_i8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnclip_wx_i8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wv_i8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnclip_wx_i8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wv_i8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnclip_wx_i8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wv_i8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnclip_wx_i8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wv_i8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnclip_wx_i8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 0,
# | ...
# `---data was truncated (10240/69839) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e20537615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e2053730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e20537689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f1c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f1c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f1c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f1c31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e20530be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e20530bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e2052f0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e204fa00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e204f9fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3f1c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f1c31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f1c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e204f9fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c (1950 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5bf6de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b5bf6db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b5bf6de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd9e2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd9e2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd9e2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd9e2b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b5bf673e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b5bf673c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b5bf658b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b5bf3080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b5bf307dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd9e2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd9e2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd9e2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b5bf307cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c (1951 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadd_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadd_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadd_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadd_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadd_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056354fbe415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056354fbe10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056354fbe489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe30b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe30b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe30b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe30b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056354fb79e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056354fb79c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056354fb5eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056354f80e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056354f80ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe30b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe30b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe30b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056354f80dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c (1952 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a37ea315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559a37ea00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559a37ea389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f155a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f155a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f155a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f155a003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a37e38e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559a37e38c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559a37e1db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559a37acd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559a37accdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f155a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f155a0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f155a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a37acccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c (1953 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 
# | ...
# `---data was truncated (10240/12465) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005615b657215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005615b656f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005615b657289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe13333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe1338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe13333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe1331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005615b6507e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005615b6507c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005615b64ecb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005615b619c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005615b619bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbe1331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe1331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe1331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005615b619bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c (1954 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ae368e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560ae368b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560ae368e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9074533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f907458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9074533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f907451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ae3623e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560ae3623c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560ae3608b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560ae32b80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560ae32b7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f907451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f907451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f907451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ae32b7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c (1955 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, ali
# | ...
# `---data was truncated (10240/60334) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7803fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d7803f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d7803fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee45c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee45ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee45c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee45c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d780391e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d780391c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d780376b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d7800260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d780025dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fee45c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee45c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee45c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d780025cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c (1956 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c  -check-prefix=RV32ZBB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @orc_b_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.orc.b.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clz_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @ctz_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.cttz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @cpop_32(i32 noundef %a) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.ctpop.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.orc.b.i32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.cttz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctpop.i32(i32) #2
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614e6ded15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005614e6dea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005614e6ded89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a61b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a61b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a61b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a61b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005614e6d82e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005614e6d82c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005614e6d67b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005614e6a170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005614e6a16dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3a61b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a61b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a61b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614e6a16cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c (1957 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/149137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c2f549615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c2f54930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c2f549689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2ab249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2ab2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2ab249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2ab231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2f542be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c2f542bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c2f5410b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c2f50c00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c2f50bfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa2ab232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2ab2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2ab2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2f50bfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vbicq.c (1958 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vbicq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = xor <16 x i8> %1, splat (i8 -1)
# |   %3 = and <16 x i8> %0, %2
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = xor <8 x i16> %1, splat (i16 -1)
# |   %3 = and <8 x i16> %0, %2
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = xor <4 x i32> %1, splat (i32 -1)
# |   %3 = and <4 x i32> %0, %2
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbicq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = xor <4 x i32> %3, splat (i32 -1)
# |   %5 = and <4 x i32> %1, %4
# |   %6 = bitcast <4 x i32> %5 to <4 x float>
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbicq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbicq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr
# | ...
# `---data was truncated (10240/11060) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ee460015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560ee45fd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560ee460089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c9d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c9d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c9d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c9d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ee4595e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560ee4595c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560ee457ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560ee422a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560ee4229dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2c9d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c9d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c9d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ee4229cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c (1959 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vand_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vand_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vand_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vand_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vand_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/424843) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d536e215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558d536df0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558d536e289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7db049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7db0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7db049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7db031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d53677e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558d53677c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558d5365cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558d5330c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558d5330bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc7db032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7db0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7db0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d5330bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c (1960 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563630f6b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563630f680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563630f6b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc701333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc70138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc701333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc70131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563630f00e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563630f00c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563630ee5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563630b950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563630b94dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc70131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc70131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc70131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563630b94cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c (1961 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005645241ba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005645241b70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005645241ba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd43581bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4358725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd43581ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd435803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056452414fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056452414fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564524134b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564523de40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564523de3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd435804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4358050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4358050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564523de3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c (1962 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_u8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %ba
# | ...
# `---data was truncated (10240/15594) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a567f4215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a567f3f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a567f4289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5921849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59218a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5921849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5921831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a567ed7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a567ed7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a567ebcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a567b6c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a567b6bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5921832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59218330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59218330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a567b6bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c (1963 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofre
# | ...
# `---data was truncated (10240/183431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b467b4215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b467b3f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b467b4289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0e43f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0e43f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0e43f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0e43f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b467ad7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b467ad7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b467abcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b46776c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b46776bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0e43f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0e43f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0e43f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b46776bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c (1964 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.
# | ...
# `---data was truncated (10240/28162) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627a80ee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005627a80eb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005627a80ee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88d7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88d758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88d7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88d751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627a8083e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005627a8083c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005627a8068b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005627a7d180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005627a7d17dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f88d751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88d751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88d751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627a7d17cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c (1965 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(targe
# | ...
# `---data was truncated (10240/53734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055964eea615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055964eea30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055964eea689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5bbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5bbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5bbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5bbf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055964ee3be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055964ee3bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055964ee20b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055964ead00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055964eacfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe5bbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5bbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5bbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055964eacfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c (1966 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | ...
# `---data was truncated (10240/302389) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2dead015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b2deacd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b2dead089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f489181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f48918725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f489181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4891803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2dea65e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b2dea65c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b2dea4ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b2de6fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b2de6f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4891804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f48918050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f48918050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b2de6f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vabavq.c (1967 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vabavq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v16i8(i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v8i16(i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v4i32(i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v16i8(i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v8i16(i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vabav.v4i32(i32 1, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2, <16 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2, <8 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2, <4 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2, <16 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
# |   %6 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2, <8 x i1> %5)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   store i16 %p, ptr %
# | ...
# `---data was truncated (10240/11173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055fc4fc3b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fc4fc380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fc4fc3b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4532133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f453218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4532133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f453211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc4fbd0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fc4fbd0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fc4fbb5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fc4f8650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fc4f864dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f453211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f453211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f453211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc4f864cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c (1968 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei32_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei32_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei32_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei32_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei32_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, <vsc
# | ...
# `---data was truncated (10240/255546) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585e264c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005585e26490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005585e264c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa971305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa97135c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa971305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9712ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005585e25e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005585e25e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005585e25c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005585e22760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005585e2275dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa9712eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9712ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9712ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005585e2275cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/thinlto-multi-module.ll (1969 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto-multi-module.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll
# |  #0 0x000055effffc815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055effffc50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055effffc889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6339733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f633978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6339733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f633971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055effff5de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055effff5dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055effff42b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055efffbf20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055efffbf1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f633971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f633971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f633971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055efffbf1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c (1970 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e22879b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e2287980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e22879b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f796f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f796f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f796f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f796f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e228730e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e228730c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e228715b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e2283c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e2283c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f796f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f796f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f796f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2283c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c (1971 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056288df1515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056288df120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056288df1589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5fc3105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5fc315c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5fc3105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5fc30ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056288deaae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056288deaac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056288de8fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056288db3f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056288db3edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5fc30eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5fc30ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5fc30ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056288db3ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c (1972 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabs_v_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabs_v_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabs_v_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabs_v_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabs_v_u8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabs_v_u8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vabd.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vabs_v_u8m8_tu(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vabd.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vabs_v_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vabd.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vabs_v_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vabd.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vabs_v_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vabd.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vabs_v_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, al
# | ...
# `---data was truncated (10240/92370) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd084d815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dd084d50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dd084d889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a79c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a79ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a79c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a79c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd0846de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dd0846dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dd08452b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dd081020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dd08101dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3a79c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a79c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a79c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd08101cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c (1973 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v_i8mf8x5
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fcea72b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fcea7280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fcea72b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f472aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f472aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f472aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f472aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fcea6c0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fcea6c0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fcea6a5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fcea3550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fcea354dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f472aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f472aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f472aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fcea354cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c (1974 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d23d8cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d23d8c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d23d8cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3cec849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3cec8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3cec849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3cec831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d23d860e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d23d860c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d23d845b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d23d4f50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d23d4f4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3cec832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3cec8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3cec8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d23d4f4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c (1975 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db5abbe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055db5abbb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055db5abbe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31ebe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31ebe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31ebe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31ebe03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db5ab53e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055db5ab53c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055db5ab38b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055db5a7e80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055db5a7e7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f31ebe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31ebe050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31ebe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db5a7e7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c (1976 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabda_vx_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabda_vx_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabda_vx_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabda_vx_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabda_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %v
# | ...
# `---data was truncated (10240/110062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c99627f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c99627c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c99627f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d50e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d50ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d50e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d50e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c996214e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c996214c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c9961f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c995ea90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c995ea8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2d50e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d50e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d50e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c995ea8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c (1977 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056239b91a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056239b9170f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056239b91a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2196e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2196ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2196e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2196e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056239b8afe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056239b8afc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056239b894b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056239b5440b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056239b543dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2196e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2196e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2196e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056239b543cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c (1978 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync 
# | ...
# `---data was truncated (10240/62063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055762073115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055762072e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055762073189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f639401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63940725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f639401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6394003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576206c6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005576206c6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005576206abb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055762035b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055762035add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6394004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63940050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63940050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055762035acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c (1979 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/94379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ebb185915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ebb18560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ebb185989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8823f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8823f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8823f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8823eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ebb17eee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ebb17eec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ebb17d3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ebb14830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ebb1482dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8823eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8823eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8823eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ebb1482cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c (1980 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2b700a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a2b70070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a2b700a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa601f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa601f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa601f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa601f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2b6f9fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a2b6f9fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a2b6f84b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a2b6c340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a2b6c33dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa601f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa601f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa601f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2b6c33cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c (1981 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = al
# | ...
# `---data was truncated (10240/14209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055842886715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005584288640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055842886789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f534ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f534ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f534ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f534ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584287fce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005584287fcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005584287e1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005584284910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558428490dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f534ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f534ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f534ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558428490cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c (1982 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566dbfe915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005566dbfe60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005566dbfe989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa92849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa928a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa92849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa92831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566dbf7ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005566dbf7ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005566dbf63b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005566dbc130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005566dbc12dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faa92832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa928330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa928330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566dbc12cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c (1983 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055965109715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005596510940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055965109789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3acfe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3acfea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3acfe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3acfe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055965102ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055965102cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559651011b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559650cc10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559650cc0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3acfe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3acfe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3acfe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559650cc0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c (1984 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabd_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabd.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabd_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabd.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabd_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabd.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabd_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabd.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabd_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabd.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabd_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 
# | ...
# `---data was truncated (10240/97240) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bfe46c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556bfe4690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556bfe46c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ca8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ca84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ca8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ca8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bfe401e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556bfe401c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556bfe3e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556bfe0960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556bfe095dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5ca8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ca84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ca84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bfe095cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c (1985 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willret
# | ...
# `---data was truncated (10240/365423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601a45ac15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005601a45a90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005601a45ac89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5910505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f591055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5910505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f59104ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601a4541e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005601a4541c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005601a4526b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005601a41d60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005601a41d5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f59104eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59104ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59104ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601a41d5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c (1986 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,102
# | ...
# `---data was truncated (10240/10769) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650acbbf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005650acbbc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005650acbbf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc6ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc6ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc6ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc6ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650acb54e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005650acb54c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005650acb39b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005650ac7e90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005650ac7e8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdc6ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc6ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc6ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650ac7e8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp (1987 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d    -target-feature +v -target-feature +zfh -target-feature +zvfh    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @_Z21test_vget_v_i8m2_i8m1u14__rvv_int8m2_t(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %0, i64 8)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @_Z21test_vset_v_i8m1_i8m2u14__rvv_int8m2_tu14__rvv_int8m1_t(<vscale x 16 x i8> %dest, <vscale x 8 x i8> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x i8>, align 1
# |   %val.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 16 x i8> %dest, ptr %dest.addr, align 1
# |   store <vscale x 8 x i8> %val, ptr %val.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %dest.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %val.addr, align 1
# |   %2 = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 8)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8>, <vscale x 8 x i8>, i64 immarg) #1
# | 
# | attributes #0 = { mustprogress noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619284df15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005619284dc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005619284df89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbb42a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbb42aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbb42a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbb42a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561928474e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561928474c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561928459b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005619281090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561928108dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbb42a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbb42a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbb42a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561928108cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c (1988 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store
# | ...
# `---data was truncated (10240/29296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560fc12d815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560fc12d50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560fc12d889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6dded33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6dded8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6dded33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6dded1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560fc126de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560fc126dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560fc1252b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560fc0f020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560fc0f01dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6dded1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6dded1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6dded1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560fc0f01cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c (1989 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8ff_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8ff_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8ff_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8ff_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8ff_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8ff_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { targe
# | ...
# `---data was truncated (10240/81756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583e575615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005583e57530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005583e575689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82e2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82e2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82e2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82e2b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583e56ebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005583e56ebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005583e56d0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005583e53800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005583e537fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f82e2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82e2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82e2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583e537fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c (1990 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple",
# | ...
# `---data was truncated (10240/40860) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055606e9fa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055606e9f70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055606e9fa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf00133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf0018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf00133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf0011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055606e98fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055606e98fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055606e974b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055606e6240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055606e623dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcf0011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf0011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf0011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055606e623cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c (1991 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055724adef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055724adec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055724adef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6210533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f621058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6210533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f621051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055724ad84e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055724ad84c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055724ad69b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055724aa190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055724aa18dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f621051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f621051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f621051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055724aa18cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c (1992 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vctz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vctz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vctz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vctz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vctz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vctz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vctz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vctz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vctz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vctz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vctz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vctz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vctz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vctz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vctz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vctz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vctz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vctz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vctz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vctz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i1
# | ...
# `---data was truncated (10240/95001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055577c90215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055577c8ff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055577c90289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa622a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa622aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa622a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa622a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055577c897e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055577c897c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055577c87cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055577c52c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055577c52bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa622a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa622a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa622a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055577c52bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c (1993 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwin
# | ...
# `---data was truncated (10240/13581) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056193d92415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056193d9210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056193d92489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d66133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d6618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d66133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d6611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056193d8b9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056193d8b9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056193d89eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056193d54e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056193d54ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9d6611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d6611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d6611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056193d54dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c (1994 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64ff_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.mask.nxv1f64.i64.p0(<vscale x 1 x double> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x double>, i64 } @llvm.riscv.vleff.mask.nxv1f64.i64.p0(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64ff_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.mask.nxv2f64.i64.p0(<vscale x 2 x double> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x double>, i64 } @llvm.riscv.vleff.mask.nxv2f64.i64.p0(<vscale x 2 x double>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64ff_v_f64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.mask.nxv4f64.i64.p0(<vscale x 4 x double> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x double>, i64 } @llvm.riscv.vleff.mask.nxv4f64.i64.p0(<vscale x 4 x double>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64ff_v_f64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.mask.nxv8f64.i64.p0(<vscale x 8 x double> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x double>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x double>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x double> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x double>, i64 } @llvm.riscv.vleff.mask.nxv8f64.i64.p0(<vscale x 8 x double>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64ff_v_i64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.mask.nxv1i64.i64.p0(<vscale x 1 x i64> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.mask.nxv1i64.i64.p0(<vscale x 1 x i64>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64ff_v_i64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.mask.nxv2i64.i64.p0(<vscale x 2 x i64> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i64>, i64 } @llvm.riscv.vleff.mask.nxv2i64.i64.p0(<vscale x 2 x i64>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64ff_v_i64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.mask.nxv4i64.i64.p0(<vscale x 4 x i64> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x i64>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i64>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x i64> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i64>, i64 } @llvm.riscv.vleff.mask.nxv4i64.i64.p0(<vscale x 4 x i64>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64ff_v_i64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x i64>, i64 } @llvm.riscv.vleff.mask.nxv8i64.i64.p0(<vscale x 8 x i64> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5
# | ...
# `---data was truncated (10240/15508) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056506f3ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056506f3a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056506f3ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc807533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc80758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc807533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc80751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056506f340e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056506f340c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056506f325b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056506efd50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056506efd4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc80751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc80751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc80751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056506efd4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c (1995 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c  -check-prefix=RV32ZBKB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @brev8_32(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.brev8.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @zip(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.zip.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @unzip(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.unzip.i32(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.brev8.i32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.zip.i32(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.unzip.i32(i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbkb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b3c09d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b3c09d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b3c09d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb48fd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb48fd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb48fd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb48fced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3c0969e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b3c0969c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b3c094eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b3c05fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b3c05fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb48fceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb48fcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb48fcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3c05fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c (1996 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, a
# | ...
# `---data was truncated (10240/44177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b411f3415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b411f310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b411f3489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a9e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a9e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a9e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a9e31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b411ec9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b411ec9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b411eaeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b411b5e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b411b5ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4a9e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a9e31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a9e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b411b5dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c (1997 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ba57e215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557ba57df0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557ba57e289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe739649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7396a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe739649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe739631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ba5777e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557ba5777c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557ba575cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557ba540c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557ba540bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe739632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7396330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7396330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ba540bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c (1998 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_xu_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_xu_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.n
# | ...
# `---data was truncated (10240/33624) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005579709de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005579709db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005579709de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c1661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c166725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c1661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c16603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557970973e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557970973c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557970958b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005579706080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557970607dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5c16604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c166050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c166050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557970607cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c (1999 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056038160115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005603815fe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056038160189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdfabf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdfabf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdfabf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdfabeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560381596e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560381596c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056038157bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056038122b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056038122add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdfabeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdfabeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdfabeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056038122acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c (2000 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m2_bf16m1(<vscale x 8 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv8bf16(<vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m4_bf16m1(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vget_v_bf16m8_bf16m1(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.extract.nxv4bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m4_bf16m2(<vscale x 16 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv16bf16(<vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vget_v_bf16m8_bf16m2(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.extract.nxv8bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vget_v_bf16m8_bf16m4(<vscale x 32 x bfloat> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.extract.nxv16bf16.nxv32bf16(<vscale x 32 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x2_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x3_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x4_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x5_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x6_bf16mf4(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %index.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %src.addr, align 2
# |   %1 = call <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, i32 0)
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vget_v_bf16mf4x7_bf16mf4(target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/30690) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b088a515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558b088a20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558b088a589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9eb905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9eb95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9eb905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9eb8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b0883ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558b0883ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558b0881fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558b084cf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558b084cedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa9eb8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9eb8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9eb8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b084cecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/neon/vpaddl.c (2001 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/vpaddl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone           -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vpaddl_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = call <4 x i16> @llvm.aarch64.neon.saddlp.v4i16.v8i8(<8 x i8> %1)
# |   store <4 x i16> %vpaddl.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vpaddlq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = call <8 x i16> @llvm.aarch64.neon.saddlp.v8i16.v16i8(<16 x i8> %1)
# |   store <8 x i16> %vpaddl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vpaddl_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <4 x i16>
# |   %vpaddl1.i = call <2 x i32> @llvm.aarch64.neon.saddlp.v2i32.v4i16(<4 x i16> %vpaddl.i)
# |   store <2 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vpaddlq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <8 x i16>
# |   %vpaddl1.i = call <4 x i32> @llvm.aarch64.neon.saddlp.v4i32.v8i16(<8 x i16> %vpaddl.i)
# |   store <4 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vpaddl_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <2 x i32>
# |   %vpaddl1.i = call <1 x i64> @llvm.aarch64.neon.saddlp.v1i64.v2i32(<2 x i32> %vpaddl.i)
# |   store <1 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vpaddlq_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <4 x i32>
# |   %vpaddl1.i = call <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32> %vpaddl.i)
# |   store <2 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vpaddl_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> %1)
# |   store <4 x i16> %vpaddl.i, ptr %ref.tmp.i, align 8
# |   %2 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %2, ptr %__ret.i, align 8
# |   %3 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vpaddlq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %a, ptr %a.addr, align 16
# |   %0 = load <16 x i8>, ptr %a.addr, align 16
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> %1)
# |   store <8 x i16> %vpaddl.i, ptr %ref.tmp.i, align 16
# |   %2 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %2, ptr %__ret.i, align 16
# |   %3 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vpaddl_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <4 x i16>
# |   %vpaddl1.i = call <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16> %vpaddl.i)
# |   store <2 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %2, ptr %__ret.i, align 8
# |   %3 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vpaddlq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <8 x i16>
# |   %vpaddl1.i = call <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16> %vpaddl.i)
# |   store <4 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %2, ptr %__ret.i, align 16
# |   %3 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i64> @test_vpaddl_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %vpaddl.i = bitcast <8 x i8> %1 to <2 x i32>
# |   %vpaddl1.i = call <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32> %vpaddl.i)
# |   store <1 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 8
# |   %2 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %2, ptr %__ret.i, align 8
# |   %3 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_vpaddlq_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <2 x i64>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   %1 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %vpaddl.i = bitcast <16 x i8> %1 to <4 x i32>
# |   %vpaddl1.i = call <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32> %vpaddl.i)
# |   store <2 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 16
# |   %2 = load <2 x i64>, ptr %ref.tmp.i, align 16
# |   store <2 x i64> %2, ptr %__ret.i, align 16
# |   %3 = load <2 x i64>, ptr %__ret.i, align 16
# |   ret <2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vpadal_s8(<4 x i16> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <8 x i8>, al
# | ...
# `---data was truncated (10240/26059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000561876ed515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561876ed20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561876ed589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15cf505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15cf55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15cf505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15cf4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561876e6ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561876e6ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561876e4fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561876aff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561876afedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f15cf4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15cf4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15cf4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561876afecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c (2002 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055604315a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005560431570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055604315a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f663be1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f663be725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f663be1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f663be03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560430efe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005560430efc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005560430d4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556042d840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556042d83dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f663be04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f663be050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f663be050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556042d83cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/idup.c (2003 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/idup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vidupq_n_u8(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %0, i32 4)
# |   %2 = extractvalue { <16 x i8>, i32 } %1, 0
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vidupq_n_u16(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %0, i32 1)
# |   %2 = extractvalue { <8 x i16>, i32 } %1, 0
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vidupq_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %0, i32 4)
# |   %2 = extractvalue { <4 x i32>, i32 } %1, 0
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vddupq_n_u8(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %0, i32 2)
# |   %2 = extractvalue { <16 x i8>, i32 } %1, 0
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vddupq_n_u16(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %0, i32 4)
# |   %2 = extractvalue { <8 x i16>, i32 } %1, 0
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vddupq_n_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %0, i32 2)
# |   %2 = extractvalue { <4 x i32>, i32 } %1, 0
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_viwdupq_n_u8(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32 %0, i32 %1, i32 4)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_viwdupq_n_u16(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32 %0, i32 %1, i32 2)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_viwdupq_n_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32 %0, i32 %1, i32 8)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdwdupq_n_u8(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32 %0, i32 %1, i32 4)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdwdupq_n_u16(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32 %0, i32 %1, i32 8)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdwdupq_n_u32(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32 %0, i32 %1, i32 1)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vidupq_wb_u8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %1, i32 8)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vidupq_wb_u16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %1, i32 1)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vidupq_wb_u32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %1, i32 4)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vddupq_wb_u8(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %1, i32 2)
# |   %3 = extractvalue { <16 x i8>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <16 x i8>, i32 } %2, 0
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vddupq_wb_u16(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %1, i32 8)
# |   %3 = extractvalue { <8 x i16>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <8 x i16>, i32 } %2, 0
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vddupq_wb_u32(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 4
# |   store ptr %a, ptr %a.addr, align 4
# |   %0 = load ptr, ptr %a.addr, align 4
# |   %1 = load i32, ptr %0, align 4
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %1, i32 2)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   store i32 %3, ptr %0, align 4
# |   %4 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i3
# | ...
# `---data was truncated (10240/57708) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f11a4e615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f11a4e30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f11a4e689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f507ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f507eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f507ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f507ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f11a47be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f11a47bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f11a460b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f11a1100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f11a10fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f507ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f507ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f507ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f11a10fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c (2004 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed85f9515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ed85f920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ed85f9589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ecfa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ecfa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ecfa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ecfa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed85f2ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ed85f2ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ed85f0fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ed85bbf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ed85bbedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8ecfa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ecfa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ecfa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed85bbecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c (2005 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>
# | ...
# `---data was truncated (10240/47764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5d7cb015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c5d7cad0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c5d7cb089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cc2505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cc255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cc2505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cc24ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5d7c45e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c5d7c45c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c5d7c2ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c5d78da0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c5d78d9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4cc24eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cc24ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cc24ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5d78d9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c (2006 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564352d6015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564352d5d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564352d6089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8574533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f857458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8574533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f857451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564352cf5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564352cf5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564352cdab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056435298a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564352989dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f857451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f857451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f857451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564352989cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c (2007 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwaddu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwaddu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwaddu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscal
# | ...
# `---data was truncated (10240/134927) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d7c633215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d7c632f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d7c633289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f33b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f33b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f33b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f33b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d7c62c7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d7c62c7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d7c62acb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d7c5f5c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d7c5f5bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4f33b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f33b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f33b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d7c5f5bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c (2008 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captu
# | ...
# `---data was truncated (10240/87308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555afe54c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555afe5490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555afe54c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82ea933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82ea98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82ea933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82ea91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555afe4e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555afe4e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555afe4c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555afe1760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555afe175dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f82ea91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82ea91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82ea91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555afe175cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c (2009 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmax_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmax_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmax.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmax_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmax.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmax_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmax.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmax_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmax.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmax_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/97647) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e0ddb015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558e0ddad0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558e0ddb089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0d9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0d9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0d9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0d9e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e0dd45e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558e0dd45c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558e0dd2ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558e0d9da0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558e0d9d9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd0d9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0d9e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0d9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e0d9d9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c (2010 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4366ee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a4366eb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a4366ee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3bfa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3bfaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3bfa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3bfa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a436683e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a436683c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a436668b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a4363180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a436317dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc3bfa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3bfa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3bfa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a436317cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c (2011 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define d
# | ...
# `---data was truncated (10240/25350) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633e15f415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005633e15f10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005633e15f489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf60a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf60aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf60a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf60a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633e1589e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005633e1589c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005633e156eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005633e121e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005633e121ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbf60a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf60a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf60a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633e121dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c (2012 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vneg_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vneg_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vneg_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = c
# | ...
# `---data was truncated (10240/41433) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644e2ea515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005644e2ea20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005644e2ea589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8235e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8235ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8235e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8235e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644e2e3ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005644e2e3ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005644e2e1fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005644e2acf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005644e2acedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8235e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8235e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8235e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644e2acecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c (2013 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056253d02515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056253d0220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056253d02589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9455d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9455d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9455d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9455d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056253cfbae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056253cfbac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056253cf9fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056253cc4f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056253cc4edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9455d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9455d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9455d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056253cc4ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c (2014 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_x_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_x_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_x_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_x_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_x_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfwcvt_f_xu_v_f16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfwcvt_f_xu_v_f16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfwcvt_f_xu_v_f16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfwcvt_f_xu_v_f16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfwcvt_f_xu_v_f16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfwcvt_f_xu_v_f16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_x_f_v_i32mf2(<vscale x
# | ...
# `---data was truncated (10240/119289) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055750224d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055750224a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055750224d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82db333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82db38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82db333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82db31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575021e2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005575021e2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005575021c7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557501e770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557501e76dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f82db31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82db31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82db31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557501e76cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c (2015 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591929c615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005591929c30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005591929c689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2cead33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2cead8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2cead33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2cead1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055919295be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055919295bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559192940b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005591925f00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005591925efdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2cead1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2cead1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2cead1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591925efcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c (2016 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_u8m1x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x 
# | ...
# `---data was truncated (10240/11943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562fc599d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562fc599a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562fc599d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2bd8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2bd8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2bd8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2bd8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fc5932e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562fc5932c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562fc5917b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562fc55c70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562fc55c6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2bd8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2bd8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2bd8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fc55c6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c (2017 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei64_v_f16mf4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei64_v_f16mf2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei64_v_f16m1(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei64_v_f16m2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei64_v_f32mf2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei64_v_f32m1(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei64_v_f32m2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei64_v_f32m4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vluxei64_v_f64m1(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(<vscale x 1 x double>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vluxei64_v_f64m2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x double> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(<vscale x 2 x doubl
# | ...
# `---data was truncated (10240/91275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056074aa2f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056074aa2c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056074aa2f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f30c4f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f30c4f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f30c4f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f30c4eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056074a9c4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056074a9c4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056074a9a9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056074a6590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056074a658dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f30c4eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f30c4eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f30c4eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056074a658cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c (2018 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac
# | ...
# `---data was truncated (10240/51796) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056296472c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005629647290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056296472c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8036449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80364a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8036449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8036431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629646c1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005629646c1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005629646a6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005629643560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562964355dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8036432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80364330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80364330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562964355cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c (2019 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f1091615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564f109130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564f1091689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ed1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ed1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ed1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ed1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f108abe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564f108abc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564f10890b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564f105400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564f1053fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3ed1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ed1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ed1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f1053fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c (2020 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f9e1aa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559f9e1a70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559f9e1aa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8c1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8c1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8c1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8c1b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f9e13fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559f9e13fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559f9e124b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559f9ddd40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559f9ddd3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd8c1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8c1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8c1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f9ddd3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c (2021 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr,
# | ...
# `---data was truncated (10240/23056) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564733a3815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564733a350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564733a3889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc958f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc958f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc958f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc958f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647339cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005647339cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005647339b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005647336620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564733661dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc958f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc958f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc958f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564733661cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c (2022 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, 
# | ...
# `---data was truncated (10240/26468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559f540b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005559f54080f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005559f540b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3b8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3b82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3b8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3b8231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559f53a0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005559f53a0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005559f5385b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005559f50350b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005559f5034dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa3b8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3b82330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3b82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005559f5034cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c (2023 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmslt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.nxv32i8.i64(<vscale x 32 x 
# | ...
# `---data was truncated (10240/95089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055558fee715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055558fee40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055558fee789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8074f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8074f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8074f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8074f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055558fe7ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055558fe7cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055558fe61b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055558fb110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055558fb10dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8074f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8074f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8074f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055558fb10cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c (2024 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsll_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsll_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsll_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vwsll_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vwsll_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>
# | ...
# `---data was truncated (10240/153805) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b85305b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b8530580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b85305b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd3de449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3de4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd3de449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3de431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b852ff0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b852ff0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b852fd5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b852c850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b852c84dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd3de432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3de4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3de4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b852c84cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c (2025 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056104eb4615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056104eb430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056104eb4689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd862849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8628a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd862849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd862831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056104eadbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056104eadbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056104eac0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056104e7700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056104e76fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd862832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8628330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8628330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056104e76fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c (2026 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) 
# | ...
# `---data was truncated (10240/27055) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f811a915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557f811a60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557f811a989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e02b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e02b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e02b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e02aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f8113ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557f8113ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557f81123b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557f80dd30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557f80dd2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9e02aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e02aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e02aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f80dd2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c (2027 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ecf8f0115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ecf8efe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ecf8f0189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd44e21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd44e2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd44e21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd44e203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ecf8e96e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ecf8e96c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ecf8e7bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ecf8b2b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ecf8b2add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd44e204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd44e2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd44e2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ecf8b2acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c (2028 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function
# | ...
# `---data was truncated (10240/12439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565210ccb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000565210cc80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000565210ccb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdae861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdae86725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdae861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdae8603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565210c60e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565210c60c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565210c45b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005652108f50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005652108f4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdae8604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdae86050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdae86050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652108f4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c (2029 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2
# | ...
# `---data was truncated (10240/32654) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be0240415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055be024010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055be0240489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe1eb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1eb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe1eb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe1eb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be02399e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055be02399c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055be0237eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055be0202e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055be0202ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe1eb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1eb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1eb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be0202dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c (2030 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync
# | ...
# `---data was truncated (10240/10618) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec52ed115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ec52ece0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ec52ed189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2bf1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2bf10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2bf1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2bf1031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec52e66e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ec52e66c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ec52e4bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ec52afb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ec52afadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2bf1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2bf10330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2bf10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec52afacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c (2031 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgather_vx_f16mf4(<vscale x 1 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgather_vx_f16mf2(<vscale x 2 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgather_vx_f16m1(<vscale x 4 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgather_vx_f16m2(<vscale x 8 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %index, ptr %index.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %index.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgather_vx_f16m4(<vscale x 16 x half> %op1, i64 noundef %index, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %index.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwin
# | ...
# `---data was truncated (10240/273705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585528ea15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005585528e70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005585528ea89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac2de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac2dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac2de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac2de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055855287fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055855287fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558552864b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005585525140b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558552513dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fac2de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac2de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac2de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558552513cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c (2032 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555aa332815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555aa33250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555aa332889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9ebb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9ebb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9ebb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9ebb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555aa32bde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555aa32bdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555aa32a2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555aa2f520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555aa2f51dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe9ebb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9ebb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9ebb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555aa2f51cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll (2033 of 27911)
******************** TEST 'Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll
# |  #0 0x0000561c6a50f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561c6a50c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561c6a50f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f112ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f112caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f112ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f112ca31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c6a4a4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561c6a4a4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561c6a489b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561c6a1390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561c6a138dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f112ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f112ca330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f112ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c6a138cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c (2034 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 
# | ...
# `---data was truncated (10240/18225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba3e81515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ba3e8120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ba3e81589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc70849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc708a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc70849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc70831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba3e7aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ba3e7aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ba3e78fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ba3e43f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ba3e43edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efc70832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc708330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc708330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba3e43ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c (2035 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulh_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulh_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulh_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, al
# | ...
# `---data was truncated (10240/65723) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557739e2e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557739e2b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557739e2e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa16db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa16db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa16db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa16db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557739dc3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557739dc3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557739da8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557739a580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557739a57dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa16db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa16db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa16db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557739a57cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c (2036 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 -1, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vnot_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vnot_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 -1, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vnot_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i
# | ...
# `---data was truncated (10240/72493) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055797ead415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055797ead10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055797ead489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f310b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f310b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f310b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f310b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055797ea69e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055797ea69c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055797ea4eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055797e6fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055797e6fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f310b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f310b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f310b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055797e6fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c (2037 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598f85ce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005598f85cb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005598f85ce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdace449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdace4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdace449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdace431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598f8563e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005598f8563c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005598f8548b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005598f81f80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005598f81f7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdace432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdace4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdace4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598f81f7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c (2038 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055afda6d215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055afda6cf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055afda6d289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f41049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f410a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f41049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f41031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afda667e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055afda667c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055afda64cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055afda2fc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055afda2fbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9f41032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f410330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f410330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afda2fbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c (2039 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056125e3ce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056125e3cb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056125e3ce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faddba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faddbaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faddba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faddba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056125e363e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056125e363c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056125e348b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056125dff80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056125dff7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faddba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faddba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faddba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056125dff7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c (2040 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056205015b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005620501580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056205015b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3884649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38846a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3884649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3884631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620500f0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005620500f0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005620500d5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056204fd850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056204fd84dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3884632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38846330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38846330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056204fd84cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c (2041 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d73b1915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562d73b160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562d73b1989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdaa7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdaa72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdaa7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdaa7231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d73aaee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562d73aaec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562d73a93b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562d737430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562d73742dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdaa7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdaa72330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdaa72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d73742cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c (2042 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2
# | ...
# `---data was truncated (10240/151911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b4fc73d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b4fc73a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b4fc73d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b81249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b812a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b81249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b81231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b4fc6d2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b4fc6d2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b4fc6b7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b4fc3670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b4fc366dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5b81232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b812330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b812330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b4fc366cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/SystemZ/zvector.c (2043 of 27911)
******************** TEST 'Clang :: CodeGen/SystemZ/zvector.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple s390x-linux-gnu -target-cpu z13 -fzvector  -emit-llvm -o - -W -Wall -Werror  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple s390x-linux-gnu -target-cpu z13 -fzvector -emit-llvm -o - -W -Wall -Werror /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c"
# | target datalayout = "E-S64-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
# | target triple = "s390x-unknown-linux-gnu"
# | 
# | @sc2 = global <16 x i8> zeroinitializer, align 8
# | @sc = global <16 x i8> zeroinitializer, align 8
# | @uc2 = global <16 x i8> zeroinitializer, align 8
# | @uc = global <16 x i8> zeroinitializer, align 8
# | @ss2 = global <8 x i16> zeroinitializer, align 8
# | @ss = global <8 x i16> zeroinitializer, align 8
# | @us2 = global <8 x i16> zeroinitializer, align 8
# | @us = global <8 x i16> zeroinitializer, align 8
# | @si2 = global <4 x i32> zeroinitializer, align 8
# | @si = global <4 x i32> zeroinitializer, align 8
# | @ui2 = global <4 x i32> zeroinitializer, align 8
# | @ui = global <4 x i32> zeroinitializer, align 8
# | @sl2 = global <2 x i64> zeroinitializer, align 8
# | @sl = global <2 x i64> zeroinitializer, align 8
# | @ul2 = global <2 x i64> zeroinitializer, align 8
# | @ul = global <2 x i64> zeroinitializer, align 8
# | @slll2 = global <1 x i128> zeroinitializer, align 8
# | @slll = global <1 x i128> zeroinitializer, align 8
# | @ulll2 = global <1 x i128> zeroinitializer, align 8
# | @ulll = global <1 x i128> zeroinitializer, align 8
# | @fd2 = global <2 x double> zeroinitializer, align 8
# | @fd = global <2 x double> zeroinitializer, align 8
# | @bc2 = global <16 x i8> zeroinitializer, align 8
# | @bc = global <16 x i8> zeroinitializer, align 8
# | @bs2 = global <8 x i16> zeroinitializer, align 8
# | @bs = global <8 x i16> zeroinitializer, align 8
# | @bi2 = global <4 x i32> zeroinitializer, align 8
# | @bi = global <4 x i32> zeroinitializer, align 8
# | @bl2 = global <2 x i64> zeroinitializer, align 8
# | @bl = global <2 x i64> zeroinitializer, align 8
# | @blll2 = global <1 x i128> zeroinitializer, align 8
# | @blll = global <1 x i128> zeroinitializer, align 8
# | @cnt = global i32 0, align 4
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_assign() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   store volatile <16 x i8> %0, ptr @sc, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   store volatile <16 x i8> %1, ptr @uc, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   store volatile <8 x i16> %2, ptr @ss, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   store volatile <8 x i16> %3, ptr @us, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   store volatile <4 x i32> %4, ptr @si, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   store volatile <4 x i32> %5, ptr @ui, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   store volatile <2 x i64> %6, ptr @sl, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   store volatile <2 x i64> %7, ptr @ul, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   store volatile <1 x i128> %8, ptr @slll, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   store volatile <1 x i128> %9, ptr @ulll, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   store volatile <2 x double> %10, ptr @fd, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_pos() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   store volatile <16 x i8> %0, ptr @sc, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   store volatile <16 x i8> %1, ptr @uc, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   store volatile <8 x i16> %2, ptr @ss, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   store volatile <8 x i16> %3, ptr @us, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   store volatile <4 x i32> %4, ptr @si, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   store volatile <4 x i32> %5, ptr @ui, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   store volatile <2 x i64> %6, ptr @sl, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   store volatile <2 x i64> %7, ptr @ul, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   store volatile <1 x i128> %8, ptr @slll, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   store volatile <1 x i128> %9, ptr @ulll, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   store volatile <2 x double> %10, ptr @fd, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_neg() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %sub = sub <16 x i8> zeroinitializer, %0
# |   store volatile <16 x i8> %sub, ptr @sc, align 8
# |   %1 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %sub1 = sub <8 x i16> zeroinitializer, %1
# |   store volatile <8 x i16> %sub1, ptr @ss, align 8
# |   %2 = load volatile <4 x i32>, ptr @si2, align 8
# |   %sub2 = sub <4 x i32> zeroinitializer, %2
# |   store volatile <4 x i32> %sub2, ptr @si, align 8
# |   %3 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %sub3 = sub <2 x i64> zeroinitializer, %3
# |   store volatile <2 x i64> %sub3, ptr @sl, align 8
# |   %4 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %sub4 = sub <1 x i128> zeroinitializer, %4
# |   store volatile <1 x i128> %sub4, ptr @slll, align 8
# |   %5 = load volatile <2 x double>, ptr @fd2, align 8
# |   %fneg = fneg <2 x double> %5
# |   store volatile <2 x double> %fneg, ptr @fd, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_preinc() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %inc = add <16 x i8> %0, splat (i8 1)
# |   store volatile <16 x i8> %inc, ptr @sc2, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   %inc1 = add <16 x i8> %1, splat (i8 1)
# |   store volatile <16 x i8> %inc1, ptr @uc2, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %inc2 = add <8 x i16> %2, splat (i16 1)
# |   store volatile <8 x i16> %inc2, ptr @ss2, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   %inc3 = add <8 x i16> %3, splat (i16 1)
# |   store volatile <8 x i16> %inc3, ptr @us2, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   %inc4 = add <4 x i32> %4, splat (i32 1)
# |   store volatile <4 x i32> %inc4, ptr @si2, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   %inc5 = add <4 x i32> %5, splat (i32 1)
# |   store volatile <4 x i32> %inc5, ptr @ui2, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %inc6 = add <2 x i64> %6, splat (i64 1)
# |   store volatile <2 x i64> %inc6, ptr @sl2, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   %inc7 = add <2 x i64> %7, splat (i64 1)
# |   store volatile <2 x i64> %inc7, ptr @ul2, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %inc8 = add <1 x i128> %8, splat (i128 1)
# |   store volatile <1 x i128> %inc8, ptr @slll2, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   %inc9 = add <1 x i128> %9, splat (i128 1)
# |   store volatile <1 x i128> %inc9, ptr @ulll2, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   %inc10 = fadd <2 x double> %10, splat (double 1.000000e+00)
# |   store volatile <2 x double> %inc10, ptr @fd2, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_postinc() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %inc = add <16 x i8> %0, splat (i8 1)
# |   store volatile <16 x i8> %inc, ptr @sc2, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   %inc1 = add <16 x i8> %1, splat (i8 1)
# |   store volatile <16 x i8> %inc1, ptr @uc2, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %inc2 = add <8 x i16> %2, splat (i16 1)
# |   store volatile <8 x i16> %inc2, ptr @ss2, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   %inc3 = add <8 x i16> %3, splat (i16 1)
# |   store volatile <8 x i16> %inc3, ptr @us2, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   %inc4 = add <4 x i32> %4, splat (i32 1)
# |   store volatile <4 x i32> %inc4, ptr @si2, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   %inc5 = add <4 x i32> %5, splat (i32 1)
# |   store volatile <4 x i32> %inc5, ptr @ui2, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %inc6 = add <2 x i64> %6, splat (i64 1)
# |   store volatile <2 x i64> %inc6, ptr @sl2, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   %inc7 = add <2 x i64> %7, splat (i64 1)
# |   store volatile <2 x i64> %inc7, ptr @ul2, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %inc8 = add <1 x i128> %8, splat (i128 1)
# |   store volatile <1 x i128> %inc8, ptr @slll2, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   %inc9 = add <1 x i128> %9, splat (i128 1)
# |   store volatile <1 x i128> %inc9, ptr @ulll2, align 8
# |   %10 = load volatile <2 x double>, ptr @fd2, align 8
# |   %inc10 = fadd <2 x double> %10, splat (double 1.000000e+00)
# |   store volatile <2 x double> %inc10, ptr @fd2, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @test_predec() #0 {
# | entry:
# |   %0 = load volatile <16 x i8>, ptr @sc2, align 8
# |   %dec = add <16 x i8> %0, splat (i8 -1)
# |   store volatile <16 x i8> %dec, ptr @sc2, align 8
# |   %1 = load volatile <16 x i8>, ptr @uc2, align 8
# |   %dec1 = add <16 x i8> %1, splat (i8 -1)
# |   store volatile <16 x i8> %dec1, ptr @uc2, align 8
# |   %2 = load volatile <8 x i16>, ptr @ss2, align 8
# |   %dec2 = add <8 x i16> %2, splat (i16 -1)
# |   store volatile <8 x i16> %dec2, ptr @ss2, align 8
# |   %3 = load volatile <8 x i16>, ptr @us2, align 8
# |   %dec3 = add <8 x i16> %3, splat (i16 -1)
# |   store volatile <8 x i16> %dec3, ptr @us2, align 8
# |   %4 = load volatile <4 x i32>, ptr @si2, align 8
# |   %dec4 = add <4 x i32> %4, splat (i32 -1)
# |   store volatile <4 x i32> %dec4, ptr @si2, align 8
# |   %5 = load volatile <4 x i32>, ptr @ui2, align 8
# |   %dec5 = add <4 x i32> %5, splat (i32 -1)
# |   store volatile <4 x i32> %dec5, ptr @ui2, align 8
# |   %6 = load volatile <2 x i64>, ptr @sl2, align 8
# |   %dec6 = add <2 x i64> %6, splat (i64 -1)
# |   store volatile <2 x i64> %dec6, ptr @sl2, align 8
# |   %7 = load volatile <2 x i64>, ptr @ul2, align 8
# |   %dec7 = add <2 x i64> %7, splat (i64 -1)
# |   store volatile <2 x i64> %dec7, ptr @ul2, align 8
# |   %8 = load volatile <1 x i128>, ptr @slll2, align 8
# |   %dec8 = add <1 x i128> %8, splat (i128 -1)
# |   store volatile <1 x i128> %dec8, ptr @slll2, align 8
# |   %9 = load volatile <1 x i128>, ptr @ulll2, align 8
# |   %dec
# | ...
# `---data was truncated (10240/152876) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9860d615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d9860d30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d9860d689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b9b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b9b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b9b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b9b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d98606be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d98606bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d986050b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d985d000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d985cffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9b9b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b9b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b9b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d985cffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c (2044 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_u32m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d465d3d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d465d3a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d465d3d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3623b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3623b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3623b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3623b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d465cd2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d465cd2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d465cb7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d4659670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d465966dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3623b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3623b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3623b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d465966cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c (2045 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_i16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e1
# | ...
# `---data was truncated (10240/63053) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055623254415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005562325410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055623254489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f63fcc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63fcca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f63fcc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63fcc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562324d9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005562324d9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005562324beb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055623216e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055623216ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f63fcc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63fcc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63fcc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055623216dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c (2046 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vclz_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vclz.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vclz_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vclz.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vclz_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vclz.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | ...
# `---data was truncated (10240/40669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d40e8d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562d40e8a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562d40e8d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c71d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c71d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c71d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c71ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d40e22e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562d40e22c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562d40e07b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562d40ab70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562d40ab6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2c71ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c71cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c71cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d40ab6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c (2047 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_u8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056442751715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005644275140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056442751789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7bc3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7bc3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7bc3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7bc3e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644274ace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005644274acc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564427491b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005644271410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564427140dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7bc3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7bc3e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7bc3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564427140cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c (2048 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv
# | ...
# `---data was truncated (10240/68225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588dd4f215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005588dd4ef0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005588dd4f289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdd4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdd46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdd4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdd4631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588dd487e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005588dd487c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005588dd46cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005588dd11c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005588dd11bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efdd4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdd46330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdd46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588dd11bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c (2049 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16           -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfma_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <4 x half>
# |   %7 = bitcast <8 x i8> %4 to <4 x half>
# |   %8 = bitcast <8 x i8> %5 to <4 x half>
# |   %9 = call <4 x half> @llvm.fma.v4f16(<4 x half> %7, <4 x half> %8, <4 x half> %6)
# |   store <4 x half> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %10, ptr %__ret.i, align 8
# |   %11 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %6 = bitcast <16 x i8> %3 to <8 x half>
# |   %7 = bitcast <16 x i8> %4 to <8 x half>
# |   %8 = bitcast <16 x i8> %5 to <8 x half>
# |   %9 = call <8 x half> @llvm.fma.v8f16(<8 x half> %7, <8 x half> %8, <8 x half> %6)
# |   store <8 x half> %9, ptr %ref.tmp.i, align 16
# |   %10 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %10, ptr %__ret.i, align 16
# |   %11 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfms_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <4 x half>, align 8
# |   %__p1.addr.i.i = alloca <4 x half>, align 8
# |   %__p2.addr.i.i = alloca <4 x half>, align 8
# |   %__ret.i.i = alloca <4 x half>, align 8
# |   %ref.tmp.i.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   store <4 x half> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <4 x half>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x half>, ptr %__p1.addr.i, align 8
# |   %fneg.i = fneg <4 x half> %4
# |   %5 = load <4 x half>, ptr %__p2.addr.i, align 8
# |   store <4 x half> %3, ptr %__p0.addr.i.i, align 8
# |   store <4 x half> %fneg.i, ptr %__p1.addr.i.i, align 8
# |   store <4 x half> %5, ptr %__p2.addr.i.i, align 8
# |   %6 = load <8 x i8>, ptr %__p0.addr.i.i, align 8
# |   %7 = load <8 x i8>, ptr %__p1.addr.i.i, align 8
# |   %8 = load <8 x i8>, ptr %__p2.addr.i.i, align 8
# |   %9 = bitcast <8 x i8> %6 to <4 x half>
# |   %10 = bitcast <8 x i8> %7 to <4 x half>
# |   %11 = bitcast <8 x i8> %8 to <4 x half>
# |   %12 = call <4 x half> @llvm.fma.v4f16(<4 x half> %10, <4 x half> %11, <4 x half> %9)
# |   store <4 x half> %12, ptr %ref.tmp.i.i, align 8
# |   %13 = load <4 x half>, ptr %ref.tmp.i.i, align 8
# |   store <4 x half> %13, ptr %__ret.i.i, align 8
# |   %14 = load <4 x half>, ptr %__ret.i.i, align 8
# |   store <4 x half> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x half>, ptr %__ret.i, align 8
# |   ret <4 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <8 x half>, align 16
# |   %__p1.addr.i.i = alloca <8 x half>, align 16
# |   %__p2.addr.i.i = alloca <8 x half>, align 16
# |   %__ret.i.i = alloca <8 x half>, align 16
# |   %ref.tmp.i.i = alloca <16 x i8>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <8 x half> %c, ptr %c.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %1, ptr %__p1.addr.i, align 16
# |   store <8 x half> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <8 x half>, ptr %__p0.addr.i, align 16
# |   %4 = load <8 x half>, ptr %__p1.addr.i, align 16
# |   %fneg.i = fneg <8 x half> %4
# |   %5 = load <8 x half>, ptr %__p2.addr.i, align 16
# |   store <8 x half> %3, ptr %__p0.addr.i.i, align 16
# |   store <8 x half> %fneg.i, ptr %__p1.addr.i.i, align 16
# |   store <8 x half> %5, ptr %__p2.addr.i.i, align 16
# |   %6 = load <16 x i8>, ptr %__p0.addr.i.i, align 16
# |   %7 = load <16 x i8>, ptr %__p1.addr.i.i, align 16
# |   %8 = load <16 x i8>, ptr %__p2.addr.i.i, align 16
# |   %9 = bitcast <16 x i8> %6 to <8 x half>
# |   %10 = bitcast <16 x i8> %7 to <8 x half>
# |   %11 = bitcast <16 x i8> %8 to <8 x half>
# |   %12 = call <8 x half> @llvm.fma.v8f16(<8 x half> %10, <8 x half> %11, <8 x half> %9)
# |   store <8 x half> %12, ptr %ref.tmp.i.i, align 16
# |   %13 = load <8 x half>, ptr %ref.tmp.i.i, align 16
# |   store <8 x half> %13, ptr %__ret.i.i, align 16
# |   %14 = load <8 x half>, ptr %__ret.i.i, align 16
# |   store <8 x half> %14, ptr %__ret.i, align 16
# |   %15 = load <8 x half>, ptr %__ret.i, align 16
# |   ret <8 x half> %15
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x half> @test_vfma_lane_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <4 x half>, align 8
# |   %__s0 = alloca <4 x half>, align 8
# |   %__s1 = alloca <4 x half>, align 8
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   store <4 x half> %0, ptr %__s0, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %1, ptr %__s1, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %2, ptr %__s2, align 8
# |   %3 = load <8 x i8>, ptr %__s0, align 8
# |   %4 = load <8 x i8>, ptr %__s1, align 8
# |   %5 = load <8 x i8>, ptr %__s2, align 8
# |   %6 = bitcast <8 x i8> %5 to <4 x half>
# |   %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   %fmla = bitcast <8 x i8> %4 to <4 x half>
# |   %fmla1 = bitcast <8 x i8> %3 to <4 x half>
# |   %fmla2 = call <4 x half> @llvm.fma.v4f16(<4 x half> %fmla, <4 x half> %lane, <4 x half> %fmla1)
# |   store <4 x half> %fmla2, ptr %ref.tmp, align 8
# |   %7 = load <4 x half>, ptr %ref.tmp, align 8
# |   store <4 x half> %7, ptr %__ret, align 8
# |   %8 = load <4 x half>, ptr %__ret, align 8
# |   store <4 x half> %8, ptr %tmp, align 8
# |   %9 = load <4 x half>, ptr %tmp, align 8
# |   ret <4 x half> %9
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x half> @test_vfmaq_lane_f16(<8 x half> noundef %a, <8 x half> noundef %b, <4 x half> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <4 x half>, align 8
# |   %__ret = alloca <8 x half>, align 16
# |   %__s0 = alloca <8 x half>, align 16
# |   %__s1 = alloca <8 x half>, align 16
# |   %__s2 = alloca <4 x half>, align 8
# |   %ref.tmp = alloca <16 x i8>, align 16
# |   %tmp = alloca <8 x half>, align 16
# |   store <8 x half> %a, ptr %a.addr, align 16
# |   store <8 x half> %b, ptr %b.addr, align 16
# |   store <4 x half> %c, ptr %c.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   store <8 x half> %0, ptr %__s0, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %1, ptr %__s1
# | ...
# `---data was truncated (10240/42739) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000561bd437a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561bd43770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561bd437a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80ee533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80ee58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80ee533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80ee51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561bd430fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561bd430fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561bd42f4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561bd3fa40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561bd3fa3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f80ee51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80ee51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80ee51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561bd3fa3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c (2050 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0c309e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c0c309b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c0c309e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f60e5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60e578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f60e5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60e571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0c3033e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c0c3033c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c0c3018b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c0c2cc80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c0c2cc7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f60e571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60e571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60e571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0c2cc7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c (2051 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), p
# | ...
# `---data was truncated (10240/87316) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c6643a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556c664370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556c6643a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab5ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab5eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab5ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab5ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c663cfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556c663cfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556c663b4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556c660640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556c66063dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fab5ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab5ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab5ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c66063cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c (2052 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %1, <vscale x 1 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %1, <vscale x 2 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %1, <vscale x 4 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %1, <vscale x 8 x i1> %0, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vse16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store 
# | ...
# `---data was truncated (10240/12644) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c0b9c815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558c0b9c50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558c0b9c889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae77933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae7798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae77933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae7791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c0b95de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558c0b95dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558c0b942b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558c0b5f20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558c0b5f1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fae7791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae7791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae7791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c0b5f1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c (2053 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64ff_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d91cb915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555d91cb60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555d91cb989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b72d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b72d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b72d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b72ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d91c4ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555d91c4ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555d91c33b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555d918e30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555d918e2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6b72ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b72cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b72cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d918e2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c (2054 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp sge <16 x i8> %0, %1
# |   %3 = select <16 x i1> %2, <16 x i8> %0, <16 x i8> %1
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp uge <8 x i16> %0, %1
# |   %3 = select <8 x i1> %2, <8 x i16> %0, <8 x i16> %1
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp sge <4 x i32> %0, %1
# |   %3 = select <4 x i1> %2, <4 x i32> %0, <4 x i32> %1
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056229c06515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056229c0620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056229c06589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc53861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5386725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc53861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc538603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056229bffae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056229bffac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056229bfdfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056229bc8f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056229bc8edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc538604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5386050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5386050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056229bc8ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c (2055 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556551c0815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556551c050f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556551c0889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7a7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7a76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7a7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7a7631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556551b9de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556551b9dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556551b82b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005565518320b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556551831dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb7a7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7a76330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7a76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556551831cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c (2056 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/128444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a34c78115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a34c77e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a34c78189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f21cb61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f21cb6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f21cb61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f21cb603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a34c716e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a34c716c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a34c6fbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a34c3ab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a34c3aadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f21cb604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f21cb6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f21cb6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a34c3aacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c (2057 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056299470615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005629947030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056299470689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0643e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0643e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0643e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0643e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056299469be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056299469bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562994680b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005629943300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056299432fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0643e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0643e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0643e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056299432fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c (2058 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 8 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 16 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.
# | ...
# `---data was truncated (10240/78156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055688955215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055688954f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055688955289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3f9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3f94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3f9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3f9431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568894e7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005568894e7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005568894ccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055688917c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055688917bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa3f9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3f94330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3f94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055688917bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c (2059 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg
# | ...
# `---data was truncated (10240/20483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dbc0de915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dbc0de60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dbc0de989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e98c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e98c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e98c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e98c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbc0d7ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dbc0d7ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dbc0d63b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dbc0a130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dbc0a12dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6e98c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e98c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e98c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbc0a12cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c (2060 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005623f803515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005623f80320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005623f803589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9947d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9947d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9947d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9947d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623f7fcae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005623f7fcac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005623f7fafb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005623f7c5f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005623f7c5edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9947d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9947d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9947d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623f7c5ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c (2061 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64
# | ...
# `---data was truncated (10240/94235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563bcd0b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563bcd0b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563bcd0b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f87cfa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87cfa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f87cfa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f87cfa03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563bcd04be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563bcd04bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563bcd030b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563bccce00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563bcccdfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f87cfa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87cfa050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87cfa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563bcccdfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c (2062 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b5992a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563b599270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563b5992a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fa5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fa50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fa5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fa5031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b598bfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563b598bfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563b598a4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563b595540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563b59553dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2fa5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fa50330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fa50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b59553cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c (2063 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 
# | ...
# `---data was truncated (10240/80500) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0157ee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d0157eb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d0157ee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0c9705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0c975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0c9705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0c96ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d015783e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d015783c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d015768b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d0154180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d015417dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd0c96eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0c96ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0c96ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d015417cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c (2064 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2_tu
# | ...
# `---data was truncated (10240/288275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b5d5be15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563b5d5bb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563b5d5be89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1672933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f167298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1672933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f167291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b5d553e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563b5d553c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563b5d538b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563b5d1e80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563b5d1e7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f167291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f167291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f167291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b5d1e7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c (2065 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af07e6915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055af07e660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055af07e6989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f747ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f747aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f747ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f747ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af07dfee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055af07dfec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055af07de3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055af07a930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055af07a92dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f747ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f747ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f747ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af07a92cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c (2066 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b2189515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557b218920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557b2189589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc86e905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc86e95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc86e905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc86e8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b2182ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557b2182ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557b2180fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557b214bf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557b214bedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc86e8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc86e8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc86e8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b214becc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c (2067 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsra_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/98343) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc071f415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dc071f10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dc071f489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d04133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d0418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d04133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d0411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc07189e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dc07189c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dc0716eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dc06e1e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dc06e1ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3d0411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d0411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d0411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc06e1dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c (2068 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4(<vscale x 16 x half> %
# | ...
# `---data was truncated (10240/149145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055615116715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005561511640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055615116789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff34e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff34e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff34e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff34e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561510fce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005561510fcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005561510e1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556150d910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556150d90dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff34e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff34e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff34e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556150d90cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c (2069 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vx_u8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhu_vv_u8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %o
# | ...
# `---data was truncated (10240/65883) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596ea37b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005596ea3780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005596ea37b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f036bc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f036bc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f036bc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f036bc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596ea310e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005596ea310c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005596ea2f5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005596e9fa50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005596e9fa4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f036bc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f036bc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f036bc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596e9fa4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c (2070 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_v_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_v_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_v_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_v_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_v_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmv_v_f_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_s_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_s_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_s_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_s_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_s_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.
# | ...
# `---data was truncated (10240/12648) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056104eca315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056104eca00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056104eca389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd5b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd5b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd5b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd5b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056104ec38e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056104ec38c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056104ec1db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056104e8cd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056104e8ccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcd5b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd5b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd5b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056104e8cccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c (2071 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.i64.i64(<vscale x 1 x i64> poison
# | ...
# `---data was truncated (10240/18569) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e38fe115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560e38fde0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560e38fe189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea9c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea9c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea9c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea9c831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e38f76e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560e38f76c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560e38f5bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560e38c0b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560e38c0add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fea9c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea9c8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea9c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e38c0acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c (2072 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055922570f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055922570c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055922570f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb83333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb8338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb83333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb8331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592256a4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005592256a4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559225689b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005592253390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559225338dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcb8331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb8331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb8331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559225338cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c (2073 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/30423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056174a2b015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056174a2ad0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056174a2b089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc0a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc0a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc0a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc0a031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056174a245e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056174a245c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056174a22ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561749eda0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561749ed9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efc0a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc0a0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc0a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561749ed9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c (2074 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf8x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf4x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8mf2x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_u8m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564de0f2c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564de0f290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564de0f2c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f287e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f287e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f287e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f287e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564de0ec1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564de0ec1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564de0ea6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564de0b560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564de0b55dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f287e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f287e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f287e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564de0b55cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c (2075 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 1, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovunbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovunbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 0, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovuntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovuntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 0, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 0, <4 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 0, <8 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   
# | ...
# `---data was truncated (10240/17536) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595f149f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005595f149c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005595f149f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4af2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4af258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4af2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4af251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595f1434e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005595f1434c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005595f1419b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005595f10c90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005595f10c8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4af251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4af251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4af251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595f10c8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c (2076 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056270b67915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056270b6760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056270b67989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ad6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ad66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ad6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ad6631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056270b60ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056270b60ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056270b5f3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056270b2a30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056270b2a2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2ad6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ad66330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ad66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056270b2a2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c (2077 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vset_v_f16m1_f16m2(<vscale x 8 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 8 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m1_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vset_v_f16m2_f16m4(<vscale x 16 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 16 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m1_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 4 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half>, <vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m2_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 8 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> %0, <vscale x 8 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half>, <vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vset_v_f16m4_f16m8(<vscale x 32 x half> %dest, i64 noundef %index, <vscale x 16 x half> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 32 x half> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x half> %val, ptr %val.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %val.addr, align 2
# |   %2 = call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> %0, <vscale x 16 x half> %1, i64 0)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half>, <vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vset_v_f32m1_f32m2(<vscale x 4 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 4 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m1_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float>, <vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vset_v_f32m2_f32m4(<vscale x 8 x float> %dest, i64 noundef %index, <vscale x 4 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 4 x float>, align 4
# |   store <vscale x 8 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> %0, <vscale x 4 x float> %1, i64 0)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float>, <vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vset_v_f32m1_f32m8(<vscale x 16 x float> %dest, i64 noundef %index, <vscale x 2 x float> %val) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   %val.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 16 x float> %dest, ptr %dest.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 2 x float> %val, ptr %val.addr, align 4
# |   %0 = load <vscale x 16 x float>, ptr %dest.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %val.addr, align 4
# |   %2 = call <vscale x 16 x float> @llvm.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> %0, <vscale x 2 x float> %1, i64 0)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16
# | ...
# `---data was truncated (10240/338692) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056418e50615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056418e5030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056418e50689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f292561bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29256725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f292561ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2925603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056418e49be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056418e49bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056418e480b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056418e1300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056418e12fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2925604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29256050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29256050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056418e12fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c (2078 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bbfb66915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bbfb6660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bbfb66989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe020449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0204a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe020449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe020431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbfb5fee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bbfb5fec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bbfb5e3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bbfb2930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bbfb292dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe020432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0204330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0204330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbfb292cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c (2079 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef4b5eb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ef4b5e80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ef4b5eb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95b8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95b8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95b8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95b8f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef4b580e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ef4b580c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ef4b565b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ef4b2150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ef4b214dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f95b8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95b8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95b8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef4b214cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c (2080 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @lshift_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shl = shl <32 x i8> %0, %1
# |   store <32 x i8> %shl, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @rshift_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shr = ashr <32 x i8> %0, %1
# |   store <32 x i8> %shr, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @lshift_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shl = shl <32 x i8> %0, %1
# |   store <32 x i8> %shl, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @rshift_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %shr = lshr <32 x i8> %0, %1
# |   store <32 x i8> %shr, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @lshift_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shl = shl <16 x i16> %0, %1
# |   store <16 x i16> %shl, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @rshift_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shr = ashr <16 x i16> %0, %1
# |   store <16 x i16> %shr, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @lshift_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shl = shl <16 x i16> %0, %1
# |   store <16 x i16> %shl, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @rshift_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %shr = lshr <16 x i16> %0, %1
# |   store <16 x i16> %shr, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @lshift_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %shl = shl <8 x i32> %0, %1
# |   store <8 x i32> %shl, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @rshift_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %r
# | ...
# `---data was truncated (10240/50943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055b3a3b8615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b3a3b830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b3a3b8689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4734133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f473418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4734133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f473411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b3a3b1be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b3a3b1bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b3a3b00b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b3a37b00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b3a37afdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f473411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f473411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f473411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b3a37afcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c (2081 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f65ffa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562f65ff70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562f65ffa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a2c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a2c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a2c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a2c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f65f8fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562f65f8fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562f65f74b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562f65c240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562f65c23dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3a2c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a2c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a2c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f65c23cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c (2082 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f32m1x2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f32m2x2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vect
# | ...
# `---data was truncated (10240/113765) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603fa9fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005603fa9f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005603fa9fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6bf8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6bf8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6bf8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6bf8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603fa990e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005603fa990c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005603fa975b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005603fa6250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005603fa624dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6bf8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6bf8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6bf8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603fa624cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c (2083 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.a
# | ...
# `---data was truncated (10240/38299) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056292e32715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056292e3240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056292e32789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f447c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f447c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f447c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f447c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056292e2bce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056292e2bcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056292e2a1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056292df510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056292df50dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f447c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f447c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f447c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056292df50cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c (2084 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d9e9b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558d9e9b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558d9e9b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f994cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f994cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f994cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f994cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d9e94be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558d9e94bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558d9e930b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558d9e5e00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558d9e5dfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f994cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f994cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f994cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d9e5dfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c (2085 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056392b31415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056392b3110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056392b31489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69bdc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69bdc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69bdc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69bdc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056392b2a9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056392b2a9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056392b28eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056392af3e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056392af3ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f69bdc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69bdc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69bdc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056392af3dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c (2086 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056185246615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005618524630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056185246689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1228e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1228ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1228e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1228e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618523fbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005618523fbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005618523e0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005618520900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056185208fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1228e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1228e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1228e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056185208fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c (2087 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b3d0ba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562b3d0b70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562b3d0ba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cef933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cef98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cef933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cef91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b3d04fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562b3d04fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562b3d034b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562b3cce40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562b3cce3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7cef91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cef91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cef91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b3cce3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c (2088 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 32 x half>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i16>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i16>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i16>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vle16ff_v_i16m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64.p0(<vscale x 4 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i16>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i16>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64.p0(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vle16ff_v_i16m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i16>, i64 } @llvm.riscv.vleff.nxv8i16.i64.p0(<vscale x 8 x i16> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale 
# | ...
# `---data was truncated (10240/39900) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e85385915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e8538560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e85385989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff62a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff62a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff62a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff62a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8537eee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e8537eec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e8537d3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e8534830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e853482dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff62a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff62a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff62a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e853482cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c (2089 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ecc3d8815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ecc3d850f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ecc3d8889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c2a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c2a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c2a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c2a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ecc3d1de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ecc3d1dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ecc3d02b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ecc39b20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ecc39b1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2c2a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c2a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c2a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ecc39b1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c (2090 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a0b9c015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564a0b9bd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564a0b9c089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f19cc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19cc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f19cc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f19cc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a0b955e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564a0b955c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564a0b93ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564a0b5ea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564a0b5e9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f19cc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19cc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19cc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a0b5e9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c (2091 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583f446215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005583f445f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005583f446289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8d4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8d498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8d4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8d491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583f43f7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005583f43f7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005583f43dcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005583f408c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005583f408bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe8d491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8d491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8d491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583f408bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c (2092 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmv_v_v_i8mf8(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmv_v_v_i8mf4(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmv_v_v_i8mf2(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmv_v_v_i8m1(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmv_v_v_i8m2(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmv_v_v_i8m4(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vmv_v_v_i8m8(<vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vmv_v_v_i16mf4(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vmv_v_v_i16mf2(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vmv_v_v_i16m1(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vmv_v_v_i16m2(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vmv_v_v_i16m4(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vmv_v_v_i16m8(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function A
# | ...
# `---data was truncated (10240/68067) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055938870715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005593887040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055938870789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f17d0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f17d08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f17d0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f17d0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055938869ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055938869cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559388681b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005593883310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559388330dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f17d0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f17d08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f17d08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559388330cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c (2093 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2_tu(<vscale
# | ...
# `---data was truncated (10240/288267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005586fee0715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005586fee040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005586fee0789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f08533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f0858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f08533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f0851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005586fed9ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005586fed9cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005586fed81b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005586fea310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005586fea30dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9f0851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f0851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f0851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005586fea30cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c (2094 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055594ea0f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055594ea0c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055594ea0f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd261505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd26155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd261505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2614ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055594e9a4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055594e9a4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055594e989b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055594e6390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055594e638dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd2614eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2614ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2614ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055594e638cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c (2095 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c877b0515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c877b020f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c877b0589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe745c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe745c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe745c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe745c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c877a9ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c877a9ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c877a7fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c87772f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c87772edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe745c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe745c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe745c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c87772ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c (2096 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563eb92fa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563eb92f70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563eb92fa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f2fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f2fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f2fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f2fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563eb928fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563eb928fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563eb9274b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563eb8f240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563eb8f23dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1f2fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f2fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f2fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563eb8f23cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c (2097 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float>, <v
# | ...
# `---data was truncated (10240/22290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c63a4015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564c63a3d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564c63a4089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e21a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e21aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e21a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e21a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c639d5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564c639d5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564c639bab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564c6366a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564c63669dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5e21a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e21a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e21a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c63669cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c (2098 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607de67f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005607de67c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005607de67f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb5df449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb5df4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb5df449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb5df431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607de614e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005607de614c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005607de5f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005607de2a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005607de2a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb5df432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb5df4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb5df4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607de2a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c (2099 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad1ea6115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ad1ea5e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ad1ea6189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8735f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8735f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8735f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8735f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad1e9f6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ad1e9f6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ad1e9dbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ad1e68b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ad1e68add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8735f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8735f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8735f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad1e68acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c (2100 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v_i8mf8x6
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056058d60915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056058d6060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056058d60989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06fe333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06fe38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06fe333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06fe31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056058d59ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056058d59ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056058d583b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056058d2330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056058d232dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f06fe31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06fe31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06fe31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056058d232cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c (2101 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562fc518915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562fc51860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562fc518989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff6d7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6d70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff6d7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6d7031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fc511ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562fc511ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562fc5103b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562fc4db30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562fc4db2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff6d7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6d70330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6d70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fc4db2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c (2102 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c7fe0215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558c7fdff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558c7fe0289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab04a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab04aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab04a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab04a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c7fd97e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558c7fd97c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558c7fd7cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558c7fa2c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558c7fa2bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fab04a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab04a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab04a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c7fa2bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c (2103 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %rs2.addr
# | ...
# `---data was truncated (10240/20623) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b159a6115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b159a5e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b159a6189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e99733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e9978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e99733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e9971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b1599f6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b1599f6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b1599dbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b15968b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b15968add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1e9971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e9971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e9971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b15968acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c (2104 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a366cab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a366ca80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a366cab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70f2a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70f2a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70f2a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70f2a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a366c40e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a366c40c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a366c25b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a3668d50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a3668d4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f70f2a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70f2a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70f2a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3668d4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c (2105 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale 
# | ...
# `---data was truncated (10240/40937) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ceb414415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ceb41410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ceb414489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9faf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9faf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9faf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9faf31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ceb40d9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ceb40d9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ceb40beb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ceb3d6e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ceb3d6ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9faf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9faf31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9faf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ceb3d6dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c (2106 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559dc2b7115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559dc2b6e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559dc2b7189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c85d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c85d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c85d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c85ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559dc2b06e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559dc2b06c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559dc2aebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559dc279b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559dc279add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5c85ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c85cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c85cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559dc279acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c (2107 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056092c5fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056092c5f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056092c5fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9d3f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9d3f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9d3f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9d3eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056092c591e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056092c591c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056092c576b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056092c2260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056092c225dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff9d3eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9d3eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9d3eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056092c225cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c (2108 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   cal
# | ...
# `---data was truncated (10240/39578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629225c915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005629225c60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005629225c989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3df905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3df95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3df905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3df8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056292255ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056292255ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562922543b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005629221f30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005629221f2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff3df8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3df8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3df8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629221f2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c (2109 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557083b4615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557083b430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557083b4689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f318e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f318e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f318e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f318e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557083adbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557083adbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557083ac0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005570837700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055708376fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f318e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f318e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f318e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055708376fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c (2110 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i
# | ...
# `---data was truncated (10240/150943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055662fe8c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055662fe890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055662fe8c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46ad305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46ad35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46ad305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46ad2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055662fe21e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055662fe21c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055662fe06b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055662fab60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055662fab5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f46ad2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46ad2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46ad2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055662fab5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c (2111 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_ran
# | ...
# `---data was truncated (10240/95347) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc6201315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dc620100f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dc6201389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb37049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb370a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb37049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb37031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc61fa8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dc61fa8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dc61f8db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dc61c3d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dc61c3cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feb37032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb370330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb370330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc61c3ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c (2112 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i6
# | ...
# `---data was truncated (10240/56171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005623c718215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005623c717f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005623c718289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f820a61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f820a6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f820a61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f820a603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623c7117e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005623c7117c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005623c70fcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005623c6dac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005623c6dabdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f820a604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f820a6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f820a6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005623c6dabcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c (2113 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 8 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 16 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 4
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i32>, i64 } @llvm.risc
# | ...
# `---data was truncated (10240/78164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de0715915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055de071560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055de0715989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0443649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f04436a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0443649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0443631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de070eee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055de070eec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055de070d3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055de06d830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055de06d82dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0443632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f04436330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f04436330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de06d82cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c (2114 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056403a7ec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056403a7e90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056403a7ec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d72933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d7298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d72933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d7291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056403a781e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056403a781c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056403a766b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056403a4160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056403a415dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4d7291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d7291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d7291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056403a415cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c (2115 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> 
# | ...
# `---data was truncated (10240/157475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad9315915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ad931560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ad9315989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd8bfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd8bfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd8bfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8bfb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad930eee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ad930eec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ad930d3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ad92d830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ad92d82dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd8bfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8bfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8bfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad92d82cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c (2116 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_loc
# | ...
# `---data was truncated (10240/37556) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d966e9b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d966e980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d966e9b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71b5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71b52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71b5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71b5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d966e30e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d966e30c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d966e15b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d966ac50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d966ac4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f71b5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71b52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71b52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d966ac4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c (2117 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_i16m1x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tu
# | ...
# `---data was truncated (10240/17844) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560bb4d3f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560bb4d3c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560bb4d3f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c19c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c19ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c19c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c19c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560bb4cd4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560bb4cd4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560bb4cb9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560bb49690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560bb4968dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6c19c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c19c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c19c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560bb4968cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c (2118 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmul_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmul_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmul_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmul_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmul_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmul_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/175155) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fda7d6615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fda7d630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fda7d6689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2094b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2094b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2094b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2094b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fda7cfbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fda7cfbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fda7ce0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fda79900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fda798fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2094b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2094b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2094b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fda798fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c (2119 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, a
# | ...
# `---data was truncated (10240/98437) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563334bca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563334bc70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563334bca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f746a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f746a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f746a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f746a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563334b5fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563334b5fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563334b44b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005633347f40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005633347f3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f746a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f746a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f746a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633347f3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c (2120 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_f32mf2(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_f32m1(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_f32m2(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_f32m4(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16.nx
# | ...
# `---data was truncated (10240/90875) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8362bf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e8362bc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e8362bf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f204c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f204c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f204c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f204c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e836254e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e836254c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e836239b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e835ee90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e835ee8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f204c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f204c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f204c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e835ee8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c (2121 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564db46a615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564db46a30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564db46a689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbf0701bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbf070725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbf0701ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbf07003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564db463be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564db463bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564db4620b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564db42d00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564db42cfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbf07004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbf070050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbf070050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564db42cfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c (2122 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055adf8bf215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055adf8bef0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055adf8bf289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa80b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa80b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa80b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa80b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055adf8b87e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055adf8b87c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055adf8b6cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055adf881c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055adf881bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa80b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa80b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa80b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055adf881bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c (2123 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdiv.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdiv_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <v
# | ...
# `---data was truncated (10240/97639) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055749156f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055749156c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055749156f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2ce105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2ce15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2ce105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2ce0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557491504e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557491504c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005574914e9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005574911990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557491198dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa2ce0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2ce0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2ce0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557491198cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c (2124 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64
# | ...
# `---data was truncated (10240/24373) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fce9d0315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fce9d000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fce9d0389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effe7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effe74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effe7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effe7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fce9c98e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fce9c98c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fce9c7db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fce992d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fce992cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007effe7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effe74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effe74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fce992ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c (2125 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64
# | ...
# `---data was truncated (10240/110129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055591c48615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055591c4830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055591c48689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ac8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ac86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ac8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ac8631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055591c41be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055591c41bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055591c400b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055591c0b00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055591c0afdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8ac8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ac86330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ac86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055591c0afcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c (2126 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_bf16m4_f32m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_bf16m4_f32m8(<vscale x 16 x bfloat> %vs2, bflo
# | ...
# `---data was truncated (10240/43940) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558e12b2415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558e12b210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558e12b2489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b11333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b1138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b11333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b1131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558e12ab9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558e12ab9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558e12a9eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558e1274e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558e1274ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6b1131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b1131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b1131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558e1274dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c (2127 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/13161) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567befdc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005567befd90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005567befdc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16f461bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16f46725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16f461ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16f4603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567bef71e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005567bef71c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005567bef56b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005567bec060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005567bec05dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f16f4604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16f46050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16f46050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567bec05cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c (2128 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_l
# | ...
# `---data was truncated (10240/13585) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0eae7a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b0eae770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b0eae7a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e60533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e6058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e60533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e6051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0eae0fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b0eae0fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b0eadf4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b0eaaa40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b0eaaa3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7e6051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e6051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e6051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0eaaa3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c (2129 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1a239215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d1a238f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d1a239289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff53d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff53d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff53d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff53d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1a2327e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d1a2327c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d1a230cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d1a1fbc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d1a1fbbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff53d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff53d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff53d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1a1fbbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/WebAssembly/builtins-table-funcref.c (2130 of 27911)
******************** TEST 'Clang :: CodeGen/WebAssembly/builtins-table-funcref.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c"
# | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"
# | target triple = "wasm32"
# | 
# | @table = internal addrspace(1) global [0 x target("wasm.funcref")] zeroinitializer, align 4
# | @other_table = internal addrspace(1) global [0 x target("wasm.funcref")] zeroinitializer, align 4
# | 
# | ; Function Attrs: noinline nounwind
# | define target("wasm.funcref") @test_builtin_wasm_table_get(i32 noundef %index) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = call target("wasm.funcref") @llvm.wasm.table.get.funcref(ptr addrspace(1) @table, i32 %0)
# |   ret target("wasm.funcref") %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("wasm.funcref") @llvm.wasm.table.get.funcref(ptr addrspace(1), i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_set(i32 noundef %index, target("wasm.funcref") noundef %ref) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.funcref"), align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.funcref") %ref, ptr %ref.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.funcref"), ptr %ref.addr, align 4
# |   call void @llvm.wasm.table.set.funcref(ptr addrspace(1) @table, i32 %0, target("wasm.funcref") %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.wasm.table.set.funcref(ptr addrspace(1), i32, target("wasm.funcref")) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_size() #0 {
# | entry:
# |   %0 = call i32 @llvm.wasm.table.size(ptr addrspace(1) @table)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare i32 @llvm.wasm.table.size(ptr addrspace(1)) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_grow(target("wasm.funcref") noundef %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %ref.addr = alloca target("wasm.funcref"), align 4
# |   %nelem.addr = alloca i32, align 4
# |   store target("wasm.funcref") %ref, ptr %ref.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load target("wasm.funcref"), ptr %ref.addr, align 4
# |   %1 = load i32, ptr %nelem.addr, align 4
# |   %2 = call i32 @llvm.wasm.table.grow.funcref(ptr addrspace(1) @table, target("wasm.funcref") %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare i32 @llvm.wasm.table.grow.funcref(ptr addrspace(1), target("wasm.funcref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_fill(i32 noundef %index, target("wasm.funcref") noundef %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.funcref"), align 4
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.funcref") %ref, ptr %ref.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.funcref"), ptr %ref.addr, align 4
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.fill.funcref(ptr addrspace(1) @table, i32 %0, target("wasm.funcref") %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.fill.funcref(ptr addrspace(1), i32, target("wasm.funcref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_table_copy(i32 noundef %dst_idx, i32 noundef %src_idx, i32 noundef %nelem) #0 {
# | entry:
# |   %dst_idx.addr = alloca i32, align 4
# |   %src_idx.addr = alloca i32, align 4
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %dst_idx, ptr %dst_idx.addr, align 4
# |   store i32 %src_idx, ptr %src_idx.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %dst_idx.addr, align 4
# |   %1 = load i32, ptr %src_idx.addr, align 4
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.copy(ptr addrspace(1) @table, ptr addrspace(1) @other_table, i32 %1, i32 %0, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.copy(ptr addrspace(1), ptr addrspace(1), i32, i32, i32) #3
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+reference-types" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563206c4d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563206c4a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563206c4d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f99d7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99d78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f99d7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f99d7831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563206be2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563206be2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563206bc7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005632068770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563206876dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f99d7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99d78330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99d78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563206876cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c (2131 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/31938) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8c7d9c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d8c7d990f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d8c7d9c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b28533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b2858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b28533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b2851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8c7d31e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d8c7d31c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d8c7d16b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d8c79c60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d8c79c5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4b2851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b2851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b2851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8c79c5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c (2132 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vrgatherei16_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vrgatherei16_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vrgatherei16_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vrgatherei16_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vrgatherei16_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vrgatherei16_vv_f16m8(<vscale x 32 x half> %op1, <vscale x 32 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vrgatherei16_vv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vrgatherei16_vv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vrgatherei16_vv_f32m2(<vscale x 4 x float> %op1, <vscale x 4 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 4 x i16> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vrgatherei16_vv_f32m4(<vscale x 8 x float> %op1, <vscale x 8 x i16> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store <vscal
# | ...
# `---data was truncated (10240/124036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648bdcbe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005648bdcbb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005648bdcbe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00b9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00b96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00b9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00b9631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648bdc53e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005648bdc53c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005648bdc38b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005648bd8e80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005648bd8e7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f00b9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00b96330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00b96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648bd8e7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c (2133 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function
# | ...
# `---data was truncated (10240/100281) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056493861a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005649386170f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056493861a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5364533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f536458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5364533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f536451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649385afe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005649385afc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564938594b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005649382440b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564938243dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f536451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f536451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f536451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564938243cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c (2134 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_v
# | ...
# `---data was truncated (10240/253156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f3588c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557f358890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557f3588c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a0c41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a0c4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a0c41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a0c403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f35821e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557f35821c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557f35806b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557f354b60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557f354b5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2a0c404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a0c4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a0c4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f354b5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c (2135 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vloxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(<vscale x 
# | ...
# `---data was truncated (10240/118164) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd14ba515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dd14ba20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dd14ba589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd6c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd6c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd6c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd6c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd14b3ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dd14b3ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dd14b1fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dd147cf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dd147cedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdd6c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd6c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd6c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd147cecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c (2136 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.
# | ...
# `---data was truncated (10240/164791) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590d6af515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005590d6af20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005590d6af589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb36af05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb36af5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb36af05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb36aeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590d6a8ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005590d6a8ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005590d6a6fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005590d671f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005590d671edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb36aeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb36aeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb36aeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590d671ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c (2137 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x flo
# | ...
# `---data was truncated (10240/101584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c4c4d515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560c4c4d20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560c4c4d589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc320333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc32038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc320333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc32031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c4c46ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560c4c46ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560c4c44fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560c4c0ff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560c4c0fedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc32031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc32031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc32031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c4c0fecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c (2138 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale 
# | ...
# `---data was truncated (10240/56179) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055632e9fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055632e9f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055632e9fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbebf505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbebf55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbebf505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbebf4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055632e991e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055632e991c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055632e976b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055632e6260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055632e625dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbebf4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbebf4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbebf4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055632e625cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c (2139 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmseq_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmseq_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmseq_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmseq_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/116267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559377ff615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559377ff30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559377ff689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f41bb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41bb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f41bb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f41bb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559377f8be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559377f8bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559377f70b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559377c200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559377c1fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f41bb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41bb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41bb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559377c1fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c (2140 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055847a67a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055847a6770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055847a67a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f843c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f843c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f843c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f843c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055847a60fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055847a60fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055847a5f4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055847a2a40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055847a2a3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f843c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f843c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f843c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055847a2a3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c (2141 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/40795) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056072347615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005607234730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056072347689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5d0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5d0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5d0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5d0d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056072340be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056072340bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005607233f0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005607230a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056072309fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc5d0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5d0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5d0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056072309fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c (2142 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vslide1up_vx_i8mf8(<vscale x 1 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vslide1up_vx_i8mf4(<vscale x 2 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vslide1up_vx_i8mf2(<vscale x 4 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vslide1up_vx_i8m1(<vscale x 8 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vslide1up_vx_i8m2(<vscale x 16 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vslide1up_vx_i8m4(<vscale x 32 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vslide1up_vx_i8m8(<vscale x 64 x i8> %src, i8 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %value.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i8 %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = load i8, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vslide1up_vx_i16mf4(<vscale x 1 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vslide1up_vx_i16mf2(<vscale x 2 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vslide1up_vx_i16m1(<vscale x 4 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i16, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vslide1up_vx_i16m2(<vscale x 8 x i16> %src, i16 noundef signext %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca i16, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i16 %value, ptr %v
# | ...
# `---data was truncated (10240/86747) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d2d08915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559d2d0860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559d2d08989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2423c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2423ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2423c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2423c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d2d01ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559d2d01ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559d2d003b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559d2ccb30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559d2ccb2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2423c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2423c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2423c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d2ccb2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c (2143 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a4731a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555a473170f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555a4731a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8602d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8602d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8602d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8602ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a472afe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555a472afc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555a47294b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555a46f440b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555a46f43dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8602ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8602cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8602cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a46f43cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c (2144 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056178ae6f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056178ae6c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056178ae6f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3bb4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3bb4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3bb4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3bb4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056178ae04e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056178ae04c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056178ade9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056178aa990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056178aa98dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3bb4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3bb4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3bb4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056178aa98cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c (2145 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredand_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredand_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/113047) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612ff30615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005612ff3030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005612ff30689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f77fc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f77fc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f77fc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f77fc431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612ff29be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005612ff29bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005612ff280b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005612fef300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005612fef2fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f77fc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f77fc4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f77fc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612fef2fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c (2146 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsne_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsne_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsne_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsne_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/116267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ddad29115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ddad28e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ddad29189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba07705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba0775c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba07705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba076ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ddad226e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ddad226c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ddad20bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ddacebb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ddacebadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fba076eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba076ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba076ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ddacebacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c (2147 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4(<vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2(<vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1(<vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2(<vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4(<vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8(<vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x half> %op1, float noun
# | ...
# `---data was truncated (10240/25091) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4ad0c815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d4ad0c50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d4ad0c889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1b8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1b88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1b8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1b8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4ad05de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d4ad05dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d4ad042b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d4accf20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d4accf1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc1b8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1b88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1b88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4accf1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c (2148 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, ali
# | ...
# `---data was truncated (10240/201234) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573f6fe015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005573f6fdd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005573f6fe089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe08d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe08d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe08d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe08d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573f6f75e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005573f6f75c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005573f6f5ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005573f6c0a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005573f6c09dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe08d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe08d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe08d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573f6c09cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c (2149 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0a8ede15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f0a8edb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f0a8ede89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07afd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07afd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07afd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07afd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0a8e73e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f0a8e73c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f0a8e58b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f0a8b080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f0a8b07dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f07afd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07afd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07afd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0a8b07cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c (2150 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f980b515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558f980b20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558f980b589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13ec933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13ec98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13ec933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13ec91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f9804ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558f9804ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558f9802fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558f97cdf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558f97cdedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f13ec91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13ec91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13ec91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f97cdecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c (2151 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f28d07b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f28d0780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f28d07b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfed133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfed18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfed133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfed11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f28d010e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f28d010c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f28cff5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f28cca50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f28cca4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcfed11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfed11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfed11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f28cca4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c (2152 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", <vs
# | ...
# `---data was truncated (10240/227771) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cde7f3915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cde7f360f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cde7f3989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13be733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13be78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13be733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13be71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cde7ecee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cde7ecec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cde7eb3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cde7b630b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cde7b62dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f13be71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13be71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13be71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cde7b62cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c (2153 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056444129415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005644412910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056444129489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6d0ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6d0ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6d0ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6d0ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564441229e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564441229c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056444120eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564440ebe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564440ebddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6d0ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6d0ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6d0ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564440ebdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c (2154 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Functi
# | ...
# `---data was truncated (10240/15986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f6313e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558f6313b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558f6313e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff340249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3402a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff340249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff340231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f630d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558f630d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558f630b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558f62d680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558f62d67dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff340232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3402330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3402330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f62d67cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c (2155 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2(<vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1(<vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2(<vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4(<vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8(<vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ffa3bf115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ffa3bee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ffa3bf189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd647133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd64718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd647133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd64711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffa3b86e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ffa3b86c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ffa3b6bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ffa381b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ffa381add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd64711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd64711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd64711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffa381acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c (2156 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v_i8mf8x8
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575e718d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005575e718a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005575e718d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f650a105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f650a15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f650a105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f650a0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575e7122e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005575e7122c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005575e7107b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005575e6db70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005575e6db6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f650a0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f650a0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f650a0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575e6db6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c (2157 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591f07d215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005591f07cf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005591f07d289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a36d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a36d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a36d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a36d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591f0767e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005591f0767c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005591f074cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005591f03fc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005591f03fbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3a36d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a36d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a36d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591f03fbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c (2158 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_u16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_u16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561993ec715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561993ec40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561993ec789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0402d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0402d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0402d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0402d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561993e5ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561993e5cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561993e41b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561993af10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561993af0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0402d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0402d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0402d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561993af0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c (2159 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ef8d2515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560ef8d220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560ef8d2589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1432e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1432e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1432e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1432e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ef8cbae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560ef8cbac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560ef8c9fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560ef894f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560ef894edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1432e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1432e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1432e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ef894ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c (2160 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b2203315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559b220300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559b2203389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33f261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33f26725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33f261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33f2603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b21fc8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559b21fc8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559b21fadb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559b21c5d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559b21c5cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f33f2604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33f26050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33f26050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b21c5ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c (2161 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595c712215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005595c711f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005595c712289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f84aa333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84aa38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f84aa333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f84aa31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595c70b7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005595c70b7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005595c709cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005595c6d4c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005595c6d4bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f84aa31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84aa31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84aa31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595c6d4bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-neon-numeric-maxmin.c (2162 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-numeric-maxmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vmaxnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vmaxnm_v.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vmaxnm_v1.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vmaxnm_v2.i = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %vmaxnm_v.i, <2 x float> %vmaxnm_v1.i)
# |   %vmaxnm_v3.i = bitcast <2 x float> %vmaxnm_v2.i to <8 x i8>
# |   store <8 x i8> %vmaxnm_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vmaxnmq_v.i = bitcast <16 x i8> %2 to <4 x float>
# |   %vmaxnmq_v1.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vmaxnmq_v2.i = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %vmaxnmq_v.i, <4 x float> %vmaxnmq_v1.i)
# |   %vmaxnmq_v3.i = bitcast <4 x float> %vmaxnmq_v2.i to <16 x i8>
# |   store <16 x i8> %vmaxnmq_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vminnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vminnm_v.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vminnm_v1.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vminnm_v2.i = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %vminnm_v.i, <2 x float> %vminnm_v1.i)
# |   %vminnm_v3.i = bitcast <2 x float> %vminnm_v2.i to <8 x i8>
# |   store <8 x i8> %vminnm_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vminnmq_v.i = bitcast <16 x i8> %2 to <4 x float>
# |   %vminnmq_v1.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vminnmq_v2.i = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %vminnmq_v.i, <4 x float> %vminnmq_v1.i)
# |   %vminnmq_v3.i = bitcast <4 x float> %vminnmq_v2.i to <16 x i8>
# |   store <16 x i8> %vminnmq_v3.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs-linux"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000056018d4a815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056018d4a50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056018d4a889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fadf2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fadf26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fadf2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fadf2631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056018d43de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056018d43dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056018d422b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056018d0d20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056018d0d1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fadf2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fadf26330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fadf26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056018d0d1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmldav.c (2163 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmldav.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vmldava.v16i8(i32, i32, i32, i32, <16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vmldava.v8i16(i32, i32, i32, i32, <8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.mve.vmldava.v4i32(i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 1, i32 0, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 1, i32 0, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 1, i32 0, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 1, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load <4 x i32>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 1, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <8 x i16>, align 8
# |   %c.addr = alloca <8 x i16>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store <8 x i16> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load <8 x i16>, ptr %c.addr, align 8
# |   %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca <4 x i32>, align 8
# |   %c.addr = alloca <4 x i32>, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store <4 x i32> %c, ptr %c.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load <4 x i32>, ptr
# | ...
# `---data was truncated (10240/44315) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000560c51bb515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560c51bb20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560c51bb589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0421733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f042178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0421733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f042171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c51b4ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560c51b4ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560c51b2fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560c517df0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560c517dedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f042171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f042171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f042171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c517decc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c (2164 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a0763815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561a076350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561a0763889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2594f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2594f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2594f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2594f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a075cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561a075cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561a075b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561a072620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561a07261dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2594f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2594f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2594f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a07261cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c (2165 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8(<vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vneg_v_i16m2(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vneg_v_i16m4(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vneg_v_i16m8(<vscale x 32 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vsc
# | ...
# `---data was truncated (10240/41425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630d26f915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005630d26f60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005630d26f989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6383b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6383b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6383b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6383b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630d268ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005630d268ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005630d2673b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005630d23230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005630d2322dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6383b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6383b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6383b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630d2322cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c (2166 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d05f8d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559d05f8a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559d05f8d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72f3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72f30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72f3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72f3031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d05f22e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559d05f22c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559d05f07b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559d05bb70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559d05bb6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f72f3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72f30330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72f30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d05bb6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c (2167 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %v
# | ...
# `---data was truncated (10240/142327) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ec03bf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556ec03bc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556ec03bf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d62a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d62aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d62a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d62a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ec0354e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556ec0354c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556ec0339b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556ebffe90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556ebffe8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3d62a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d62a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d62a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ebffe8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c (2168 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db3975b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055db397580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055db3975b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0514f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0514f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0514f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0514f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db396f0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055db396f0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055db396d5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055db393850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055db39384dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0514f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0514f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0514f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db39384cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c (2169 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("ri
# | ...
# `---data was truncated (10240/13634) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055869b6ec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055869b6e90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055869b6ec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f018d01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f018d0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f018d01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f018d003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055869b681e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055869b681c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055869b666b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055869b3160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055869b315dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f018d004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f018d0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f018d0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055869b315cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c (2170 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16mf2_f16mf4(<vscale x 2 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv2f16(<vscale x 2 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m1_f16mf4(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m1_f16mf2(<vscale x 4 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv4f16(<vscale x 4 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m2_f16mf4(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m2_f16mf2(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m2_f16m1(<vscale x 8 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m4_f16mf4(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m4_f16mf2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m4_f16m1(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m4_f16m2(<vscale x 16 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlmul_trunc_v_f16m8_f16mf4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.vector.extract.nxv1f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlmul_trunc_v_f16m8_f16mf2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlmul_trunc_v_f16m8_f16m1(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlmul_trunc_v_f16m8_f16m2(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlmul_trunc_v_f16m8_f16m4(<vscale x 32 x half> %op1) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | ...
# `---data was truncated (10240/78234) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056320577f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056320577c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056320577f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0462a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0462a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0462a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0462a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563205714e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563205714c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005632056f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005632053a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005632053a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0462a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0462a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0462a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632053a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c (2171 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/31876) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ae79a015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557ae799d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557ae79a089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9ffe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9ffea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9ffe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9ffe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ae7935e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557ae7935c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557ae791ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557ae75ca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557ae75c9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe9ffe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9ffe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9ffe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ae75c9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c (2172 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <v
# | ...
# `---data was truncated (10240/157467) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055875736215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055875735f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055875736289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd3f9a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3f9a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd3f9a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3f9a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587572f7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005587572f7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005587572dcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558756f8c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558756f8bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd3f9a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3f9a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3f9a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558756f8bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c (2173 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e4m3mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e4m3mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e4m3mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e4m3m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e4m3m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e4m3m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e4m3m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e4m3mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e4m3mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e4m3mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e4m3m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e4m3m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e4m3m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e4m3m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e5m2mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e5m2mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e5m2mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e5m2m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e5m2m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e5m2m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e5m2m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e5m2mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e5m2mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e5m2mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e5m2m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e5m2m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e5m2m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e5m2m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 =
# | ...
# `---data was truncated (10240/10936) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055808983815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005580898350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055808983889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc108a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc108aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc108a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc108a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580897cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005580897cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005580897b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005580894620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558089461dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc108a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc108a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc108a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558089461cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c (2174 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.ad
# | ...
# `---data was truncated (10240/306619) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564dc78415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005564dc7810f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005564dc78489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8779c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8779ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8779c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8779c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564dc719e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005564dc719c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005564dc6feb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005564dc3ae0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005564dc3addd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8779c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8779c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8779c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564dc3adcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c (2175 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005575b2b7215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005575b2b6f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005575b2b7289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5bfc049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5bfc0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5bfc049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5bfc031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005575b2b07e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005575b2b07c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005575b2aecb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005575b279c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005575b279bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5bfc032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5bfc0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5bfc0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575b279bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c (2176 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b27cee115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b27cede0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b27cee189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d35133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d3518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d35133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d3511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b27ce76e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b27ce76c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b27ce5bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b27cb0b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b27cb0add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5d3511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d3511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d3511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b27cb0acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c (2177 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %o
# | ...
# `---data was truncated (10240/70102) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d5d16c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564d5d1690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564d5d16c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0693733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f069378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0693733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f069371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d5d101e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564d5d101c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564d5d0e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564d5cd960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564d5cd95dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f069371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f069371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f069371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d5cd95cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c (2178 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f39cab215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f39caaf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f39cab289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fadad933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fadad98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fadad933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fadad91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f39ca47e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f39ca47c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f39ca2cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f39c6dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f39c6dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fadad91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fadad91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fadad91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f39c6dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c (2179 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf2_i32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf2_i64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf2_i64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %op
# | ...
# `---data was truncated (10240/28563) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f37f92215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f37f91f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f37f92289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f831b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f831b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f831b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f831b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f37f8b7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f37f8b7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f37f89cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f37f54c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f37f54bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f831b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f831b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f831b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f37f54bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c (2180 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.minnum.v8f16(<8 x half> %0, <8 x half> %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %0, <4 x float> %1)
# |   ret <4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x half>, ptr %inactive.addr, align 8
# |   %6 = call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> %5)
# |   ret <8 x half> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> undef)
# |   ret <4 x float> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2a12ad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e2a12aa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e2a12ad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb48a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb48aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb48a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb48a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2a1242e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e2a1242c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e2a1227b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e2a0ed70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e2a0ed6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcb48a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb48a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb48a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2a0ed6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm_acle.c (2181 of 27911)
******************** TEST 'Clang :: CodeGen/arm_acle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple armv8a-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple armv8a-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8a-unknown-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_dmb() #0 {
# | entry:
# |   call void @llvm.arm.dmb(i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dmb(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_dsb() #0 {
# | entry:
# |   call void @llvm.arm.dsb(i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dsb(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_isb() #0 {
# | entry:
# |   call void @llvm.arm.isb(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.isb(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_yield() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.hint(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_wfe() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_wfi() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sev() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sevl() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_dbg() #0 {
# | entry:
# |   call void @llvm.arm.dbg(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.arm.dbg(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_swp(i32 noundef %x, ptr noundef %p) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__p.addr.i = alloca ptr, align 4
# |   %__v.i = alloca i32, align 4
# |   %.atomictmp.i = alloca i32, align 4
# |   %atomic-temp.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %p.addr = alloca ptr, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store ptr %p, ptr %p.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load ptr, ptr %p.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store ptr %1, ptr %__p.addr.i, align 4
# |   %2 = load ptr, ptr %__p.addr.i, align 4
# |   %3 = load i32, ptr %__x.addr.i, align 4
# |   store i32 %3, ptr %.atomictmp.i, align 4
# |   %4 = load i32, ptr %.atomictmp.i, align 4
# |   %5 = atomicrmw volatile xchg ptr %2, i32 %4 monotonic, align 4
# |   store i32 %5, ptr %atomic-temp.i, align 4
# |   %6 = load i32, ptr %atomic-temp.i, align 4
# |   store i32 %6, ptr %__v.i, align 4
# |   %7 = load i32, ptr %__v.i, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_pld() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
# | declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg range(i32 0, 2), i32 immarg range(i32 0, 4), i32 immarg range(i32 0, 2)) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_pldx() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 1, i32 3, i32 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_pli() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_plix() #0 {
# | entry:
# |   call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_nop() #0 {
# | entry:
# |   call void @llvm.arm.hint(i32 0)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ror(i32 noundef %x, i32 noundef %y) #0 {
# | entry:
# |   %retval.i = alloca i32, align 4
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load i32, ptr %y.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__y.addr.i, align 4
# |   %rem.i = urem i32 %2, 32
# |   store i32 %rem.i, ptr %__y.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %cmp.i = icmp eq i32 %3, 0
# |   br i1 %cmp.i, label %if.then.i, label %if.end.i
# | 
# | if.then.i:                                        ; preds = %entry
# |   %4 = load i32, ptr %__x.addr.i, align 4
# |   store i32 %4, ptr %retval.i, align 4
# |   br label %__ror.exit
# | 
# | if.end.i:                                         ; preds = %entry
# |   %5 = load i32, ptr %__x.addr.i, align 4
# |   %6 = load i32, ptr %__y.addr.i, align 4
# |   %shr.i = lshr i32 %5, %6
# |   %7 = load i32, ptr %__x.addr.i, align 4
# |   %8 = load i32, ptr %__y.addr.i, align 4
# |   %sub.i = sub i32 32, %8
# |   %shl.i = shl i32 %7, %sub.i
# |   %or.i = or i32 %shr.i, %shl.i
# |   store i32 %or.i, ptr %retval.i, align 4
# |   br label %__ror.exit
# | 
# | __ror.exit:                                       ; preds = %if.then.i, %if.end.i
# |   %9 = load i32, ptr %retval.i, align 4
# |   ret i32 %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_rorl(i32 noundef %x, i32 noundef %y) #0 {
# | entry:
# |   %retval.i.i = alloca i32, align 4
# |   %__x.addr.i.i = alloca i32, align 4
# |   %__y.addr.i.i = alloca i32, align 4
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %x.addr = alloca i32, align 4
# |   %y.addr = alloca i32, align 4
# |   store i32 %x, ptr %x.addr, align 4
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load i32, ptr %x.addr, align 4
# |   %1 = load i32, ptr %y.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   store i32 %2, ptr %__x.addr.i.i, align 4
# |   store i32 %3, ptr %__y.addr.i.i, align 4
# |   %4 = load i32, ptr %__y.addr.i.i, align 4
# |   %rem.i.i = urem i32 %4, 32
# |   store i32 %rem.i.i, ptr %__y.addr.i.i, align 4
# |   %5 = load i32, ptr %__y.addr.i.i, align 4
# |   %cmp.i.i = icmp eq i32 %5, 0
# |   br i1 %cmp.i.i, label %if.then.i.i, label %if.end.i.i
# | 
# | if.then.i.i:                                      ; preds = %entry
# |   %6 = load i32, ptr %__x.addr.i.i, align 4
# |   store i32 %6, ptr %retval.i.i, align 4
# |   br label %__rorl.exit
# | 
# | if.end.i.i:                                       ; preds = %entry
# |   %7 = load i32, ptr %__x.addr.i.i, align 4
# |   %8 = load i32, ptr %__y.addr.i.i, align 4
# |   %shr.i.i = lshr i32 %7, %8
# |   %9 = load i32, ptr %__x.addr.i.i, align 4
# |   %10 = load i32, ptr %__y.addr.i.i, align 4
# |   %sub.i.i = sub i32 32, %10
# |   %shl.i.i = shl i32 %9, %sub.i.i
# |   %or.i.i = or i32 %shr.i.i, %shl.i.i
# |   store i32 %or.i.i, ptr %retval.i.i, align 4
# |   br label %__rorl.exit
# | 
# | __rorl.exit:                                      ; preds = %if.then.i.i, %if.end.i.i
# |   %11 = load i32, ptr %retval.i.i, align 4
# |   ret i32 %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_rorll(i64 noundef %x, i32 noundef %y) #0 {
# | entry:
# |   %retval.i = alloca i64, align 8
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i32, align 4
# |   %x.addr = alloca i64, align 8
# |   %y.addr = alloca i32, align 4
# |   store i64 %x, ptr %x.addr, align 8
# |   store i32 %y, ptr %y.addr, align 4
# |   %0 = load i64, ptr %x.addr, align 8
# |   %1 = load i32, ptr %y.addr, align 4
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__y.addr.i, align 4
# |   %rem.i = urem i32 %2, 64
# |   store i32 %rem.i, ptr %__y.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %cmp.i = icmp eq i32 %3, 0
# |   br i1 %cmp.i, label %if.then.i, label %if.end.i
# | 
# | if.then.i:                                        ; preds = %entry
# |   %4 = load i64, ptr %__x.addr.i, align 8
# |   store i64 %4, ptr %retval.i, align 8
# |   br label %__rorll.exit
# | 
# | if.end.i:                                         ; preds = %entry
# |   %5 = load i64, ptr %__x.addr.i, align 8
# |   %6 = load i32, ptr %__y.addr.i, align 4
# |   %sh_prom.i = zext i32 %6 to i64
# |   %shr.i = lshr i64 %5, %sh_prom.i
# |   %7 = load i64, ptr %__x.addr.i, align 8
# |   %8 = load i32, ptr %__y.addr.i, align 4
# |   %sub.i = sub i32 64, %8
# |   %sh_prom1.i = zext i32 %sub.i to i64
# |   %shl.i = shl i64 %7, %sh_prom1.i
# |   %or.i = or i64 %shr.i, %shl.i
# |   store i64 %or.i, ptr %retval.i, align 8
# |   br label %__rorll.exit
# | 
# | __rorll.exit:                                     ; preds = %if.then.i, %if.end.i
# |   %9 = load i64, ptr %retval.i, align 8
# |   ret i64 %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_clz(i32 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i32, align 4
# |   %t.addr = alloca i32, align 4
# |   store i32 %t, ptr %t.addr, align 4
# |   %0 = load i32, ptr %t.addr, align 4
# |   store i32 %0, ptr %__t.addr.i, align 4
# |   %1 = load i32, ptr %__t.addr.i, align 4
# |   %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_clzl(i32 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i32, align 4
# |   %t.addr = alloca i32, align 4
# |   store i32 %t, ptr %t.addr, align 4
# |   %0 = load i32, ptr %t.addr, align 4
# |   store i32 %0, ptr %__t.addr.i, align 4
# |   %1 = load i32, ptr %__t.addr.i, align 4
# |   %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_clzll(i64 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i64, align 8
# |   %t.addr = alloca i64, align 8
# |   store i64 %t, ptr %t.addr, align 8
# |   %0 = load i64, ptr %t.addr, align 8
# |   store i64 %0, ptr %__t.addr.i, align 8
# |   %1 = load i64, ptr %__t.addr.i, align 8
# |   %2 = call i64 @llvm.ctlz.i64(i64 %1, i1 false)
# |   %3 = trunc i64 %2 to i32
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_cls(i32 noundef %t) #0 {
# | entry:
# |   %__t.addr.i = alloca i32, align 4
# |   %t.addr = alloca i32, align 4
# |   store i32 %t, ptr %t.addr, align 4
# |   %0 = load i32, ptr %t.addr, align 4
# |   store i32 %0, ptr %__t.addr.i, align 4
# |   %1 = load i32, ptr %__t.addr.i, align 4
# |   %cls.i = call i32 @llvm.arm.cls(i32 %1)
# |   ret i32 %cls.i
# | }
# | 
# | ; Function Attrs: noinline
# | ...
# `---data was truncated (10240/86891) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e36bfee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e36bfeb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e36bfee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7389f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7389f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7389f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7389f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e36bf83e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e36bf83c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e36bf68b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e36bc180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e36bc17dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7389f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7389f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7389f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e36bc17cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c (2182 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv
# | ...
# `---data was truncated (10240/53726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605ab3cc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005605ab3c90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005605ab3cc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe9d4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe9d48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe9d4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe9d4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605ab361e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005605ab361c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005605ab346b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005605aaff60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005605aaff5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe9d4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe9d48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe9d48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605aaff5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c (2183 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa3091715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aa309140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aa3091789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8fb4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8fb498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8fb4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8fb491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa308ace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aa308acc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aa30891b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aa305410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aa30540dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8fb491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8fb491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8fb491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa30540cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c (2184 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vgmul_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vgmul.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vgmul_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vgmul.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vgmul_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vgmul.vv.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vgmul_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vgmul.vv.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vgmul_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vgmul.vv.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a3a188e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a3a188b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a3a188e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa913a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa913aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa913a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa913a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3a1823e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a3a1823c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a3a1808b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a3a14b80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a3a14b7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa913a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa913a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa913a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a3a14b7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c (2185 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffb(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.ffb.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffzmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.ffzmism.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.ffmism.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_flmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i32, align 4
# |   %__b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %__a.addr.i, align 4
# |   store i32 %1, ptr %__b.addr.i, align 4
# |   %2 = load i32, ptr %__a.addr.i, align 4
# |   %3 = load i32, ptr %__b.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.nds.flmism.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffb.i32(i32, i32) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffzmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.flmism.i32(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560087cd215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560087ccf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560087cd289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff92b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff92b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff92b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff92b431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560087c67e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560087c67c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560087c4cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005600878fc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005600878fbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff92b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff92b4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff92b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600878fbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c (2186 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_x_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_x_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_x_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_x_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_x_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_x_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_xu_v_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_xu_v_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_xu_v_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_xu_v_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_xu_v_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_xu_v_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16
# | ...
# `---data was truncated (10240/33616) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055670038015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055670037d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055670038089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb8a5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb8a58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb8a5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb8a5831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556700315e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556700315c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005567002fab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005566fffaa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005566fffa9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb8a5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb8a58330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb8a58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566fffa9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c (2187 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e94c2c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e94c2c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e94c2c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3ec905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3ec95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3ec905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3ec8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e94c25ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e94c25ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e94c23fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e94beef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e94beeedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff3ec8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3ec8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3ec8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e94beeecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c (2188 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbf_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbf_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsbf_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsbf_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsbf_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsbf_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbf_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/13031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c903a4815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c903a450f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c903a4889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64eb333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64eb38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64eb333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64eb31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9039dde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c9039ddc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c9039c2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c9036720b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c903671dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f64eb31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64eb31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64eb31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c903671cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c (2189 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlsseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be1ca2415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055be1ca210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055be1ca2489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda83049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda830a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda83049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda83031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be1c9b9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055be1c9b9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055be1c99eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055be1c64e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055be1c64ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fda83032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda830330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda830330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be1c64dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c (2190 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055898e94b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055898e9480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055898e94b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7cca849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7cca8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7cca849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7cca831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055898e8e0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055898e8e0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055898e8c5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055898e5750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055898e574dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7cca832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7cca8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7cca8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055898e574cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/builtins-arm-exclusive.c (2191 of 27911)
******************** TEST 'Clang :: CodeGen/builtins-arm-exclusive.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8-unknown-linux-gnueabi"
# | 
# | %struct.Simple = type { i8, i8 }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ldrex(ptr noundef %addr, ptr noundef %addr64, ptr noundef %addrfloat) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %addr64.addr = alloca ptr, align 4
# |   %addrfloat.addr = alloca ptr, align 4
# |   %sum = alloca i32, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store ptr %addr64, ptr %addr64.addr, align 4
# |   store ptr %addrfloat, ptr %addrfloat.addr, align 4
# |   store i32 0, ptr %sum, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %ldrex = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %0)
# |   %1 = trunc i32 %ldrex to i8
# |   %conv = zext i8 %1 to i32
# |   %2 = load i32, ptr %sum, align 4
# |   %add = add nsw i32 %2, %conv
# |   store i32 %add, ptr %sum, align 4
# |   %3 = load ptr, ptr %addr.addr, align 4
# |   %ldrex1 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %3)
# |   %4 = trunc i32 %ldrex1 to i16
# |   %conv2 = sext i16 %4 to i32
# |   %5 = load i32, ptr %sum, align 4
# |   %add3 = add nsw i32 %5, %conv2
# |   store i32 %add3, ptr %sum, align 4
# |   %6 = load ptr, ptr %addr.addr, align 4
# |   %ldrex4 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %6)
# |   %7 = load i32, ptr %sum, align 4
# |   %add5 = add nsw i32 %7, %ldrex4
# |   store i32 %add5, ptr %sum, align 4
# |   %8 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd = call { i32, i32 } @llvm.arm.ldrexd(ptr %8)
# |   %9 = extractvalue { i32, i32 } %ldrexd, 1
# |   %10 = extractvalue { i32, i32 } %ldrexd, 0
# |   %11 = zext i32 %9 to i64
# |   %12 = zext i32 %10 to i64
# |   %shl = shl nuw i64 %11, 32
# |   %13 = or i64 %shl, %12
# |   %14 = load i32, ptr %sum, align 4
# |   %conv6 = sext i32 %14 to i64
# |   %add7 = add nsw i64 %conv6, %13
# |   %conv8 = trunc i64 %add7 to i32
# |   store i32 %conv8, ptr %sum, align 4
# |   %15 = load ptr, ptr %addr64.addr, align 4
# |   %ldrexd9 = call { i32, i32 } @llvm.arm.ldrexd(ptr %15)
# |   %16 = extractvalue { i32, i32 } %ldrexd9, 1
# |   %17 = extractvalue { i32, i32 } %ldrexd9, 0
# |   %18 = zext i32 %16 to i64
# |   %19 = zext i32 %17 to i64
# |   %shl10 = shl nuw i64 %18, 32
# |   %20 = or i64 %shl10, %19
# |   %21 = load i32, ptr %sum, align 4
# |   %conv11 = sext i32 %21 to i64
# |   %add12 = add nsw i64 %conv11, %20
# |   %conv13 = trunc i64 %add12 to i32
# |   store i32 %conv13, ptr %sum, align 4
# |   %22 = load ptr, ptr %addrfloat.addr, align 4
# |   %ldrex14 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %22)
# |   %23 = bitcast i32 %ldrex14 to float
# |   %24 = load i32, ptr %sum, align 4
# |   %conv15 = sitofp i32 %24 to float
# |   %add16 = fadd float %conv15, %23
# |   %conv17 = fptosi float %add16 to i32
# |   store i32 %conv17, ptr %sum, align 4
# |   %25 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd18 = call { i32, i32 } @llvm.arm.ldrexd(ptr %25)
# |   %26 = extractvalue { i32, i32 } %ldrexd18, 1
# |   %27 = extractvalue { i32, i32 } %ldrexd18, 0
# |   %28 = zext i32 %26 to i64
# |   %29 = zext i32 %27 to i64
# |   %shl19 = shl nuw i64 %28, 32
# |   %30 = or i64 %shl19, %29
# |   %31 = bitcast i64 %30 to double
# |   %32 = load i32, ptr %sum, align 4
# |   %conv20 = sitofp i32 %32 to double
# |   %add21 = fadd double %conv20, %31
# |   %conv22 = fptosi double %add21 to i32
# |   store i32 %conv22, ptr %sum, align 4
# |   %33 = load ptr, ptr %addr.addr, align 4
# |   %ldrex23 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %33)
# |   %34 = inttoptr i32 %ldrex23 to ptr
# |   %35 = load i32, ptr %34, align 4
# |   %36 = load i32, ptr %sum, align 4
# |   %add24 = add nsw i32 %36, %35
# |   store i32 %add24, ptr %sum, align 4
# |   %37 = load ptr, ptr %addr.addr, align 4
# |   %ldrex25 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %37)
# |   %38 = inttoptr i32 %ldrex25 to ptr
# |   %a = getelementptr inbounds nuw %struct.Simple, ptr %38, i32 0, i32 0
# |   %39 = load i8, ptr %a, align 1
# |   %conv26 = zext i8 %39 to i32
# |   %40 = load i32, ptr %sum, align 4
# |   %add27 = add nsw i32 %40, %conv26
# |   store i32 %add27, ptr %sum, align 4
# |   %41 = load i32, ptr %sum, align 4
# |   ret i32 %41
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.ldrex.p0(ptr) #1
# | 
# | ; Function Attrs: nounwind
# | declare { i32, i32 } @llvm.arm.ldrexd(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ldaex(ptr noundef %addr, ptr noundef %addr64, ptr noundef %addrfloat) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %addr64.addr = alloca ptr, align 4
# |   %addrfloat.addr = alloca ptr, align 4
# |   %sum = alloca i32, align 4
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store ptr %addr64, ptr %addr64.addr, align 4
# |   store ptr %addrfloat, ptr %addrfloat.addr, align 4
# |   store i32 0, ptr %sum, align 4
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %ldrex = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i8) %0)
# |   %1 = trunc i32 %ldrex to i8
# |   %conv = zext i8 %1 to i32
# |   %2 = load i32, ptr %sum, align 4
# |   %add = add nsw i32 %2, %conv
# |   store i32 %add, ptr %sum, align 4
# |   %3 = load ptr, ptr %addr.addr, align 4
# |   %ldrex1 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i16) %3)
# |   %4 = trunc i32 %ldrex1 to i16
# |   %conv2 = sext i16 %4 to i32
# |   %5 = load i32, ptr %sum, align 4
# |   %add3 = add nsw i32 %5, %conv2
# |   store i32 %add3, ptr %sum, align 4
# |   %6 = load ptr, ptr %addr.addr, align 4
# |   %ldrex4 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %6)
# |   %7 = load i32, ptr %sum, align 4
# |   %add5 = add nsw i32 %7, %ldrex4
# |   store i32 %add5, ptr %sum, align 4
# |   %8 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd = call { i32, i32 } @llvm.arm.ldaexd(ptr %8)
# |   %9 = extractvalue { i32, i32 } %ldrexd, 1
# |   %10 = extractvalue { i32, i32 } %ldrexd, 0
# |   %11 = zext i32 %9 to i64
# |   %12 = zext i32 %10 to i64
# |   %shl = shl nuw i64 %11, 32
# |   %13 = or i64 %shl, %12
# |   %14 = load i32, ptr %sum, align 4
# |   %conv6 = sext i32 %14 to i64
# |   %add7 = add nsw i64 %conv6, %13
# |   %conv8 = trunc i64 %add7 to i32
# |   store i32 %conv8, ptr %sum, align 4
# |   %15 = load ptr, ptr %addr64.addr, align 4
# |   %ldrexd9 = call { i32, i32 } @llvm.arm.ldaexd(ptr %15)
# |   %16 = extractvalue { i32, i32 } %ldrexd9, 1
# |   %17 = extractvalue { i32, i32 } %ldrexd9, 0
# |   %18 = zext i32 %16 to i64
# |   %19 = zext i32 %17 to i64
# |   %shl10 = shl nuw i64 %18, 32
# |   %20 = or i64 %shl10, %19
# |   %21 = load i32, ptr %sum, align 4
# |   %conv11 = sext i32 %21 to i64
# |   %add12 = add nsw i64 %conv11, %20
# |   %conv13 = trunc i64 %add12 to i32
# |   store i32 %conv13, ptr %sum, align 4
# |   %22 = load ptr, ptr %addrfloat.addr, align 4
# |   %ldrex14 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %22)
# |   %23 = bitcast i32 %ldrex14 to float
# |   %24 = load i32, ptr %sum, align 4
# |   %conv15 = sitofp i32 %24 to float
# |   %add16 = fadd float %conv15, %23
# |   %conv17 = fptosi float %add16 to i32
# |   store i32 %conv17, ptr %sum, align 4
# |   %25 = load ptr, ptr %addr.addr, align 4
# |   %ldrexd18 = call { i32, i32 } @llvm.arm.ldaexd(ptr %25)
# |   %26 = extractvalue { i32, i32 } %ldrexd18, 1
# |   %27 = extractvalue { i32, i32 } %ldrexd18, 0
# |   %28 = zext i32 %26 to i64
# |   %29 = zext i32 %27 to i64
# |   %shl19 = shl nuw i64 %28, 32
# |   %30 = or i64 %shl19, %29
# |   %31 = bitcast i64 %30 to double
# |   %32 = load i32, ptr %sum, align 4
# |   %conv20 = sitofp i32 %32 to double
# |   %add21 = fadd double %conv20, %31
# |   %conv22 = fptosi double %add21 to i32
# |   store i32 %conv22, ptr %sum, align 4
# |   %33 = load ptr, ptr %addr.addr, align 4
# |   %ldrex23 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %33)
# |   %34 = inttoptr i32 %ldrex23 to ptr
# |   %35 = load i32, ptr %34, align 4
# |   %36 = load i32, ptr %sum, align 4
# |   %add24 = add nsw i32 %36, %35
# |   store i32 %add24, ptr %sum, align 4
# |   %37 = load ptr, ptr %addr.addr, align 4
# |   %ldrex25 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %37)
# |   %38 = inttoptr i32 %ldrex25 to ptr
# |   %a = getelementptr inbounds nuw %struct.Simple, ptr %38, i32 0, i32 0
# |   %39 = load i8, ptr %a, align 1
# |   %conv26 = zext i8 %39 to i32
# |   %40 = load i32, ptr %sum, align 4
# |   %add27 = add nsw i32 %40, %conv26
# |   store i32 %add27, ptr %sum, align 4
# |   %41 = load i32, ptr %sum, align 4
# |   ret i32 %41
# | }
# | 
# | ; Function Attrs: nounwind
# | declare i32 @llvm.arm.ldaex.p0(ptr) #1
# | 
# | ; Function Attrs: nounwind
# | declare { i32, i32 } @llvm.arm.ldaexd(ptr) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_strex(ptr noundef %addr) #0 {
# | entry:
# |   %addr.addr = alloca ptr, align 4
# |   %res = alloca i32, align 4
# |   %var = alloca %struct.Simple, align 1
# |   %tmp = alloca i64, align 8
# |   %tmp8 = alloca double, align 8
# |   store ptr %addr, ptr %addr.addr, align 4
# |   store i32 0, ptr %res, align 4
# |   call void @llvm.memset.p0.i32(ptr align 1 %var, i8 0, i32 2, i1 false)
# |   %0 = load ptr, ptr %addr.addr, align 4
# |   %strex = call i32 @llvm.arm.strex.p0(i32 4, ptr elementtype(i8) %0)
# |   %1 = load i32, ptr %res, align 4
# |   %or = or i32 %1, %strex
# |   store i32 %or, ptr %res, align 4
# |   %2 = load ptr, ptr %addr.addr, align 4
# |   %strex1 = call i32 @llvm.arm.strex.p0(i32 42, ptr elementtype(i16) %2)
# |   %3 = load i32, ptr %res, align 4
# |   %or2 = or i32 %3, %strex1
# |   store i32 %or2, ptr %res, align 4
# |   %4 = load ptr, ptr %addr.addr, align 4
# |   %strex3 = call i32 @llvm.arm.strex.p0(i32 42, ptr elementtype(i32) %4)
# |   %5 = load i32, ptr %res, align 4
# |   %or4 = or i32 %5, %strex3
# |   store i32 %or4, ptr %res, align 4
# |   store i64 42, ptr %tmp, align 8
# |   %6 = load { i32, i32 }, ptr %tmp, align 8
# |   %7 = extractvalue { i32, i32 } %6, 0
# |   %8 = extractvalue { i32, i32 } %6, 1
# |   %9 = load ptr, ptr %addr.addr, align 4
# |   %strexd = call i32 @llvm.arm.strexd(i32 %7, i32 %8, ptr %9)
# |   %10 = load i32, ptr %res, align 4
# |   %or5 = or i32 %10, %strexd
# |   store i32 %or5, ptr %res, align 4
# |   %11 = load ptr, ptr %addr.addr, align 4
# |   %strex6 = call i32 @llvm.arm.strex.p0(i32 1076754509, ptr elementtype(i32) %11)
# |   %12 = load i32, ptr %res, align 4
# |   %or7 = or i32 %12, %strex6
# |   store i32 %or7, ptr %res, align 4
# |   store double 3.141590e+00, ptr %tmp8, align 8
# |   %13 = load { i32, i32 }, ptr %tmp8, align 8
# |   %14 = extractvalue { i32, i32 } %13, 0
# |   %15 = extractvalue { i32, i32 } %13, 1
# |   %16 = load ptr, ptr %addr.addr, align 4
# |   %strexd9 = call i32 @llvm.arm.strexd(i32 %14, i32 %15, ptr %16)
# |   %17 = load i32, ptr %res, align 4
# |   %or10 = or i32 %17, %strexd9
# |   store i32 %or10, ptr %res, align 4
# |   %18 = load ptr, ptr %addr.addr, ali
# | ...
# `---data was truncated (10240/16971) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e173f515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560e173f20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560e173f589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47d6049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47d60a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47d6049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47d6031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e1738ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560e1738ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560e1736fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560e1701f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560e1701edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f47d6032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47d60330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47d60330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e1701ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c (2192 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_viota_m_u8mf8(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_viota_m_u8mf4(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_viota_m_u8mf2(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_viota_m_u8m1(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_viota_m_u8m2(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_viota_m_u8m4(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_viota_m_u8m8(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_viota_m_u16mf4(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_viota_m_u16mf2(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_viota_m_u16m1(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_viota_m_u16m2(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_viota_m_u16m4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_viota_m_u16m8(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <
# | ...
# `---data was truncated (10240/40411) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd9dad215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bd9dacf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bd9dad289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa83f01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa83f0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa83f01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa83f003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd9da67e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bd9da67c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bd9da4cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bd9d6fc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bd9d6fbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa83f004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa83f0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa83f0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd9d6fbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c (2193 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055976bef715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055976bef40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055976bef789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ebd105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ebd15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ebd105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ebd0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055976be8ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055976be8cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055976be71b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055976bb210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055976bb20dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4ebd0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ebd0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ebd0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055976bb20cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c (2194 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m1x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f16m2x4(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m1x4(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f32m2x4(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei8_v_f64m1x4(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590f589e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005590f589b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005590f589e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9314133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f931418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9314133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f931411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590f5833e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005590f5833c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005590f5818b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005590f54c80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005590f54c7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f931411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f931411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f931411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590f54c7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c (2195 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.
# | ...
# `---data was truncated (10240/101402) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f650f1415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f650f110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f650f1489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fe1e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fe1e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fe1e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fe1e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f650ea9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f650ea9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f650e8eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f650b3e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f650b3ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6fe1e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fe1e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fe1e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f650b3dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c (2196 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vv_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnmsub_vx_i8mf8_tu(<vscale x 1 x i8> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vv_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnmsub_vx_i8mf4_tu(<vscale x 2 x i8> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vv_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnmsub_vx_i8mf2_tu(<vscale x 4 x i8> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vv_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnmsub_vx_i8m1_tu(<vscale x 8 x i8> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnmsub_vv_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   
# | ...
# `---data was truncated (10240/415319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b77cdd115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b77cdce0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b77cdd189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6daf449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6daf4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6daf449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6daf431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b77cd66e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b77cd66c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b77cd4bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b77c9fb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b77c9fadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6daf432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6daf4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6daf4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b77c9facc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c (2197 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ec14ae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560ec14ab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560ec14ae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff885d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff885d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff885d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff885d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ec1443e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560ec1443c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560ec1428b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560ec10d80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560ec10d7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff885d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff885d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff885d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ec10d7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c (2198 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnot_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnot_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnot_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnot_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnot_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vnot_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vnot_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 -1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vnot_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vnot_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vnot_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 -1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16.i6
# | ...
# `---data was truncated (10240/182165) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622939dd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005622939da0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005622939dd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f559121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55912725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f559121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5591203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562293972e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562293972c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562293957b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005622936070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562293606dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5591204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55912050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55912050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562293606cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c (2199 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561726cd415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561726cd10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561726cd489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9712933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f971298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9712933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f971291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561726c69e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561726c69c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561726c4eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005617268fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005617268fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f971291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f971291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f971291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617268fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c (2200 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 5)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 3)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592335f315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005592335f00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005592335f389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f887e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f887e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f887e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f887e11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559233588e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559233588c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055923356db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055923321d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055923321cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f887e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f887e11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f887e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055923321ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c (2201 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055898ecb715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055898ecb40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055898ecb789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5bee505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5bee55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5bee505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5bee4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055898ec4ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055898ec4cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055898ec31b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055898e8e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055898e8e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5bee4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5bee4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5bee4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055898e8e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c (2202 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8ff_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8ff_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8ff_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8ff_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8ff_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv
# | ...
# `---data was truncated (10240/68225) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5a457c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d5a45790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d5a457c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fe6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fe618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fe6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fe611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d5a4511e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d5a4511c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d5a44f6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d5a41a60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d5a41a5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9fe611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fe611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fe611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5a41a5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c (2203 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrec7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrec7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local
# | ...
# `---data was truncated (10240/51412) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de5305415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055de530510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055de5305489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f978be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f978bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f978be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f978be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de52fe9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055de52fe9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055de52fceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055de52c7e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055de52c7ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f978be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f978be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f978be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de52c7dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c (2204 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i8.i64(<
# | ...
# `---data was truncated (10240/17495) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e55e6f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561e55e6c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561e55e6f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46a5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46a558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46a5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46a551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e55e04e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561e55e04c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561e55de9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561e55a990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561e55a98dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f46a551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46a551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46a551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e55a98cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c (2205 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/296951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005585cf8ed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005585cf8ea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005585cf8ed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa78c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa78c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa78c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa78c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005585cf882e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005585cf882c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005585cf867b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005585cf5170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005585cf516dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa78c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa78c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa78c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005585cf516cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c (2206 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566c50fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005566c50f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005566c50fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8022933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f802298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8022933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f802291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566c5091e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005566c5091c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005566c5076b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005566c4d260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005566c4d25dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f802291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f802291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f802291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566c4d25cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c (2207 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16bf16.i64(<vscale x 16 x i16> poison, <vscale x 16 x bfloat> 
# | ...
# `---data was truncated (10240/12298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfd671b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dfd67180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dfd671b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcebd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcebd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcebd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcebd231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfd66b0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dfd66b0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dfd6695b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dfd63450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dfd6344dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcebd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcebd2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcebd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfd6344cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c (2208 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b86730515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b8673020f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b86730589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa278733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa27878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa278733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa27871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b86729ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b86729ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b86727fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b866f2f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b866f2edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa27871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa27871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa27871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b866f2ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c (2209 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561fa4bbd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561fa4bba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561fa4bbd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3042933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f304298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3042933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f304291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561fa4b52e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561fa4b52c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561fa4b37b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561fa47e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561fa47e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f304291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f304291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f304291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561fa47e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/thinlto_backend_local_name_conflict.ll (2210 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto_backend_local_name_conflict.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 8
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc
# |  #0 0x00005655058ae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005655058ab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005655058ae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f93cc049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f93cc0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f93cc049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f93cc031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565505843e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565505843c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565505828b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005655054d80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005655054d7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f93cc032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f93cc0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f93cc0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005655054d7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c (2211 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055847e3fe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055847e3fb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055847e3fe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46c1f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46c1f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46c1f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46c1eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055847e393e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055847e393c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055847e378b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055847e0280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055847e027dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f46c1eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46c1eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46c1eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055847e027cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c (2212 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m1(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_q_f8e4m3m2(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8_m(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   s
# | ...
# `---data was truncated (10240/69534) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630c109515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005630c10920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005630c109589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f75e5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f75e56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f75e5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f75e5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630c102ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005630c102ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005630c100fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005630c0cbf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005630c0cbedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f75e5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f75e56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f75e56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630c0cbecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c (2213 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_u8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_u8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_u8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %
# | ...
# `---data was truncated (10240/21774) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556a2961115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556a2960e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556a2961189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf29333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf2938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf29333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf2931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556a295a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556a295a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556a2958bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556a2923b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556a2923add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcf2931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf2931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf2931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556a2923acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c (2214 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589d0d2f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005589d0d2c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005589d0d2f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb8c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb8c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb8c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb8c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589d0cc4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005589d0cc4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005589d0ca9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005589d09590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005589d0958dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdb8c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb8c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb8c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589d0958cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c (2215 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkx -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c  -check-prefix=RV32ZBKX
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkx -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @xperm8_32(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.xperm8.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @xperm4_32(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.xperm4.i32(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.xperm8.i32(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.xperm4.i32(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkx" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zbkx1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b5f75515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564b5f7520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564b5f75589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4dd4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4dd4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4dd4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4dd4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b5f6eae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564b5f6eac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564b5f6cfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564b5f37f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564b5f37edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4dd4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4dd4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4dd4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b5f37ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c (2216 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsbc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsbc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsbc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsbc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsbc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |  
# | ...
# `---data was truncated (10240/98589) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a611de715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a611de40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a611de789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd425249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4252a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd425249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd425231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a611d7ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a611d7cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a611d61b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a611a110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a611a10dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd425232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4252330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4252330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a611a10cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c (2217 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_v_f_bf16mf4(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_v_f_bf16mf2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_v_f_bf16m1(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_v_f_bf16m2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_v_f_bf16m4(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmv_v_f_bf16m8(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf4_bf16(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv1bf16(<vscale x 1 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_s_f_bf16mf4(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16mf2_bf16(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv2bf16(<vscale x 2 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_s_f_bf16mf2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m1_bf16(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv4bf16(<vscale x 4 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_s_f_bf16m1(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m2_bf16(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat> %0)
# |   ret bfloat %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare bfloat @llvm.riscv.vfmv.f.s.nxv8bf16(<vscale x 8 x bfloat>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_s_f_bf16m2(bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load bfloat, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat> poison, bfloat %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local bfloat @test_vfmv_f_s_bf16m4_bf16(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %
# | ...
# `---data was truncated (10240/13308) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c49262c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c4926290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c49262c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc234333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc23438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc234333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc23431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c4925c1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c4925c1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c4925a6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c4922560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c492255dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc23431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc23431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc23431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c492255cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c (2218 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056232662715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005623266240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056232662789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5c3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5c38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5c3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5c3831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005623265bce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005623265bcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005623265a1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005623262510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562326250dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd5c3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5c38330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5c38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562326250cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c (2219 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560112ecc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560112ec90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560112ecc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb985c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb985ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb985c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb985c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560112e61e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560112e61c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560112e46b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560112af60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560112af5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb985c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb985c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb985c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560112af5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c (2220 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>,
# | ...
# `---data was truncated (10240/296943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b2da2415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556b2da210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556b2da2489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2e2f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2e2f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2e2f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2e2eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b2d9b9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556b2d9b9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556b2d99eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556b2d64e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556b2d64ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc2e2eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2e2eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2e2eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b2d64dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c (2221 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei32_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei32_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei32_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei32_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei32_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i
# | ...
# `---data was truncated (10240/25624) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb7d20115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fb7d1fe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fb7d20189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f354e105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f354e15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f354e105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f354e0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb7d196e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fb7d196c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fb7d17bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fb7ce2b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fb7ce2add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f354e0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f354e0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f354e0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb7ce2acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c (2222 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | defin
# | ...
# `---data was truncated (10240/13035) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f661ab215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f661aaf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f661ab289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fdab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fdab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fdab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fdab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f661a47e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f661a47c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f661a2cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f6616dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f6616dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2fdab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fdab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fdab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6616dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c (2223 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   
# | ...
# `---data was truncated (10240/81304) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eaf902015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eaf901d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eaf902089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1f0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1f0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1f0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1f0e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eaf8fb5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eaf8fb5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eaf8f9ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eaf8c4a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eaf8c49dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff1f0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1f0e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1f0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eaf8c49cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c (2224 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_f64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_i64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_i64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e64_v_i64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e64_v_u64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e64_v_u64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_
# | ...
# `---data was truncated (10240/11895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b6b2b515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560b6b2b20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560b6b2b589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e86b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e86b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e86b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e86b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b6b24ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560b6b24ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560b6b22fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560b6aedf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560b6aededd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1e86b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e86b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e86b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b6aedecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c (2225 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d62e2515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562d62e220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562d62e2589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25a2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25a22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25a2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25a2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d62dbae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562d62dbac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562d62d9fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562d62a4f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562d62a4edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f25a2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25a22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25a22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d62a4ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c (2226 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb7941015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bb7940d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bb7941089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc97b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc97b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc97b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc97b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb793a5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bb793a5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bb7938ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bb7903a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bb79039dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc97b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc97b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc97b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb79039cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c (2227 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v_i8mf8x7
# | ...
# `---data was truncated (10240/160903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563ae34715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005563ae3440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005563ae34789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46bfc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46bfc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46bfc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46bfc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563ae2dce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005563ae2dcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005563ae2c1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005563adf710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005563adf70dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f46bfc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46bfc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46bfc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563adf70cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c (2228 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd9f87e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cd9f87b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cd9f87e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab22c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab22ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab22c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab22c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd9f813e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cd9f813c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cd9f7f8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cd9f4a80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cd9f4a7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fab22c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab22c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab22c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd9f4a7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c (2229 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/100952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d28140415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d2814010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d28140489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05c7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05c74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05c7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05c7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d281399e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d281399c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d28137eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d28102e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d28102ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f05c7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05c74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05c74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d28102dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c (2230 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpaire_vv_f16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpaire.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpaire_vv_f16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpaire.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpaire_vv_f16m1(<vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpaire.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpaire_vv_f16m2(<vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpaire.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpaire_vv_f16m4(<vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpaire.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpaire_vv_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpaire.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpaire_vv_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpaire.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpaire_vv_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpaire.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpaire_vv_f32m2(<vscale x 4 x float> %vs2, <vscale x 4 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vpaire.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vpaire_vv_f32m4(<vscale x 8 x float> %vs2, <vscale x 8 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load <v
# | ...
# `---data was truncated (10240/125480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561091ff615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561091ff30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561091ff689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc36305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc3635c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc36305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc362ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561091f8be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561091f8bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561091f70b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561091c200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561091c1fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdc362eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc362ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc362ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561091c1fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c (2231 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9e518215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a9e517f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a9e518289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b50849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b508a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b50849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b50831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9e5117e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a9e5117c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a9e50fcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a9e4dac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a9e4dabdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0b50832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b508330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b508330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9e4dabcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/thinlto-opaque-typed-mix.ll (2232 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto-opaque-typed-mix.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 4
mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp
# executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll
# |  #0 0x00005588728b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005588728b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005588728b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13fc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13fc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13fc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13fc431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055887284ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055887284cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558872831b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005588724e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005588724e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f13fc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13fc4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13fc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588724e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c (2233 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ms_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ms_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ms_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ms_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ms_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ms_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ms_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ms_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/12227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563dc6f3c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563dc6f390f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563dc6f3c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ba1d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ba1d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ba1d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ba1ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563dc6ed1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563dc6ed1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563dc6eb6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563dc6b660b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563dc6b65dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0ba1ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ba1cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ba1cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563dc6b65cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c (2234 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_i16m2x4_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8
# | ...
# `---data was truncated (10240/15457) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056174060815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005617406050f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056174060889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff9d0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9d0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff9d0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff9d0f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056174059de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056174059dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561740582b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005617402320b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561740231dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff9d0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9d0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9d0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561740231cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c (2235 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 5)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e8m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 6)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e16m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32mf2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 7)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e32m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m1(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m2(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m4(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvl_e64m8(i64 noundef %avl) #0 {
# | entry:
# |   %avl.addr = alloca i64, align 8
# |   store i64 %avl, ptr %avl.addr, align 8
# |   %0 = load i64, ptr %avl.addr, align 8
# |   %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 3)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f18c48515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f18c4820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f18c48589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ac1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ac1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ac1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ac1c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f18c41ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f18c41ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f18c3ffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f18c0af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f18c0aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2ac1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ac1c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ac1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f18c0aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c (2236 of 27911)
******************** TEST 'Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.2a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_f32(<2 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u32(<2 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_p8(<8 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_p16(<4 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s64(<1 x i64> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <4 x bfloat>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <4 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <4 x bfloat>, ptr %__ret.i, align 8
# |   ret <4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 8
# |   %__ret.i = alloca <8 x bfloat>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 8
# |   %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8
# |   store <8 x bfloat> %1, ptr %__ret.i, align 8
# |   %2 = load <8 x bfloat>, ptr %__ret.i, align 8
# |   ret <8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u32(<4 x i32> nou
# | ...
# `---data was truncated (10240/28396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# |  #0 0x000055870b17815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055870b1750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055870b17889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b0661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b066725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b0661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b06603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055870b10de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055870b10dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055870b0f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055870ada20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055870ada1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4b06604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b066050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b066050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055870ada1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c (2237 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   
# | ...
# `---data was truncated (10240/132462) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ec595115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564ec594e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564ec595189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa300a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa300aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa300a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa300a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ec58e6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564ec58e6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564ec58cbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564ec557b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564ec557add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa300a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa300a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa300a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ec557acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c (2238 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = all
# | ...
# `---data was truncated (10240/147390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557079c3115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557079c2e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557079c3189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f925b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f925b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f925b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f925b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557079bc6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557079bc6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557079babb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055707985b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055707985add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f925b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f925b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f925b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055707985acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c (2239 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570518ae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005570518ab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005570518ae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a13133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a1318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a13133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a1311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557051843e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557051843c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557051828b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005570514d80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005570514d7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2a1311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a1311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a1311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570514d7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-neon-dot-product.c (2240 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-dot-product.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-unknown-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.arm.neon.udot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.arm.neon.sdot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <16 x i8>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <16 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load <16 x i8>, ptr %c.addr, align 8
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   store <16 x i8> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vdot1.i = call <4 x i32> @llvm.arm.neon.sdot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5)
# |   store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 8
# |   store <4 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i32>, ptr %__ret.i, align 8
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__p2.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_831 = alloca <2 x i32>, align 8
# |   %__s0_831 = alloca <2 x i32>, align 8
# |   %__s1_831 = alloca <8 x i8>, align 8
# |   %__s2_831 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <2 x i32>, align 8
# |   %__ret = alloca <2 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <8 x i8>, align 8
# |   %tmp = alloca <2 x i32>, align 8
# |   %tmp2 = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0_831, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1_831, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_831, align 8
# |   %3 = load <2 x i32>, ptr %__s0_831, align 8
# |   %4 = load <8 x i8>, ptr %__s1_831, align 8
# |   %5 = load <2 x i32>, ptr %__s2_831, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> <i32 1, i32 1>
# |   store <2 x i32> %lane, ptr %ref.tmp1, align 8
# |   %8 = load <2 x i32>, ptr %ref.tmp1, align 8
# |   store <2 x i32> %8, ptr %__ret, align 8
# |   %9 = load <2 x i32>, ptr %__ret, align 8
# |   store <2 x i32> %9, ptr %tmp, align 8
# |   %10 = load <2 x i32>, ptr %tmp, align 8
# |   store <2 x i32> %10, ptr %ref.tmp, align 8
# |   %11 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <2 x i32> %3, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %4, ptr %__p1.addr.i, align 8
# |   store <8 x i8> %11, ptr %__p2.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %14 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vdot.i = bitcast <8 x i8> %12 to <2 x i32>
# |   %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %13, <8 x i8> %14)
# |   store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8
# |   %15 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %15, ptr %__ret.i, align 8
# |   %16 = load <2 x i32>, ptr %__ret.i, align 8
# |   store <2 x i32> %16, ptr %__ret_831, align 8
# |   %17 = load <2 x i32>, ptr %__ret_831, align 8
# |   store <2 x i32> %17, ptr %tmp2, align 8
# |   %18 = load <2 x i32>, ptr %tmp2, align 8
# |   ret <2 x i32> %18
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__p2.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <4 x i32>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %c.addr = alloca <8 x i8>, align 8
# |   %__ret_827 = alloca <4 x i32>, align 8
# |   %__s0_827 = alloca <4 x i32>, align 8
# |   %__s1_827 = alloca <16 x i8>, align 8
# |   %__s2_827 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <4 x i32>, align 8
# |   %__ret = alloca <4 x i32>, align 8
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp1 = alloca <16 x i8>, align 8
# |   %tmp = alloca <4 x i32>, align 8
# |   %tmp2 = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store <8 x i8> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0_827, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   store <16 x i8> %1, ptr %__s1_827, align 8
# |   %2 = load <8 x i8>, ptr %c.addr, align 8
# |   store <8 x i8> %2, ptr %__s2_827, align 8
# |   %3 = load <4 x i32>, ptr %__s0_827, align 8
# |   %4 = load <16 x i8>, ptr %__s1_827, align 8
# |   %5 = load <2 x i32>, ptr %__s2_827, align 8
# |   store <2 x i32> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <2 x i32>
# |   %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <4 x i32> <i32 1, i32 1,
# | ...
# `---data was truncated (10240/18322) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine
# |  #0 0x000055a30cb7e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a30cb7b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a30cb7e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff20f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff20f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff20f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff20f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a30cb13e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a30cb13c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a30caf8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a30c7a80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a30c7a7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007eff20f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff20f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff20f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a30c7a7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c (2241 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8975fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d8975f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d8975fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0246d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0246d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0246d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0246d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d897591e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d897591c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d897576b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d8972260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d897225dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0246d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0246d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0246d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d897225cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c (2242 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %6
# | 
# | ...
# `---data was truncated (10240/34641) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556992a0715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556992a040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556992a0789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc29933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc2998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc29933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc2991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055699299ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055699299cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556992981b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005569926310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556992630dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbc2991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc2991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc2991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556992630cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c (2243 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale
# | ...
# `---data was truncated (10240/32108) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055663f6e915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055663f6e60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055663f6e989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efeb0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efeb02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efeb0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efeb0231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055663f67ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055663f67ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055663f663b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055663f3130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055663f312dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efeb0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efeb02330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efeb02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055663f312cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c (2244 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_bf16m1_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_bf16m2_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.
# | ...
# `---data was truncated (10240/101394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005628fd78815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005628fd7850f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005628fd78889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff12f21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff12f2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff12f21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff12f203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005628fd71de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005628fd71dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005628fd702b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005628fd3b20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005628fd3b1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff12f204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff12f2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff12f2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005628fd3b1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c (2245 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/14338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec2bf7b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ec2bf780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ec2bf7b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f81733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f8178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f81733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f8171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec2bf10e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ec2bf10c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ec2bef5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ec2bba50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ec2bba4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5f8171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f8171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f8171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec2bba4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c (2246 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652bfb3315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005652bfb300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005652bfb3389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca5a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca5a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca5a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca5a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652bfac8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005652bfac8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005652bfaadb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005652bf75d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005652bf75cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fca5a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca5a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca5a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652bf75ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c (2247 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6cd50c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d6cd5090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d6cd50c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27d9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27d96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27d9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27d9631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6cd4a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d6cd4a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d6cd486b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d6cd1360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d6cd135dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f27d9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27d96330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27d96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6cd135cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c (2248 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vset_v_bf16m1_bf16m2(<vscale x 8 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m1_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vset_v_bf16m2_bf16m4(<vscale x 16 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m1_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m2_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vset_v_bf16m4_bf16m8(<vscale x 32 x bfloat> %dest, i64 noundef %index, <vscale x 16 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 16 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %dest.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %value.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 0)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vset_v_bf16mf4_bf16mf4x2(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vset_v_bf16mf4_bf16mf4x3(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, <vscale x 1 x bfloat> %1, i32 0)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), <vscale x 1 x bfloat>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vset_v_bf16mf4_bf16mf4x4(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, i64 noundef %index, <vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %dest.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %index.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %dest, ptr %dest.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %dest.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %2 = call target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/41659) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1a0ed515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d1a0ed20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d1a0ed589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1875b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1875b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1875b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1875b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1a0e6ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d1a0e6ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d1a0e4fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d1a0aff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d1a0afedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1875b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1875b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1875b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1a0afecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c (2249 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055781fea115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055781fe9e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055781fea189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf39b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf39b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf39b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf39b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055781fe36e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055781fe36c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055781fe1bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055781facb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055781facadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcf39b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf39b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf39b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055781facacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c (2250 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align
# | ...
# `---data was truncated (10240/47596) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555dbc55015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555dbc54d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555dbc55089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1646f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1646f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1646f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1646eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555dbc4e5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555dbc4e5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555dbc4cab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555dbc17a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555dbc179dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1646eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1646eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1646eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555dbc179cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c (2251 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055799a35f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055799a35c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055799a35f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f585cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f585cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f585cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f585cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055799a2f4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055799a2f4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055799a2d9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557999f890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557999f88dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f585cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f585cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f585cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557999f88cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c (2252 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/24381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6edf5315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b6edf500f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b6edf5389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff984449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9844a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff984449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff984431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6edee8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b6edee8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b6edecdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b6edb7d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b6edb7cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff984432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9844330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9844330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6edb7ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c (2253 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_u32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("ris
# | ...
# `---data was truncated (10240/26965) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c57029315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c5702900f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c57029389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f8e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f8e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f8e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f8e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c570228e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c570228c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c57020db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c56febd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c56febcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3f8e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f8e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f8e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c56febccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c (2254 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x
# | ...
# `---data was truncated (10240/15614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560a45e9015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560a45e8d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560a45e9089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8692649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f86926a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8692649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8692631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560a45e25e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560a45e25c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560a45e0ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560a45aba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560a45ab9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8692632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f86926330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f86926330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560a45ab9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c (2255 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad408f915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ad408f60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ad408f989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f280b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f280b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f280b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f280b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad4088ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ad4088ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ad40873b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ad405230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ad40522dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f280b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f280b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f280b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad40522cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c (2256 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563a6eee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005563a6eeb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005563a6eee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0553933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f055398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0553933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f055391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563a6e83e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005563a6e83c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005563a6e68b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005563a6b180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005563a6b17dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f055391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f055391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f055391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563a6b17cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c (2257 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056321a49715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056321a4940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056321a49789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f9121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f912725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f9121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f91203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056321a42ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056321a42cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056321a411b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056321a0c10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056321a0c0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6f91204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f912050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f912050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056321a0c0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c (2258 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557d423c615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557d423c30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557d423c689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff221b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff221b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff221b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff221b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557d4235be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557d4235bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557d42340b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557d41ff00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557d41fefdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff221b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff221b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff221b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557d41fefcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c (2259 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_f32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_i32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32ff_v_i32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32ff_v_i32m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32ff_v_u32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base
# | ...
# `---data was truncated (10240/60683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005611a7aa015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005611a7a9d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005611a7aa089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff238133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff23818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff238133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff23811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005611a7a35e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005611a7a35c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005611a7a1ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005611a76ca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005611a76c9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff23811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff23811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff23811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005611a76c9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c (2260 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvt_x_x_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvt_x_x_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvt_x_x_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvt_x_x_v_i16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvt_x_x_v_i16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvt_x_x_v_i16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvt_x_x_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvt_x_x_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvt_x_x_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvt_x_x_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 
# | ...
# `---data was truncated (10240/67006) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055559f02015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055559f01d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055559f02089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac91a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac91aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac91a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac91a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055559efb5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055559efb5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055559ef9ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055559ec4a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055559ec49dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fac91a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac91a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac91a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055559ec49cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c (2261 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad6e1ca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ad6e1c70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ad6e1ca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff7d1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7d12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff7d1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff7d1231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad6e15fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ad6e15fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ad6e144b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ad6ddf40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ad6ddf3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff7d1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7d12330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7d12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad6ddf3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c (2262 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c311a115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561c3119e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561c311a189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f352d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f352d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f352d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f352d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c31136e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561c31136c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561c3111bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561c30dcb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561c30dcadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f352d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f352d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f352d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c30dcacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mfp8.c (2263 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mfp8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -disable-O0-optnone -o -        /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_ret_mfloat8x16_t(<16 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <16 x i8>, align 16
# |   store <16 x i8> %v, ptr %v.addr, align 16
# |   %0 = load <16 x i8>, ptr %v.addr, align 16
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_ret_mfloat8x8_t(<8 x i8> %v) #0 {
# | entry:
# |   %v.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %v, ptr %v.addr, align 8
# |   %0 = load <8 x i8>, ptr %v.addr, align 8
# |   ret <8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i8> @func1n(<1 x i8> %mfp8) #0 {
# | entry:
# |   %mfp8.addr = alloca <1 x i8>, align 1
# |   %f1n = alloca [10 x <1 x i8>], align 1
# |   store <1 x i8> %mfp8, ptr %mfp8.addr, align 1
# |   %0 = load <1 x i8>, ptr %mfp8.addr, align 1
# |   %arrayidx = getelementptr inbounds [10 x <1 x i8>], ptr %f1n, i64 0, i64 2
# |   store <1 x i8> %0, ptr %arrayidx, align 1
# |   %arrayidx1 = getelementptr inbounds [10 x <1 x i8>], ptr %f1n, i64 0, i64 2
# |   %1 = load <1 x i8>, ptr %arrayidx1, align 1
# |   ret <1 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <1 x i8> @test_extract_element(<16 x i8> %x, i32 noundef %i) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   %i.addr = alloca i32, align 4
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   store i32 %i, ptr %i.addr, align 4
# |   %0 = load <16 x i8>, ptr %x.addr, align 16
# |   %1 = load i32, ptr %i.addr, align 4
# |   %vecext = extractelement <16 x i8> %0, i32 %1
# |   %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0
# |   ret <1 x i8> %mfp8ext
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <16 x i8> @test_insert_element(<16 x i8> %x, i32 noundef %i, <1 x i8> %v) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 16
# |   %i.addr = alloca i32, align 4
# |   %v.addr = alloca <1 x i8>, align 1
# |   store <16 x i8> %x, ptr %x.addr, align 16
# |   store i32 %i, ptr %i.addr, align 4
# |   store <1 x i8> %v, ptr %v.addr, align 1
# |   %0 = load <1 x i8>, ptr %v.addr, align 1
# |   %1 = load i32, ptr %i.addr, align 4
# |   %2 = load <16 x i8>, ptr %x.addr, align 16
# |   %3 = bitcast <1 x i8> %0 to i8
# |   %vecins = insertelement <16 x i8> %2, i8 %3, i32 %1
# |   store <16 x i8> %vecins, ptr %x.addr, align 16
# |   %4 = load <16 x i8>, ptr %x.addr, align 16
# |   ret <16 x i8> %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,-fp8" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg
# |  #0 0x00005583bed5315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005583bed500f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005583bed5389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3154a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3154aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3154a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3154a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583bece8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005583bece8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005583beccdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005583be97d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005583be97cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3154a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3154a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3154a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583be97ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c (2264 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16mf2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m1(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m4(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m8(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m1(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m2(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m8(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m8(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m8(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale
# | ...
# `---data was truncated (10240/12129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f12631615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f1263130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f12631689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf9d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf9d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf9d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf9d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1262abe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f1262abc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f126290b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f125f400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f125f3fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcf9d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf9d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf9d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f125f3fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c (2265 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vvm_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vadc_vxm_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vvm_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vadc_vxm_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vadc.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vvm_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vadc_vxm_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vadc.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vvm_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vadc_vxm_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, <vscale x 8 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %carryin.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %carryin, ptr %carryin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %carryin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vadc.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vadc_vvm_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i1> %carryin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, a
# | ...
# `---data was truncated (10240/98149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561a1438715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561a143840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561a1438789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1aed133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1aed18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1aed133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1aed11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561a1431ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561a1431cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561a14301b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561a13fb10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561a13fb0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1aed11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1aed11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1aed11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561a13fb0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c (2266 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e889e815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564e889e50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564e889e889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee26333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee2638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee26333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee2631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e8897de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564e8897dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564e88962b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564e886120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564e88611dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fee2631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee2631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee2631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e88611cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c (2267 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb2907b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cb290780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cb2907b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f9a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f9a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f9a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f9a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb29010e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cb29010c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cb28ff5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cb28ca50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cb28ca4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0f9a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f9a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f9a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb28ca4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c (2268 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d53508715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d5350840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d53508789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc579a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc579aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc579a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc579a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d53501ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d53501cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d535001b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d534cb10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d534cb0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc579a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc579a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc579a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d534cb0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c (2269 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %o
# | ...
# `---data was truncated (10240/29054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056301cf2815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056301cf250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056301cf2889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f97a4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f97a498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f97a4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f97a491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056301cebde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056301cebdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056301cea2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056301cb520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056301cb51dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f97a491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f97a491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f97a491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056301cb51cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c (2270 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f94eaf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555f94eac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555f94eaf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e58e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e58ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e58e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e58e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f94e44e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555f94e44c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555f94e29b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555f94ad90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555f94ad8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2e58e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e58e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e58e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f94ad8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c (2271 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8
# | ...
# `---data was truncated (10240/160141) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650ae16915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005650ae1660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005650ae16989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe978b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe978b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe978b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe978b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650ae0fee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005650ae0fec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005650ae0e3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005650add930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005650add92dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe978b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe978b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe978b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650add92cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c (2272 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab41af115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ab41aee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ab41af189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0883849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08838a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0883849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0883831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab41a86e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ab41a86c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ab41a6bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ab4171b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ab4171add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0883832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08838330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08838330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab4171acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c (2273 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa7411515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aa741120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aa7411589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f877321bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87732725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f877321ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8773203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa740aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aa740aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aa7408fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aa73d3f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aa73d3edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8773204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87732050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87732050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa73d3ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c (2274 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e1124e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563e1124b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563e1124e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd09821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0982725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd09821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd098203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e111e3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563e111e3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563e111c8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563e10e780b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563e10e77dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd098204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0982050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0982050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e10e77cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c (2275 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vv_u8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vabdu_vx_u8mf8(<vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vabdu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vv_u8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vabdu_vx_u8mf4(<vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vabdu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vv_u8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vabdu_vx_u8mf2(<vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vabdu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vv_u8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vabdu_vx_u8m1(<vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vabdu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vv_u8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vabdu_vx_u8m2(<vscale x 16 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vabdu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vabdu_vv_u8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 
# | ...
# `---data was truncated (10240/97506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df74c1315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055df74c100f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055df74c1389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3abc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3abc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3abc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3abc831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df74ba8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055df74ba8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055df74b8db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055df7483d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055df7483cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3abc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3abc8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3abc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df7483ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c (2276 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfne_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfne_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/66565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca2016715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ca201640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ca2016789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9936649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f99366a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9936649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9936631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca200fce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ca200fcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ca200e1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ca1fd910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ca1fd90dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9936632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f99366330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f99366330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca1fd90cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c (2277 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a891f5615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a891f530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a891f5689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c31b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c31b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c31b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c31aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a891eebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a891eebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a891ed0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a891b800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a891b7fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8c31aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c31aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c31aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a891b7fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c (2278 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055755648615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005575564830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055755648689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4438a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4438aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4438a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4438a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055755641be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055755641bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557556400b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005575560b00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005575560afdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4438a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4438a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4438a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005575560afcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c (2279 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619965bf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005619965bc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005619965bf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec06a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec06aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec06a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec06a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561996554e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561996554c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561996539b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005619961e90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005619961e8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fec06a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec06a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec06a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619961e8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c (2280 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/24381) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e83d75d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e83d75a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e83d75d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf8f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf8f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf8f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf8f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e83d6f2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e83d6f2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e83d6d7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e83d3870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e83d386dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faf8f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf8f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf8f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e83d386cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c (2281 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ec14f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563ec14f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563ec14f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6635b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6635b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6635b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6635b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ec148de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563ec148dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563ec1472b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563ec11220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563ec1121dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6635b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6635b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6635b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ec1121cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c (2282 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f6db7f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562f6db7c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562f6db7f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f687b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f687b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f687b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f687b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f6db14e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562f6db14c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562f6daf9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562f6d7a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562f6d7a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f687b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f687b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f687b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f6d7a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c (2283 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc38f7b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dc38f780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dc38f7b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec04449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec044a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec04449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec04431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc38f10e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dc38f10c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dc38ef5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dc38ba50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dc38ba4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fec04432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec044330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec044330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc38ba4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c (2284 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, 
# | ...
# `---data was truncated (10240/32646) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055efa0f0315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055efa0f000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055efa0f0389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2cc7c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2cc7c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2cc7c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2cc7c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055efa0e98e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055efa0e98c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055efa0e7db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055efa0b2d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055efa0b2cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2cc7c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2cc7c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2cc7c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055efa0b2ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c (2285 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffb(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.ffb.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffb.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffzmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.ffzmism.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffzmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.ffmism.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_flmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i64 @llvm.riscv.nds.flmism.i64(i64 %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.flmism.i64(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561420e415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005561420e10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005561420e489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6875849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68758a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6875849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6875831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556142079e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556142079c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055614205eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556141d0e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556141d0ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6875832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68758330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68758330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556141d0dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c (2286 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b7fdfc815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b7fdfc50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b7fdfc889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f339ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f339eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f339ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f339ee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7fdf5de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b7fdf5dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b7fdf42b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b7fdbf20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b7fdbf1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f339ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f339ee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f339ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7fdbf1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c (2287 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = allo
# | ...
# `---data was truncated (10240/154609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056419eb6415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056419eb610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056419eb6489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fadc4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fadc4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fadc4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fadc4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056419eaf9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056419eaf9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056419eadeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056419e78e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056419e78ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fadc4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fadc4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fadc4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056419e78dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c (2288 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b5751d115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b5751ce0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b5751d189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7a2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7a298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7a2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7a291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b575166e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b575166c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b57514bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b574dfb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b574dfadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc7a291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7a291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7a291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b574dfacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c (2289 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesvsintload,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvsintload5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de3426115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055de3425e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055de3426189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f259f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f259f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f259f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f259f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de341f6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055de341f6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055de341dbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055de33e8b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055de33e8add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f259f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f259f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f259f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de33e8acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c (2290 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559440dc115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559440dbe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559440dc189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3be733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3be78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3be733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3be71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559440d56e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559440d56c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559440d3bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005594409eb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005594409eadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa3be71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3be71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3be71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594409eacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c (2291 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsubu_wx_u16mf4(<vscale x 1 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsubu_wx_u16mf2(<vscale x 2 x i16> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsubu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscal
# | ...
# `---data was truncated (10240/134927) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005635a30a215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005635a309f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005635a30a289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d25d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d25d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d25d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d25d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005635a3037e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005635a3037c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005635a301cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005635a2ccc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005635a2ccbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0d25d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d25d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d25d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635a2ccbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c (2292 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff
# | ...
# `---data was truncated (10240/44185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d48e9ce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d48e9cb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d48e9ce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6bcd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6bcd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6bcd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6bcd631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d48e963e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d48e963c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d48e948b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d48e5f80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d48e5f7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6bcd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6bcd6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6bcd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d48e5f7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c (2293 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsle_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsle_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsle_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsle_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005635152f115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005635152ee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005635152f189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c4281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c428725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c4281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c42803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563515286e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563515286c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056351526bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563514f1b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563514f1add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0c42804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c428050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c428050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563514f1acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c (2294 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vneg_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vneg_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vneg_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vneg_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vneg_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vneg_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vneg_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vneg_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vneg_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vneg_v_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4
# | ...
# `---data was truncated (10240/96257) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0fb44315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c0fb4400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c0fb44389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9b7c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9b7c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9b7c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9b7c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0fb3d8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c0fb3d8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c0fb3bdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c0fb06d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c0fb06cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa9b7c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9b7c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9b7c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0fb06ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c (2295 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0914d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a0914d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a0914d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f03cc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f03cc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f03cc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f03cc631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a091469e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a091469c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a09144eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a0910fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a0910fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f03cc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f03cc6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f03cc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0910fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c (2296 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vmulhu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vsca
# | ...
# `---data was truncated (10240/98171) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a2f910315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a2f91000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a2f910389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc26649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc266a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc26649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc26631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a2f9098e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a2f9098c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a2f907db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a2f8d2d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a2f8d2cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdc26632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc266330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc266330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2f8d2ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c (2297 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f16m1x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f16m2x3(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f32m1x3(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_f32m2x3(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_f64m1x3(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e84964615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e8496430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e84964689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007febb6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007febb6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007febb6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007febb6a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8495dbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e8495dbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e8495c0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e8492700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e84926fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007febb6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007febb6a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007febb6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e84926fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/AArch64/neon-shifts.c (2298 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon-shifts.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon   -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vshr(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = lshr <8 x i8> %1, splat (i8 5)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vshr_smax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   %vshr_n = ashr <8 x i8> %1, splat (i8 7)
# |   store <8 x i8> %vshr_n, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vshr_umax(<8 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %__s0, align 8
# |   store <8 x i8> zeroinitializer, ptr %ref.tmp, align 8
# |   %2 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %2, ptr %__ret, align 8
# |   %3 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %3, ptr %tmp, align 8
# |   %4 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vsra(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = lshr <8 x i8> %3, splat (i8 5)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vsra_smax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %vsra_n = ashr <8 x i8> %3, splat (i8 7)
# |   %4 = add <8 x i8> %2, %vsra_n
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i8> @test_shift_vsra_umax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   %__ret = alloca <8 x i8>, align 8
# |   %__s0 = alloca <8 x i8>, align 8
# |   %__s1 = alloca <8 x i8>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   store <8 x i8> %0, ptr %__s0, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %1, ptr %__s1, align 8
# |   %2 = load <8 x i8>, ptr %__s0, align 8
# |   %3 = load <8 x i8>, ptr %__s1, align 8
# |   %4 = add <8 x i8> %2, zeroinitializer
# |   store <8 x i8> %4, ptr %ref.tmp, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp, align 8
# |   store <8 x i8> %5, ptr %__ret, align 8
# |   %6 = load <8 x i8>, ptr %__ret, align 8
# |   store <8 x i8> %6, ptr %tmp, align 8
# |   %7 = load <8 x i8>, ptr %tmp, align 8
# |   ret <8 x i8> %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b5cc4515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559b5cc420f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559b5cc4589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96b5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96b558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96b5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96b551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b5cbdae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559b5cbdac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559b5cbbfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559b5c86f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559b5c86edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f96b551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96b551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96b551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b5c86ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c (2299 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = loa
# | ...
# `---data was truncated (10240/135111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eab7e8715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eab7e840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eab7e8789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb10d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb10d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb10d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb10d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eab7e1ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eab7e1cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eab7e01b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eab7ab10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eab7ab0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdb10d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb10d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb10d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eab7ab0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c (2300 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: noca
# | ...
# `---data was truncated (10240/40803) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055727f81715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055727f8140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055727f81789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5f7a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5f7a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5f7a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5f7a231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055727f7ace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055727f7acc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055727f791b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055727f4410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055727f440dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5f7a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5f7a2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5f7a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055727f440cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c (2301 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056534832915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005653483260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056534832989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe13681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe1368725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe13681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe136803507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653482bee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005653482bec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005653482a3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000565347f530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000565347f52dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe136804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe1368050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe1368050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565347f52cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c (2302 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0673d615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f0673d30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f0673d689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f70b321bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70b32725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f70b321ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f70b3203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f06736be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f06736bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f067350b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f0670000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f066fffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f70b3204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70b32050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70b32050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f066fffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c (2303 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64
# | ...
# `---data was truncated (10240/99178) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602e193315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005602e19300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005602e193389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31c4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31c4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31c4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31c4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602e18c8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005602e18c8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005602e18adb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005602e155d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005602e155cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f31c4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31c4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31c4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602e155ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c (2304 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055892b4b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055892b4b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055892b4b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54cb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54cb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54cb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54cb031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055892b44ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055892b44cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055892b431b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055892b0e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055892b0e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f54cb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54cb0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54cb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055892b0e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c (2305 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_lo
# | ...
# `---data was truncated (10240/70863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f4ccc515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556f4ccc20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556f4ccc589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e84849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e848a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e84849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e84831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f4cc5ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556f4cc5ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556f4cc3fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556f4c8ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556f4c8eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1e84832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e848330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e848330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f4c8eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c (2306 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055711966d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055711966a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055711966d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d86705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d8675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d86705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d866ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557119602e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557119602c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005571195e7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005571192970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557119296dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9d866eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d866ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d866ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557119296cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c (2307 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0dcb3115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b0dcb2e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b0dcb3189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9818705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f981875c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9818705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98186ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0dcac6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b0dcac6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b0dcaabb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b0dc75b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b0dc75add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f98186eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98186ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98186ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0dc75acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c (2308 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwin
# | ...
# `---data was truncated (10240/10610) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630758f915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005630758f60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005630758f989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5d4105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5d415c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5d4105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5d40ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056307588ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056307588ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563075873b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005630755230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563075522dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd5d40eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5d40ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5d40ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563075522cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c (2309 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1(ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m2(ptr noundef %base, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m4(ptr noundef %base, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m8(ptr noundef %base, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 
# | ...
# `---data was truncated (10240/22890) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559657ef915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559657ef60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559657ef989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcc90733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcc9078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcc90733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcc9071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559657e8ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559657e8ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559657e73b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559657b230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559657b22dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcc9071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcc9071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcc9071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559657b22cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c (2310 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558245c3c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558245c390f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558245c3c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7210649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72106a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7210649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7210631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558245bd1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558245bd1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558245bb6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005582458660b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558245865dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7210632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72106330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72106330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558245865cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/riscv-xcvalu.c (2311 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xcvalu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_abs(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.abs.i32(i32 %0, i1 true)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.abs.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sle(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = icmp sle i32 %0, %1
# |   %sle = zext i1 %2 to i32
# |   ret i32 %sle
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sleu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = icmp ule i32 %0, %1
# |   %sleu = zext i1 %2 to i32
# |   ret i32 %sleu
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exths(i16 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %conv = sext i16 %0 to i32
# |   %1 = trunc i32 %conv to i16
# |   %exths = sext i16 %1 to i32
# |   ret i32 %exths
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exthz(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   %conv = zext i16 %0 to i32
# |   %1 = trunc i32 %conv to i16
# |   %exthz = zext i16 %1 to i32
# |   ret i32 %exthz
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbs(i8 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %conv = sext i8 %0 to i32
# |   %1 = trunc i32 %conv to i8
# |   %extbs = sext i8 %1 to i32
# |   ret i32 %extbs
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbz(i8 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   %conv = zext i8 %0 to i32
# |   %1 = trunc i32 %conv to i8
# |   %extbz = zext i8 %1 to i32
# |   ret i32 %extbz
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clip(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.cv.alu.clip(i32 %0, i32 15)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.clip(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clipu(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.riscv.cv.alu.clipu(i32 %0, i32 15)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.clipu(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.addN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.addN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.adduN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.adduN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.addRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.addRN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.adduRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.adduRN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subuN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subuN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subuN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subRN(i32, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subuRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.cv.alu.subuRN(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.cv.alu.subuRN(i32, i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xcvalu" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xcvalu1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ecf40715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563ecf4040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563ecf40789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fddbe61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fddbe6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fddbe61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fddbe603507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ecf39ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563ecf39cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563ecf381b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563ecf0310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563ecf030dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fddbe604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fddbe6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fddbe6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ecf030cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c (2312 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsaddu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsaddu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsaddu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsaddu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsaddu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsaddu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsaddu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsaddu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, ali
# | ...
# `---data was truncated (10240/223367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfd931315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dfd93100f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dfd931389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b29f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b29f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b29f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b29f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfd92a8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dfd92a8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dfd928db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dfd8f3d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dfd8f3cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7b29f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b29f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b29f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfd8f3ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c (2313 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e8w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtzero.t.i64(i64 immarg, i64, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e8w2(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e8w4(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e16w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e16w2(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e16w4(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e32w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 5, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e32w2(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 5, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtzero_t_e64w1(i64 noundef %tm, i64 noundef %tn) #0 {
# | entry:
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tm.addr, align 8
# |   %1 = load i64, ptr %tn.addr, align 8
# |   call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 6, i64 1)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ae647815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555ae64750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555ae647889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7c0cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7c0cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7c0cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7c0cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ae640de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555ae640dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555ae63f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555ae60a20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555ae60a1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7c0cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7c0cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7c0cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ae60a1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c (2314 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl
# | ...
# `---data was truncated (10240/27434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555fd04c415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555fd04c10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555fd04c489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f491bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f491bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f491bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f491bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555fd0459e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555fd0459c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555fd043eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555fd00ee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555fd00eddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f491bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f491bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f491bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555fd00edcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c (2315 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac9669d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ac9669a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ac9669d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe51ff05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe51ff5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe51ff05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe51feed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac96632e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ac96632c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ac96617b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ac962c70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ac962c6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe51feeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe51feef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe51feef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac962c6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c (2316 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b2447e315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b2447e00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b2447e389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbdde61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbdde6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbdde61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbdde603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b244778e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b244778c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b24475db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b24440d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b24440cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbdde604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbdde6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbdde6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b24440ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c (2317 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055903404a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005590340470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055903404a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f046be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f046bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f046be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f046be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559033fdfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559033fdfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559033fc4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559033c740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559033c73dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f046be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f046be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f046be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559033c73cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c (2318 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604e6fc415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005604e6fc10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005604e6fc489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31dde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31ddea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31dde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31dde31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604e6f59e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005604e6f59c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005604e6f3eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005604e6bee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005604e6beddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f31dde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31dde330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31dde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604e6bedcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c (2319 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16
# | ...
# `---data was truncated (10240/15367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055989b5ad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055989b5aa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055989b5ad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1171c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1171ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1171c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1171c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055989b542e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055989b542c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055989b527b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055989b1d70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055989b1d6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1171c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1171c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1171c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055989b1d6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c (2320 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vx.
# | ...
# `---data was truncated (10240/28427) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1c5b5a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a1c5b570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a1c5b5a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff061a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff061aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff061a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff061a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1c5aefe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a1c5aefc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a1c5ad4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a1c57840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a1c5783dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff061a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff061a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff061a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1c5783cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c (2321 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = al
# | ...
# `---data was truncated (10240/14209) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636d2d8e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005636d2d8b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005636d2d8e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe098933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe09898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe098933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe09891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636d2d23e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005636d2d23c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005636d2d08b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005636d29b80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005636d29b7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe09891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe09891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe09891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636d29b7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c (2322 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055778e7de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055778e7db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055778e7de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fadb3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fadb318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fadb3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fadb311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055778e773e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055778e773c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055778e758b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055778e4080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055778e407dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fadb311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fadb311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fadb311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055778e407cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c (2323 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llv
# | ...
# `---data was truncated (10240/51751) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3c50cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c3c50c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c3c50cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f401da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f401daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f401da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f401da31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3c5060e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c3c5060c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c3c5045b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c3c4cf50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c3c4cf4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f401da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f401da330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f401da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3c4cf4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c (2324 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601dfda115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005601dfd9e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005601dfda189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe47d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe47d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe47d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe47d31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601dfd36e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005601dfd36c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005601dfd1bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005601df9cb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005601df9cadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe47d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe47d31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe47d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601df9cacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c (2325 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmacc_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmacc_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmacc_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmacc_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmacc
# | ...
# `---data was truncated (10240/51796) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8a0bfe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d8a0bfb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d8a0bfe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc425049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4250a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc425049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc425031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8a0b93e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d8a0b93c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d8a0b78b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d8a08280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d8a0827dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc425032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4250330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4250330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8a0827cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c (2326 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6636ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a6636a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a6636ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f389f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f389f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f389f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f389f31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a663640e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a663640c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a663625b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a6632d50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a6632d4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f389f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f389f31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f389f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6632d4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c (2327 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f76d4fa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f76d4f70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f76d4fa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a34d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a34d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a34d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a34d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f76d48fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f76d48fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f76d474b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f76d1240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f76d123dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8a34d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a34d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a34d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f76d123cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c (2328 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tu(<vs
# | ...
# `---data was truncated (10240/295861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558111b9515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558111b920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558111b9589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b00505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b0055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b00505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b004ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558111b2ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558111b2ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558111b0fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005581117bf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005581117bedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3b004eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b004ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b004ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581117becc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c (2329 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649c880115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005649c87fe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005649c880189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f302f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f302f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f302f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f302f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649c8796e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005649c8796c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005649c877bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005649c842b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005649c842add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f302f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f302f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f302f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649c842acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c (2330 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f57bb2415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f57bb210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f57bb2489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2c1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2c178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2c1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2c171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f57bab9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f57bab9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f57ba9eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f57b74e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f57b74ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa2c171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2c171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2c171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f57b74dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c (2331 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwabdau_vx_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwabdau_vx_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwabdau_vx_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwabdau_vx_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %rs1.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i8, ptr %rs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwabdau_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x 
# | ...
# `---data was truncated (10240/58468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d2e33515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559d2e3320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559d2e33589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd196505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd19655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd196505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1964ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d2e2cae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559d2e2cac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559d2e2afb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559d2df5f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559d2df5edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd1964eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1964ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1964ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d2df5ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c (2332 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e528d1615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e528d130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e528d1689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4db4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4db48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4db4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4db4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e528cabe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e528cabc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e528c90b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e5289400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e52893fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4db4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4db48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4db48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e52893fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c (2333 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e352bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555e352ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555e352bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc78fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc78fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc78fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc78fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e35252e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555e35252c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555e35237b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555e34ee70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555e34ee6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc78fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc78fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc78fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e34ee6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c (2334 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +xsfvfexp32e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexp_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexp.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexp_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexp_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexp_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexp_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(<vscale x 8 x fl
# | ...
# `---data was truncated (10240/22298) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563f66e4815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563f66e450f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563f66e4889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c95733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c9578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c95733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c9571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563f66ddde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563f66dddc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563f66dc2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563f66a720b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563f66a71dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6c9571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c9571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c9571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563f66a71cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c (2335 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c587e215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563c587df0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563c587e289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f789d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f789d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f789d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f789d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c58777e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563c58777c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563c5875cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563c5840c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563c5840bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f789d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f789d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f789d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c5840bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c (2336 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565068e0115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000565068dfe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000565068e0189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6550105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f655015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6550105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f65500ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565068d96e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565068d96c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565068d7bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000565068a2b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000565068a2add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f65500eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f65500ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f65500ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565068a2acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c (2337 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,
# | ...
# `---data was truncated (10240/70979) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598c198b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005598c19880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005598c198b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb9dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb9dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb9dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb9dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598c1920e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005598c1920c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005598c1905b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005598c15b50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005598c15b4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ffb9dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb9dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb9dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598c15b4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c (2338 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560791e9215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560791e8f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560791e9289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcea6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcea64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcea6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcea6431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560791e27e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560791e27c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560791e0cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560791abc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560791abbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcea6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcea64330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcea64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560791abbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c (2339 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_
# | ...
# `---data was truncated (10240/13617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8d877815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c8d87750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c8d877889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7f6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7f6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7f6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7f6e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8d870de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c8d870dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c8d86f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c8d83a20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c8d83a1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe7f6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7f6e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7f6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8d83a1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c (2340 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b694c4915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b694c460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b694c4989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fabbc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fabbc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fabbc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fabbc91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b694bdee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b694bdec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b694bc3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b6948730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b694872dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fabbc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fabbc91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fabbc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b694872cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c (2341 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9c1a3915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d9c1a360f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d9c1a3989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdabb649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdabb6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdabb649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdabb631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9c19cee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d9c19cec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d9c19b3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d9c16630b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d9c1662dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdabb632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdabb6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdabb6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9c1662cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c (2342 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulh_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulh_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulh_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulh_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.i64.i64(<vs
# | ...
# `---data was truncated (10240/18591) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644b597115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005644b596e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005644b597189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4bb9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4bb90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4bb9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4bb9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644b5906e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005644b5906c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005644b58ebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005644b559b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005644b559add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4bb9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4bb90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4bb90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644b559acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c (2343 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target
# | ...
# `---data was truncated (10240/10700) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055573f69c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055573f6990f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055573f69c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5fdc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5fdc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5fdc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5fdc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055573f631e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055573f631c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055573f616b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055573f2c60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055573f2c5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5fdc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5fdc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5fdc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055573f2c5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c (2344 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562035d2b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562035d280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562035d2b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f10b3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10b3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f10b3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10b3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562035cc0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562035cc0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562035ca5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005620359550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562035954dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f10b3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10b3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10b3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562035954cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c (2345 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c2d31f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560c2d31c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560c2d31f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9716b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9716b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9716b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9716b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c2d2b4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560c2d2b4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560c2d299b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560c2cf490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560c2cf48dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9716b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9716b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9716b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c2cf48cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c (2346 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f374dcb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f374dc80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f374dcb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f41a9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f41a9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f41a9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f41a9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f374d60e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f374d60c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f374d45b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f3749f50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f3749f4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f41a9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f41a9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f41a9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3749f4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c (2347 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056135d15c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056135d1590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056135d15c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa480c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa480c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa480c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa480c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056135d0f1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056135d0f1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056135d0d6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056135cd860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056135cd85dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa480c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa480c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa480c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056135cd85cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c (2348 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056510d7ea15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056510d7e70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056510d7ea89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fccb4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fccb46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fccb4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fccb4631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056510d77fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056510d77fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056510d764b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056510d4140b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056510d413dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fccb4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fccb46330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fccb46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056510d413cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c (2349 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# | ...
# `---data was truncated (10240/60691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ecca3d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564ecca3a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564ecca3d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0361d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0361d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0361d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0361d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ecc9d2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564ecc9d2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564ecc9b7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564ecc6670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564ecc666dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0361d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0361d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0361d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ecc666cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c (2350 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564797b5815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564797b550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564797b5889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0ed933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0ed98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0ed933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0ed91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564797aede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564797aedc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564797ad2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005647977820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564797781dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff0ed91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0ed91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0ed91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564797781cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c (2351 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633f7cb215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005633f7caf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005633f7cb289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7006449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70064a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7006449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7006431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633f7c47e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005633f7c47c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005633f7c2cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005633f78dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005633f78dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7006432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70064330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70064330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633f78dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c (2352 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh    -target-feature +xsfvfexpa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4(<vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexpa_v_f16mf2(<vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexpa_v_f16m1(<vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexpa_v_f16m2(<vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexpa_v_f16m4(<vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexpa_v_f16m8(<vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfexpa_v_f32mf2(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfexpa_v_f32m1(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfexpa_v_f32m2(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfexpa_v_f32m4(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfexpa_v_f32m8(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexpa_v_f16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vsc
# | ...
# `---data was truncated (10240/21473) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056343d8f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056343d8f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056343d8f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c16f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c16f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c16f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c16f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056343d88de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056343d88dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056343d872b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056343d5220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056343d521dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2c16f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c16f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c16f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056343d521cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c (2353 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x 
# | ...
# `---data was truncated (10240/53338) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da2f4c415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055da2f4c10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055da2f4c489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f73849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f738a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f73849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f73831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da2f459e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055da2f459c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055da2f43eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055da2f0ee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055da2f0eddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7f73832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f738330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f738330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da2f0edcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c (2354 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564a8767615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564a876730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564a8767689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42c0a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42c0a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42c0a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42c0a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564a8760be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564a8760bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564a875f0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564a872a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564a8729fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f42c0a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42c0a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42c0a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564a8729fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c (2355 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ad5b8515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556ad5b820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556ad5b8589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13bd449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13bd4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13bd449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13bd431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ad5b1ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556ad5b1ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556ad5affb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556ad57af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556ad57aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f13bd432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13bd4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13bd4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ad57aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c (2356 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define d
# | ...
# `---data was truncated (10240/26976) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653a31d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005653a31d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005653a31d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb28cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb28cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb28cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb28cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653a3169e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005653a3169c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005653a314eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005653a2dfe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005653a2dfddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb28cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb28cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb28cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653a2dfdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c (2357 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa7469615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aa746930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aa7469689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d8cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d8cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d8cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d8cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa7462be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aa7462bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aa74610b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aa742c00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aa742bfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1d8cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d8cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d8cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa742bfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c (2358 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmin_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmin_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmin.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmin_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmin.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmin_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmin.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmin_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0767b015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e0767ad0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e0767b089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9be041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9be04725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9be041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9be0403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e076745e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e076745c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e07672ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e0763da0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e0763d9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9be0404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9be04050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9be04050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0763d9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c (2359 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vid_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vid_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vid_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vid_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vid_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vid_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vid_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vid_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vid_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vid_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vid_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vid_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vid_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vid_v_u32mf2_tu(<vscale x 1 x i32
# | ...
# `---data was truncated (10240/75405) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646f315515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005646f31520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005646f315589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce7d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce7d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce7d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce7d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646f30eae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005646f30eac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005646f30cfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005646f2d7f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005646f2d7edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fce7d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce7d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce7d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646f2d7ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c (2360 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfsqrt_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfsqrt_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define d
# | ...
# `---data was truncated (10240/51420) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9315b215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c9315af0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c9315b289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4862133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f486218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4862133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f486211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c931547e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c931547c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c93152cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c9311dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c9311dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f486211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f486211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f486211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9311dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c (2361 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bfb831915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bfb83160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bfb831989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff55e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff55e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff55e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff55e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bfb82aee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bfb82aec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bfb8293b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bfb7f430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bfb7f42dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007eff55e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff55e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff55e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bfb7f42cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c (2362 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf9c44115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bf9c43e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bf9c44189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe838a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe838aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe838a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe838a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf9c3d6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bf9c3d6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bf9c3bbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bf9c06b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bf9c06add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe838a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe838a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe838a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf9c06acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c (2363 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmul_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmul_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmul_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vv_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmul_vf_bf16m2_f32m4(<vscale x 8 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vv_bf16m4_f32m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwmul_vf_bf16m4_f32m8(<vscale x 16 x bfloat> %v
# | ...
# `---data was truncated (10240/43948) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653527dc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005653527d90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005653527dc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea8a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea8a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea8a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea8a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565352771e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565352771c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565352756b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005653524060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000565352405dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fea8a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea8a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea8a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565352405cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c (2364 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m1x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f16m2x3(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m1x3(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f32m2x3(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg3ei8_v_f64m1x3(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tu
# | ...
# `---data was truncated (10240/99186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005609866ed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005609866ea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005609866ed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f25abc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f25abca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f25abc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f25abc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560986682e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560986682c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560986667b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005609863170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560986316dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f25abc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f25abc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f25abc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560986316cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c (2365 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, al
# | ...
# `---data was truncated (10240/128416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a05868a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a0586870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a05868a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0bc1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0bc198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0bc1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0bc191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a05861fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a05861fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a058604b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a0582b40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a0582b3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0bc191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0bc191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0bc191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0582b3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c (2366 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwadd_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwadd_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwadd_wv_i16m1(<vscal
# | ...
# `---data was truncated (10240/134557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bad5f3515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bad5f320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bad5f3589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e87e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e87ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e87e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e87e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bad5ecae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bad5ecac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bad5eafb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bad5b5f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bad5b5edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7e87e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e87e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e87e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bad5b5ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c (2367 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssub_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssub_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssub_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssub_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssub_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssub.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vssub_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   
# | ...
# `---data was truncated (10240/97913) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563eb318d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563eb318a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563eb318d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16e441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16e44725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16e441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16e4403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563eb3122e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563eb3122c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563eb3107b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563eb2db70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563eb2db6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f16e4404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16e44050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16e44050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563eb2db6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c (2368 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i
# | ...
# `---data was truncated (10240/12756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b785a715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555b785a40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555b785a789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f46aaa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46aaaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f46aaa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f46aaa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b7853ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555b7853cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555b78521b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555b781d10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555b781d0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f46aaa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46aaa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46aaa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b781d0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c (2369 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b7e516015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b7e515d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b7e516089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4aacb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4aacb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4aacb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4aacb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7e50f5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b7e50f5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b7e50dab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b7e4d8a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b7e4d89dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4aacb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4aacb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4aacb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7e4d89cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c (2370 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmflt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmflt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6de32415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c6de3210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c6de32489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9cff649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9cff6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9cff649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9cff631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6de2b9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c6de2b9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c6de29eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c6ddf4e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c6ddf4ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9cff632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9cff6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9cff6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6ddf4dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c (2371 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8
# | ...
# `---data was truncated (10240/96911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6e903115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b6e902e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b6e903189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5138f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5138f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5138f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5138f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6e8fc6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b6e8fc6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b6e8fabb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b6e8c5b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b6e8c5add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5138f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5138f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5138f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6e8c5acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c (2372 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 1)
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_poly_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, i32 1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3)
# |   %5 = load <2 x i64>, ptr %inactive.addr, align 8
# |   %6 = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, i32 1, <2 x i1> %4, <2 x i64> %5)
# |   ret <2 x i64> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_poly_m_p8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |  
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c72ccd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561c72cca0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561c72ccd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffad9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffad9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffad9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffad9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c72c62e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561c72c62c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561c72c47b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561c728f70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561c728f6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ffad9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffad9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffad9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c728f6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c (2373 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_i8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf8x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e8_v_u8m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   cal
# | ...
# `---data was truncated (10240/23487) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559aaa76915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559aaa7660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559aaa76989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f63f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f63f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f63f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f63f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559aaa6fee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559aaa6fec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559aaa6e3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559aaa3930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559aaa392dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4f63f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f63f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f63f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559aaa392cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c (2374 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056528d36115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056528d35e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056528d36189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3efc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3efc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3efc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3efc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056528d2f6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056528d2f6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056528d2dbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056528cf8b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056528cf8add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3efc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3efc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3efc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056528cf8acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c (2375 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055832f5fa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055832f5f70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055832f5fa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd944e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd944ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd944e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd944e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055832f58fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055832f58fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055832f574b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055832f2240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055832f223dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd944e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd944e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd944e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055832f223cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c (2376 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561db553015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561db552d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561db553089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc2df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc2df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc2df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc2df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561db54c5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561db54c5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561db54aab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561db515a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561db5159dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efc2df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc2df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc2df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561db5159cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c (2377 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560615c3815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560615c350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560615c3889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd015a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd015aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd015a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd015a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560615bcde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560615bcdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560615bb2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005606158620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560615861dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd015a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd015a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd015a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560615861cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c (2378 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b432d515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561b432d20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561b432d589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa8cd01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa8cd0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa8cd01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa8cd003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b4326ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561b4326ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561b4324fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561b42eff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561b42efedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa8cd004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa8cd0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa8cd0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b42efecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c (2379 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c  -check-prefix=RV32ZKNH
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sig0(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sig1(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sig1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sum0(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha256sum1(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sha256sum1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig0h(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig0h(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig0l(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig0l(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig1h(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig1h(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sig1l(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sig1l(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sum0r(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sum0r(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sha512sum1r(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %__y.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   store i32 %1, ptr %__y.addr.i, align 4
# |   %2 = load i32, ptr %__x.addr.i, align 4
# |   %3 = load i32, ptr %__y.addr.i, align 4
# |   %4 = call i32 @llvm.riscv.sha512sum1r(i32 %2, i32 %3)
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sig1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha256sum1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig0h(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig0l(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig1h(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sig1l(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sum0r(i32, i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sha512sum1r(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zknh" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zknh1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b96287c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b9628790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b96287c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f036b41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f036b4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f036b41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f036b403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b962811e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b962811c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b9627f6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b9624a60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b9624a5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f036b404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f036b4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f036b4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9624a5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c (2380 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4_tu(<vscale x 1 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2_tu(<vscale x 2 x i16> %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x 2 x i16> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(<vscale x
# | ...
# `---data was truncated (10240/93466) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b293a3e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b293a3b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b293a3e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f058f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f058f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f058f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f058f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b2939d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b2939d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b2939b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b2936680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b293667dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f058f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f058f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f058f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b293667cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c (2381 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_u32m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595e6d2915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005595e6d260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005595e6d2989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f49bda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49bdaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f49bda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f49bda31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595e6cbee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005595e6cbec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005595e6ca3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005595e69530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005595e6952dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f49bda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49bda330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49bda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595e6952cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c (2382 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc059bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fc059ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fc059bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa862f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa862f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa862f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa862eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc05952e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fc05952c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fc05937b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fc055e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fc055e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa862eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa862eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa862eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc055e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10..
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c (2383 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale
# | ...
# `---data was truncated (10240/306025) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556bb635015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556bb634d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556bb635089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1305733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f130578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1305733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f130571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556bb62e5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556bb62e5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556bb62cab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556bb5f7a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556bb5f79dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f130571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f130571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f130571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556bb5f79cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c (2384 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tu(<vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tu(<vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tu(<vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tu(<vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8bf16.i64(<vscale x 8 x i16>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_bf16m4_u16m4_tu(<vscale x 16 x i16> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16bf16.i64(<vscale x 16 x i16>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_bf16m8_u16m8_tu(<vscale x 32 x i16> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32bf16.i64(<vscale x 32 x i16>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_bf16mf4_u16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i16> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1bf16.i64(<vscale x 1 x i16>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_bf16mf2_u16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i16> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2bf16.i64(<vscale x 2 x i16>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_bf16m1_u16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i16> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4bf16.i64(<vscale x 4 x i16>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_bf16m2_u16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x i16> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #
# | ...
# `---data was truncated (10240/26584) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e678bc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564e678b90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564e678bc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b92449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b924a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b92449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b92431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e67851e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564e67851c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564e67836b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564e674e60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564e674e5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9b92432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b924330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b924330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e674e5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c (2385 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load 
# | ...
# `---data was truncated (10240/29128) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055920122e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055920122b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055920122e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff420449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4204a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff420449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff420431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592011c3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005592011c3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005592011a8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559200e580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559200e57dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff420432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4204330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4204330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559200e57cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c (2386 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) 
# | ...
# `---data was truncated (10240/25094) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fbaa09715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fbaa0940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fbaa09789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f7e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f7e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f7e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f7e431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbaa02ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fbaa02cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fbaa011b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fba9cc10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fba9cc0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1f7e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f7e4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f7e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fba9cc0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c (2387 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3
# | ...
# `---data was truncated (10240/64366) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056031f9d515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056031f9d20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056031f9d589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5554d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5554d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5554d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5554d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056031f96ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056031f96ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056031f94fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056031f5ff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056031f5fedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5554d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5554d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5554d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056031f5fecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c (2388 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056294384215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056294383f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056294384289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d45533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d4558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d45533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d4551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629437d7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005629437d7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005629437bcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056294346c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056294346bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0d4551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d4551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d4551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056294346bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c (2389 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/69980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589361b015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005589361ad0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005589361b089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9265b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9265b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9265b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9265aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558936145e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558936145c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055893612ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558935dda0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558935dd9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9265aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9265aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9265aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558935dd9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c (2390 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f084dc815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f084dc50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f084dc889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2aac533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2aac58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2aac533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2aac51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f084d5de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f084d5dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f084d42b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f0849f20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f0849f1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2aac51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2aac51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2aac51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0849f1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c (2391 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vx_u16m4(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline n
# | ...
# `---data was truncated (10240/68255) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e9f24115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557e9f23e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557e9f24189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fddccf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fddccf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fddccf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fddccf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e9f1d6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557e9f1d6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557e9f1bbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557e9ee6b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557e9ee6add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fddccf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fddccf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fddccf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e9ee6acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vandq.c (2392 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vandq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = and <16 x i8> %0, %1
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = and <8 x i16> %0, %1
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = and <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vandq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = and <4 x i32> %1, %3
# |   %5 = bitcast <4 x i32> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vandq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vandq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5)
# |   %7 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x
# | ...
# `---data was truncated (10240/10901) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055929765b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005592976580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055929765b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b54733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b5478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b54733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b5471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592975f0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005592975f0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005592975d5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005592972850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559297284dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7b5471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b5471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b5471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559297284cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c (2393 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_u16m1x5_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055caca1ca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055caca1c70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055caca1ca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd01d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd01d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd01d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd01d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055caca15fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055caca15fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055caca144b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cac9df40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cac9df3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdd01d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd01d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd01d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cac9df3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c (2394 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f418a715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562f418a40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562f418a789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9ffa849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9ffa8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9ffa849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9ffa831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f4183ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562f4183cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562f41821b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562f414d10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562f414d0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9ffa832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9ffa8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9ffa8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f414d0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c (2395 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055578052315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005557805200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055578052389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7d2ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7d2aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7d2ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7d2ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557804b8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005557804b8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055578049db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055578014d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055578014cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7d2ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7d2ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7d2ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055578014ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c (2396 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vlse64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64.p0.i64(<vscale x 1 x double> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vlse64_v_f64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64.p0.i64(<vscale x 2 x double> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vlse64_v_f64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64.p0.i64(<vscale x 4 x double> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vlse64_v_f64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64.p0.i64(<vscale x 8 x double> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_i64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vlse64_v_i64m2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64.p0.i64(<vscale x 2 x i64> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vlse64_v_i64m4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64.p0.i64(<vscale x 4 x i64> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vlse64_v_i64m8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64.p0.i64(<vscale x 8 x i64> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vlse64_v_u64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.ad
# | ...
# `---data was truncated (10240/13903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec882c715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ec882c40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ec882c789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e4c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e4c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e4c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e4c631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec8825ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ec8825cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ec88241b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ec87ef10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ec87ef0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4e4c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e4c6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e4c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec87ef0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c (2397 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_i8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_i8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e8_v_i8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e8_v_i8m1x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e8_v_i8m2x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e8_v_i8m4x2_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlsseg2e8_v_u8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e8_v_u8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 nounde
# | ...
# `---data was truncated (10240/16083) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055908bdfc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055908bdf90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055908bdfc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc648e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc648ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc648e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc648e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055908bd91e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055908bd91c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055908bd76b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055908ba260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055908ba25dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc648e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc648e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc648e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055908ba25cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c (2398 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b715a0915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b715a060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b715a0989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00a7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00a70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00a7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00a7031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b71599ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b71599ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b715983b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b7156330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b715632dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f00a7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00a70330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00a70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b715632cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c (2399 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9d46a215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f9d469f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f9d46a289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb525333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb52538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb525333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb52531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9d4637e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f9d4637c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f9d461cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f9d42cc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f9d42cbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb52531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb52531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb52531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9d42cbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c (2400 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmul_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmul_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmul_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmul_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmul_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, ha
# | ...
# `---data was truncated (10240/125649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7352ef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f7352ec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f7352ef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd68333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd6838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd68333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd6831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f735284e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f735284c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f735269b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f734f190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f734f18dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcd6831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd6831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd6831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f734f18cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c (2401 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/113047) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fa2049f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fa2049c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fa2049f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90b621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90b62725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90b621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90b6203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fa20434e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fa20434c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fa20419b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fa200c90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fa200c8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f90b6204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90b62050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90b62050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fa200c8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c (2402 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/30826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7d288a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c7d28870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c7d288a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3706f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3706f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3706f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3706f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7d281fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c7d281fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c7d2804b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c7d24b40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c7d24b3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3706f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3706f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3706f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7d24b3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/cx-complex-range-real.c (2403 of 27911)
******************** TEST 'Clang :: CodeGen/cx-complex-range-real.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown  -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @mulaf(<2 x float> noundef %a.coerce, float noundef %b) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b.addr = alloca float, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store float %b, ptr %b.addr, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %mul.rl = fmul float %a.real, %0
# |   %mul.il = fmul float %a.imag, %0
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %mul.rl, ptr %retval.realp, align 4
# |   store float %mul.il, ptr %retval.imagp, align 4
# |   %1 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @mulassignf(ptr noundef %a, float noundef %b) #1 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca float, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %mul.rl = fmul float %.real, %0
# |   %mul.il = fmul float %.imag, %0
# |   %.realp1 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   store float %mul.rl, ptr %.realp1, align 4
# |   store float %mul.il, ptr %.imagp2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @mulbf(float noundef %a, <2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %b = alloca { float, float }, align 4
# |   %a.addr = alloca float, align 4
# |   store <2 x float> %b.coerce, ptr %b, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0
# |   %b.real = load float, ptr %b.realp, align 4
# |   %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1
# |   %b.imag = load float, ptr %b.imagp, align 4
# |   %mul.rl = fmul float %0, %b.real
# |   %mul.ir = fmul float %0, %b.imag
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %mul.rl, ptr %retval.realp, align 4
# |   store float %mul.ir, ptr %retval.imagp, align 4
# |   %1 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @divf(<2 x float> noundef %a.coerce, float noundef %b) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %a = alloca { float, float }, align 4
# |   %b.addr = alloca float, align 4
# |   store <2 x float> %a.coerce, ptr %a, align 4
# |   store float %b, ptr %b.addr, align 4
# |   %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0
# |   %a.real = load float, ptr %a.realp, align 4
# |   %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1
# |   %a.imag = load float, ptr %a.imagp, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %1 = fdiv float %a.real, %0
# |   %2 = fdiv float %a.imag, %0
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %1, ptr %retval.realp, align 4
# |   store float %2, ptr %retval.imagp, align 4
# |   %3 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignf(ptr noundef %a, float noundef %b) #1 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca float, align 4
# |   store ptr %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   %0 = load float, ptr %b.addr, align 4
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.real = load float, ptr %.realp, align 4
# |   %.imagp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   %.imag = load float, ptr %.imagp, align 4
# |   %2 = fdiv float %.real, %0
# |   %3 = fdiv float %.imag, %0
# |   %.realp1 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1
# |   store float %2, ptr %.realp1, align 4
# |   store float %3, ptr %.imagp2, align 4
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local { double, double } @divd(double noundef %a.coerce0, double noundef %a.coerce1, double noundef %b) #1 {
# | entry:
# |   %retval = alloca { double, double }, align 8
# |   %a = alloca { double, double }, align 8
# |   %b.addr = alloca double, align 8
# |   %0 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   store double %a.coerce0, ptr %0, align 8
# |   %1 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   store double %a.coerce1, ptr %1, align 8
# |   store double %b, ptr %b.addr, align 8
# |   %a.realp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0
# |   %a.real = load double, ptr %a.realp, align 8
# |   %a.imagp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1
# |   %a.imag = load double, ptr %a.imagp, align 8
# |   %2 = load double, ptr %b.addr, align 8
# |   %3 = fdiv double %a.real, %2
# |   %4 = fdiv double %a.imag, %2
# |   %retval.realp = getelementptr inbounds nuw { double, double }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { double, double }, ptr %retval, i32 0, i32 1
# |   store double %3, ptr %retval.realp, align 8
# |   store double %4, ptr %retval.imagp, align 8
# |   %5 = load { double, double }, ptr %retval, align 8
# |   ret { double, double } %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @divbd(double noundef %a, double noundef %b.coerce0, double noundef %b.coerce1) #0 {
# | entry:
# |   %retval = alloca { float, float }, align 4
# |   %b = alloca { double, double }, align 8
# |   %a.addr = alloca double, align 8
# |   %0 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0
# |   store double %b.coerce0, ptr %0, align 8
# |   %1 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1
# |   store double %b.coerce1, ptr %1, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %2 = load double, ptr %a.addr, align 8
# |   %b.realp = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0
# |   %b.real = load double, ptr %b.realp, align 8
# |   %b.imagp = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1
# |   %b.imag = load double, ptr %b.imagp, align 8
# |   %call = call { double, double } @__divdc3(double noundef %2, double noundef 0.000000e+00, double noundef %b.real, double noundef %b.imag) #2
# |   %3 = extractvalue { double, double } %call, 0
# |   %4 = extractvalue { double, double } %call, 1
# |   %conv = fptrunc double %3 to float
# |   %conv1 = fptrunc double %4 to float
# |   %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1
# |   store float %conv, ptr %retval.realp, align 4
# |   store float %conv1, ptr %retval.imagp, align 4
# |   %5 = load <2 x float>, ptr %retval, align 4
# |   ret <2 x float> %5
# | }
# | 
# | declare { double, double } @__divdc3(double, double, double, double)
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignd(ptr noundef %a, double noundef %b) #1 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca double, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store double %b, ptr %b.addr, align 8
# |   %0 = load double, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   %.realp = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 0
# |   %.real = load double, ptr %.realp, align 8
# |   %.imagp = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 1
# |   %.imag = load double, ptr %.imagp, align 8
# |   %2 = fdiv double %.real, %0
# |   %3 = fdiv double %.imag, %0
# |   %.realp1 = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 0
# |   %.imagp2 = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 1
# |   store double %2, ptr %.realp1, align 8
# |   store double %3, ptr %.imagp2, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local { x86_fp80, x86_fp80 } @divld(ptr noundef byval({ x86_fp80, x86_fp80 }) align 16 %a, x86_fp80 noundef %b) #1 {
# | entry:
# |   %retval = alloca { x86_fp80, x86_fp80 }, align 16
# |   %b.addr = alloca x86_fp80, align 16
# |   store x86_fp80 %b, ptr %b.addr, align 16
# |   %a.realp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %a, i32 0, i32 0
# |   %a.real = load x86_fp80, ptr %a.realp, align 16
# |   %a.imagp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %a, i32 0, i32 1
# |   %a.imag = load x86_fp80, ptr %a.imagp, align 16
# |   %0 = load x86_fp80, ptr %b.addr, align 16
# |   %1 = fdiv x86_fp80 %a.real, %0
# |   %2 = fdiv x86_fp80 %a.imag, %0
# |   %retval.realp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %retval, i32 0, i32 0
# |   %retval.imagp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %retval, i32 0, i32 1
# |   store x86_fp80 %1, ptr %retval.realp, align 16
# |   store x86_fp80 %2, ptr %retval.imagp, align 16
# |   %3 = load { x86_fp80, x86_fp80 }, ptr %retval, align 16
# |   ret { x86_fp80, x86_fp80 } %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @divassignld(ptr noundef %a, x86_fp80 noundef %b) #1 {
# | entry:
# |   %a.addr 
# | ...
# `---data was truncated (10240/11567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000563399c4015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563399c3d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563399c4089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cedd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cedd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cedd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cedd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563399bd5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563399bd5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563399bbab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056339986a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563399869dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4cedd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cedd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cedd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563399869cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c (2404 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/47706) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c81eb5715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c81eb540f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c81eb5789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fc3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fc3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fc3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fc3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c81eaece2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c81eaecc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c81ead1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c81e7810b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c81e780dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0fc3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fc3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fc3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c81e780cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c (2405 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e4m3mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e4m3mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e4m3mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e4m3m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e4m3m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e4m3m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e4m3m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e4m3mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e4m3mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e4m3mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e4m3m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e4m3m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e4m3m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e4m3m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_f8e5m2mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_f8e5m2mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_f8e5m2mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_f8e5m2m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_f8e5m2m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_f8e5m2m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_f8e5m2m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_f8e5m2mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_f8e5m2mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_f8e5m2mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_f8e5m2m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_f8e5m2m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_f8e5m2m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_f8e5m2m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 
# | ...
# `---data was truncated (10240/10944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d629b5715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d629b540f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d629b5789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7932449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f79324a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7932449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7932431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d629aece2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d629aecc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d629ad1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d6297810b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d629780dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7932432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f79324330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f79324330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d629780cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c (2406 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfclass_v_u32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfclass_v_u64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfclass_v_u64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <v
# | ...
# `---data was truncated (10240/28691) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056422242515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005642224220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056422242589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f136d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f136d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f136d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f136d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642223bae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005642223bac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056422239fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056422204f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056422204edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f136d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f136d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f136d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056422204ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c (2407 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16
# | ...
# `---data was truncated (10240/295311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593beba115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005593beb9e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005593beba189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff825249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8252a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff825249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff825231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593beb36e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005593beb36c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005593beb1bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005593be7cb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005593be7cadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff825232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8252330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8252330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593be7cacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c (2408 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfadd_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfadd_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfadd_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfadd_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfa
# | ...
# `---data was truncated (10240/65574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055679774915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005567977460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055679774989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f2a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f2a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f2a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f2a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567976dee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005567976dec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005567976c3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005567973730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556797372dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4f2a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f2a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f2a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556797372cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c (2409 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b7d3a2715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b7d3a240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b7d3a2789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f318a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f318a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f318a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f318a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7d39bce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b7d39bcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b7d39a1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b7d36510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b7d3650dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f318a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f318a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f318a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7d3650cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c (2410 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsub_vf_bf16m8(<vscale x 32 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsub_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsub_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsub_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64 immar
# | ...
# `---data was truncated (10240/14780) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cfc45fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cfc45fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cfc45fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf4fb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf4fb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf4fb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf4faed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cfc4592e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cfc4592c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cfc4577b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cfc42270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cfc4226dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdf4faeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf4faef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf4faef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cfc4226cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c (2411 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005654fe54a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005654fe5470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005654fe54a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13d161bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13d16725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13d161ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13d1603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654fe4dfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005654fe4dfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005654fe4c4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005654fe1740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005654fe173dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f13d1604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13d16050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13d16050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654fe173cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/builtins-riscv.c (2412 of 27911)
******************** TEST 'Clang :: CodeGen/builtins-riscv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_eh_return_data_regno() #0 {
# | entry:
# |   %res = alloca i32, align 4
# |   store volatile i32 10, ptr %res, align 4
# |   store volatile i32 11, ptr %res, align 4
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577dceda15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005577dced70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005577dceda89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed72533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed7258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed72533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed7251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577dce6fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005577dce6fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005577dce54b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005577dcb040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005577dcb03dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fed7251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed7251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed7251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577dcb03cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c (2413 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625ecc5815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005625ecc550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005625ecc5889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f40bc21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40bc2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f40bc21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f40bc203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625ecbede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005625ecbedc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005625ecbd2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005625ec8820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005625ec881dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f40bc204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40bc2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40bc2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625ec881cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c (2414 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vvm_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vxm_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsbc_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vvm_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vxm_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %borrowin.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsbc_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vvm_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %borrowin.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %borrowin, ptr %borrowin.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %borrowin.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsbc_vxm_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %borrowin, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# | ...
# `---data was truncated (10240/170489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056246217d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056246217a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056246217d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd63f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd63f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd63f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd63f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562462112e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562462112c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005624620f7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562461da70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562461da6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd63f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd63f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd63f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562461da6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c (2415 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b04cf7415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b04cf710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b04cf7489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa55c105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa55c15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa55c105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa55c0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b04cf09e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b04cf09c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b04ceeeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b04cb9e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b04cb9ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa55c0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa55c0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa55c0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b04cb9dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c (2416 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f16m1x5(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f32m1x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_f64m1x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei32_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1cb0e215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d1cb0df0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d1cb0e289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa86f105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa86f15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa86f105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa86f0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1cb077e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d1cb077c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d1cb05cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d1cad0c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d1cad0bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa86f0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa86f0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa86f0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1cad0bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c (2417 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   
# | ...
# `---data was truncated (10240/21558) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563354f0a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563354f070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563354f0a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51adb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51adb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51adb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51adb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563354e9fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563354e9fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563354e84b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563354b340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563354b33dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f51adb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51adb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51adb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563354b33cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c (2418 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b68823215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b68822f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b68823289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2061505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f206155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2061505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20614ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6881c7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b6881c7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b6881acb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b687e5c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b687e5bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f20614eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20614ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20614ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b687e5bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c (2419 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = all
# | ...
# `---data was truncated (10240/41587) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c4be1a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564c4be170f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564c4be1a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3f2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3f2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3f2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3f2a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c4bdafe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564c4bdafc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564c4bd94b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564c4ba440b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564c4ba43dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc3f2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3f2a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3f2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c4ba43cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c (2420 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_i64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_i64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_u64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_u64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64ff_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64ff_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/16424) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565243ff715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000565243ff40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000565243ff789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd141133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd14118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd141133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd14111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565243f8ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565243f8cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565243f71b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000565243c210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000565243c20dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd14111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd14111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd14111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565243c20cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c (2421 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca 
# | ...
# `---data was truncated (10240/14311) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1a36db15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d1a36d80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d1a36db89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ea3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ea378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ea3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ea371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1a3670e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d1a3670c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d1a3655b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d1a33050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d1a3304dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5ea371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ea371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ea371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1a3304cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c (2422 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c  -check-prefix=RV64ZKNE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64es(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64es(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64esm(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64esm(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64es(i64, i64) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64esm(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zkne" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zkne1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055996254115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055996253e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055996254189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb49f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb49f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb49f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb49f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599624d6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005599624d6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005599624bbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055996216b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055996216add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb49f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb49f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb49f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055996216acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c (2423 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_loca
# | ...
# `---data was truncated (10240/18587) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005637ba0c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005637ba0c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005637ba0c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f60d1905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60d195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f60d1905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60d18ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637ba05ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005637ba05ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005637ba03fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005637b9cef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005637b9ceedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f60d18eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60d18ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60d18ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005637b9ceecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c (2424 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vluxei16_v_f16mf4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vluxei16_v_f16mf2(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vluxei16_v_f16m1(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vluxei16_v_f16m2(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vluxei16_v_f16m4(ptr noundef %base, <vscale x 16 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vluxei16_v_f16m8(ptr noundef %base, <vscale x 32 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vluxei16_v_f32mf2(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vluxei16_v_f32m1(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vluxei16_v_f32m2(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vluxei16_v_f32m4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(<vscale x 8 x floa
# | ...
# `---data was truncated (10240/118156) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056002de7615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056002de730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056002de7689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf9b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf9b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf9b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf9b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056002de0be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056002de0bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056002ddf0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056002daa00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056002da9fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcf9b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf9b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf9b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056002da9fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c (2425 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, alig
# | ...
# `---data was truncated (10240/41669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573d939715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005573d93940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005573d939789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc632333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc63238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc632333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc63231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573d932ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005573d932cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005573d9311b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005573d8fc10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005573d8fc0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc63231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc63231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc63231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573d8fc0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c (2426 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_bf16mf4x7_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056278156315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005627815600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056278156389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d1c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d1c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d1c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d1c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627814f8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005627814f8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005627814ddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056278118d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056278118cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8d1c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d1c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d1c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056278118ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c (2427 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005621f24a515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005621f24a20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005621f24a589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6bf9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6bf998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6bf9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6bf991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005621f243ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005621f243ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005621f241fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005621f20cf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005621f20cedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6bf991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6bf991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6bf991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005621f20cecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c (2428 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e32_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e32_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noun
# | ...
# `---data was truncated (10240/17567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d5863815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563d586350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563d5863889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58b8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58b80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58b8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58b8031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d585cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563d585cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563d585b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563d582620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563d58261dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f58b8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58b80330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58b80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d58261cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c (2429 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16  -disable-O0-optnone  -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vceqzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oeq half %1, 0.000000e+00
# |   %vceqz = sext i1 %2 to i16
# |   store i16 %vceqz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oge half %1, 0.000000e+00
# |   %vcgez = sext i1 %2 to i16
# |   store i16 %vcgez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcgtzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ogt half %1, 0.000000e+00
# |   %vcgtz = sext i1 %2 to i16
# |   store i16 %vcgtz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vclezh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp ole half %1, 0.000000e+00
# |   %vclez = sext i1 %2 to i16
# |   store i16 %vclez, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcltzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp olt half %1, 0.000000e+00
# |   %vcltz = sext i1 %2 to i16
# |   store i16 %vcltz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = sitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = sitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_s64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = sitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u16(i16 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i16, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i16, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %__s0, align 2
# |   %1 = load i16, ptr %__s0, align 2
# |   %2 = uitofp i16 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i32, align 4
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %__s0, align 4
# |   %1 = load i32, ptr %__s0, align 4
# |   %2 = uitofp i32 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vcvth_f16_u64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca i64, align 8
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   store i64 %0, ptr %__s0, align 8
# |   %1 = load i64, ptr %__s0, align 8
# |   %2 = uitofp i64 %1 to half
# |   store half %2, ptr %ref.tmp, align 2
# |   %3 = load half, ptr %ref.tmp, align 2
# |   store half %3, ptr %__ret, align 2
# |   %4 = load half, ptr %__ret, align 2
# |   store half %4, ptr %tmp, align 2
# |   %5 = load half, ptr %tmp, align 2
# |   ret half %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vcvth_s16_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s16_f16 = call i16 @llvm.fptosi.sat.i16.f16(half %1)
# |   store i16 %vcvth_s16_f16, ptr %ref.tmp, align 2
# |   %2 = load i16, ptr %ref.tmp, align 2
# |   store i16 %2, ptr %__ret, align 2
# |   %3 = load i16, ptr %__ret, align 2
# |   store i16 %3, ptr %tmp, align 2
# |   %4 = load i16, ptr %tmp, align 2
# |   ret i16 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i16 @llvm.fptosi.sat.i16.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_vcvth_s32_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vcvth_s32_f16 = call i32 @llvm.fptosi.sat.i32.f16(half %1)
# |   store i32 %vcvth_s32_f16, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.fptosi.sat.i32.f16(half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_vcvth_s64_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, al
# | ...
# `---data was truncated (10240/28866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e2070715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560e207040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560e2070789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc858649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8586a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc858649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc858631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e2069ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560e2069cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560e20681b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560e203310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560e20330dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc858632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8586330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8586330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e20330cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c (2430 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c0b0dd315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c0b0dd00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c0b0dd389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f101d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f101d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f101d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f101d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c0b0d68e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c0b0d68c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c0b0d4db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c0b09fd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c0b09fcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f101d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f101d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f101d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c0b09fccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c (2431 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1(<vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2(<vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4(<vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8(<vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x double> @test_sf_vfexpa_v_f64m1_m(<vscale x 1 x i1> %vm, <vscale x 1 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x double> @test_sf_vfexpa_v_f64m2_m(<vscale x 2 x i1> %vm, <vscale x 2 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double> poison, <vscale x 2 x double> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x double> @test_sf_vfexpa_v_f64m4_m(<vscale x 4 x i1> %vm, <vscale x 4 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vfexpa_v_f64m8_m(<vscale x 8 x i1> %vm, <vscale x 8 x double> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double> poison, <vscale x 8 x double> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfvfexpa,+xsfvfexpa64e,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexpa0p2_xsfvfexpa64e0p2"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646b510615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005646b51030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005646b510689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8619a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8619a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8619a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8619a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646b509be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005646b509bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005646b5080b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005646b4d300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005646b4d2fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8619a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8619a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8619a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646b4d2fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c (2432 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %
# | ...
# `---data was truncated (10240/47698) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8f276b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d8f27680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d8f276b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce27533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce2758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce27533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce2751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8f2700e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d8f2700c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d8f26e5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d8f23950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d8f2394dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fce2751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce2751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce2751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8f2394cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c (2433 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cdf30d915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cdf30d60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cdf30d989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f415fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f415fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f415fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f415fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cdf306ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cdf306ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cdf3053b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cdf2d030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cdf2d02dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f415fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f415fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f415fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cdf2d02cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c (2434 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff6477615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ff647730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ff6477689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe3a9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3a9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe3a9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe3a9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff6470be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ff6470bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ff646f0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ff643a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ff6439fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe3a9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3a9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3a9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff6439fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c (2435 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/284344) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6308f115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d6308ee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d6308f189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7f181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7f18725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7f181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7f1803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d630886e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d630886c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d63086bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d63051b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d63051add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe7f1804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7f18050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7f18050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d63051acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c (2436 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredusum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredusum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/60342) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055921caea15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055921cae70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055921caea89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98bee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98beea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98bee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98bee31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055921ca7fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055921ca7fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055921ca64b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055921c7140b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055921c713dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f98bee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98bee330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98bee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055921c713cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c (2437 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmul_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmul_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmul_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmul_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmul_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscal
# | ...
# `---data was truncated (10240/29510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a13c53315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a13c5300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a13c53389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16f8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16f838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16f8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16f831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a13c4c8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a13c4c8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a13c4adb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a13c15d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a13c15cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f16f831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16f831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16f831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a13c15ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c (2438 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | d
# | ...
# `---data was truncated (10240/95223) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633b109415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005633b10910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005633b109489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f64d4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f64d4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f64d4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f64d4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633b1029e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005633b1029c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005633b100eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005633b0cbe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005633b0cbddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f64d4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f64d4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f64d4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633b0cbdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c (2439 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscal
# | ...
# `---data was truncated (10240/12235) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9287fa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d9287f70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d9287fa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f26fa505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26fa55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f26fa505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26fa4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d92878fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d92878fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d928774b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d9284240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d928423dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f26fa4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26fa4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26fa4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d928423cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c (2440 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b18aa015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558b18a9d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558b18aa089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feebb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feebb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feebb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feebb831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b18a35e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558b18a35c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558b18a1ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558b186ca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558b186c9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feebb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feebb8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feebb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b186c9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c (2441 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 
# | ...
# `---data was truncated (10240/126436) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b70ff915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556b70ff60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556b70ff989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8e3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8e32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8e3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8e3231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b70f8ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556b70f8ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556b70f73b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556b70c230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556b70c22dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe8e3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8e32330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8e32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b70c22cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c (2442 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4e
# | ...
# `---data was truncated (10240/228857) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ecb03415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556ecb0310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556ecb03489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f10a5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10a5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f10a5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10a5c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ecafc9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556ecafc9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556ecafaeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556ecac5e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556ecac5ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f10a5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10a5c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10a5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ecac5dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c (2443 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsra_wx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsra_wx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsra_wx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsra_wx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %shift.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsra_wv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vsca
# | ...
# `---data was truncated (10240/154601) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c3598615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560c359830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560c3598689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb54fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb54fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb54fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb54fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c3591be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560c3591bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560c35900b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560c355b00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560c355afdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb54fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb54fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb54fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c355afcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c (2444 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsub_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsub_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsub_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsub_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsub_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsub_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsub_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsub_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsub_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsub_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x 
# | ...
# `---data was truncated (10240/61066) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056127e6d715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056127e6d40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056127e6d789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38da305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38da35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38da305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38da2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056127e66ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056127e66cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056127e651b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056127e3010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056127e300dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f38da2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38da2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38da2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056127e300cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c (2445 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_u8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3ddfb515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e3ddfb20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e3ddfb589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ea1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ea1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ea1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ea1c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3ddf4ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e3ddf4ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e3ddf2fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e3ddbdf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e3ddbdedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0ea1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ea1c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ea1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3ddbdecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c (2446 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593f28d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005593f28d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005593f28d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb20f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb20f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb20f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb20f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593f2869e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005593f2869c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005593f284eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005593f24fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005593f24fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feb20f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb20f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb20f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593f24fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c (2447 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) 
# | ...
# `---data was truncated (10240/25094) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557be498115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557be497e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557be498189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f890c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f890c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f890c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f890c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557be4916e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557be4916c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557be48fbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557be45ab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557be45aadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f890c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f890c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f890c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557be45aacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/packed-structure.c (2448 of 27911)
******************** TEST 'Clang :: CodeGen/packed-structure.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64"
# | 
# | %struct.s0 = type { i32, i32 }
# | %struct.s1 = type { i32, i32 }
# | %struct.s2 = type { i32, i32 }
# | %struct.s3 = type <{ i16, i32, [10 x i8] }>
# | 
# | @s0_align_x = global i32 4, align 4
# | @s0_align_y = global i32 1, align 4
# | @s0_align = global i32 4, align 4
# | @s1_align_x = global i32 1, align 4
# | @s1_align_y = global i32 1, align 4
# | @s1_align = global i32 1, align 4
# | @s2_align_x = global i32 2, align 4
# | @s2_align_y = global i32 2, align 4
# | @s2_align = global i32 2, align 4
# | @s3_1 = global i32 1, align 4
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s0_load_x(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %x = getelementptr inbounds nuw %struct.s0, ptr %0, i32 0, i32 0
# |   %1 = load i32, ptr %x, align 4
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s0_load_y(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %y = getelementptr inbounds nuw %struct.s0, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %y, align 4
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @s0_copy(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %0, ptr align 4 %1, i64 8, i1 false)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
# | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s1_load_x(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %x = getelementptr inbounds nuw %struct.s1, ptr %0, i32 0, i32 0
# |   %1 = load i32, ptr %x, align 1
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s1_load_y(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %y = getelementptr inbounds nuw %struct.s1, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %y, align 1
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @s1_copy(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 1 %0, ptr align 1 %1, i64 8, i1 false)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s2_load_x(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %x = getelementptr inbounds nuw %struct.s2, ptr %0, i32 0, i32 0
# |   %1 = load i32, ptr %x, align 2
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @s2_load_y(ptr noundef %a) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   %0 = load ptr, ptr %a.addr, align 8
# |   %y = getelementptr inbounds nuw %struct.s2, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %y, align 2
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @s2_copy(ptr noundef %a, ptr noundef %b) #0 {
# | entry:
# |   %a.addr = alloca ptr, align 8
# |   %b.addr = alloca ptr, align 8
# |   store ptr %a, ptr %a.addr, align 8
# |   store ptr %b, ptr %b.addr, align 8
# |   %0 = load ptr, ptr %b.addr, align 8
# |   %1 = load ptr, ptr %a.addr, align 8
# |   call void @llvm.memcpy.p0.p0.i64(ptr align 2 %0, ptr align 2 %1, i64 8, i1 false)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @test3(ptr noundef %ptr) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %anInt = getelementptr inbounds nuw %struct.s3, ptr %0, i32 0, i32 1
# |   %1 = load i32, ptr %anInt, align 2
# |   ret i32 %1
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp
# |  #0 0x000055a71194f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a71194c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a71194f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce74d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce74d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce74d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce74d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7118e4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a7118e4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a7118c9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a7115790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a711578dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fce74d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce74d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce74d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a711578cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c (2449 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x float> @llvm.riscv.vle.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x float> @llvm.riscv.vle.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x float> @llvm.riscv.vle.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32_v_f32m4_tu(<vscale x 8 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x float> @llvm.riscv.vle.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32_v_f32m8_tu(<vscale x 16 x float> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_i32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32_v_i32m1_tu(<vscale x 2 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32_v_i32m2_tu(<vscale x 4 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32_v_i32m4_tu(<vscale x 8 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32_v_i32m8_tu(<vscale x 16 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, 
# | ...
# `---data was truncated (10240/60217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555698f3b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555698f380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555698f3b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5df6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5df6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5df6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5df6e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555698ed0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555698ed0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555698eb5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555698b650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555698b64dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5df6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5df6e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5df6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555698b64cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c (2450 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607349aa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005607349a70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005607349aa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4058733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f405878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4058733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f405871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056073493fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056073493fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560734924b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005607345d40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005607345d3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f405871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f405871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f405871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607345d3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vabdq.c (2451 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vabdq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabdq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabdq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabdq_f32(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = call <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half> %0, <8 x half> %1, i32 0)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half>, <8 x half>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabdq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabdq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vabdq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabdq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabdq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabdq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626a5a7c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005626a5a790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005626a5a7c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdbdff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdbdff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdbdff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdbdff1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005626a5a11e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005626a5a11c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005626a59f6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005626a56a60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005626a56a5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdbdff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdbdff1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdbdff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626a56a5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c (2452 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563071fd615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563071fd30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563071fd689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1434249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14342a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1434249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1434231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563071f6be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563071f6bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563071f50b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563071c000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563071bffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1434232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14342330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14342330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563071bffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c (2453 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tum(<vscale x 1 x i1> %mas
# | ...
# `---data was truncated (10240/43111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056127244d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056127244a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056127244d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20bcd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20bcd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20bcd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20bcd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005612723e2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005612723e2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005612723c7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005612720770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561272076dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f20bcd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20bcd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20bcd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561272076cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c (2454 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8(<vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vx_u8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vdivu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vdivu_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr
# | ...
# `---data was truncated (10240/97905) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056104549615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005610454930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056104549689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a7ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a7cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a7ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a7ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056104542be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056104542bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561045410b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005610450c00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005610450bfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0a7ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a7ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a7ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610450bfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c (2455 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ed324c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558ed32490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558ed324c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f704401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70440725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f704401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7044003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ed31e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558ed31e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558ed31c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558ed2e760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558ed2e75dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7044004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70440050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70440050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ed2e75cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c (2456 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.bf16.nxv8bf16.i6
# | ...
# `---data was truncated (10240/51694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563fa778415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563fa77810f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563fa778489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4562e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4562ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4562e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4562e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563fa7719e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563fa7719c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563fa76feb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563fa73ae0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563fa73addd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4562e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4562e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4562e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563fa73adcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/linker-diagnostic.ll (2457 of 27911)
******************** TEST 'Clang :: CodeGen/linker-diagnostic.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 2
mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp
# executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll
# |  #0 0x00005596eed0715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005596eed040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005596eed0789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c1ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c1ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c1ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c1ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596eec9ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005596eec9cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005596eec81b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005596ee9310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005596ee930dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2c1ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c1ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c1ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596ee930cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c (2458 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056254f39915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056254f3960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056254f39989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0687705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f068775c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0687705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06876ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056254f32ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056254f32ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056254f313b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056254efc30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056254efc2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f06876eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06876ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06876ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056254efc2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c (2459 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/108848) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558749a2d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558749a2a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558749a2d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6502b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6502b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6502b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6502b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587499c2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005587499c2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005587499a7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005587496570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558749656dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6502b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6502b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6502b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558749656cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c (2460 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscal
# | ...
# `---data was truncated (10240/13282) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564b0f65515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564b0f6520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564b0f65589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae1fb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae1fb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae1fb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae1faed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564b0f5eae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564b0f5eac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564b0f5cfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564b0f27f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564b0f27edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fae1faeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae1faef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae1faef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564b0f27ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c (2461 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_tum(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_tumu(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64>
# | ...
# `---data was truncated (10240/18217) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005613c216415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005613c21610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005613c216489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1ee933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1ee98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1ee933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1ee91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005613c20f9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005613c20f9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005613c20deb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005613c1d8e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005613c1d8ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb1ee91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1ee91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1ee91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005613c1d8dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c (2462 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @
# | ...
# `---data was truncated (10240/23479) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592c2fce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005592c2fcb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005592c2fce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f382f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f382f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f382f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f382f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005592c2f63e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005592c2f63c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005592c2f48b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005592c2bf80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005592c2bf7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f382f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f382f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f382f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005592c2bf7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c (2463 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056349ec8c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056349ec890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056349ec8c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0da449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0da4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0da449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0da431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056349ec21e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056349ec21c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056349ec06b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056349e8b60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056349e8b5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa0da432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0da4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0da4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056349e8b5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c (2464 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7e2fa415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f7e2fa10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f7e2fa489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b55d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b55d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b55d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b55d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7e2f39e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f7e2f39c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f7e2f1eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f7e2bce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f7e2bcddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0b55d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b55d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b55d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7e2bcdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c (2465 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0f256515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f0f25620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f0f256589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8753e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8753e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8753e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8753e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0f24fae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f0f24fac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f0f24dfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f0f218f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f0f218edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8753e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8753e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8753e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0f218ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll (2466 of 27911)
******************** TEST 'Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
# |  #0 0x000055e29f65c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e29f6590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e29f65c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fe2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fe22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fe2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fe2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e29f5f1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e29f5f1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e29f5d6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e29f2860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e29f285dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0fe2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fe22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fe22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e29f285cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c (2467 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple",
# | ...
# `---data was truncated (10240/80648) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630e448e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005630e448b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005630e448e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7484533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f748458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7484533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f748451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630e4423e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005630e4423c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005630e4408b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005630e40b80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005630e40b7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f748451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f748451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f748451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630e40b7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c (2468 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, 
# | ...
# `---data was truncated (10240/20307) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561c7c60615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561c7c6030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561c7c60689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2bed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2bed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2bed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2bed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561c7c59be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561c7c59bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561c7c580b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561c7c2300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561c7c22fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff2bed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2bed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2bed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561c7c22fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vadc.c (2469 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vadc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadciq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   %4 = lshr i32 %3, 29
# |   %5 = and i32 1, %4
# |   %6 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %5, ptr %6, align 4
# |   %7 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadcq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load ptr, ptr %carry.addr, align 4
# |   %3 = load i32, ptr %2, align 4
# |   %4 = shl i32 %3, 29
# |   %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4)
# |   %6 = extractvalue { <4 x i32>, i32 } %5, 1
# |   %7 = lshr i32 %6, 29
# |   %8 = and i32 1, %7
# |   store i32 %8, ptr %2, align 4
# |   %9 = extractvalue { <4 x i32>, i32 } %5, 0
# |   ret <4 x i32> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadciq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, <4 x i1> %5)
# |   %7 = extractvalue { <4 x i32>, i32 } %6, 1
# |   %8 = lshr i32 %7, 29
# |   %9 = and i32 1, %8
# |   %10 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %9, ptr %10, align 4
# |   %11 = extractvalue { <4 x i32>, i32 } %6, 0
# |   ret <4 x i32> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i32>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadcq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = load ptr, ptr %carry.addr, align 4
# |   %4 = load i32, ptr %3, align 4
# |   %5 = shl i32 %4, 29
# |   %6 = load i16, ptr %p.addr, align 2
# |   %7 = zext i16 %6 to i32
# |   %8 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %7)
# |   %9 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 %5, <4 x i1> %8)
# |   %10 = extractvalue { <4 x i32>, i32 } %9, 1
# |   %11 = lshr i32 %10, 29
# |   %12 = and i32 1, %11
# |   store i32 %12, ptr %3, align 4
# |   %13 = extractvalue { <4 x i32>, i32 } %9, 0
# |   ret <4 x i32> %13
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 536870912)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   %4 = lshr i32 %3, 29
# |   %5 = and i32 1, %4
# |   %6 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %5, ptr %6, align 4
# |   %7 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 536870912)
# |   %3 = extractvalue { <4 x i32>, i32 } %2, 1
# |   %4 = lshr i32 %3, 29
# |   %5 = and i32 1, %4
# |   %6 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %5, ptr %6, align 4
# |   %7 = extractvalue { <4 x i32>, i32 } %2, 0
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbcq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load ptr, ptr %carry.addr, align 4
# |   %3 = load i32, ptr %2, align 4
# |   %4 = shl i32 %3, 29
# |   %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4)
# |   %6 = extractvalue { <4 x i32>, i32 } %5, 1
# |   %7 = lshr i32 %6, 29
# |   %8 = and i32 1, %7
# |   store i32 %8, ptr %2, align 4
# |   %9 = extractvalue { <4 x i32>, i32 } %5, 0
# |   ret <4 x i32> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbcq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry.addr = alloca ptr, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry, ptr %carry.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load ptr, ptr %carry.addr, align 4
# |   %3 = load i32, ptr %2, align 4
# |   %4 = shl i32 %3, 29
# |   %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4)
# |   %6 = extractvalue { <4 x i32>, i32 } %5, 1
# |   %7 = lshr i32 %6, 29
# |   %8 = and i32 1, %7
# |   store i32 %8, ptr %2, align 4
# |   %9 = extractvalue { <4 x i32>, i32 } %5, 0
# |   ret <4 x i32> %9
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %carry_out.addr = alloca ptr, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store ptr %carry_out, ptr %carry_out.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x i32>, ptr %a.addr, align 8
# |   %2 = load <4 x i32>, ptr %b.addr, align 8
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 536870912, <4 x i1> %5)
# |   %7 = extractvalue { <4 x i32>, i32 } %6, 1
# |   %8 = lshr i32 %7, 29
# |   %9 = and i32 1, %8
# |   %10 = load ptr, ptr %carry_out.addr, align 4
# |   store i32 %9, ptr %10, align 4
# |   %11 = extractvalue { <4 x i32>, i32 } %6, 0
# |   ret <4 x i32> %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32>,
# | ...
# `---data was truncated (10240/14775) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557fbbf9415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557fbbf910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557fbbf9489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3082733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f308278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3082733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f308271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fbbf29e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557fbbf29c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557fbbf0eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557fbbbbe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557fbbbbddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f308271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f308271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f308271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fbbbbdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c (2470 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %
# | ...
# `---data was truncated (10240/29210) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb7c12e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eb7c12b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eb7c12e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5a1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5a1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5a1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5a1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb7c0c3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eb7c0c3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eb7c0a8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eb7bd580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eb7bd57dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe5a1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5a1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5a1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb7bd57cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c (2471 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16mf2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m1(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m2(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m4(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m8(<vscale x 1 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat>, <vscale x 1 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m1(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m2(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m4(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m8(<vscale x 2 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat>, <vscale x 2 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m2(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m4(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m8(<vscale x 4 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m4(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %value, ptr %value.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %value.addr, align 2
# |   %1 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m8(<vscale x 8 x bfloat> %value) #0 {
# | entry:
# |   %value.addr = alloca
# | ...
# `---data was truncated (10240/12137) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d3dbbdc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d3dbbd90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d3dbbdc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb57d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb57d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb57d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb57d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3dbb71e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d3dbb71c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d3dbb56b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d3db8060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d3db805dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb57d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb57d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb57d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3db805cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c (2472 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de801a015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055de8019d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055de801a089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc2c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc2c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc2c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc2c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de80135e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055de80135c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055de8011ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055de7fdca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055de7fdc9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efc2c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc2c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc2c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de7fdc9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c (2473 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsc
# | ...
# `---data was truncated (10240/11789) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb956db15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eb956d80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eb956db89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f104e81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f104e8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f104e81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f104e803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb95670e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eb95670c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eb95655b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eb953050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eb95304dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f104e804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f104e8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f104e8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb95304cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c (2474 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfge
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650bf7fe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005650bf7fb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005650bf7fe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f331a21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f331a2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f331a21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f331a203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650bf793e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005650bf793c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005650bf778b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005650bf4280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005650bf427dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f331a204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f331a2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f331a2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650bf427cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c (2475 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d556aec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d556ae90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d556aec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7aa4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7aa48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7aa4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7aa4831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d556a81e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d556a81c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d556a66b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d5567160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d556715dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7aa4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7aa48330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7aa48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d556715cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c (2476 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561f9fe7815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561f9fe750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561f9fe7889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe338449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3384a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe338449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe338431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561f9fe0de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561f9fe0dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561f9fdf2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561f9faa20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561f9faa1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe338432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3384330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3384330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561f9faa1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c (2477 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vv_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmin_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vv_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmin_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vv_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmin_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vv_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmin_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmin_vv_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, <vscale x 16 x half> 
# | ...
# `---data was truncated (10240/157173) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b73a10d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b73a10a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b73a10d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ff5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ff5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ff5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ff5a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b73a0a2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b73a0a2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b73a087b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b739d370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b739d36dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8ff5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ff5a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ff5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b739d36cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c (2478 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1up_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1up_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1up_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1up_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1up_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1up_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1up_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1up_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1up_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1up_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,
# | ...
# `---data was truncated (10240/34589) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556390c0a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556390c070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556390c0a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f15f0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f15f06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f15f0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f15f0631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556390b9fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556390b9fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556390b84b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005563908340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556390833dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f15f0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f15f06330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f15f06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556390833cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c (2479 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_u8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.
# | ...
# `---data was truncated (10240/13557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3a724c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e3a72490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e3a724c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce53733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce5378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce53733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce5371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3a71e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e3a71e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e3a71c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e3a6e760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e3a6e75dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fce5371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce5371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce5371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3a6e75cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c (2480 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005567169fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005567169fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005567169fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f082a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f082a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f082a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f082a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556716992e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556716992c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556716977b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005567166270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556716626dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f082a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f082a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f082a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556716626cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c (2481 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m1x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f16m2x2(ptr noundef %base, <vscale x 8 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m1x2(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m2x2(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg2ei64_v_f32m4x2(ptr noundef %base, <vscale x 8 x i64
# | ...
# `---data was truncated (10240/110129) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607e0e7015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005607e0e6d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005607e0e7089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f80505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f8055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f80505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f804ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607e0e05e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005607e0e05c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005607e0deab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005607e0a9a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005607e0a99dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0f804eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f804ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f804ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607e0a99cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c (2482 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3d435215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e3d434f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e3d435289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f33fd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f33fd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f33fd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f33fd31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3d42e7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e3d42e7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e3d42ccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e3d3f7c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e3d3f7bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f33fd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f33fd31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f33fd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3d3f7bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c (2483 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a16172915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a1617260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a16172989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76c0b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76c0b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76c0b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76c0aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1616bee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a1616bec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a1616a3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a1613530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a161352dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f76c0aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76c0aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76c0aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a161352cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c (2484 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwin
# | ...
# `---data was truncated (10240/10798) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558ccb61415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558ccb6110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558ccb61489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4dc041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4dc04725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4dc041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4dc0403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558ccb5a9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558ccb5a9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558ccb58eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558ccb23e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558ccb23ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4dc0404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4dc04050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4dc04050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558ccb23dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c (2485 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 0, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 immarg, i64 immarg, i64 immarg, i64, i64 immarg, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 1, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 2, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_x_se_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 3, i64 %1)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_x_se_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_x_se_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_x_se_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_x_se_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_x_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_x_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_x_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_x_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvcp,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nounwind }
# | attributes #2 = { nounwind memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvcp1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557987cb115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557987cae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557987cb189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe45049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe450a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe45049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe45031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557987c46e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557987c46c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557987c2bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005579878db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005579878dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbe45032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe450330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe450330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005579878dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c (2486 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree no
# | ...
# `---data was truncated (10240/13023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2e504e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e2e504b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e2e504e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9aea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9aeaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9aea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9aea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e2e4fe3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e2e4fe3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e2e4fc8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e2e4c780b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e2e4c77dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa9aea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9aea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9aea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e2e4c77cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c (2487 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvpackfph -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(<vscale x 2 x half>, <vscale x 2 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_nds_vfpmadt_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(<vscale x 4 x half>, <vscale x 4 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_nds_vfpmadt_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(<vscale x 8 x half>, <vscale x 8 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_nds_vfpmadt_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(<vscale x 16 x half>, <vscale x 16 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_nds_vfpmadt_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(<vscale x 32 x half>, <vscale x 32 x half>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_nds_vfpmadt_vf_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(<vscale x 1 x half>, <vscale x 1 x half>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_nds_vfpmadt_vf_f16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load float, ptr %op2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, float %3, <vscale x 2 
# | ...
# `---data was truncated (10240/59595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558eca6b415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558eca6b10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558eca6b489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2e1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2e14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2e1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2e1431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558eca649e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558eca649c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558eca62eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558eca2de0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558eca2dddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb2e1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2e14330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2e14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558eca2ddcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c (2488 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmax_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmax_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmax_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmax_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmax_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmax.
# | ...
# `---data was truncated (10240/69313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605690f615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005605690f30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005605690f689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc00733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc0078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc00733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc0071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056056908be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056056908bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560569070b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560568d200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560568d1fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdc0071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc0071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc0071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560568d1fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c (2489 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce803f115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ce803ee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ce803f189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fddeb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fddeb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fddeb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fddeb831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce80386e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ce80386c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ce8036bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ce8001b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ce8001add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fddeb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fddeb8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fddeb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce8001acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c (2490 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32ff_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32ff_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056477314015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056477313d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056477314089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f81b2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f81b278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f81b2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f81b271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005647730d5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005647730d5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005647730bab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564772d6a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564772d69dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f81b271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f81b271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f81b271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564772d69cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c (2491 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredsum_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredsum_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/94379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e83c3f915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e83c3f60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e83c3f989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6539b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6539b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6539b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6539aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e83c38ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e83c38ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e83c373b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e83c0230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e83c022dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6539aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6539aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6539aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e83c022cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c (2492 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x 
# | ...
# `---data was truncated (10240/59787) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5a53f315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c5a53f00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c5a53f389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f239b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f239b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f239b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f239b31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5a5388e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c5a5388c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c5a536db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c5a501d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c5a501cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f239b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f239b31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f239b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5a501ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c (2493 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e385c015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555e385bd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555e385c089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f83b4305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f83b435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f83b4305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83b42ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e38555e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555e38555c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555e3853ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555e381ea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555e381e9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f83b42eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83b42ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83b42ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e381e9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c (2494 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601b6e2e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005601b6e2b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005601b6e2e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec93d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec93d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec93d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec93d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601b6dc3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005601b6dc3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005601b6da8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005601b6a580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005601b6a57dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fec93d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec93d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec93d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601b6a57cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c (2495 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsge_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsge_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsge_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsge_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055593d8a815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055593d8a50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055593d8a889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b4481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b448725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b4481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b44803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055593d83de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055593d83dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055593d822b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055593d4d20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055593d4d1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6b44804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b448050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b448050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055593d4d1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c (2496 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vssra_vx_i8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vssra_vx_i8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vssra.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vssra_vx_i8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vssra.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vssra_vx_i8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vssra.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vssra_vx_i8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vssra.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg, i64) #1
# | 
# | ; 
# | ...
# `---data was truncated (10240/100289) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d5626d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558d5626a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558d5626d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45ee249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45ee2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45ee249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45ee231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d56202e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558d56202c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558d561e7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558d55e970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558d55e96dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f45ee232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45ee2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45ee2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d55e96cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c (2497 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560334d6815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560334d650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560334d6889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34fe049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34fe0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34fe049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34fe031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560334cfde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560334cfdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560334ce2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005603349920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560334991dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f34fe032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34fe0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34fe0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560334991cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c (2498 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vsrl_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>
# | ...
# `---data was truncated (10240/98343) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561fa3ac315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561fa3ac00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561fa3ac389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdc4d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdc4d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdc4d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdc4d91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561fa3a58e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561fa3a58c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561fa3a3db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561fa36ed0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561fa36ecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdc4d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdc4d91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdc4d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561fa36eccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c (2499 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat>
# | ...
# `---data was truncated (10240/53686) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055738b8d315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055738b8d00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055738b8d389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee00649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee006a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee00649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee00631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055738b868e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055738b868c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055738b84db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055738b4fd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055738b4fcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fee00632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee006330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee006330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055738b4fccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c (2500 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055734f4c115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055734f4be0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055734f4c189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fc2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fc258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fc2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fc251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055734f456e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055734f456c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055734f43bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055734f0eb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055734f0eadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4fc251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fc251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fc251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055734f0eacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c (2501 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cd9396915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cd939660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cd9396989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa96aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa96aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa96aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa96aa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cd938fee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cd938fec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cd938e3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cd935930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cd93592dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa96aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa96aa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa96aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cd93592cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c (2502 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %ma
# | ...
# `---data was truncated (10240/18353) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e9f276515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e9f27620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e9f276589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4cbcb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4cbcb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4cbcb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4cbcb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e9f26fae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e9f26fac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e9f26dfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e9f238f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e9f238edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4cbcb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4cbcb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4cbcb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9f238ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c (2503 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056087149915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005608714960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056087149989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c40933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c4098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c40933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c4091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056087142ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056087142ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560871413b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005608710c30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005608710c2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3c4091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c4091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c4091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005608710c2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c (2504 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6364e815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c6364e50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c6364e889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f442db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f442db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f442db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f442db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c63647de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c63647dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c636462b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c6361120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c636111dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f442db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f442db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f442db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c636111cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c (2505 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589817c015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005589817bd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005589817c089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8cecc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8cecca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8cecc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8cecc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558981755e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558981755c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055898173ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005589813ea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005589813e9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8cecc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8cecc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8cecc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589813e9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c (2506 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650ca9e515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005650ca9e20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005650ca9e589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd74933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd7498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd74933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd7491b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650ca97ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005650ca97ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005650ca95fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005650ca60f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005650ca60edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdd7491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd7491d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd7491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650ca60ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c (2507 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556abcd3815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556abcd350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556abcd3889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2715c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2715ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2715c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2715c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556abcccde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556abcccdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556abccb2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556abc9620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556abc961dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2715c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2715c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2715c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556abc961cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c (2508 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i
# | ...
# `---data was truncated (10240/41934) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e022c615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559e022c30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559e022c689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcff5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcff558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcff5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcff551b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e0225be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559e0225bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559e02240b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559e01ef00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559e01eefdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcff551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcff551d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcff551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e01eefcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c (2509 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005597c844915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005597c84460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005597c844989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc8b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc8b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc8b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc8b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005597c83dee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005597c83dec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005597c83c3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005597c80730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005597c8072dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efc8b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc8b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc8b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597c8072cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c (2510 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7c6f3615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f7c6f330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f7c6f3689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a42049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a420a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a42049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a42031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7c6ecbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f7c6ecbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f7c6eb0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f7c6b600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f7c6b5fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0a42032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a420330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a420330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7c6b5fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcvt.c (2511 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_f16_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = sitofp <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_f16_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = uitofp <8 x i16> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_f32_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = sitofp <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_f32_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = uitofp <4 x i32> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_s16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = fptosi <8 x half> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_s32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = fptosi <4 x float> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_u16_f16(<8 x half> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = fptoui <8 x half> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_u32_f32(<4 x float> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = fptoui <4 x float> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_s16(<8 x half> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %0, i32 0, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_u16(<8 x half> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x half>, ptr %inactive.addr, align 8
# |   %5 = call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %0, i32 1, <8 x i1> %3, <8 x half> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_s32(<4 x float> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %3, <4 x float> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32>, i32, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_u32(<4 x float> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x float>, ptr %inactive.addr, align 8
# |   %5 = call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 1, <4 x i1> %3, <4 x float> %4)
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_s16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %0, i32 0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_s32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float> %0, i32 0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_u16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %0, i32 1, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_u32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm
# | ...
# `---data was truncated (10240/37578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b69a60415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b69a6010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b69a60489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f375e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f375e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f375e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f375e91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b69a599e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b69a599c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b69a57eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b69a22e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b69a22ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f375e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f375e91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f375e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b69a22dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c (2512 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.mask.nxv1f32.i64.p0(<vscale x 1 x float> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.mask.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.mask.nxv2f32.i64.p0(<vscale x 2 x float> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.mask.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.mask.nxv4f32.i64.p0(<vscale x 4 x float> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.mask.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.mask.nxv8f32.i64.p0(<vscale x 8 x float> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.mask.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.mask.nxv16f32.i64.p0(<vscale x 16 x float> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x float>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.mask.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0(<vscale x 1 x i32> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0(<vscale x 2 x i32> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x i32>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.mask.nxv4i32.i64.p0(<vscale x 4 x i32> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   
# | ...
# `---data was truncated (10240/19123) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d3d2cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556d3d2c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556d3d2cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb652e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb652ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb652e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb652e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d3d260e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556d3d260c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556d3d245b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556d3cef50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556d3cef4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb652e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb652e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb652e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d3cef4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c (2513 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f46d4c415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f46d4c10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f46d4c489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20a0e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20a0e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20a0e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20a0e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f46d459e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f46d459c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f46d43eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f46d0ee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f46d0eddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f20a0e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20a0e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20a0e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f46d0edcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c (2514 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055640b0a615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055640b0a30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055640b0a689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f3b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f3b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f3b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f3b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055640b03be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055640b03bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055640b020b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055640acd00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055640accfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1f3b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f3b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f3b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055640accfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c (2515 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nx
# | ...
# `---data was truncated (10240/25567) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b1877fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b1877f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b1877fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78be849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78be8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78be849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78be831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b187791e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b187791c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b187776b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b1874260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b187425dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f78be832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78be8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78be8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b187425cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c (2516 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vx_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vx_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vx_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vx_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vx_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/25086) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593a327215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005593a326f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005593a327289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd499849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4998a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd499849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd499831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593a3207e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005593a3207c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005593a31ecb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005593a2e9c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005593a2e9bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd499832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4998330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4998330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593a2e9bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c (2517 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/22107) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9c8b0f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c9c8b0c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c9c8b0f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb2ad849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2ad8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb2ad849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb2ad831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9c8aa4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c9c8aa4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c9c8a89b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c9c87390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c9c8738dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb2ad832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2ad8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2ad8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9c8738cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c (2518 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# | ...
# `---data was truncated (10240/30866) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f82ca115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559f82c9e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559f82ca189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee40449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee404a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee40449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee40431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f82c36e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559f82c36c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559f82c1bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559f828cb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559f828cadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fee40432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee404330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee404330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f828cacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c (2519 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c  -check-prefix=RV32ZKND
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32dsi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32dsi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32dsi(i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32dsmi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32dsmi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32dsmi(i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zknd" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zknd1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b63620115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b6361fe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b63620189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f31e3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31e3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f31e3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f31e3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b636196e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b636196c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b63617bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b635e2b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b635e2add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f31e3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31e3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31e3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b635e2acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c (2520 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568b700d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005568b700a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005568b700d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f440d105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f440d15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f440d105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f440d0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568b6fa2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005568b6fa2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005568b6f87b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005568b6c370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005568b6c36dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f440d0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f440d0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f440d0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568b6c36cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c (2521 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f62786f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f62786c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f62786f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5933733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f593378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5933733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f593371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f627804e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f627804c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f6277e9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f6274990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f627498dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f593371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f593371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f593371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f627498cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c (2522 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055872b46615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055872b4630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055872b46689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0dd9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0dd9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0dd9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0dd9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055872b3fbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055872b3fbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055872b3e0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055872b0900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055872b08fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0dd9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0dd9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0dd9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055872b08fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c (2523 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.t
# | ...
# `---data was truncated (10240/12089) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f73e0d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559f73e0a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559f73e0d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f91a3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f91a3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f91a3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f91a3d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f73da2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559f73da2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559f73d87b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559f73a370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559f73a36dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f91a3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f91a3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f91a3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f73a36cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c (2524 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Funct
# | ...
# `---data was truncated (10240/64950) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055955207915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005595520760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055955207989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32efc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32efc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32efc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32efc03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055955200ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055955200ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559551ff3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559551ca30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559551ca2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f32efc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32efc050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32efc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559551ca2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c (2525 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>
# | ...
# `---data was truncated (10240/63169) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d428ef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555d428ec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555d428ef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa476a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa476aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa476a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa476a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d42884e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555d42884c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555d42869b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555d425190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555d42518dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa476a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa476a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa476a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d42518cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c (2526 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractval
# | ...
# `---data was truncated (10240/13669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9767a215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f97679f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f9767a289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06bc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06bc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06bc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06bc631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f976737e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f976737c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f97671cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f9763cc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f9763cbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f06bc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06bc6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06bc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9763cbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c (2527 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8_v_u8m2x4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8_v_i8mf8x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8_v_i8mf4x4_m(<vscale x 2 x i1> %mask, ptr noundef %bas
# | ...
# `---data was truncated (10240/20340) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b9ad1415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562b9ad110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562b9ad1489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b81f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b81f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b81f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b81f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b9aca9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562b9aca9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562b9ac8eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562b9a93e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562b9a93ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8b81f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b81f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b81f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b9a93dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c (2528 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563abc5215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005563abc4f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005563abc5289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe08f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe08f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe08f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe08f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563abbe7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005563abbe7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005563abbccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005563ab87c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005563ab87bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe08f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe08f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe08f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563ab87bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c (2529 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556825eb515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556825eb20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556825eb589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f760f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f760f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f760f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f760f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556825e4ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556825e4ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556825e2fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556825adf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556825adedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f760f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f760f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f760f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556825adecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c (2530 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 2, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 2, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: 
# | ...
# `---data was truncated (10240/12431) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633598ca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005633598c70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005633598ca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa535249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5352a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa535249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa535231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056335985fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056335985fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563359844b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005633594f40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005633594f3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa535232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5352330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5352330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633594f3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c (2531 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cb8dc515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557cb8dc20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557cb8dc589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff49c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff49c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff49c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff49c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cb8d5ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557cb8d5ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557cb8d3fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557cb89ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557cb89eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff49c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff49c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff49c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cb89eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/WebAssembly/builtins-table-externref.c (2532 of 27911)
******************** TEST 'Clang :: CodeGen/WebAssembly/builtins-table-externref.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c"
# | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"
# | target triple = "wasm32"
# | 
# | @table = internal addrspace(1) global [0 x target("wasm.externref")] zeroinitializer, align 1
# | @const_table = internal addrspace(1) constant [0 x target("wasm.externref")] zeroinitializer, align 1
# | @other_table = internal addrspace(1) global [0 x target("wasm.externref")] zeroinitializer, align 1
# | 
# | ; Function Attrs: noinline nounwind
# | define target("wasm.externref") @test_builtin_wasm_table_get(i32 noundef %index) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = call target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1) @table, i32 %0)
# |   ret target("wasm.externref") %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1), i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define target("wasm.externref") @test_builtin_wasm_table_get_const(i32 noundef %index) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = call target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1) @table, i32 %0)
# |   ret target("wasm.externref") %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_set(i32 noundef %index, target("wasm.externref") %ref) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @const_table, i32 %0, target("wasm.externref") %1)
# |   %2 = load i32, ptr %index.addr, align 4
# |   %3 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @table, i32 %2, target("wasm.externref") %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.wasm.table.set.externref(ptr addrspace(1), i32, target("wasm.externref")) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_set_const(i32 noundef %index, target("wasm.externref") %ref) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @table, i32 %0, target("wasm.externref") %1)
# |   %2 = load i32, ptr %index.addr, align 4
# |   %3 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   call void @llvm.wasm.table.set.externref(ptr addrspace(1) @const_table, i32 %2, target("wasm.externref") %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_size() #0 {
# | entry:
# |   %0 = call i32 @llvm.wasm.table.size(ptr addrspace(1) @table)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare i32 @llvm.wasm.table.size(ptr addrspace(1)) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define i32 @test_builtin_wasm_table_grow(target("wasm.externref") %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   %nelem.addr = alloca i32, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   %1 = load i32, ptr %nelem.addr, align 4
# |   %2 = call i32 @llvm.wasm.table.grow.externref(ptr addrspace(1) @table, target("wasm.externref") %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare i32 @llvm.wasm.table.grow.externref(ptr addrspace(1), target("wasm.externref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_builtin_wasm_table_fill(i32 noundef %index, target("wasm.externref") %ref, i32 noundef %nelem) #0 {
# | entry:
# |   %index.addr = alloca i32, align 4
# |   %ref.addr = alloca target("wasm.externref"), align 1
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %index, ptr %index.addr, align 4
# |   store target("wasm.externref") %ref, ptr %ref.addr, align 1
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %index.addr, align 4
# |   %1 = load target("wasm.externref"), ptr %ref.addr, align 1
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.fill.externref(ptr addrspace(1) @table, i32 %0, target("wasm.externref") %1, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.fill.externref(ptr addrspace(1), i32, target("wasm.externref"), i32) #3
# | 
# | ; Function Attrs: noinline nounwind
# | define void @test_table_copy(i32 noundef %dst_idx, i32 noundef %src_idx, i32 noundef %nelem) #0 {
# | entry:
# |   %dst_idx.addr = alloca i32, align 4
# |   %src_idx.addr = alloca i32, align 4
# |   %nelem.addr = alloca i32, align 4
# |   store i32 %dst_idx, ptr %dst_idx.addr, align 4
# |   store i32 %src_idx, ptr %src_idx.addr, align 4
# |   store i32 %nelem, ptr %nelem.addr, align 4
# |   %0 = load i32, ptr %dst_idx.addr, align 4
# |   %1 = load i32, ptr %src_idx.addr, align 4
# |   %2 = load i32, ptr %nelem.addr, align 4
# |   call void @llvm.wasm.table.copy(ptr addrspace(1) @table, ptr addrspace(1) @other_table, i32 %1, i32 %0, i32 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.wasm.table.copy(ptr addrspace(1), ptr addrspace(1), i32, i32, i32) #3
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+reference-types" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | attributes #3 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556cf836e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556cf836b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556cf836e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b7ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b7baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b7ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b7ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556cf8303e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556cf8303c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556cf82e8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556cf7f980b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556cf7f97dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2b7ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b7ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b7ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556cf7f97cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c (2533 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m2_f16m1(<vscale x 8 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m4_f16m1(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m8_f16m1(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m4_f16m2(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m8_f16m2(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vget_v_f16m8_f16m4(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m2_f32m1(<vscale x 4 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m4_f32m1(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m8_f32m1(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m4_f32m2(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m8_f32m2(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vget_v_f32m8_f32m4(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 8 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vget_v_f64m2_f64m1(<vscale x 2 x double> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> %0, i64 0)
# |   ret <vscale x 1 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double>, i64 immarg) #1
# | 
# | ; Function Attrs: noinli
# | ...
# `---data was truncated (10240/246614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557587c6515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557587c620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557587c6589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b92505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b9255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b92505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b924ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557587bfae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557587bfac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557587bdfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055758788f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055758788edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1b924eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b924ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b924ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055758788ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c (2534 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = and <8 x i16> %0, splat (i16 11007)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = and <4 x i32> %0, splat (i32 -252)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = and <8 x i16> %0, splat (i16 -243)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = and <4 x i32> %0, splat (i32 -8193)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = or <8 x i16> %0, splat (i16 195)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_s32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = or <4 x i32> %0, splat (i32 65536)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = or <8 x i16> %0, splat (i16 -4096)
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = or <4 x i32> %0, splat (i32 8978432)
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_s16() #0 {
# | entry:
# |   ret <8 x i16> splat (i16 27391)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_s32() #0 {
# | entry:
# |   ret <4 x i32> splat (i32 -5570561)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_u16() #0 {
# | entry:
# |   ret <8 x i16> splat (i16 -18689)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_u32() #0 {
# | entry:
# |   ret <4 x i32> splat (i32 1023410175)
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = and <8 x i16> %3, splat (i16 -11265)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = and <4 x i32> %3, splat (i32 -13893633)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = and <8 x i16> %3, splat (i16 -37)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = and <4 x i32> %3, splat (i32 -1644167169)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = or <8 x i16> %3, splat (i16 13568)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = or <4 x i32> %3, splat (i32 654311424)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %a.addr, align 8
# |   %4 = or <8 x i16> %3, splat (i16 175)
# |   %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %a.addr, align 8
# |   %4 = or <4 x i32> %3, splat (i32 89)
# |   %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_s16(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %4 = select <8 x i1> %2, <8 x i16> splat (i16 -3841), <8 x i16> %3
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_n_s32(<4 x i32> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
# |   %3 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %4 = select <4 x i1> %2, <4 x i32> splat (i32 -18945), <4 x i32> %3
# |   ret <4 x i32> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_u16(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load i16, ptr %p.addr, align 2
# |   %1 = zext i16 %0 to i32
# |   %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
# |   %3 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %4 = select <8 x i1> %
# | ...
# `---data was truncated (10240/13125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f40051915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f4005160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f40051989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f95c1c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f95c1c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f95c1c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f95c1c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4004aee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f4004aec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f400493b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f4001430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f400142dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f95c1c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f95c1c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f95c1c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f400142cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c (2535 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vv_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdivu_vx_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vv_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdivu_vx_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdivu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vv_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdivu_vx_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdivu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vv_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdivu_vx_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdivu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdivu_vv_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c6523a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564c652370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564c6523a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac31c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac31ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac31c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac31c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c651cfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564c651cfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564c651b4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564c64e640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564c64e63dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fac31c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac31c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac31c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c64e63cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c (2536 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xvv_se_u64m8(<vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.nxv8i64.i64.i64(i64 immarg, <vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xvv_se_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_xvv_se_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_xvv_se_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_xvv_se_u64m8(<vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 immarg, <vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xvv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, <vsca
# | ...
# `---data was truncated (10240/14360) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c3cb6215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559c3cb5f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559c3cb6289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f121121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12112725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f121121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1211203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c3caf7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559c3caf7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559c3cadcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559c3c78c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559c3c78bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1211204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12112050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12112050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c3c78bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c (2537 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x
# | ...
# `---data was truncated (10240/15614) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556be615b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556be61580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556be615b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2bfe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2bfea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2bfe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2bfe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556be60f0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556be60f0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556be60d5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556be5d850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556be5d84dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff2bfe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2bfe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2bfe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556be5d84cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c (2538 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1(<vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2(<vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4(<vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8(<vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmerge_vfm_f32m1(<vscale x 2 x float> %op1, float noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmerge_vfm_f32m2(<vscale x 4 x float> %op1, float noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 4 x i1>, align
# | ...
# `---data was truncated (10240/19041) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055703cdf415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055703cdf10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055703cdf489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f329141bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32914725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f329141ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3291403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055703cd89e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055703cd89c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055703cd6eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055703ca1e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055703ca1ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3291404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32914050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32914050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055703ca1dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c (2539 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>
# | ...
# `---data was truncated (10240/15607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c88d26715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c88d2640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c88d26789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efed1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efed1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efed1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efed1d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c88d1fce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c88d1fcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c88d1e1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c88ce910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c88ce90dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efed1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efed1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efed1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c88ce90cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c (2540 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055babe7d915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055babe7d60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055babe7d989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e4ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e4ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e4ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e4ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055babe76ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055babe76ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055babe753b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055babe4030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055babe402dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4e4ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e4ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e4ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055babe402cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c (2541 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, a
# | ...
# `---data was truncated (10240/43486) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0e3b0b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e0e3b080f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e0e3b0b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6af7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6af72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6af7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6af7231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0e3aa0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e0e3aa0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e0e3a85b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e0e37350b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e0e3734dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6af7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6af72330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6af72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0e3734cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c (2542 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bf04b2315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bf04b200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bf04b2389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8164c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8164ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8164c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8164c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bf04ab8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bf04ab8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bf04a9db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bf0474d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bf0474cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8164c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8164c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8164c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bf0474ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c (2543 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f16m1x7(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f32m1x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_f64m1x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei16_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c44a08815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c44a0850f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c44a08889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f530061bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53006725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f530061ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5300603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c44a01de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c44a01dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c44a002b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c449cb20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c449cb1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5300604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53006050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53006050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c449cb1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c (2544 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_i32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_u32m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void
# | ...
# `---data was truncated (10240/20489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ec36e215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555ec36df0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555ec36e289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5ddd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5ddd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5ddd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5ddd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ec3677e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555ec3677c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555ec365cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555ec330c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555ec330bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff5ddd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5ddd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5ddd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ec330bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c (2545 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs1, <vsc
# | ...
# `---data was truncated (10240/148835) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557aaab115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005557aaaae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005557aaab189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda3d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda3d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda3d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda3d231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557aaa46e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005557aaa46c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005557aaa2bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005557aa6db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005557aa6dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fda3d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda3d2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda3d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557aa6dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c (2546 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005562d7de615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005562d7de30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005562d7de689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca82f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca82f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca82f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca82eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005562d7d7be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005562d7d7bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005562d7d60b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005562d7a100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005562d7a0fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fca82eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca82eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca82eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005562d7a0fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c (2547 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16
# | ...
# `---data was truncated (10240/99762) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055662180615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005566218030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055662180689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdce1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdce118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdce1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdce111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055662179be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055662179bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556621780b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005566214300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055662142fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdce111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdce111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdce111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055662142fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c (2548 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bflo
# | ...
# `---data was truncated (10240/34364) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b9f3bfd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b9f3bfa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b9f3bfd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff559133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff55918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff559133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff55911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b9f3b92e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b9f3b92c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b9f3b77b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b9f38270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b9f3826dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff55911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff55911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff55911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b9f3826cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c (2549 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb4e9f415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fb4e9f10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fb4e9f489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52c7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52c7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52c7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52c7e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb4e989e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fb4e989c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fb4e96eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fb4e61e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fb4e61ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f52c7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52c7e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52c7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb4e61dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c (2550 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b8296e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556b8296b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556b8296e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ebe649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ebe6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ebe649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ebe631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b82903e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556b82903c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556b828e8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556b825980b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556b82597dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5ebe632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ebe6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ebe6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b82597cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c (2551 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f7cacf915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f7cacf60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f7cacf989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff589d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff589d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff589d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff589ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f7cac8ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f7cac8ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f7cac73b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f7ca9230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f7ca922dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff589ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff589cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff589cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f7ca922cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c (2552 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/15952) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631111f415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005631111f10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005631111f489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27edb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27edb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27edb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27edb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563111189e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563111189c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056311116eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563110e1e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563110e1ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f27edb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27edb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27edb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563110e1dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c (2553 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e94477b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e9447780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e94477b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c4ad05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c4ad5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c4ad05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c4aced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e944710e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e944710c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e9446f5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e9443a50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e9443a4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9c4aceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c4acef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c4acef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e9443a4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c (2554 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556539b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005556539b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005556539b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6df4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6df4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6df4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6df4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055565394ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055565394cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555653931b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005556535e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005556535e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6df4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6df4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6df4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556535e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c (2555 of 27911)
******************** TEST 'Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon   -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "armv8.1a-unknown-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrdmlah_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %c.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   %2 = load <4 x i16>, ptr %c.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s16.i = bitcast <8 x i8> %3 to <4 x i16>
# |   %vqrdmlah_s161.i = bitcast <8 x i8> %4 to <4 x i16>
# |   %vqrdmlah_s162.i = bitcast <8 x i8> %5 to <4 x i16>
# |   %vqrdmlah_s163.i = call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i)
# |   %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vqrdmlah_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x i32>, align 8
# |   %b.addr = alloca <2 x i32>, align 8
# |   %c.addr = alloca <2 x i32>, align 8
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   store <2 x i32> %b, ptr %b.addr, align 8
# |   store <2 x i32> %c, ptr %c.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   %1 = load <2 x i32>, ptr %b.addr, align 8
# |   %2 = load <2 x i32>, ptr %c.addr, align 8
# |   store <2 x i32> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i32> %1, ptr %__p1.addr.i, align 8
# |   store <2 x i32> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s32.i = bitcast <8 x i8> %3 to <2 x i32>
# |   %vqrdmlah_s321.i = bitcast <8 x i8> %4 to <2 x i32>
# |   %vqrdmlah_s322.i = bitcast <8 x i8> %5 to <2 x i32>
# |   %vqrdmlah_s323.i = call <2 x i32> @llvm.arm.neon.vqrdmlah.v2i32(<2 x i32> %vqrdmlah_s32.i, <2 x i32> %vqrdmlah_s321.i, <2 x i32> %vqrdmlah_s322.i)
# |   %vqrdmlah_s324.i = bitcast <2 x i32> %vqrdmlah_s323.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s324.i, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i32>, ptr %ref.tmp.i, align 8
# |   store <2 x i32> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i32>, ptr %__ret.i, align 8
# |   ret <2 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <8 x i16> @test_vqrdmlahq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x i16>, align 16
# |   %__p2.addr.i = alloca <8 x i16>, align 16
# |   %__ret.i = alloca <8 x i16>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x i16>, align 16
# |   %c.addr = alloca <8 x i16>, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x i16> %b, ptr %b.addr, align 16
# |   store <8 x i16> %c, ptr %c.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x i16>, ptr %b.addr, align 16
# |   %2 = load <8 x i16>, ptr %c.addr, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 16
# |   store <8 x i16> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vqrdmlahq_s16.i = bitcast <16 x i8> %3 to <8 x i16>
# |   %vqrdmlahq_s161.i = bitcast <16 x i8> %4 to <8 x i16>
# |   %vqrdmlahq_s162.i = bitcast <16 x i8> %5 to <8 x i16>
# |   %vqrdmlahq_s163.i = call <8 x i16> @llvm.arm.neon.vqrdmlah.v8i16(<8 x i16> %vqrdmlahq_s16.i, <8 x i16> %vqrdmlahq_s161.i, <8 x i16> %vqrdmlahq_s162.i)
# |   %vqrdmlahq_s164.i = bitcast <8 x i16> %vqrdmlahq_s163.i to <16 x i8>
# |   store <16 x i8> %vqrdmlahq_s164.i, ptr %ref.tmp.i, align 16
# |   %6 = load <8 x i16>, ptr %ref.tmp.i, align 16
# |   store <8 x i16> %6, ptr %__ret.i, align 16
# |   %7 = load <8 x i16>, ptr %__ret.i, align 16
# |   ret <8 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vqrdmlahq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i32>, align 16
# |   %__p1.addr.i = alloca <4 x i32>, align 16
# |   %__p2.addr.i = alloca <4 x i32>, align 16
# |   %__ret.i = alloca <4 x i32>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %a.addr = alloca <4 x i32>, align 16
# |   %b.addr = alloca <4 x i32>, align 16
# |   %c.addr = alloca <4 x i32>, align 16
# |   store <4 x i32> %a, ptr %a.addr, align 16
# |   store <4 x i32> %b, ptr %b.addr, align 16
# |   store <4 x i32> %c, ptr %c.addr, align 16
# |   %0 = load <4 x i32>, ptr %a.addr, align 16
# |   %1 = load <4 x i32>, ptr %b.addr, align 16
# |   %2 = load <4 x i32>, ptr %c.addr, align 16
# |   store <4 x i32> %0, ptr %__p0.addr.i, align 16
# |   store <4 x i32> %1, ptr %__p1.addr.i, align 16
# |   store <4 x i32> %2, ptr %__p2.addr.i, align 16
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vqrdmlahq_s32.i = bitcast <16 x i8> %3 to <4 x i32>
# |   %vqrdmlahq_s321.i = bitcast <16 x i8> %4 to <4 x i32>
# |   %vqrdmlahq_s322.i = bitcast <16 x i8> %5 to <4 x i32>
# |   %vqrdmlahq_s323.i = call <4 x i32> @llvm.arm.neon.vqrdmlah.v4i32(<4 x i32> %vqrdmlahq_s32.i, <4 x i32> %vqrdmlahq_s321.i, <4 x i32> %vqrdmlahq_s322.i)
# |   %vqrdmlahq_s324.i = bitcast <4 x i32> %vqrdmlahq_s323.i to <16 x i8>
# |   store <16 x i8> %vqrdmlahq_s324.i, ptr %ref.tmp.i, align 16
# |   %6 = load <4 x i32>, ptr %ref.tmp.i, align 16
# |   store <4 x i32> %6, ptr %__ret.i, align 16
# |   %7 = load <4 x i32>, ptr %__ret.i, align 16
# |   ret <4 x i32> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i16> @test_vqrdmlah_lane_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__p2.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   %c.addr = alloca <4 x i16>, align 8
# |   %__ret_140 = alloca <4 x i16>, align 8
# |   %__s0_140 = alloca <4 x i16>, align 8
# |   %__s1_140 = alloca <4 x i16>, align 8
# |   %__s2_140 = alloca <4 x i16>, align 8
# |   %__ret = alloca <4 x i16>, align 8
# |   %__s0 = alloca <4 x i16>, align 8
# |   %ref.tmp = alloca <8 x i8>, align 8
# |   %tmp = alloca <4 x i16>, align 8
# |   %tmp1 = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   store <4 x i16> %c, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   store <4 x i16> %0, ptr %__s0_140, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %1, ptr %__s1_140, align 8
# |   %2 = load <4 x i16>, ptr %c.addr, align 8
# |   store <4 x i16> %2, ptr %__s2_140, align 8
# |   %3 = load <4 x i16>, ptr %__s0_140, align 8
# |   %4 = load <4 x i16>, ptr %__s1_140, align 8
# |   %5 = load <4 x i16>, ptr %__s2_140, align 8
# |   store <4 x i16> %5, ptr %__s0, align 8
# |   %6 = load <8 x i8>, ptr %__s0, align 8
# |   %7 = bitcast <8 x i8> %6 to <4 x i16>
# |   %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
# |   store <4 x i16> %lane, ptr %ref.tmp, align 8
# |   %8 = load <4 x i16>, ptr %ref.tmp, align 8
# |   store <4 x i16> %8, ptr %__ret, align 8
# |   %9 = load <4 x i16>, ptr %__ret, align 8
# |   store <4 x i16> %9, ptr %tmp, align 8
# |   %10 = load <4 x i16>, ptr %tmp, align 8
# |   store <4 x i16> %3, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %4, ptr %__p1.addr.i, align 8
# |   store <4 x i16> %10, ptr %__p2.addr.i, align 8
# |   %11 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %12 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %13 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vqrdmlah_s16.i = bitcast <8 x i8> %11 to <4 x i16>
# |   %vqrdmlah_s161.i = bitcast <8 x i8> %12 to <4 x i16>
# |   %vqrdmlah_s162.i = bitcast <8 x i8> %13 to <4 x i16>
# |   %vqrdmlah_s163.i = call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i)
# |   %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8>
# |   store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8
# |   %14 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %14, ptr %__ret.i, align 8
# |   %15 = load <4 x i16>, ptr %__ret.i, align 8
# |   store <4 x i16> %15, ptr %__ret_140, align 8
# |   %16 = load <4 x i16>, ptr %__ret_140, align 8
# |   store <4 x i16> %16, ptr %tmp1, align 8
# |   %17 = load <4 x i16>, ptr %tmp1, align 8
# |   ret <4 x i16> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vqrdmlah_lane_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i32>, align 8
# |   %__p1.addr.i = alloca <2 x i32>, align 8
# |   %__p2.addr.i = alloca <2 x i32>, align 8
# |   %__ret.i = alloca <2 x i32>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr
# | ...
# `---data was truncated (10240/38786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S
# |  #0 0x0000564d113b315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564d113b00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564d113b389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd48c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd48c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd48c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd48c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d11348e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564d11348c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564d1132db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564d10fdd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564d10fdcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd48c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd48c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd48c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d10fdccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c (2556 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578f6a7315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005578f6a700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005578f6a7389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffa3a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffa3a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffa3a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffa3a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578f6a08e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005578f6a08c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005578f69edb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005578f669d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005578f669cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ffa3a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffa3a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffa3a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578f669ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c (2557 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b0f1bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557b0f1ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557b0f1bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2fb6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2fb638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2fb6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2fb631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b0f152e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557b0f152c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557b0f137b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557b0ede70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557b0ede6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2fb631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2fb631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2fb631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b0ede6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c (2558 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f1760915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564f176060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564f1760989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8098049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80980a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8098049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8098031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f1759ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564f1759ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564f17583b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564f172330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564f17232dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8098032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80980330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80980330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f17232cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-neon-fma.c (2559 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-fma.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-none-linux-gnueabihf    -target-abi aapcs    -target-cpu cortex-a7    -mfloat-abi hard    -ffreestanding    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-none-linux-gnueabihf -target-abi aapcs -target-cpu cortex-a7 -mfloat-abi hard -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv7-none-linux-gnueabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_fma_order(<2 x float> noundef %accum, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %accum.addr = alloca <2 x float>, align 8
# |   %lhs.addr = alloca <2 x float>, align 8
# |   %rhs.addr = alloca <2 x float>, align 8
# |   store <2 x float> %accum, ptr %accum.addr, align 8
# |   store <2 x float> %lhs, ptr %lhs.addr, align 8
# |   store <2 x float> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <2 x float>, ptr %accum.addr, align 8
# |   %1 = load <2 x float>, ptr %lhs.addr, align 8
# |   %2 = load <2 x float>, ptr %rhs.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store <2 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <8 x i8> %3 to <2 x float>
# |   %7 = bitcast <8 x i8> %4 to <2 x float>
# |   %8 = bitcast <8 x i8> %5 to <2 x float>
# |   %9 = call <2 x float> @llvm.fma.v2f32(<2 x float> %7, <2 x float> %8, <2 x float> %6)
# |   store <2 x float> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %10, ptr %__ret.i, align 8
# |   %11 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_fmaq_order(<4 x float> noundef %accum, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__p2.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %accum.addr = alloca <4 x float>, align 8
# |   %lhs.addr = alloca <4 x float>, align 8
# |   %rhs.addr = alloca <4 x float>, align 8
# |   store <4 x float> %accum, ptr %accum.addr, align 8
# |   store <4 x float> %lhs, ptr %lhs.addr, align 8
# |   store <4 x float> %rhs, ptr %rhs.addr, align 8
# |   %0 = load <4 x float>, ptr %accum.addr, align 8
# |   %1 = load <4 x float>, ptr %lhs.addr, align 8
# |   %2 = load <4 x float>, ptr %rhs.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   store <4 x float> %2, ptr %__p2.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %4 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %5 = load <16 x i8>, ptr %__p2.addr.i, align 8
# |   %6 = bitcast <16 x i8> %3 to <4 x float>
# |   %7 = bitcast <16 x i8> %4 to <4 x float>
# |   %8 = bitcast <16 x i8> %5 to <4 x float>
# |   %9 = call <4 x float> @llvm.fma.v4f32(<4 x float> %7, <4 x float> %8, <4 x float> %6)
# |   store <4 x float> %9, ptr %ref.tmp.i, align 8
# |   %10 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %10, ptr %__ret.i, align 8
# |   %11 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %11
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x float> @test_vfma_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %n) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <2 x float>, align 8
# |   %__p1.addr.i.i = alloca <2 x float>, align 8
# |   %__p2.addr.i.i = alloca <2 x float>, align 8
# |   %__ret.i.i = alloca <2 x float>, align 8
# |   %ref.tmp.i.i = alloca <8 x i8>, align 8
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <2 x float>, align 8
# |   %.compoundliteral.i = alloca <2 x float>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %n.addr = alloca float, align 4
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   store float %n, ptr %n.addr, align 4
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %n.addr, align 4
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <2 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <2 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <2 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1
# |   store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8
# |   %7 = load <2 x float>, ptr %.compoundliteral.i, align 8
# |   store <2 x float> %3, ptr %__p0.addr.i.i, align 8
# |   store <2 x float> %4, ptr %__p1.addr.i.i, align 8
# |   store <2 x float> %7, ptr %__p2.addr.i.i, align 8
# |   %8 = load <8 x i8>, ptr %__p0.addr.i.i, align 8
# |   %9 = load <8 x i8>, ptr %__p1.addr.i.i, align 8
# |   %10 = load <8 x i8>, ptr %__p2.addr.i.i, align 8
# |   %11 = bitcast <8 x i8> %8 to <2 x float>
# |   %12 = bitcast <8 x i8> %9 to <2 x float>
# |   %13 = bitcast <8 x i8> %10 to <2 x float>
# |   %14 = call <2 x float> @llvm.fma.v2f32(<2 x float> %12, <2 x float> %13, <2 x float> %11)
# |   store <2 x float> %14, ptr %ref.tmp.i.i, align 8
# |   %15 = load <2 x float>, ptr %ref.tmp.i.i, align 8
# |   store <2 x float> %15, ptr %__ret.i.i, align 8
# |   %16 = load <2 x float>, ptr %__ret.i.i, align 8
# |   store <2 x float> %16, ptr %__ret.i, align 8
# |   %17 = load <2 x float>, ptr %__ret.i, align 8
# |   ret <2 x float> %17
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %n) #0 {
# | entry:
# |   %__p0.addr.i.i = alloca <4 x float>, align 8
# |   %__p1.addr.i.i = alloca <4 x float>, align 8
# |   %__p2.addr.i.i = alloca <4 x float>, align 8
# |   %__ret.i.i = alloca <4 x float>, align 8
# |   %ref.tmp.i.i = alloca <16 x i8>, align 8
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__p2.addr.i = alloca float, align 4
# |   %__ret.i = alloca <4 x float>, align 8
# |   %.compoundliteral.i = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %n.addr = alloca float, align 4
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store float %n, ptr %n.addr, align 4
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load float, ptr %n.addr, align 4
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   store float %2, ptr %__p2.addr.i, align 4
# |   %3 = load <4 x float>, ptr %__p0.addr.i, align 8
# |   %4 = load <4 x float>, ptr %__p1.addr.i, align 8
# |   %5 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit.i = insertelement <4 x float> poison, float %5, i32 0
# |   %6 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1
# |   %7 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2
# |   %8 = load float, ptr %__p2.addr.i, align 4
# |   %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3
# |   store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 8
# |   %9 = load <4 x float>, ptr %.compoundliteral.i, align 8
# |   store <4 x float> %3, ptr %__p0.addr.i.i, align 8
# |   store <4 x float> %4, ptr %__p1.addr.i.i, align 8
# |   store <4 x float> %9, ptr %__p2.addr.i.i, align 8
# |   %10 = load <16 x i8>, ptr %__p0.addr.i.i, align 8
# |   %11 = load <16 x i8>, ptr %__p1.addr.i.i, align 8
# |   %12 = load <16 x i8>, ptr %__p2.addr.i.i, align 8
# |   %13 = bitcast <16 x i8> %10 to <4 x float>
# |   %14 = bitcast <16 x i8> %11 to <4 x float>
# |   %15 = bitcast <16 x i8> %12 to <4 x float>
# |   %16 = call <4 x float> @llvm.fma.v4f32(<4 x float> %14, <4 x float> %15, <4 x float> %13)
# |   store <4 x float> %16, ptr %ref.tmp.i.i, align 8
# |   %17 = load <4 x float>, ptr %ref.tmp.i.i, align 8
# |   store <4 x float> %17, ptr %__ret.i.i, align 8
# |   %18 = load <4 x float>, ptr %__ret.i.i, align 8
# |   store <4 x float> %18, ptr %__ret.i, align 8
# |   %19 = load <4 x float>, ptr %__ret.i, align 8
# |   ret <4 x float> %19
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
# | 
# | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a7" "target-features"="+armv7-a,+d32,+dsp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" }
# | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x000055ce4376615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ce437630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ce4376689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa02c505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa02c55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa02c505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa02c4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce436fbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ce436fbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ce436e0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ce433900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ce4338fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa02c4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa02c4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa02c4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce4338fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c (2560 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrsqrt7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrsqrt7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrsqrt7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrsqrt7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrsqrt7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrsqrt7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrsqrt7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrsqrt7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrsqrt7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrsqrt7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrsqrt7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrsqrt7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfrsqrt7_v_f64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align
# | ...
# `---data was truncated (10240/29111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055764739115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055764738e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055764739189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71b5f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71b5f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71b5f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71b5eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557647326e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557647326c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055764730bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557646fbb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557646fbadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f71b5eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71b5eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71b5eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557646fbacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c (2561 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vv_u16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccu_vx_u16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vv_u16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccu_vx_u16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vv_u16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccu_vx_u16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vv_u16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccu_vx_u16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccu_vv_u16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.ad
# | ...
# `---data was truncated (10240/79671) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bec25b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bec25b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bec25b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f574f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f574f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f574f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f574f51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bec254be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bec254bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bec2530b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bec21e00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bec21dfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f574f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f574f51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f574f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bec21dfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c (2562 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr =
# | ...
# `---data was truncated (10240/14319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd7747b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bd774780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bd7747b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f16e6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f16e658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f16e6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f16e651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd77410e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bd77410c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bd773f5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bd770a50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bd770a4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f16e651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f16e651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f16e651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd770a4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c (2563 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056361ea6615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056361ea630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056361ea6689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd4a8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd4a8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd4a8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd4a8d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056361e9fbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056361e9fbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056361e9e0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056361e6900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056361e68fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd4a8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd4a8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd4a8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056361e68fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c (2564 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.add
# | ...
# `---data was truncated (10240/14453) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005563fdc4015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005563fdc3d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005563fdc4089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4007649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f40076a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4007649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4007631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005563fdbd5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005563fdbd5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005563fdbbab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005563fd86a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005563fd869dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4007632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f40076330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f40076330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005563fd869cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c (2565 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgtu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgtu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgtu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgtu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056352249b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005635224980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056352249b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f090bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f090bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f090bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f090bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563522430e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563522430c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563522415b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005635220c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005635220c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f090bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f090bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f090bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005635220c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c (2566 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmflt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmflt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmflt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmflt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a07c48315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a07c4800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a07c48389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4895733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f489578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4895733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f489571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a07c418e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a07c418c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a07c3fdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a07c0ad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a07c0acdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f489571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f489571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f489571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a07c0accc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c (2567 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556100bb815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556100bb50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556100bb889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f769de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f769dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f769de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f769de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556100b4de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556100b4dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556100b32b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005561007e20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005561007e1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f769de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f769de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f769de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561007e1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll (2568 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 7
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll
# |  #0 0x000055bd7a9bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bd7a9ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bd7a9bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa998733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa99878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa998733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa99871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd7a952e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bd7a952c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bd7a937b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bd7a5e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bd7a5e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa99871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa99871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa99871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd7a5e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c (2569 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c75e6615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564c75e630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564c75e6689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe28249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe282a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe28249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe28231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c75dfbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564c75dfbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564c75de0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564c75a900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564c75a8fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbe28232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe282330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe282330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c75a8fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c (2570 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_u16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/26921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f6f45c815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f6f45c50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f6f45c889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f72ed249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f72ed2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f72ed249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f72ed231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6f455de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f6f455dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f6f4542b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f6f41f20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f6f41f1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f72ed232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f72ed2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f72ed2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6f41f1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c (2571 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei8_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei8_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564eb538115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564eb537e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564eb538189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc70dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc70dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc70dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc70dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564eb5316e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564eb5316c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564eb52fbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564eb4fab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564eb4faadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc70dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc70dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc70dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564eb4faacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c (2572 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596131cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005596131cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005596131cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b4fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b4faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b4fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b4fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559613164e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559613164c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559613149b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559612df90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559612df8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7b4fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b4fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b4fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559612df8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c (2573 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vbrev8_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vbrev8.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vbrev8_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vbrev8.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vbrev8_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vbrev8.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i
# | ...
# `---data was truncated (10240/40929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639a84f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005639a84f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005639a84f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe2f461bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe2f46725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe2f461ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe2f4603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639a848de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005639a848dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005639a8472b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005639a81220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005639a8121dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe2f4604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe2f46050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe2f46050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639a8121cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c (2574 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vrem_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vrem_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vrem.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vrem_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vrem.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vrem_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vrem.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vrem_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |  
# | ...
# `---data was truncated (10240/222475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef7ce8715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ef7ce840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ef7ce8789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faaa7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faaa7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faaa7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faaa7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef7ce1ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ef7ce1cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ef7ce01b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ef7cab10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ef7cab0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faaa7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faaa7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faaa7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef7cab0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c (2575 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596dd9d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005596dd9d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005596dd9d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8bcc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8bcc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8bcc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8bcc31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596dd969e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005596dd969c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005596dd94eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005596dd5fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005596dd5fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8bcc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8bcc31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8bcc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596dd5fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c (2576 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vid_v_u8mf8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8> poison, i64 %0)
# |   ret <vscale x 1 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vid_v_u8mf4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8> poison, i64 %0)
# |   ret <vscale x 2 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vid_v_u8mf2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8> poison, i64 %0)
# |   ret <vscale x 4 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vid_v_u8m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8> poison, i64 %0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vid_v_u8m2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8> poison, i64 %0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vid_v_u8m4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8> poison, i64 %0)
# |   ret <vscale x 32 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vid_v_u8m8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8> poison, i64 %0)
# |   ret <vscale x 64 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vid_v_u16mf4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16> poison, i64 %0)
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vid_v_u16mf2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16> poison, i64 %0)
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vid_v_u16m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16> poison, i64 %0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vid_v_u16m2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16> poison, i64 %0)
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vid_v_u16m4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16> poison, i64 %0)
# |   ret <vscale x 16 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vid_v_u16m8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16> poison, i64 %0)
# |   ret <vscale x 32 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vid_v_u32mf2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32.i64(<vscale x 1 x i32> poison, i64 %0)
# |   ret <vscale x 1 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32.i64(<vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vid_v_u32m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32.i64(<vscale x 2 x i32> poison, i64 %0)
# |   ret <vscale x 2 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32.i64(<vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vid_v_u32m2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32.i64(<vscale x 4 x i32> poison, i64 %0)
# |   ret <vscale x 4 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32.i64(<vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vid_v_u32m4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32.i64(<vscale x 8 x i32> poison, i64 %0)
# |   ret <vscale x 8 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32.i64(<vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vid_v_u32m8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32.i64(<vscale x 16 x i32> poison, i64 %0)
# |   ret <vscale x 16 x i32> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32.i64(<vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vid_v_u64m1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align
# | ...
# `---data was truncated (10240/30303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f1ff7c415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f1ff7c10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f1ff7c489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d2a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d2a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d2a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d2a003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f1ff759e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f1ff759c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f1ff73eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f1ff3ee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f1ff3eddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3d2a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d2a0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d2a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f1ff3edcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c (2577 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bcac8815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555bcac850f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555bcac8889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbed3d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbed3d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbed3d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbed3ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bcac1de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555bcac1dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555bcac02b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555bca8b20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555bca8b1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbed3ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbed3cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbed3cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bca8b1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c (2578 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566b3c1815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005566b3c150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005566b3c1889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f7be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f7bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f7be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f7be31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566b3bade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005566b3badc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005566b3b92b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005566b38420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005566b3841dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7f7be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f7be330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f7be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566b3841cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c (2579 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale 
# | ...
# `---data was truncated (10240/26702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056220150815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005622015050f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056220150889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0ab849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0ab8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0ab849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0ab831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056220149de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056220149dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562201482b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005622011320b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562201131dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc0ab832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0ab8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0ab8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562201131cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c (2580 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none)
# | ...
# `---data was truncated (10240/30609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d88a5d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d88a5d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d88a5d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fab72049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fab720a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fab72049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fab72031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d88a569e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d88a569c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d88a54eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d88a1fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d88a1fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fab72032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fab720330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fab720330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d88a1fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c (2581 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 2, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, alig
# | ...
# `---data was truncated (10240/26754) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055628f31f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055628f31c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055628f31f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f903f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f903f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f903f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f903f031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055628f2b4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055628f2b4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055628f299b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055628ef490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055628ef48dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f903f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f903f0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f903f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055628ef48cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c (2582 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f16m1x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f16m2x3(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f32m1x3(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_f32m2x3(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_f64m1x3(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/82983) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f990afc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f990af90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f990afc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0388b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0388b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0388b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0388b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f990a91e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f990a91c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f990a76b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f9907260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f990725dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0388b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0388b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0388b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f990725cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c (2583 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e172cfe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e172cfb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e172cfe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4977449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49774a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4977449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4977431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e172c93e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e172c93c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e172c78b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e1729280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e172927dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4977432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49774330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49774330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e172927cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c (2584 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b966db15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558b966d80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558b966db89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1efac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1efaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1efac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1efac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b96670e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558b96670c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558b96655b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558b963050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558b96304dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1efac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1efac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1efac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b96304cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c (2585 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vbrev8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vbrev8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vbrev8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vbrev8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vbrev8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vbrev8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vbrev8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vbrev8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vbrev8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vbrev8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vbrev8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vbrev8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vbrev8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vbrev8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vbrev8_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vbrev8.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vbrev8_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vbrev8.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vbrev8_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vbrev8.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline
# | ...
# `---data was truncated (10240/95445) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591b0d8515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005591b0d820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005591b0d8589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b50933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b5098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b50933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b5091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591b0d1ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005591b0d1ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005591b0cffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005591b09af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005591b09aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2b5091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b5091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b5091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591b09aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c (2586 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c57c57e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c57c57b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c57c57e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fedc781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fedc78725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fedc781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fedc7803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c57c513e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c57c513c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c57c4f8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c57c1a80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c57c1a7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fedc7804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fedc78050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fedc78050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c57c1a7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c (2587 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv32i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv32i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_u8mf2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align
# | ...
# `---data was truncated (10240/14145) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055be2e13415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055be2e1310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055be2e13489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffae9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffae9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffae9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffae9e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055be2e0c9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055be2e0c9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055be2e0aeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055be2dd5e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055be2dd5ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ffae9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffae9e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffae9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055be2dd5dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c (2588 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vlm_v_b1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vlm_v_b2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vlm_v_b4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vlm_v_b8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vlm_v_b16(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vlm_v_b32(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1.p0.i64(ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vlm_v_b64(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1.p0.i64(ptr %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1.p0.i64(ptr captures(none), i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056463dfe215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056463dfdf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056463dfe289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc068c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc068c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc068c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc068c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056463df77e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056463df77c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056463df5cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056463dc0c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056463dc0bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc068c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc068c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc068c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056463dc0bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c (2589 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d2cab615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562d2cab30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562d2cab689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa5bfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5bfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa5bfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa5bfd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d2ca4be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562d2ca4bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562d2ca30b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562d2c6e00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562d2c6dfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa5bfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5bfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5bfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d2c6dfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c (2590 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, target("riscv
# | ...
# `---data was truncated (10240/70386) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620cdb3115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005620cdb2e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005620cdb3189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa25c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa25ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa25c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa25c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620cdac6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005620cdac6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005620cdaabb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005620cd75b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005620cd75add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faa25c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa25c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa25c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620cd75acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c (2591 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmin_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmin_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, a
# | ...
# `---data was truncated (10240/44177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562eadb9715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562eadb940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562eadb9789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06b8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06b88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06b8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06b8831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562eadb2ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562eadb2cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562eadb11b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562ead7c10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562ead7c0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f06b8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06b88330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06b88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ead7c0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c (2592 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_u16m1x8_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624b4e3615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005624b4e330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005624b4e3689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec1941bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec194725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec1941ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec19403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624b4dcbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005624b4dcbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005624b4db0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005624b4a600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005624b4a5fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fec19404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec194050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec194050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624b4a5fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c (2593 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> 
# | ...
# `---data was truncated (10240/68054) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056187230315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005618723000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056187230389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1db8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1db8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1db8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1db8f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561872298e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561872298c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056187227db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561871f2d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561871f2cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1db8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1db8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1db8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561871f2ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c (2594 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055faf684a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055faf68470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055faf684a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6375649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63756a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6375649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6375631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055faf67dfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055faf67dfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055faf67c4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055faf64740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055faf6473dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6375632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63756330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63756330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055faf6473cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c (2595 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559c8988f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559c8988c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559c8988f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf97333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf9738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf97333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf9731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559c89824e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559c89824c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559c89809b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559c894b90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559c894b8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faf9731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf9731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf9731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559c894b8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c (2596 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |  
# | ...
# `---data was truncated (10240/18867) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641f4e5915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005641f4e560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005641f4e5989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f441921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44192725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f441921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4419203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641f4deee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005641f4deec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005641f4dd3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005641f4a830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005641f4a82dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4419204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44192050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44192050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641f4a82cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c (2597 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eaa519115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eaa518e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eaa519189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa968c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa968ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa968c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa968c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eaa5126e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eaa5126c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eaa510bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eaa4dbb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eaa4dbadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa968c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa968c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa968c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eaa4dbacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c (2598 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x
# | ...
# `---data was truncated (10240/29379) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af566ce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055af566cb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055af566ce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea47d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea47d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea47d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea47d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af56663e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055af56663c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055af56648b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055af562f80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055af562f7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fea47d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea47d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea47d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af562f7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c (2599 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmand_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmand_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmand_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmand_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmand_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmand_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmand_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557c762b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005557c76280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005557c762b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f534c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f534c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f534c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f534c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557c75c0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005557c75c0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005557c75a5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005557c72550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005557c7254dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f534c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f534c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f534c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557c7254cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c (2600 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: n
# | ...
# `---data was truncated (10240/66314) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e7fdcf115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e7fdcee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e7fdcf189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f26a6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26a6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f26a6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26a6d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e7fdc86e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e7fdc86c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e7fdc6bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e7fd91b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e7fd91add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f26a6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26a6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26a6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7fd91acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c (2601 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmacc_vf_f32mf2_tu(<vscale x 1 x float> %vd, half noundef %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(<vscale x 1 x float>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmacc_vf_f32m1_tu(<vscale x 2 x float> %vd, half noundef %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(<vscale x 2 x float>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmacc_vf_f32m2_tu(<vscale x 4 x float> %vd, half noundef %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(<vscale x 4 x float>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmacc_vf_f32m4_tu(<vscale x 8 x float> %vd, half noundef %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store half %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load half, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(
# | ...
# `---data was truncated (10240/179185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055992481215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055992480f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055992481289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07bb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07bb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07bb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07bb031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599247a7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005599247a7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055992478cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055992443c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055992443bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f07bb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07bb0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07bb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055992443bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c (2602 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, i64 7, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %op1.addr = all
# | ...
# `---data was truncated (10240/147390) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fc31d5015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fc31d4d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fc31d5089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5ef7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5ef7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5ef7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5ef7d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc31ce5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fc31ce5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fc31ccab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fc3197a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fc31979dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5ef7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5ef7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5ef7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc31979cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c (2603 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcreate_v_bf16m1_bf16m2(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x bfloat> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   %3 = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> %2, <vscale x 4 x bfloat> %1, i64 4)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcreate_v_bf16m1_bf16m4(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x bfloat> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x bfloat> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x bfloat> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   %5 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %4, <vscale x 4 x bfloat> %1, i64 4)
# |   %6 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %5, <vscale x 4 x bfloat> %2, i64 8)
# |   %7 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> %6, <vscale x 4 x bfloat> %3, i64 12)
# |   ret <vscale x 16 x bfloat> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcreate_v_bf16m1_bf16m8(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3, <vscale x 4 x bfloat> %v4, <vscale x 4 x bfloat> %v5, <vscale x 4 x bfloat> %v6, <vscale x 4 x bfloat> %v7) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v4.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v5.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v6.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %v7.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 4 x bfloat> %v1, ptr %v1.addr, align 2
# |   store <vscale x 4 x bfloat> %v2, ptr %v2.addr, align 2
# |   store <vscale x 4 x bfloat> %v3, ptr %v3.addr, align 2
# |   store <vscale x 4 x bfloat> %v4, ptr %v4.addr, align 2
# |   store <vscale x 4 x bfloat> %v5, ptr %v5.addr, align 2
# |   store <vscale x 4 x bfloat> %v6, ptr %v6.addr, align 2
# |   store <vscale x 4 x bfloat> %v7, ptr %v7.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %v3.addr, align 2
# |   %4 = load <vscale x 4 x bfloat>, ptr %v4.addr, align 2
# |   %5 = load <vscale x 4 x bfloat>, ptr %v5.addr, align 2
# |   %6 = load <vscale x 4 x bfloat>, ptr %v6.addr, align 2
# |   %7 = load <vscale x 4 x bfloat>, ptr %v7.addr, align 2
# |   %8 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 0)
# |   %9 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %8, <vscale x 4 x bfloat> %1, i64 4)
# |   %10 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %9, <vscale x 4 x bfloat> %2, i64 8)
# |   %11 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %10, <vscale x 4 x bfloat> %3, i64 12)
# |   %12 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %11, <vscale x 4 x bfloat> %4, i64 16)
# |   %13 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %12, <vscale x 4 x bfloat> %5, i64 20)
# |   %14 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %13, <vscale x 4 x bfloat> %6, i64 24)
# |   %15 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> %14, <vscale x 4 x bfloat> %7, i64 28)
# |   ret <vscale x 32 x bfloat> %15
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat>, <vscale x 4 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcreate_v_bf16m2_bf16m4(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x bfloat> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   %3 = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> %2, <vscale x 8 x bfloat> %1, i64 8)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcreate_v_bf16m2_bf16m8(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %v3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 8 x bfloat> %v1, ptr %v1.addr, align 2
# |   store <vscale x 8 x bfloat> %v2, ptr %v2.addr, align 2
# |   store <vscale x 8 x bfloat> %v3, ptr %v3.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %v1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %v2.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %v3.addr, align 2
# |   %4 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 0)
# |   %5 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %4, <vscale x 8 x bfloat> %1, i64 8)
# |   %6 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %5, <vscale x 8 x bfloat> %2, i64 16)
# |   %7 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> %6, <vscale x 8 x bfloat> %3, i64 24)
# |   ret <vscale x 32 x bfloat> %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat>, <vscale x 8 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcreate_v_bf16m4_bf16m8(<vscale x 16 x bfloat> %v0, <vscale x 16 x bfloat> %v1) #0 {
# | entry:
# |   %v0.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %v1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %v0, ptr %v0.addr, align 2
# |   store <vscale x 16 x bfloat> %v1, ptr %v1.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %v0.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %v1.addr, align 2
# |   %2 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 0)
# |   %3 = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> %2, <vscale x 16 x bfloat> %1, i64 16)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vcreate_v_bf16mf4x2(<vscale x 1 x bfloat> %v0, <vscale x 1 x bfloat> %v1) #0 {
# | entry:
# |   %v0.add
# | ...
# `---data was truncated (10240/71275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e378bb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564e378b80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564e378bb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0bcad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0bcad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0bcad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0bcad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e37850e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564e37850c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564e37835b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564e374e50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564e374e4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0bcad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0bcad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0bcad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e374e4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c (2604 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(
# | ...
# `---data was truncated (10240/12227) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056260669415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005626066910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056260669489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7ba81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7ba8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7ba81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7ba803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562606629e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562606629c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056260660eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005626062be0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005626062bddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc7ba804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7ba8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7ba8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005626062bdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c (2605 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a6f9e6e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a6f9e6b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a6f9e6e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d78b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d78b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d78b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d78b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a6f9e03e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a6f9e03c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a6f9de8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a6f9a980b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a6f9a97dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1d78b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d78b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d78b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a6f9a97cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c (2606 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/15978) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056184225d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056184225a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056184225d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1362849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13628a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1362849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1362831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618421f2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005618421f2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005618421d7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561841e870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561841e86dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1362832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13628330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13628330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561841e86cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c (2607 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %rs2.addr
# | ...
# `---data was truncated (10240/20623) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055907ec4415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055907ec410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055907ec4489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f849041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f84904725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f849041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8490403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055907ebd9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055907ebd9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055907ebbeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055907e86e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055907e86ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8490404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f84904050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f84904050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055907e86dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c (2608 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %sc
# | ...
# `---data was truncated (10240/52741) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cab7bc915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cab7bc60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cab7bc989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28d2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28d2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28d2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28d2b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cab7b5ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cab7b5ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cab7b43b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cab77f30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cab77f2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f28d2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28d2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28d2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cab77f2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c (2609 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   stor
# | ...
# `---data was truncated (10240/52599) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556419bd015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556419bcd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556419bd089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2a17f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2a17f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2a17f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2a17f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556419b65e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556419b65c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556419b4ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005564197fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005564197f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2a17f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2a17f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2a17f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564197f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c (2610 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f6e409e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f6e409b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f6e409e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3ec1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3ec118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3ec1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3ec111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6e4033e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f6e4033c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f6e4018b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f6e3cc80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f6e3cc7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3ec111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3ec111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3ec111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6e3cc7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c (2611 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16ff_v_bf16m2x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16ff_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16ff_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16ff_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i
# | ...
# `---data was truncated (10240/12756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8f17df15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c8f17dc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c8f17df89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcdb9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcdb90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcdb9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcdb9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8f1774e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c8f1774c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c8f1759b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c8f14090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c8f1408dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcdb9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcdb90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcdb90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8f1408cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c (2612 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(<vscale x 16 x bfloat>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(<vscale x 32 x bfloat>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(<vscale x 1 x bfloat>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(<vscale x 2 x bfloat>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(<vscale x 4 x bfloat>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(<vscale x 8 x bfloat>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vsca
# | ...
# `---data was truncated (10240/24214) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3f507b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f3f50780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f3f507b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78c4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78c42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78c4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78c4231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3f5010e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f3f5010c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f3f4ff5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f3f4ca50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f3f4ca4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f78c4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78c42330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78c42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3f4ca4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c (2613 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c2f0d915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564c2f0d60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564c2f0d989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1da905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1da95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1da905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1da8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c2f06ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564c2f06ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564c2f053b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564c2ed030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564c2ed02dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff1da8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1da8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1da8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c2ed02cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c (2614 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_i16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_u16m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.ri
# | ...
# `---data was truncated (10240/20449) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055efd355815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055efd35550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055efd355889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7084249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70842a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7084249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7084231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055efd34ede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055efd34edc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055efd34d2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055efd31820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055efd3181dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7084232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70842330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70842330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055efd3181cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c (2615 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor
# | ...
# `---data was truncated (10240/61929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad1423e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ad1423b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ad1423e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b5cf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b5cf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b5cf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b5ceed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad141d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ad141d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ad141b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ad13e680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ad13e67dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6b5ceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b5ceef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b5ceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad13e67cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c (2616 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005612189b215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005612189af0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005612189b289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12c6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12c62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12c6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12c6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561218947e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561218947c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056121892cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005612185dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005612185dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f12c6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12c62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12c62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005612185dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c (2617 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m1x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m2x2(ptr noundef %base, <vscale x 8 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f16m4x2(ptr noundef %base, <vscale x 16 x i8> %bindex, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m1x2(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg2ei8_v_f32m2x2(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/128444) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652673ad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005652673aa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005652673ad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57ece49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57ecea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57ece49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57ece31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565267342e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565267342c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565267327b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000565266fd70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000565266fd6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f57ece32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57ece330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57ece330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565266fd6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c (2618 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei8_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei8_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei8_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e51ad9015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e51ad8d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e51ad9089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb75133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb7518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb75133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb7511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e51ad25e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e51ad25c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e51ad0ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e51a9ba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e51a9b9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdb7511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb7511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb7511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e51a9b9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c (2619 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfneg_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfneg_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfneg_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfneg_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfneg_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfneg_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>
# | ...
# `---data was truncated (10240/13290) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561659e1415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561659e110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561659e1489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8d0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8d038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8d0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8d031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561659da9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561659da9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561659d8eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561659a3e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561659a3ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff8d031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8d031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8d031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561659a3dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c (2620 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr
# | ...
# `---data was truncated (10240/126428) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a870e9415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a870e910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a870e9489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca53e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca53ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca53e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca53e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a870e29e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a870e29c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a870e0eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a870abe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a870abddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fca53e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca53e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca53e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a870abdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c (2621 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_nds_vfwcvt_s_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_nds_vfwcvt_s_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_nds_vfwcvt_s_bf16_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_nds_vfwcvt_s_bf16_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_nds_vfwcvt_s_bf16_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056525ab3815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056525ab350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056525ab3889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8011c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8011c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8011c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8011c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056525aacde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056525aacdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056525aab2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056525a7620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056525a761dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8011c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8011c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8011c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056525a761cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c (2622 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, ali
# | ...
# `---data was truncated (10240/63510) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055878969815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005587896950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055878969889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7d5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7d50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7d5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7d5031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055878962de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055878962dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558789612b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005587892c20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005587892c1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb7d5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7d50330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7d50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587892c1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c (2623 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8_tu(<vscale x 32 x i16> %maskedoff, <vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i16>, align 2
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 0, i64 %2)
# |   ret <vscale x 32 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %
# | ...
# `---data was truncated (10240/67150) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d11e42c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d11e4290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d11e42c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe502905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe50295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe502905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5028ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d11e3c1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d11e3c1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d11e3a6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d11e0560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d11e055dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe5028eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5028ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5028ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d11e055cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c (2624 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, 
# | ...
# `---data was truncated (10240/32646) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ff5bc715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555ff5bc40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555ff5bc789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ba7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ba778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ba7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ba771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ff5b5ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555ff5b5cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555ff5b41b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555ff57f10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555ff57f0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4ba771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ba771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ba771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ff57f0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c (2625 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vv_f16mf4_b64(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfge_vf_f16mf4_b64(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vv_f16mf2_b32(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfge_vf_f16mf2_b32(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vv_f16m1_b16(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfge_vf_f16m1_b16(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vv_f16m2_b8(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfge_vf_f16m2_b8(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vv_f16m4_b4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfge_vf_f16m4_b4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfge_vv_f16m8_b2(<vscale x 32 x half> %op1, <vscale x 32 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 32 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/66557) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cdd1ca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557cdd1c70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557cdd1ca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5767333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f576738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5767333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f576731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cdd15fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557cdd15fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557cdd144b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557cdcdf40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557cdcdf3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f576731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f576731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f576731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cdcdf3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c (2626 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_f16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e16_v_i16m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 2
# |   %2 = load i64, p
# | ...
# `---data was truncated (10240/33435) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c45fe1e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c45fe1b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c45fe1e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c0df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c0df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c0df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c0df1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c45fdb3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c45fdb3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c45fd98b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c45fa480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c45fa47dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8c0df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c0df1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c0df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c45fa47cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c (2627 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555db20a915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555db20a60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555db20a989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f699b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f699b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f699b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f699b831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555db203ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555db203ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555db2023b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555db1cd30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555db1cd2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f699b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f699b8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f699b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555db1cd2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c (2628 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559bbd49015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559bbd48d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559bbd49089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1789f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1789f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1789f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1789f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559bbd425e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559bbd425c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559bbd40ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559bbd0ba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559bbd0b9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1789f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1789f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1789f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559bbd0b9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c (2629 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056313efed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056313efea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056313efed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc0a0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc0a098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc0a0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc0a091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056313ef82e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056313ef82c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056313ef67b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056313ec170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056313ec16dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc0a091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc0a091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc0a091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056313ec16cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c (2630 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 7, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64
# | ...
# `---data was truncated (10240/32186) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e2356e415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e2356e10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e2356e489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feeae733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feeae78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feeae733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feeae71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e235679e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e235679c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e23565eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e23530e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e23530ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feeae71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feeae71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feeae71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e23530dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c (2631 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte32.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cc2468d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cc2468a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cc2468d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56d0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56d098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56d0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56d091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cc24622e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cc24622c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cc24607b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cc242b70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cc242b6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f56d091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56d091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56d091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cc242b6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c (2632 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c2cc37415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c2cc3710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c2cc37489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f612ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f612eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f612ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f612ea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2cc309e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c2cc309c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c2cc2eeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c2cbf9e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c2cbf9ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f612ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f612ea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f612ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2cbf9dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c (2633 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598f3e7c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005598f3e790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005598f3e7c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0790b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0790b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0790b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0790b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005598f3e11e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005598f3e11c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005598f3df6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005598f3aa60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005598f3aa5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0790b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0790b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0790b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005598f3aa5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c (2634 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwcvtu_x_x_v_u16mf4(<vscale x 1 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwcvtu_x_x_v_u16mf2(<vscale x 2 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwcvtu_x_x_v_u16m1(<vscale x 4 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwcvtu_x_x_v_u16m2(<vscale x 8 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwcvtu_x_x_v_u16m4(<vscale x 16 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwcvtu_x_x_v_u16m8(<vscale x 32 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i8 0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwcvtu_x_x_v_u32mf2(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwcvtu_x_x_v_u32m1(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwcvtu_x_x_v_u32m2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vwcvtu_x_x_v_u32m4(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vwcvtu_x_x_v_u32m8(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i16 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i16, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vwcvtu_x_x_v_u64m1(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i32 0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vwcvtu_x
# | ...
# `---data was truncated (10240/29267) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566ca4e015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005566ca4dd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005566ca4e089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a12533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a1258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a12533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a1251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566ca475e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005566ca475c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005566ca45ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005566ca10a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005566ca109dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1a1251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a1251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a1251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566ca109cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c (2635 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c  -check-prefix=RV32ZKNE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32esi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32esi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32esi(i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @aes32esmi(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.aes32esmi(i32 %0, i32 %1, i32 3)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.aes32esmi(i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zkne" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zkne1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624764ff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005624764fc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005624764ff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f09733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f0978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f09733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f0971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562476494e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562476494c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562476479b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005624761290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562476128dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4f0971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f0971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f0971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562476128cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c (2636 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca targ
# | ...
# `---data was truncated (10240/11920) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561abd54115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561abd53e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561abd54189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ec9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ec998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ec9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ec991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561abd4d6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561abd4d6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561abd4bbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561abd16b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561abd16add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8ec991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ec991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ec991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561abd16acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c (2637 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vclz_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vclz.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vclz_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vclz.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vclz_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vclz.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vclz_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vclz.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vclz_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vclz.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vclz_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vclz.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vclz_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vclz.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vclz_v_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vclz.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vclz_v_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vclz.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vclz_v_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vclz.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test
# | ...
# `---data was truncated (10240/94993) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617bdce115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005617bdcde0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005617bdce189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff546d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff546d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff546d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff546d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617bdc76e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005617bdc76c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005617bdc5bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005617bd90b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005617bd90add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff546d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff546d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff546d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617bd90acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c (2638 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vlse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vlse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vlse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vlse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vlse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vlse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vlse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vlse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.p0.i64(<vscale x 16 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32.p0.i64(<vscale x 16 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vlse32_v_u32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vlse32_v_u32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, a
# | ...
# `---data was truncated (10240/29450) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d1815b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562d181580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562d1815b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe730705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe73075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe730705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7306ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d180f0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562d180f0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562d180d5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562d17d850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562d17d84dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe7306eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7306ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7306ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d17d84cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminaq.c (2639 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminaq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = icmp slt <16 x i8> %0, zeroinitializer
# |   %2 = sub <16 x i8> zeroinitializer, %0
# |   %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0
# |   %4 = load <16 x i8>, ptr %a.addr, align 8
# |   %5 = icmp ule <16 x i8> %4, %3
# |   %6 = select <16 x i1> %5, <16 x i8> %4, <16 x i8> %3
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminaq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = icmp slt <8 x i16> %0, zeroinitializer
# |   %2 = sub <8 x i16> zeroinitializer, %0
# |   %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0
# |   %4 = load <8 x i16>, ptr %a.addr, align 8
# |   %5 = icmp ule <8 x i16> %4, %3
# |   %6 = select <8 x i1> %5, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminaq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = icmp slt <4 x i32> %0, zeroinitializer
# |   %2 = sub <4 x i32> zeroinitializer, %0
# |   %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0
# |   %4 = load <4 x i32>, ptr %a.addr, align 8
# |   %5 = icmp ule <4 x i32> %4, %3
# |   %6 = select <4 x i1> %5, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminaq_m_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminaq_m_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmina.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmina.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminaq_m_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vmina.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmina.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d5934f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561d5934c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561d5934f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efe0a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efe0a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efe0a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efe0a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d592e4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561d592e4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561d592c9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561d58f790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561d58f78dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efe0a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efe0a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efe0a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d58f78cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c (2640 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa8054415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aa805410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aa8054489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fca133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fca18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fca133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fca11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa804d9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aa804d9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aa804beb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aa8016e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aa8016ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0fca11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fca11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fca11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa8016dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/X86/sse.c (2641 of 27911)
******************** TEST 'Clang :: CodeGen/X86/sse.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple x86_64-- -target-feature +sse4.1 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple x86_64-- -target-feature +sse4.1 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-unknown"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_slli_si128(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %pslldq = shufflevector <16 x i8> zeroinitializer, <16 x i8> %1, <16 x i32> <i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26>
# |   %2 = bitcast <16 x i8> %pslldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_slli_si128_0(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %pslldq = shufflevector <16 x i8> zeroinitializer, <16 x i8> %1, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
# |   %2 = bitcast <16 x i8> %pslldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_slli_si128_16(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   ret <2 x i64> zeroinitializer
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_srli_si128(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %psrldq = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20>
# |   %2 = bitcast <16 x i8> %psrldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_srli_si128_0(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %psrldq = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
# |   %2 = bitcast <16 x i8> %psrldq to <2 x i64>
# |   ret <2 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i64> @test_mm_srli_si128_16(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 16
# |   store <2 x i64> %a, ptr %a.addr, align 16
# |   %0 = load <2 x i64>, ptr %a.addr, align 16
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   ret <2 x i64> zeroinitializer
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="128" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+sse3,+sse4.1,+ssse3,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8a989a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d8a98970f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d8a989a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f68fd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68fd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f68fd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f68fd71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8a982fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d8a982fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d8a9814b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d8a94c40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d8a94c3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f68fd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68fd71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68fd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8a94c3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c (2642 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557572b3515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557572b320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557572b3589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f606ad05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f606ad5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f606ad05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f606aced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557572acae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557572acac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557572aafb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055757275f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055757275edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f606aceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f606acef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f606acef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055757275ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c (2643 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e471f0515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e471f020f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e471f0589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9676a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9676aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9676a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9676a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e471e9ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e471e9ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e471e7fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e471b2f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e471b2edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9676a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9676a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9676a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e471b2ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c (2644 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vundefined_bf16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vundefined_bf16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vundefined_bf16m1() #0 {
# | entry:
# |   ret <vscale x 4 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vundefined_bf16m2() #0 {
# | entry:
# |   ret <vscale x 8 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vundefined_bf16m4() #0 {
# | entry:
# |   ret <vscale x 16 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vundefined_bf16m8() #0 {
# | entry:
# |   ret <vscale x 32 x bfloat> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vundefined_bf16mf4x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vundefined_bf16mf4x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vundefined_bf16mf4x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vundefined_bf16mf4x5() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vundefined_bf16mf4x6() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vundefined_bf16mf4x7() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vundefined_bf16mf4x8() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vundefined_bf16mf2x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vundefined_bf16mf2x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vundefined_bf16mf2x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vundefined_bf16mf2x5() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vundefined_bf16mf2x6() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vundefined_bf16mf2x7() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vundefined_bf16mf2x8() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vundefined_bf16m1x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vundefined_bf16m1x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vundefined_bf16m1x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vundefined_bf16m1x5() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vundefined_bf16m1x6() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vundefined_bf16m1x7() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vundefined_bf16m1x8() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vundefined_bf16m2x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vundefined_bf16m2x3() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vundefined_bf16m2x4() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vundefined_bf16m4x2() #0 {
# | entry:
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558fb0a2615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558fb0a230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558fb0a2689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b62105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b6215c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b62105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b620ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558fb09bbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558fb09bbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558fb09a0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558fb06500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558fb064fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5b620eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b620ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b620ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558fb064fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c (2645 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055591111b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005559111180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055591111b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe384049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3840a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe384049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe384031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005559110b0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005559110b0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555911095b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555910d450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555910d44dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe384032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3840330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3840330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555910d44cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c (2646 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e4718915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563e471860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563e4718989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b8dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b8dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b8dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b8dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e4711ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563e4711ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563e47103b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563e46db30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563e46db2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3b8dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b8dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b8dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e46db2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c (2647 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606b4c1115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005606b4c0e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005606b4c1189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1f68133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1f6818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1f68133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1f6811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606b4ba6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005606b4ba6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005606b4b8bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005606b483b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005606b483add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1f6811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1f6811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1f6811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606b483acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c (2648 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d27c09915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d27c0960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d27c09989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6737649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67376a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6737649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6737631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d27c02ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d27c02ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d27c013b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d27bcc30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d27bcc2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6737632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67376330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67376330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d27bcc2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c (2649 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055924aff615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055924aff30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055924aff689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff7fb649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7fb6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff7fb649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff7fb631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055924af8be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055924af8bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055924af70b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055924ac200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055924ac1fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff7fb632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7fb6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7fb6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055924ac1fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c (2650 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fbea62215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fbea61f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fbea62289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6f59d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6f59d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6f59d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6f59d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fbea5b7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fbea5b7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fbea59cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fbea24c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fbea24bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6f59d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6f59d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6f59d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fbea24bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c (2651 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = l
# | ...
# `---data was truncated (10240/64341) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005566b97c315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005566b97c00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005566b97c389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92b4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92b458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92b4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92b451b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005566b9758e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005566b9758c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005566b973db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005566b93ed0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005566b93ecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f92b451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92b451d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92b451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566b93eccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c (2652 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmax_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmax.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmax_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmax.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmax_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmax.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmax_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmax.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmax_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>
# | ...
# `---data was truncated (10240/29062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557bb26ef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557bb26ec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557bb26ef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c13333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c1338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c13333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c1331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557bb2684e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557bb2684c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557bb2669b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557bb23190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557bb2318dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0c1331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c1331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c1331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557bb2318cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c (2653 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3f828515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c3f82820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c3f828589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1409f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1409f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1409f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1409f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3f821ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c3f821ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c3f81ffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c3f7eaf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c3f7eaedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1409f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1409f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1409f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3f7eaecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c (2654 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulhsu_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i
# | ...
# `---data was truncated (10240/223809) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636e0afb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005636e0af80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005636e0afb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff86ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff86ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff86ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff86ef1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636e0a90e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005636e0a90c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005636e0a75b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005636e07250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005636e0724dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff86ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff86ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff86ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636e0724cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c (2655 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffb(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.ffb.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffb.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffzmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.ffzmism.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffzmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_ffmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.ffmism.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.ffmism.i32(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_flmism(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.riscv.nds.flmism.i32(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i32 @llvm.riscv.nds.flmism.i32(i32, i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ca297915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559ca29760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559ca297989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f630cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f630cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f630cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f630cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ca290ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559ca290ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559ca28f3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559ca25a30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559ca25a2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f630cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f630cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f630cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ca25a2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c (2656 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2(<vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1(<vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2(<vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4(<vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8(<vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfa4e2515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dfa4e220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dfa4e2589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ee6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ee638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ee6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ee631b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfa4dbae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dfa4dbac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dfa4d9fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dfa4a4f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dfa4a4edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7ee631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ee631d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ee631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfa4a4ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c (2657 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei8_v_bf16m1x4_tum(<v
# | ...
# `---data was truncated (10240/25687) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055883f5b915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055883f5b60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055883f5b989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f71fdc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71fdca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f71fdc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f71fdc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055883f54ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055883f54ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055883f533b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055883f1e30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055883f1e2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f71fdc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71fdc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71fdc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055883f1e2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c (2658 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f16m1x6(ptr noundef %base, <vscale x 4 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f32m1x6(ptr noundef %base, <vscale x 2 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_f64m1x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i16> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxseg6ei16_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i16> %bindex, targe
# | ...
# `---data was truncated (10240/70394) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fcc030415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fcc03010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fcc030489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe29a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe29a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe29a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe29a51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fcc0299e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fcc0299c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fcc027eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fcbff2e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fcbff2ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe29a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe29a51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe29a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fcbff2dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c (2659 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df5dabd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055df5daba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055df5dabd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f57b0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f57b018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f57b0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f57b011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df5da52e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055df5da52c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055df5da37b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055df5d6e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055df5d6e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f57b011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f57b011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f57b011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df5d6e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c (2660 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = loa
# | ...
# `---data was truncated (10240/23447) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555706b1b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555706b180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555706b1b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0462733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f046278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0462733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f046271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555706ab0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555706ab0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555706a95b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005557067450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555706744dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f046271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f046271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f046271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555706744cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c (2661 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32ff_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32ff_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32ff_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base
# | ...
# `---data was truncated (10240/60683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c46f6ba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c46f6b70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c46f6ba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff37049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff370a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff37049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff37031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c46f64fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c46f64fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c46f634b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c46f2e40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c46f2e3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007eff37032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff370330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff370330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c46f2e3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp (2662 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2    -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-none-linux-gnu"
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @in_zt0() #0 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @out_zt0() #1 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @inout_zt0() #2 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @preserves_zt0() #3 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @new_zt0() #4 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @in_za_zt0() #5 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @out_za_zt0() #6 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @inout_za_zt0() #7 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @preserves_za_zt0() #8 {
# | entry:
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind
# | define dso_local void @new_za_zt0() #9 {
# | entry:
# |   ret void
# | }
# | 
# | attributes #0 = { mustprogress noinline nounwind "aarch64_in_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #1 = { mustprogress noinline nounwind "aarch64_out_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #2 = { mustprogress noinline nounwind "aarch64_inout_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #3 = { mustprogress noinline nounwind "aarch64_preserves_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #4 = { mustprogress noinline nounwind "aarch64_new_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #5 = { mustprogress noinline nounwind "aarch64_in_za" "aarch64_in_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #6 = { mustprogress noinline nounwind "aarch64_out_za" "aarch64_out_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #7 = { mustprogress noinline nounwind "aarch64_inout_za" "aarch64_inout_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #8 = { mustprogress noinline nounwind "aarch64_preserves_za" "aarch64_preserves_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | attributes #9 = { mustprogress noinline nounwind "aarch64_new_za" "aarch64_new_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df49eab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055df49ea80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055df49eab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7d4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7d4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7d4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7d4c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df49e40e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055df49e40c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055df49e25b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055df49ad50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055df49ad4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe7d4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7d4c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7d4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df49ad4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline
# |  #0 0x0000564352fd715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564352fd40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564352fd789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22f4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22f4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22f4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22f4d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564352f6ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564352f6cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564352f51b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564352c010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564352c00dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f22f4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22f4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22f4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564352c00cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c (2663 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tu(<vscale x 1 x half> %vd, half noundef %rs1, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half>, half, <vscale x 1 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tu(<vscale x 2 x half> %vd, half noundef %rs1, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half>, half, <vscale x 2 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tu(<vscale x 4 x half> %vd, half noundef %rs1, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half>, half, <vscale x 4 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tu(<vscale x 8 x half> %vd, half noundef %rs1, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %rs1.addr = alloca half, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store half %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load half, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half>, half, <vscale x 8 x half>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tu(<vscale x 16 x half> %vd, <vsc
# | ...
# `---data was truncated (10240/295319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005600e43d915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005600e43d60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005600e43d989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9a9105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9a915c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9a9105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9a90ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005600e436ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005600e436ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005600e4353b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005600e40030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005600e4002dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa9a90eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9a90ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9a90ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005600e4002cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c (2664 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c280f1515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c280f120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c280f1589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa195933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa19598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa195933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa19591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c280eaae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c280eaac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c280e8fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c280b3f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c280b3edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa19591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa19591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa19591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c280b3ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c (2665 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksed -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c  -check-prefix=RV32ZKSED
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksed -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm4ks(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.sm4ks(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm4ks(i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm4ed(i32 noundef %rs1, i32 noundef %rs2) #0 {
# | entry:
# |   %rs1.addr = alloca i32, align 4
# |   %rs2.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i32 %rs2, ptr %rs2.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   %1 = load i32, ptr %rs2.addr, align 4
# |   %2 = call i32 @llvm.riscv.sm4ed(i32 %0, i32 %1, i32 0)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm4ed(i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zksed" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zksed1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f97031815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f9703150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f97031889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12f3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12f3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12f3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12f3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9702ade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f9702adc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f970292b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f96ff420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f96ff41dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f12f3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12f3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12f3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f96ff41cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c (2666 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_i8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_i8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_i8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_i8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_i8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_i8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8>, <vscale x 32 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vncvt_x_x_w_u8mf8(<vscale x 1 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vncvt_x_x_w_u8mf4(<vscale x 2 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vncvt_x_x_w_u8mf2(<vscale x 4 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vncvt_x_x_w_u8m1(<vscale x 8 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vncvt_x_x_w_u8m2(<vscale x 16 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vncvt_x_x_w_u8m4(<vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i16> %0, i64 0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vncvt_x_x_w_i16mf4(<vscale x 1 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i32> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(<vscale x 1 x i16>, <vscale x 1 x i32>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vncvt_x_x_w_i16mf2(<vscale x 2 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64(<vscale x 2 x i16> po
# | ...
# `---data was truncated (10240/50898) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005587a95d315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005587a95d00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005587a95d389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f536ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f536aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f536ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f536ac31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005587a9568e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005587a9568c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005587a954db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005587a91fd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005587a91fcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f536ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f536ac330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f536ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005587a91fccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c (2667 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b420f7415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b420f710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b420f7489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5163505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f516355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5163505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51634ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b420f09e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b420f09c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b420eeeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b420b9e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b420b9ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f51634eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51634ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51634ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b420b9dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c (2668 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564269b8415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564269b810f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564269b8489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4113933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f411398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4113933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f411391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564269b19e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564269b19c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564269afeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005642697ae0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005642697addd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f411391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f411391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f411391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642697adcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c (2669 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056464b76215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056464b75f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056464b76289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa650505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa65055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa650505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6504ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056464b6f7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056464b6f7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056464b6dcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056464b38c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056464b38bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa6504eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6504ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6504ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056464b38bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c (2670 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/65072) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056040336815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005604033650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056040336889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f280bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f280bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f280bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f280bb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604032fde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005604032fdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005604032e2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560402f920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560402f91dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f280bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f280bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f280bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560402f91cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c (2671 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee9b13815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ee9b1350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ee9b13889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1115333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f111538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1115333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f111531b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee9b0cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ee9b0cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ee9b0b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ee9ad620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ee9ad61dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f111531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f111531d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f111531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee9ad61cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c (2672 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ed52ba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560ed52b70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560ed52ba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45f141bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45f14725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45f141ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45f1403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ed524fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560ed524fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560ed5234b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560ed4ee40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560ed4ee3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f45f1404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45f14050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45f14050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ed4ee3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c (2673 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei64_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei64_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dde038415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dde03810f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dde038489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff727049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7270a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff727049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff727031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dde0319e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dde0319c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dde02feb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dddffae0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dddffaddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff727032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7270330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7270330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dddffadcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c (2674 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_u16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005556b570b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005556b57080f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005556b570b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5331f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5331f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5331f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5331f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005556b56a0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005556b56a0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005556b5685b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005556b53350b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005556b5334dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5331f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5331f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5331f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005556b5334cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c (2675 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564626d5b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564626d580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564626d5b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0708933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f070898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0708933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f070891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564626cf0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564626cf0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564626cd5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005646269850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564626984dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f070891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f070891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f070891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564626984cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c (2676 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load
# | ...
# `---data was truncated (10240/14493) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561111f8515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561111f820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561111f8589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13a881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13a88725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13a881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13a8803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561111f1ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561111f1ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561111effb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561111baf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561111baedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f13a8804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13a88050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13a88050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561111baecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c (2677 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4r_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4r_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4r_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4r_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4r_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare 
# | ...
# `---data was truncated (10240/20139) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a271aae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a271aab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a271aae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff22ff05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff22ff5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff22ff05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff22feed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a271a43e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a271a43c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a271a28b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a2716d80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a2716d7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff22feeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff22feef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff22feef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a2716d7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c (2678 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c20b5b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c20b5b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c20b5b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51f0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51f0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51f0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51f0b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c20b54ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c20b54cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c20b531b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c20b1e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c20b1e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f51f0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51f0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51f0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c20b1e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c (2679 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055624faba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055624fab70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055624faba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbea9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbea96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbea9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbea9631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055624fa4fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055624fa4fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055624fa34b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055624f6e40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055624f6e3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbea9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbea96330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbea96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055624f6e3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c (2680 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055978a53715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055978a5340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055978a53789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb826133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb82618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb826133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb82611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055978a4cce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055978a4ccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055978a4b1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055978a1610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055978a160dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb82611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb82611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb82611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055978a160cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c (2681 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m4x2(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   
# | ...
# `---data was truncated (10240/13255) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac0a52315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ac0a5200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ac0a52389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7005649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70056a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7005649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7005631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac0a4b8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ac0a4b8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ac0a49db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ac0a14d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ac0a14cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7005632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70056330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70056330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac0a14ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c (2682 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_u16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("ri
# | ...
# `---data was truncated (10240/47480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005640418a215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056404189f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005640418a289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fb0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fb08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fb0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fb0831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564041837e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564041837c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056404181cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005640414cc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005640414cbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9fb0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fb08330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fb08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005640414cbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c (2683 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_bf16m4_u8m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_bf16m8_u8m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8
# | ...
# `---data was truncated (10240/24320) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055925729615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005592572930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055925729689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12d7a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12d7aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12d7a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12d7a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055925722be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055925722bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559257210b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559256ec00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559256ebfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f12d7a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12d7a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12d7a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559256ebfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c (2684 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d6f6ad615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d6f6ad30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d6f6ad689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4572d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4572d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4572d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4572d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d6f6a6be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d6f6a6bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d6f6a50b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d6f67000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d6f66ffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4572d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4572d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4572d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d6f66ffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c (2685 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f5238415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557f523810f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557f5238489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6191a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6191aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6191a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6191a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f52319e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557f52319c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557f522feb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557f51fae0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557f51faddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6191a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6191a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6191a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f51fadcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c (2686 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1(<vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> poison, <vscale x 1 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1(<vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1(<vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1(<vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1(<vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> poison, <vscale x 16 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1(<vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> poison, <vscale x 32 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1(<vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1(<vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m2_f32m1(<vscale x 4 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define
# | ...
# `---data was truncated (10240/37564) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055611b98215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055611b97f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055611b98289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb55c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb55c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb55c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb55c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055611b917e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055611b917c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055611b8fcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055611b5ac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055611b5abdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb55c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb55c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb55c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055611b5abcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c (2687 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e32cc3515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e32cc320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e32cc3589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e28733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e2878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e28733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e2871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e32cbcae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e32cbcac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e32cbafb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e32c85f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e32c85edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1e2871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e2871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e2871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e32c85ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c (2688 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c  -check-prefix=RV32ZKSH
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm3p0(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sm3p0(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @sm3p1(i32 noundef %rs1) #0 {
# | entry:
# |   %__x.addr.i = alloca i32, align 4
# |   %rs1.addr = alloca i32, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   %0 = load i32, ptr %rs1.addr, align 4
# |   store i32 %0, ptr %__x.addr.i, align 4
# |   %1 = load i32, ptr %__x.addr.i, align 4
# |   %2 = call i32 @llvm.riscv.sm3p1(i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm3p0(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.riscv.sm3p1(i32) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zksh" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_zksh1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563fe111615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563fe11130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563fe111689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7afd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7afd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7afd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7afd51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563fe10abe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563fe10abc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563fe1090b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563fe0d400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563fe0d3fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7afd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7afd51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7afd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563fe0d3fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c (2689 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a7cd9b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a7cd9ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a7cd9b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad02f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad02f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad02f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad02f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a7cd946e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a7cd946c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a7cd92bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a7cd5db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a7cd5dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fad02f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad02f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad02f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a7cd5dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c (2690 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bcd41715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562bcd4140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562bcd41789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f269341bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26934725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f269341ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2693403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bcd3ace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562bcd3acc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562bcd391b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562bcd0410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562bcd040dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2693404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26934050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26934050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562bcd040cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c (2691 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056488a7a415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056488a7a10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056488a7a489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5170d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5170d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5170d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5170d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056488a739e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056488a739c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056488a71eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056488a3ce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056488a3cddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5170d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5170d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5170d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056488a3cdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c (2692 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4
# | ...
# `---data was truncated (10240/47636) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602c4bf715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005602c4bf40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005602c4bf789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f940b705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f940b75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f940b705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f940b6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602c4b8ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005602c4b8cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005602c4b71b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005602c48210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005602c4820dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f940b6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f940b6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f940b6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602c4820cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c (2693 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrec7_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrec7_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrec7_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrec7_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrec7_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrec7_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrec7_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrec7_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrec7_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrec7_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfrec7_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfrec7_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define d
# | ...
# `---data was truncated (10240/51420) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9fe57115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a9fe56e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a9fe57189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd821905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd82195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd821905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd8218ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9fe506e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a9fe506c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a9fe4ebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a9fe19b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a9fe19add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd8218eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd8218ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd8218ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9fe19acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c (2694 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vv_f16mf4(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsgnj_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vv_f16mf2(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsgnj_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnj.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vv_f16m1(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsgnj_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnj.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vv_f16m2(<vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsgnj_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnj.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vv_f16m4(<vscale x 16 x half> %op1, <vscale x 16 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsgnj_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfsgnj.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale 
# | ...
# `---data was truncated (10240/69495) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec643ec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ec643e90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ec643ec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90c8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90c838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90c8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90c831b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec64381e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ec64381c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ec64366b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ec640160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ec64015dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f90c831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90c831d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90c831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec64015cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c (2695 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte8.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c9b5cd315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c9b5cd00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c9b5cd389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd58a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd58a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd58a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd58a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c9b5c68e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c9b5c68c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c9b5c4db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c9b58fd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c9b58fcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd58a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd58a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd58a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c9b58fccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c (2696 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564fcdfbe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564fcdfbb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564fcdfbe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb77cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb77cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb77cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb77cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564fcdf53e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564fcdf53c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564fcdf38b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564fcdbe80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564fcdbe7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb77cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb77cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb77cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564fcdbe7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c (2697 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf2_vi_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf2.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf2_vi_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf2.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf2_vi_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf2.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf2_vi_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf2.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf2_vi_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf2.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005650a22dc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005650a22d90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005650a22dc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd264f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd264f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd264f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd264f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005650a2271e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005650a2271c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005650a2256b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005650a1f060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005650a1f05dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd264f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd264f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd264f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005650a1f05cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c (2698 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvt_rod_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvt_rod_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvt_rod_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvt_rod_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# | 
# | ...
# `---data was truncated (10240/23255) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580bcb9615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005580bcb930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005580bcb9689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff16c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff16c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff16c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff16c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580bcb2be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005580bcb2bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005580bcb10b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005580bc7c00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005580bc7bfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff16c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff16c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff16c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580bc7bfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c (2699 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f16m1x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f16m2x4(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f32m1x4(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_f32m2x4(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_f64m1x4(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563b6315215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563b6314f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563b6315289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3500c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3500ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3500c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3500c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563b630e7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563b630e7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563b630ccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563b62d7c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563b62d7bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3500c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3500c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3500c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563b62d7bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c (2700 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64ff_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64ff_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple",
# | ...
# `---data was truncated (10240/40860) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558113fc815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558113fc50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558113fc889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0168849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f01688a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0168849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0168831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558113f5de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558113f5dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558113f42b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558113bf20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558113bf1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0168832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f01688330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f01688330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558113bf1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c (2701 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_i8m8(ptr noundef %base, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf8(ptr noundef %base, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf4(ptr noundef %base, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8mf2(ptr noundef %base, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m1(ptr noundef %base, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i8.p0.i64(<vscale x 8 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m2(ptr noundef %base, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i8.p0.i64(<vscale x 16 x i8> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse8_v_u8m4(ptr noundef %base, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32i8.p0.i64(<vscale x 32 x i8> %1, ptr %0, i64 %2)
# |   ret 
# | ...
# `---data was truncated (10240/25287) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005603fdcd715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005603fdcd40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005603fdcd789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2352649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23526a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2352649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2352631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005603fdc6ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005603fdc6cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005603fdc51b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005603fd9010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005603fd900dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2352632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23526330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23526330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005603fd900cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c (2702 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f  -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f  -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone  -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w2_f16m8(<vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, <vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2, i64 %3, i64 %4, i64 2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 immarg, <vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f32m8(<vscale x 16 x float> %vs2, <vscale x 16 x float> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 16 x float>, align 4
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, <vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 immarg, <vscale x 16 x float>, <vscale x 16 x float>, i64, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_mm_f_f_w1_f64m8(<vscale x 8 x double> %vs2, <vscale x 8 x double> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x double>, align 8
# |   %vs1.addr = alloca <vscale x 8 x double>, align 8
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x double> %vs1, ptr %vs1.addr, align 8
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, <vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2, i64 %3, i64 %4, i64 1)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 immarg, <vscale x 8 x double>, <vscale x 8 x double>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfmm32a16f,+xsfmm32a32f,+xsfmm64a64f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl32b1p0_zvl64b1p0_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm64a64f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e3ce3b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557e3ce380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557e3ce3b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb213f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb213f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb213f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb213f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e3cdd0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557e3cdd0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557e3cdb5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557e3ca650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557e3ca64dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb213f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb213f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb213f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e3ca64cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c (2703 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.ve
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f04569b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f0456980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f04569b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f432fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f432fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f432fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f432fc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f045630e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f045630c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f045615b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f0452c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f0452c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f432fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f432fc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f432fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0452c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c (2704 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vhadd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vhadd.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8> %0, <16 x i8> %.splat, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> 
# | ...
# `---data was truncated (10240/16951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055930d13b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055930d1380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055930d13b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd91e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd91ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd91e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd91e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055930d0d0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055930d0d0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055930d0b5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055930cd650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055930cd64dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcd91e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd91e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd91e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055930cd64cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c (2705 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e16_v_u16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/26921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642a95da15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005642a95d70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005642a95da89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe404d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe404d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe404d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe404d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642a956fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005642a956fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005642a9554b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005642a92040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005642a9203dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe404d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe404d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe404d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642a9203cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c (2706 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005617a484c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005617a48490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005617a484c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd3b5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3b5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd3b5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3b5d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005617a47e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005617a47e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005617a47c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005617a44760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005617a4475dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd3b5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3b5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3b5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005617a4475cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c (2707 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei32_v
# | ...
# `---data was truncated (10240/160911) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f6a4c7b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f6a4c780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f6a4c7b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54f4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54f4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54f4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54f4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6a4c10e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f6a4c10c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f6a4bf5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f6a48a50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f6a48a4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f54f4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54f4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54f4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6a48a4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c (2708 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c  -check-prefix=RV32XTHEADBB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clz_32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 false)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @clo_32(i32 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %not = xor i32 %0, -1
# |   %1 = call i32 @llvm.ctlz.i32(i32 %not, i1 false)
# |   ret i32 %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xtheadbb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_xtheadbb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e920fa015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e920f9d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e920fa089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc48dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc48dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc48dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc48dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e920f35e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e920f35c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e920f1ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e920bca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e920bc9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc48dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc48dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc48dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e920bc9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c (2709 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563335e9415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563335e910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563335e9489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6067049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60670a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6067049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6067031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563335e29e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563335e29c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563335e0eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563335abe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563335abddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6067032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60670330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60670330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563335abdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c (2710 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local t
# | ...
# `---data was truncated (10240/36031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd9dcd715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bd9dcd40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bd9dcd789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe574b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe574b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe574b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe574b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd9dc6ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bd9dc6cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bd9dc51b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bd9d9010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bd9d900dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe574b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe574b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe574b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd9d900cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c (2711 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648cf14315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005648cf1400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005648cf14389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3192333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f319238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3192333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f319231b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648cf0d8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005648cf0d8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005648cf0bdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005648ced6d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005648ced6cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f319231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f319231d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f319231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648ced6ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c (2712 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055840ed7315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055840ed700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055840ed7389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa880f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa880f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa880f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa880f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055840ed08e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055840ed08c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055840ecedb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055840e99d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055840e99cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa880f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa880f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa880f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055840e99ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c (2713 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0
# | ...
# `---data was truncated (10240/10425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631d39cd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005631d39ca0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005631d39cd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa569f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa569f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa569f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa569f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631d3962e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005631d3962c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005631d3947b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005631d35f70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005631d35f6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa569f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa569f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa569f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631d35f6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c (2714 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei8_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   st
# | ...
# `---data was truncated (10240/11797) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557be0bb915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557be0bb60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557be0bb989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff13a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff13a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff13a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff13a831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557be0b4ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557be0b4ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557be0b33b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557be07e30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557be07e2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff13a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff13a8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff13a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557be07e2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c (2715 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dots_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dots_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dots_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dots_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dots_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dots_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dots_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dots_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv1
# | ...
# `---data was truncated (10240/47628) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636d3fb115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005636d3fae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005636d3fb189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9271333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f927138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9271333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f927131b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636d3f46e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005636d3f46c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005636d3f2bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005636d3bdb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005636d3bdadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f927131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f927131d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f927131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636d3bdacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c (2716 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589f0c0b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005589f0c080f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005589f0c0b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4165133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f416518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4165133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f416511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589f0ba0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005589f0ba0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005589f0b85b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005589f08350b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005589f0834dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f416511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f416511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f416511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589f0834cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c (2717 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @eq_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %cmp = icmp eq <32 x i8> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i8>
# |   store <32 x i8> %sext, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @eq_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %cmp = icmp eq <16 x i16> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x i16>
# |   store <16 x i16> %sext, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @eq_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %cmp = icmp eq <8 x i32> %0, %1
# |   %sext = sext <8 x i1> %cmp to <8 x i32>
# |   store <8 x i32> %sext, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @eq_i64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %cmp = icmp eq <4 x i64> %0, %1
# |   %sext = sext <4 x i1> %cmp to <4 x i64>
# |   store <4 x i64> %sext, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64>, <4 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @eq_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %cmp = icmp eq <32 x i8> %0, %1
# |   %sext = sext <32 x i1> %cmp to <32 x i8>
# |   store <32 x i8> %sext, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @eq_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %cmp = icmp eq <16 x i16> %0, %1
# |   %sext = sext <16 x i1> %cmp to <16 x i16>
# |   store <16 x i16> %sext, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @eq_u32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %cmp = icmp eq <8 x i32> %0, %1
# |   %sext = sext <8 x i1> %cmp to <8 x i32>
# |   store <8 x i32> %sext, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @eq_u64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %cmp = icmp eq <4 x i64> %0, %1
# |   %sext = sext <4 x i1> %cmp to <4 x i64>
# |   store <4 x i64> %sext, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @eq_f32(<vscale x 2 x float> noundef %a.coerce, <vscale x 2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x float>, align 8
# |   %b.addr = alloca <8 x float>, align 8
# |   %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %a.coerce, i64 0)
# |   %b = call <8 x float> 
# | ...
# `---data was truncated (10240/63117) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x0000558c847ff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558c847fc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558c847ff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80a4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80a4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80a4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80a4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c84794e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558c84794c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558c84779b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558c844290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558c84428dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f80a4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80a4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80a4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c84428cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c (2718 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_f16mf4x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f16mf2x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f16m1x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f16m2x3(ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_f32mf2x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f32m1x3(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_f32m2x3(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_f64m1x3(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i
# | ...
# `---data was truncated (10240/87892) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056529c7ee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056529c7eb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056529c7ee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f421ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f421cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f421ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f421ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056529c783e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056529c783c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056529c768b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056529c4180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056529c417dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f421ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f421ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f421ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056529c417cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c (2719 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredosum_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 7, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredosum_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, al
# | ...
# `---data was truncated (10240/81312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c96c7615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556c96c730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556c96c7689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b3d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b3d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b3d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b3d71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c96c0be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556c96c0bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556c96bf0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556c968a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556c9689fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1b3d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b3d71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b3d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c9689fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c (2720 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056088a8a315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056088a8a00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056088a8a389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe85c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe85c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe85c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe85c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056088a838e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056088a838c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056088a81db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056088a4cd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056088a4ccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe85c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe85c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe85c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056088a4cccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c (2721 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b02d0d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556b02d0a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556b02d0d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f599c105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f599c15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f599c105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f599c0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b02ca2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556b02ca2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556b02c87b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556b029370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556b02936dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f599c0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f599c0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f599c0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b02936cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c (2722 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.
# | ...
# `---data was truncated (10240/18972) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e651fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556e651f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556e651fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3aa733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3aa78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3aa733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3aa71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e65191e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556e65191c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556e65176b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556e64e260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556e64e25dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff3aa71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3aa71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3aa71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e64e25cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vornq.c (2723 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vornq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = xor <16 x i8> %1, splat (i8 -1)
# |   %3 = or <16 x i8> %0, %2
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = xor <8 x i16> %1, splat (i16 -1)
# |   %3 = or <8 x i16> %0, %2
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = xor <4 x i32> %1, splat (i32 -1)
# |   %3 = or <4 x i32> %0, %2
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vornq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = xor <4 x i32> %3, splat (i32 -1)
# |   %5 = or <4 x i32> %1, %4
# |   %6 = bitcast <4 x i32> %5 to <4 x float>
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vornq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x half>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %inactive, ptr %inactive.addr, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <8 x i16>
# |   %2 = load <8 x half>, ptr %b.addr, align 8
# |   %3 = bitcast <8 x half> %2 to <8 x i16>
# |   %4 = load i16, ptr %p.addr, align 2
# |   %5 = zext i16 %4 to i32
# |   %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5)
# |   %7 = load <8 x half>, ptr %inactive.addr, align 8
# |   %8 = bitcast <8 x half> %7 to <8 x i16>
# |   %9 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8)
# |   %10 = bitcast <8 x i16> %9 to <8 x half>
# |   ret <8 x half> %10
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vornq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <4 x i32>
# |   %2 = load <4 x float>, ptr %b.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <4 x i32>
# |   %4 = load i16, ptr %p.addr, al
# | ...
# `---data was truncated (10240/11056) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557628f1915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557628f160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557628f1989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58ad533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58ad58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58ad533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58ad51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557628eaee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557628eaec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557628e93b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557628b430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557628b42dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f58ad51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58ad51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58ad51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557628b42cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c (2724 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4aus_vx_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4aus.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4aus_vx_i32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4aus.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4aus_vx_i32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4aus_vx_i32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4aus_vx_i32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/13649) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f0e70015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558f0e6fd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558f0e70089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f08bc41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f08bc4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f08bc41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f08bc403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f0e695e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558f0e695c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558f0e67ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558f0e32a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558f0e329dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f08bc404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f08bc4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f08bc4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f0e329cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c (2725 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vpairo_vv_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, <vscale x 1 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vs1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vpairo.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vpairo_vv_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, <vscale x 2 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vs1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vpairo.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vpairo_vv_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, <vscale x 4 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vs1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vpairo.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vpairo_vv_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, <vscale x 8 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vs1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vpairo.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vpairo_vv_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, <vscale x 16 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vs1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vpairo.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vpairo_vv_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, <vscale x 32 x half> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vs1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x half> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x half>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vpairo.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vpairo_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vpairo.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vpairo_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x float> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x float> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vpairo.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vpairo_vv_f32m2_tu
# | ...
# `---data was truncated (10240/288275) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d51e05415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d51e0510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d51e05489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98c9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98c998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98c9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98c991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d51dfe9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d51dfe9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d51dfceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d51dc7e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d51dc7ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f98c991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98c991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98c991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d51dc7dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c (2726 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vdiv_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vdiv_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vdiv.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vdiv_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vdiv.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vdiv_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vdiv.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vdiv_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/222483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563a8a0f615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563a8a0f30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563a8a0f689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc055a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc055a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc055a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc055a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563a8a08be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563a8a08bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563a8a070b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563a89d200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563a89d1fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc055a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc055a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc055a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563a89d1fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c (2727 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c8f8dae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c8f8dab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c8f8dae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0c07333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0c0738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0c07333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0c0731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8f8d43e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c8f8d43c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c8f8d28b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c8f89d80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c8f89d7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0c0731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0c0731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0c0731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c8f89d7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c (2728 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i32> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i32> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei32_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i
# | ...
# `---data was truncated (10240/13153) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555844acd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555844aca0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555844acd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6cb4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6cb418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6cb4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6cb411b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555844a62e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555844a62c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555844a47b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005558446f70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005558446f6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6cb411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6cb411d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6cb411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558446f6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c (2729 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a35663115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a35662e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a35663189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9203733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f920378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9203733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f920371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a3565c6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a3565c6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a3565abb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a35625b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a35625add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f920371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f920371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f920371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a35625acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c (2730 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a4389515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559a438920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559a4389589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8517133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f851718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8517133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f851711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a4382ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559a4382ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559a4380fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559a434bf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559a434bedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f851711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f851711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f851711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a434becc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c (2731 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_v_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_v_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_v_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_v_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_v_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmv_v_f_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16.i64(<vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmv_s_f_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.s.f.nxv1bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmv_s_f_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.s.f.nxv2bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmv_s_f_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.s.f.nxv4bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmv_s_f_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store bfloat %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load bfloat, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.s.f.nxv8bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmv_s_f_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %ma
# | ...
# `---data was truncated (10240/12656) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596b192f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005596b192c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005596b192f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c46849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c468a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c46849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c46831507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596b18c4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005596b18c4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005596b18a9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005596b15590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005596b1558dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2c46832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c468330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c468330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596b1558cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c (2732 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_i8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_i8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_i8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_i8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_i8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_i8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_u8mf8(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_u8mf4(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_u8mf2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_u8m1(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_xu_f_w_u8m2(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_xu_f_w_u8m4(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8>, <vscale x
# | ...
# `---data was truncated (10240/58661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564eb962415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564eb96210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564eb962489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fabfb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fabfb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fabfb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fabfb031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564eb95b9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564eb95b9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564eb959eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564eb924e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564eb924ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fabfb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fabfb0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fabfb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564eb924dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c (2733 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c38f8115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564c38f7e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564c38f8189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2c54d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2c54d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2c54d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2c54d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c38f16e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564c38f16c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564c38efbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564c38bab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564c38baadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2c54d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2c54d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2c54d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c38baacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c (2734 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056296556c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005629655690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056296556c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d37f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d37f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d37f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d37eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562965501e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562965501c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005629654e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005629651960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562965195dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4d37eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d37eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d37eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562965195cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c (2735 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f411d5215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f411d4f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f411d5289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f73e0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f73e098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f73e0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f73e091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f411ce7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f411ce7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f411cccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f41197c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f41197bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f73e091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f73e091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f73e091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f41197bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c (2736 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bf
# | ...
# `---data was truncated (10240/65202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f58b7c415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f58b7c10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f58b7c489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f15933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f1598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f15933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f1591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f58b759e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f58b759c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f58b73eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f58b3ee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f58b3eddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3f1591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f1591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f1591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f58b3edcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c (2737 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b1b42215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560b1b41f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560b1b42289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5d3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5d318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5d3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5d311b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b1b3b7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560b1b3b7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560b1b39cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560b1b04c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560b1b04bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc5d311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5d311d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5d311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b1b04bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c (2738 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d36886115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d36885e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d36886189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fcfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fcfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fcfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fcfb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3687f6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d3687f6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d3687dbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d36848b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d36848add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0fcfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fcfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fcfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d36848acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c (2739 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf8_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf8_i64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf8_i64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf8_i64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eedf48b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eedf4880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eedf48b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd55d61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd55d6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd55d61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd55d603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eedf420e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eedf420c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eedf405b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eedf0b50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eedf0b4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd55d604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd55d6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd55d6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eedf0b4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c (2740 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b26b30715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b26b3040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b26b30789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f38f0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f38f0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f38f0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f38f0c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b26b29ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b26b29cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b26b281b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b26af310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b26af30dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f38f0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f38f0c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f38f0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b26af30cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c (2741 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> 
# | ...
# `---data was truncated (10240/32133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559953c5d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559953c5a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559953c5d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb30b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb30b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb30b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb30aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559953bf2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559953bf2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559953bd7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005599538870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559953886dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ffb30aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb30aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb30aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559953886cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c (2742 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @
# | ...
# `---data was truncated (10240/60228) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e5d722d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e5d722a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e5d722d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0397333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f039738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0397333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f039731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e5d71c2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e5d71c2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e5d71a7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e5d6e570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e5d6e56dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f039731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f039731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f039731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e5d6e56cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c (2743 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056074ce4215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056074ce3f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056074ce4289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9550f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9550f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9550f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9550f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056074cdd7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056074cdd7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056074cdbcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056074ca6c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056074ca6bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9550f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9550f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9550f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056074ca6bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c (2744 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vloxei8_v_f16mf4_tu(<vscale x 1 x half> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vloxei8_v_f16mf2_tu(<vscale x 2 x half> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vloxei8_v_f16m1_tu(<vscale x 4 x half> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vloxei8_v_f16m2_tu(<vscale x 8 x half> %maskedoff, ptr noundef %base, <vscale x 8 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vloxei8_v_f16m4_tu(<vscale x 16 x half> %maskedoff, ptr noundef %base, <vscale x 16 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vloxei8_v_f16m8_tu(<vscale x 32 x half> %maskedoff, ptr noundef %base, <vscale x 32 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vloxei8_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vloxei8_v_f32m1_tu(<vscale x 2 x float> %maskedoff, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vloxei8_v_f32m2_tu(<vscale x 4 x float> %maskedoff, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.
# | ...
# `---data was truncated (10240/288058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c79663915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c7966360f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c79663989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5fd8a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5fd8a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5fd8a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5fd8a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7965cee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c7965cec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c7965b3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c7962630b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c796262dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5fd8a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5fd8a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5fd8a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c796262cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c (2745 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf4(ptr noundef %base, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16mf2(ptr noundef %base, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m1(ptr noundef %base, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m2(ptr noundef %base, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m4(ptr noundef %base, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_f16m8(ptr noundef %base, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf4(ptr noundef %base, <vscale x 1 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16mf2(ptr noundef %base, <vscale x 2 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m1(ptr noundef %base, <vscale x 4 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m2(ptr noundef %base, <vscale x 8 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m4(ptr noundef %base, <vscale x 16 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse16_v_i16m8(ptr noundef %base, <vscale x 32 x i16> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i16> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/33764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ae63dc615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ae63dc30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ae63dc689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5893333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f589338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5893333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f589331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ae63d5be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ae63d5bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ae63d40b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ae639f00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ae639efdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f589331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f589331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f589331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ae639efcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c (2746 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 2 x i8> @test_vmulhsu_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 4 x i8> @test_vmulhsu_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 8 x i8> @test_vmulhsu_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 16 x i8> @test_vmulhsu_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 32 x i8> @test_vmulhsu_vx_i8m4(<vscale x 32 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <vscale x 64 x i8> @test_vmulhsu_vv_i8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i8>, align 1
# |   %op2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 
# | ...
# `---data was truncated (10240/66065) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b89463815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b8946350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b89463889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff657133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff65718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff657133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff65711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8945cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b8945cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b8945b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b8942620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b894261dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff65711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff65711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff65711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b894261cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c (2747 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16ff_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16ff_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16ff_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { targ
# | ...
# `---data was truncated (10240/21111) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b43016c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b4301690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b43016c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f67afe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f67afea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f67afe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f67afe31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b430101e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b430101c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b4300e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b42fd960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b42fd95dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f67afe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f67afe330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f67afe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b42fd95cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c (2748 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0eaa9115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d0eaa8e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d0eaa9189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6fdb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6fdb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6fdb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6fdb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0eaa26e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d0eaa26c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d0eaa0bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d0ea6bb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d0ea6badd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6fdb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6fdb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6fdb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0ea6bacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c (2749 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedof
# | ...
# `---data was truncated (10240/40734) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558debce515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558debce20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558debce589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6926933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f692698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6926933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f692691b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558debc7ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558debc7ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558debc5fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558deb90f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558deb90edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f692691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f692691d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f692691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558deb90ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c (2750 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrdiv_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x 
# | ...
# `---data was truncated (10240/61066) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce35fec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ce35fe90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ce35fec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4846c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4846ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4846c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4846c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce35f81e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ce35f81c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ce35f66b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ce35c160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ce35c15dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4846c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4846c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4846c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce35c15cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c (2751 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055642cf5d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055642cf5a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055642cf5d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0240849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02408a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0240849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0240831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055642cef2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055642cef2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055642ced7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055642cb870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055642cb86dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0240832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02408330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02408330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055642cb86cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c (2752 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0da53e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b0da53b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b0da53e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23ba449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23ba4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23ba449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23ba431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b0da4d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b0da4d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b0da4b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b0da1680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b0da167dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f23ba432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23ba4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23ba4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b0da167cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c (2753 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vlse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.p0.i64(<vscale x 1 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vlse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.p0.i64(<vscale x 2 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vlse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.p0.i64(<vscale x 4 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vlse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.p0.i64(<vscale x 8 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vlse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.p0.i64(<vscale x 16 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vlse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.p0.i64(<vscale x 32 x half>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vlse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16.p0.i64(<vscale x 1 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vlse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16.p0.i64(<vscale x 2 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vlse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16.p0.i64(<vscale x 4 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vlse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16.p0.i64(<vscale x 8 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16.p0.i64(<vscale x 8 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vlse16_v_i16m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16.p0.i64(<vscale x 16 x i16> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16.p0.i64(<vscale x 16 x i16>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vlse16_v_
# | ...
# `---data was truncated (10240/35087) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aefccc615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aefccc30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aefccc689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23f8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23f82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23f8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23f8231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aefcc5be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aefcc5bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aefcc40b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aefc8f00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aefc8efdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f23f8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23f82330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23f82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aefc8efcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c (2754 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf7172315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cf717200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cf7172389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fece4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fece4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fece4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fece4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf716b8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cf716b8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cf7169db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cf7134d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cf7134cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fece4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fece4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fece4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf7134ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c (2755 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local vo
# | ...
# `---data was truncated (10240/26928) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005588e525c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005588e52590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005588e525c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f42905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f4295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f42905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f428ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005588e51f1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005588e51f1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005588e51d6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005588e4e860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005588e4e85dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4f428eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f428ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f428ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005588e4e85cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c (2756 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vlse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vlse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vlse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vlse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vlse16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vlse.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vlse.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vlse16_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vlse.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vlse.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559048ef515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559048ef20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559048ef589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7267c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7267ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7267c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7267c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559048e8ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559048e8ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559048e6fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559048b1f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559048b1edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7267c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7267c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7267c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559048b1ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c (2757 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captur
# | ...
# `---data was truncated (10240/30617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ec723715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556ec72340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556ec723789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6903933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f690398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6903933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f690391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556ec71cce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556ec71ccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556ec71b1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556ec6e610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556ec6e60dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f690391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f690391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f690391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556ec6e60cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c (2758 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8.i64(<vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8.i64(<vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8.i64(<vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vx_i8m1_b8(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8.i64(<vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vv_i8m2_b4(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmslt_vx_i8m2_b4(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8.i64(<vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmslt_vv_i8m4_b2(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %0, 
# | ...
# `---data was truncated (10240/95081) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557bf6dbc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557bf6db90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557bf6dbc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f815f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f815f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f815f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f815f831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557bf6d51e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557bf6d51c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557bf6d36b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557bf69e60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557bf69e5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f815f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f815f8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f815f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557bf69e5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c (2759 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsub_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsub_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsub_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsub_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <v
# | ...
# `---data was truncated (10240/64252) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb880da15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bb880d70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bb880da89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5682533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f568258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5682533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f568251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb8806fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bb8806fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bb88054b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bb87d040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bb87d03dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f568251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f568251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f568251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb87d03cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c (2760 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store targ
# | ...
# `---data was truncated (10240/14667) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653ef22815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005653ef2250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005653ef22889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4d22e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4d22ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4d22e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4d22e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653ef1bde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005653ef1bdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005653ef1a2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005653eee520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005653eee51dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4d22e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4d22e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4d22e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653eee51cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c (2761 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# | 
# | ...
# `---data was truncated (10240/100521) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005564b6b1515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005564b6b120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005564b6b1589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7b36305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7b3635c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7b36305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7b362ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005564b6aaae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005564b6aaac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005564b6a8fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005564b673f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005564b673edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7b362eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7b362ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7b362ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564b673ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c (2762 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdm_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdm_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdm_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdm_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdm_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d1c31ec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d1c31e90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d1c31ec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f49de249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49de2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f49de249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f49de231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d1c3181e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d1c3181c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d1c3166b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d1c2e160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d1c2e15dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f49de232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49de2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49de2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1c2e15cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c (2763 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056201fd7115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056201fd6e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056201fd7189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f92e3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f92e3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f92e3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f92e3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056201fd06e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056201fd06c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056201fcebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056201f99b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056201f99add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f92e3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f92e3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f92e3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056201f99acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c (2764 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558db8c7f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558db8c7c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558db8c7f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdfbc41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdfbc4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdfbc41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdfbc403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558db8c14e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558db8c14c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558db8bf9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558db88a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558db88a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdfbc404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdfbc4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdfbc4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558db88a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c (2765 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ffead0915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ffead060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ffead0989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f20ff449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f20ff4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f20ff449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f20ff431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ffeac9ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ffeac9ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ffeac83b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ffea9330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ffea932dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f20ff432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f20ff4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f20ff4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ffea932cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c (2766 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# | 
# | ...
# `---data was truncated (10240/64349) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d217e4b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d217e480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d217e4b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9f4d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9f4d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9f4d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9f4d51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d217de0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d217de0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d217dc5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d217a750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d217a74dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9f4d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9f4d51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9f4d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d217a74cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c (2767 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei8_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei8_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei8_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei8_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei8_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = loa
# | ...
# `---data was truncated (10240/14529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056087dfc915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056087dfc60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056087dfc989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa27fd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa27fd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa27fd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa27fced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056087df5ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056087df5ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056087df43b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056087dbf30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056087dbf2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa27fceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa27fcef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa27fcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056087dbf2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c (2768 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vv_i16mf4(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_vx_i16mf4(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wv_i16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwsub_wx_i16mf4(<vscale x 1 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vv_i16mf2(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_vx_i16mf2(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wv_i16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwsub_wx_i16mf2(<vscale x 2 x i16> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vv_i16m1(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_vx_i16m1(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwsub_wv_i16m
# | ...
# `---data was truncated (10240/134565) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055789d17715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055789d1740f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055789d17789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f790e41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f790e4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f790e41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f790e403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055789d10ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055789d10cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055789d0f1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055789cda10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055789cda0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f790e404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f790e4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f790e4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055789cda0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c (2769 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_u64m1x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_f64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e64_v_i64m1x6_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d68e2815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560d68e250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560d68e2889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2310b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2310b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2310b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2310b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d68dbde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560d68dbdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560d68da2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560d68a520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560d68a51dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2310b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2310b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2310b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d68a51cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c (2770 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005592448ff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005592448fc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005592448ff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f519841bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51984725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f519841ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5198403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559244894e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559244894c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559244879b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005592445290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559244528dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5198404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51984050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51984050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559244528cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c (2771 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_
# | ...
# `---data was truncated (10240/10396) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005636840ea15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005636840e70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005636840ea89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ff4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ff4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ff4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ff4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056368407fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056368407fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563684064b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563683d140b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563683d13dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8ff4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ff4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ff4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563683d13cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c (2772 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638fa19715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005638fa1940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005638fa19789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0bed333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0bed38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0bed333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0bed31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638fa12ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005638fa12cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005638fa111b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005638f9dc10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005638f9dc0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0bed31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0bed31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0bed31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638f9dc0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c (2773 of 27911)
******************** TEST 'Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wno-error=return-type -std=c99 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c -emit-llvm -o - |     /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wno-error=return-type -std=c99 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c -emit-llvm -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | @X = global i32 0, align 4
# | @Y = global i32 0, align 4
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local i32 @foo() #0 {
# | entry:
# |   %retval = alloca i32, align 4
# |   %i = alloca i32, align 4
# |   store i32 0, ptr %i, align 4
# |   br label %for.cond
# | 
# | for.cond:                                         ; preds = %for.inc, %entry
# |   %0 = load i32, ptr %i, align 4
# |   %cmp = icmp slt i32 %0, 100
# |   br i1 %cmp, label %for.body, label %for.end
# | 
# | for.body:                                         ; preds = %for.cond
# |   br label %for.end
# | 
# | for.inc:                                          ; No predecessors!
# |   %1 = load i32, ptr %i, align 4
# |   %inc = add nsw i32 %1, 1
# |   store i32 %inc, ptr %i, align 4
# |   br label %for.cond
# | 
# | for.end:                                          ; preds = %for.body, %for.cond
# |   %2 = load i32, ptr %retval, align 4
# |   ret i32 %2
# | }
# | 
# | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# .---command stderr------------
# | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c:13:1: warning: non-void function does not return a value [-Wreturn-type]
# |    13 | }
# |       | ^
# | 1 warning generated.
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output
# |  #0 0x00005567abb8a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005567abb870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005567abb8a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbbde649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbbde6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbbde649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbbde631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005567abb1fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005567abb1fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005567abb04b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005567ab7b40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005567ab7b3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbbde632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbbde6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbbde6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005567ab7b3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c (2774 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm4k_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm4k.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm4k_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm4k.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm4k_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm4k_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm4k_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056427362615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005642736230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056427362689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f604b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f604b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f604b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f604b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642735bbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005642735bbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005642735a0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005642732500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056427324fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f604b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f604b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f604b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056427324fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c (2775 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.ris
# | ...
# `---data was truncated (10240/60220) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6fdaa515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b6fdaa20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b6fdaa589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f39f2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39f278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f39f2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f39f271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6fda3ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b6fda3ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b6fda1fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b6fd6cf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b6fd6cedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f39f271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39f271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39f271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6fd6cecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c (2776 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_f16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_i16m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf4x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e16_v_u16mf2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_
# | ...
# `---data was truncated (10240/26936) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056543552415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005654355210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056543552489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5922b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5922b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5922b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5922b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654354b9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005654354b9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056543549eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056543514e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056543514ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5922b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5922b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5922b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056543514dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c (2777 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -target-feature +zve64d    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_bf16m8(i64 noundef %tss, <vscale x 32 x bfloat> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f16m8(i64 noundef %tss, <vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 %0, <vscale x 32 x half> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f32m8(i64 noundef %tss, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 %0, <vscale x 16 x float> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f64m8(i64 noundef %tss, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 %0, <vscale x 8 x double> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64, <vscale x 16 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_i64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u8m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x i8> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u16m8(i64 noundef %tss, <vscale x 32 x i16> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, <vscale x 32 x i16> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u32m8(i64 noundef %tss, <vscale x 16 x i32> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 16 x i32> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_u64m8(i64 noundef %tss, <vscale x 8 x i64> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 8 x i64> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_sf_vtmv_t_v_f8e4m3m8(i64 noundef %tss, <vscale x 64 x i8> %src, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, <vscale x 64 x 
# | ...
# `---data was truncated (10240/11632) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ff6bdb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562ff6bd80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562ff6bdb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5902049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59020a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5902049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5902031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ff6b70e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562ff6b70c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562ff6b55b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562ff68050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562ff6804dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5902032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59020330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59020330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ff6804cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c (2778 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_i8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_i8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e8ff_v_i8m1x7_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlseg7e8ff_v_u8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e8ff_v_u8mf4x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e8ff_v_u8mf2x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>,
# | ...
# `---data was truncated (10240/12668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055565547015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055565546d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055565547089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb145733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb14578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb145733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb14571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555655405e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555655405c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005556553eab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055565509a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555655099dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb14571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb14571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb14571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555655099cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c (2779 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x 
# | ...
# `---data was truncated (10240/26696) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d9eff1015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d9eff0d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d9eff1089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7f5fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7f5faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7f5fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7f5fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d9efea5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d9efea5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d9efe8ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d9efb3a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d9efb39dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7f5fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7f5fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7f5fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d9efb39cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c (2780 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei8_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei8_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/31938) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005616c1b3e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005616c1b3b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005616c1b3e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd69333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd6938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd69333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd6931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616c1ad3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005616c1ad3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005616c1ab8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005616c17680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005616c1767dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcd6931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd6931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd6931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005616c1767cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c (2781 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define d
# | ...
# `---data was truncated (10240/12208) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055609a89b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055609a8980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055609a89b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa3bc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa3bc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa3bc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa3bc631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055609a830e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055609a830c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055609a815b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055609a4c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055609a4c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa3bc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa3bc6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa3bc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055609a4c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c (2782 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf8x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf4x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8mf2x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_u8m1x8(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555db8a5715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555db8a540f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555db8a5789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5bb3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5bb36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5bb3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5bb3631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555db89ece2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555db89ecc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555db89d1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555db86810b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555db8680dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5bb3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5bb36330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5bb36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555db8680cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c (2783 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = loa
# | ...
# `---data was truncated (10240/18917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056381256d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056381256a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056381256d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa6a0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6a0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa6a0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa6a0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563812502e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563812502c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005638124e7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005638121970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563812196dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa6a0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6a0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6a0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563812196cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c (2784 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlsseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e8_v_u8m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_
# | ...
# `---data was truncated (10240/23574) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3862ea15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e3862e70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e3862ea89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9403f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9403f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9403f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9403f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e38627fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e38627fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e386264b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e385f140b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e385f13dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9403f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9403f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9403f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e385f13cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c (2785 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1down_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1down_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1down_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1down_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1down_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1down_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load 
# | ...
# `---data was truncated (10240/32702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005654233f215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005654233ef0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005654233f289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd317133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd31718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd317133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd31711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565423387e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565423387c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056542336cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056542301c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056542301bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd31711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd31711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd31711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056542301bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c (2786 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055611a33c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055611a3390f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055611a33c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02a4b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02a4b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02a4b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02a4aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055611a2d1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055611a2d1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055611a2b6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556119f660b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556119f65dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f02a4aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02a4aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02a4aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556119f65cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c (2787 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 32 x bfloat>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ...
# `---data was truncated (10240/14904) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4f4d1515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d4f4d120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d4f4d1589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2d9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2d9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2d9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2d9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4f4caae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d4f4caac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d4f4c8fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d4f493f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d4f493edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff2d9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2d9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2d9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4f493ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c (2788 of 27911)
******************** TEST 'Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature -fullfp16  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature -fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
# | target triple = "armv8.2a-unknown-linux-gnu"
# | 
# | %struct.float16x4x2_t = type { [2 x <4 x half>] }
# | %struct.float16x8x2_t = type { [2 x <8 x half>] }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <2 x i32> @test_vbsl_f16(<4 x i16> noundef %a, <2 x i32> noundef %b.coerce, <2 x i32> noundef %c.coerce) #0 {
# | entry:
# |   %retval.i = alloca <4 x half>, align 8
# |   %__p1.i = alloca <4 x half>, align 8
# |   %__p2.i = alloca <4 x half>, align 8
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__p2.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %retval = alloca <4 x half>, align 8
# |   %b = alloca <4 x half>, align 8
# |   %c = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %c.addr = alloca <4 x half>, align 8
# |   %coerce = alloca <4 x half>, align 8
# |   %coerce3 = alloca <4 x half>, align 8
# |   %coerce4 = alloca <4 x half>, align 8
# |   store <2 x i32> %b.coerce, ptr %b, align 8
# |   %b1 = load <4 x half>, ptr %b, align 8
# |   store <2 x i32> %c.coerce, ptr %c, align 8
# |   %c2 = load <4 x half>, ptr %c, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x half> %b1, ptr %b.addr, align 8
# |   store <4 x half> %c2, ptr %c.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   %2 = load <4 x half>, ptr %c.addr, align 8
# |   store <4 x half> %1, ptr %coerce, align 8
# |   %3 = load <2 x i32>, ptr %coerce, align 8
# |   store <4 x half> %2, ptr %coerce3, align 8
# |   %4 = load <2 x i32>, ptr %coerce3, align 8
# |   store <2 x i32> %3, ptr %__p1.i, align 8
# |   %__p11.i = load <4 x half>, ptr %__p1.i, align 8
# |   store <2 x i32> %4, ptr %__p2.i, align 8
# |   %__p22.i = load <4 x half>, ptr %__p2.i, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %__p11.i, ptr %__p1.addr.i, align 8
# |   store <4 x half> %__p22.i, ptr %__p2.addr.i, align 8
# |   %5 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %6 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %7 = load <8 x i8>, ptr %__p2.addr.i, align 8
# |   %vbsl_v.i = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %5, <8 x i8> %6, <8 x i8> %7)
# |   store <8 x i8> %vbsl_v.i, ptr %ref.tmp.i, align 8
# |   %8 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %8, ptr %__ret.i, align 8
# |   %9 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %9, ptr %retval.i, align 8
# |   %10 = load <2 x i32>, ptr %retval.i, align 8
# |   store <2 x i32> %10, ptr %coerce4, align 8
# |   %11 = load <4 x half>, ptr %coerce4, align 8
# |   store <4 x half> %11, ptr %retval, align 8
# |   %12 = load <2 x i32>, ptr %retval, align 8
# |   ret <2 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local <4 x i32> @test_vbslq_f16(<8 x i16> noundef %a, <4 x i32> noundef %b.coerce, <4 x i32> noundef %c.coerce) #0 {
# | entry:
# |   %retval.i = alloca <8 x half>, align 16
# |   %__p1.i = alloca <8 x half>, align 16
# |   %__p2.i = alloca <8 x half>, align 16
# |   %__p0.addr.i = alloca <8 x i16>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %__p2.addr.i = alloca <8 x half>, align 16
# |   %__ret.i = alloca <8 x half>, align 16
# |   %ref.tmp.i = alloca <16 x i8>, align 16
# |   %retval = alloca <8 x half>, align 16
# |   %b = alloca <8 x half>, align 16
# |   %c = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x i16>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %c.addr = alloca <8 x half>, align 16
# |   %coerce = alloca <8 x half>, align 16
# |   %coerce3 = alloca <8 x half>, align 16
# |   %coerce4 = alloca <8 x half>, align 16
# |   store <4 x i32> %b.coerce, ptr %b, align 16
# |   %b1 = load <8 x half>, ptr %b, align 16
# |   store <4 x i32> %c.coerce, ptr %c, align 16
# |   %c2 = load <8 x half>, ptr %c, align 16
# |   store <8 x i16> %a, ptr %a.addr, align 16
# |   store <8 x half> %b1, ptr %b.addr, align 16
# |   store <8 x half> %c2, ptr %c.addr, align 16
# |   %0 = load <8 x i16>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   %2 = load <8 x half>, ptr %c.addr, align 16
# |   store <8 x half> %1, ptr %coerce, align 16
# |   %3 = load <4 x i32>, ptr %coerce, align 16
# |   store <8 x half> %2, ptr %coerce3, align 16
# |   %4 = load <4 x i32>, ptr %coerce3, align 16
# |   store <4 x i32> %3, ptr %__p1.i, align 16
# |   %__p11.i = load <8 x half>, ptr %__p1.i, align 16
# |   store <4 x i32> %4, ptr %__p2.i, align 16
# |   %__p22.i = load <8 x half>, ptr %__p2.i, align 16
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 16
# |   store <8 x half> %__p11.i, ptr %__p1.addr.i, align 16
# |   store <8 x half> %__p22.i, ptr %__p2.addr.i, align 16
# |   %5 = load <16 x i8>, ptr %__p0.addr.i, align 16
# |   %6 = load <16 x i8>, ptr %__p1.addr.i, align 16
# |   %7 = load <16 x i8>, ptr %__p2.addr.i, align 16
# |   %vbslq_v.i = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %5, <16 x i8> %6, <16 x i8> %7)
# |   store <16 x i8> %vbslq_v.i, ptr %ref.tmp.i, align 16
# |   %8 = load <8 x half>, ptr %ref.tmp.i, align 16
# |   store <8 x half> %8, ptr %__ret.i, align 16
# |   %9 = load <8 x half>, ptr %__ret.i, align 16
# |   store <8 x half> %9, ptr %retval.i, align 16
# |   %10 = load <4 x i32>, ptr %retval.i, align 16
# |   store <4 x i32> %10, ptr %coerce4, align 16
# |   %11 = load <8 x half>, ptr %coerce4, align 16
# |   store <8 x half> %11, ptr %retval, align 16
# |   %12 = load <4 x i32>, ptr %retval, align 16
# |   ret <4 x i32> %12
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vzip_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 %agg.result, <2 x i32> noundef %a.coerce, <2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %__p0.i = alloca <4 x half>, align 8
# |   %__p1.i = alloca <4 x half>, align 8
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %a = alloca <4 x half>, align 8
# |   %b = alloca <4 x half>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %coerce = alloca <4 x half>, align 8
# |   %coerce3 = alloca <4 x half>, align 8
# |   store <2 x i32> %a.coerce, ptr %a, align 8
# |   %a1 = load <4 x half>, ptr %a, align 8
# |   store <2 x i32> %b.coerce, ptr %b, align 8
# |   %b2 = load <4 x half>, ptr %b, align 8
# |   store <4 x half> %a1, ptr %a.addr, align 8
# |   store <4 x half> %b2, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %coerce, align 8
# |   %2 = load <2 x i32>, ptr %coerce, align 8
# |   store <4 x half> %1, ptr %coerce3, align 8
# |   %3 = load <2 x i32>, ptr %coerce3, align 8
# |   call void @llvm.experimental.noalias.scope.decl(metadata !3)
# |   store <2 x i32> %2, ptr %__p0.i, align 8, !noalias !3
# |   %__p01.i = load <4 x half>, ptr %__p0.i, align 8, !noalias !3
# |   store <2 x i32> %3, ptr %__p1.i, align 8, !noalias !3
# |   %__p12.i = load <4 x half>, ptr %__p1.i, align 8, !noalias !3
# |   store <4 x half> %__p01.i, ptr %__p0.addr.i, align 8, !noalias !3
# |   store <4 x half> %__p12.i, ptr %__p1.addr.i, align 8, !noalias !3
# |   %4 = load <8 x i8>, ptr %__p0.addr.i, align 8, !noalias !3
# |   %5 = load <8 x i8>, ptr %__p1.addr.i, align 8, !noalias !3
# |   %6 = bitcast <8 x i8> %4 to <4 x i16>
# |   %7 = bitcast <8 x i8> %5 to <4 x i16>
# |   %vzip.i = shufflevector <4 x i16> %6, <4 x i16> %7, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
# |   store <4 x i16> %vzip.i, ptr %agg.result, align 4, !alias.scope !3
# |   %8 = getelementptr inbounds <4 x i16>, ptr %agg.result, i32 1
# |   %vzip3.i = shufflevector <4 x i16> %6, <4 x i16> %7, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
# |   store <4 x i16> %vzip3.i, ptr %8, align 4, !alias.scope !3
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vzipq_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x8x2_t) align 16 %agg.result, <4 x i32> noundef %a.coerce, <4 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %__p0.i = alloca <8 x half>, align 16
# |   %__p1.i = alloca <8 x half>, align 16
# |   %__p0.addr.i = alloca <8 x half>, align 16
# |   %__p1.addr.i = alloca <8 x half>, align 16
# |   %a = alloca <8 x half>, align 16
# |   %b = alloca <8 x half>, align 16
# |   %a.addr = alloca <8 x half>, align 16
# |   %b.addr = alloca <8 x half>, align 16
# |   %coerce = alloca <8 x half>, align 16
# |   %coerce3 = alloca <8 x half>, align 16
# |   store <4 x i32> %a.coerce, ptr %a, align 16
# |   %a1 = load <8 x half>, ptr %a, align 16
# |   store <4 x i32> %b.coerce, ptr %b, align 16
# |   %b2 = load <8 x half>, ptr %b, align 16
# |   store <8 x half> %a1, ptr %a.addr, align 16
# |   store <8 x half> %b2, ptr %b.addr, align 16
# |   %0 = load <8 x half>, ptr %a.addr, align 16
# |   %1 = load <8 x half>, ptr %b.addr, align 16
# |   store <8 x half> %0, ptr %coerce, align 16
# |   %2 = load <4 x i32>, ptr %coerce, align 16
# |   store <8 x half> %1, ptr %coerce3, align 16
# |   %3 = load <4 x i32>, ptr %coerce3, align 16
# |   call void @llvm.experimental.noalias.scope.decl(metadata !6)
# |   store <4 x i32> %2, ptr %__p0.i, align 16, !noalias !6
# |   %__p01.i = load <8 x half>, ptr %__p0.i, align 16, !noalias !6
# |   store <4 x i32> %3, ptr %__p1.i, align 16, !noalias !6
# |   %__p12.i = load <8 x half>, ptr %__p1.i, align 16, !noalias !6
# |   store <8 x half> %__p01.i, ptr %__p0.addr.i, align 16, !noalias !6
# |   store <8 x half> %__p12.i, ptr %__p1.addr.i, align 16, !noalias !6
# |   %4 = load <16 x i8>, ptr %__p0.addr.i, align 16, !noalias !6
# |   %5 = load <16 x i8>, ptr %__p1.addr.i, align 16, !noalias !6
# |   %6 = bitcast <16 x i8> %4 to <8 x i16>
# |   %7 = bitcast <16 x i8> %5 to <8 x i16>
# |   %vzip.i = shufflevector <8 x i16> %6, <8 x i16> %7, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
# |   store <8 x i16> %vzip.i, ptr %agg.result, align 4, !alias.scope !6
# |   %8 = getelementptr inbounds <8 x i16>, ptr %agg.result, i32 1
# |   %vzip3.i = shufflevector <8 x i16> %6, <8 x i16> %7, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
# |   store <8 x i16> %vzip3.i, ptr %8, align 4, !alias.scope !6
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_vuzp_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 %agg.result, <2 x i32> noundef
# | ...
# `---data was truncated (10240/35874) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055fc5423415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fc542310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fc5423489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1752c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1752ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1752c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1752c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fc541c9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fc541c9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fc541aeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fc53e5e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fc53e5ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1752c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1752c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1752c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fc53e5dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c (2789 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.v
# | ...
# `---data was truncated (10240/23413) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056097055d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056097055a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056097055d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd867b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd867b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd867b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd867b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005609704f2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005609704f2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005609704d7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005609701870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560970186dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd867b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd867b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd867b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560970186cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c (2790 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8_v_u8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8_v_i8mf8x8_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f2a83115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562f2a82e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562f2a83189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd5da81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd5da8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd5da81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd5da803507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f2a7c6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562f2a7c6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562f2a7abb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562f2a45b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562f2a45add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd5da804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd5da8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd5da8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f2a45acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c (2791 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.a
# | ...
# `---data was truncated (10240/63518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624ffa0d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005624ffa0a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005624ffa0d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fdef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fdef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fdef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fdeeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624ff9a2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005624ff9a2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005624ff987b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005624ff6370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005624ff636dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4fdeeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fdeeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fdeeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624ff636cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c (2792 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056012327915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005601232760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056012327989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3d1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3d10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3d1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3d1031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056012320ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056012320ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005601231f3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560122ea30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560122ea2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff3d1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3d10330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3d10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560122ea2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c (2793 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vv_i16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccsu_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef signext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vv_i16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccsu_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef signext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vv_i16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccsu_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef signext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vv_i16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccsu_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef signext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccsu_vv_i16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store 
# | ...
# `---data was truncated (10240/79861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed1771f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ed1771c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ed1771f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d71d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d71d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d71d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d71d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed176b4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ed176b4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ed17699b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ed173490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ed17348dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5d71d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d71d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d71d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed17348cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c (2794 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vmulhsu_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vmulhsu_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vmulhsu_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vmulhsu_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load i64, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llv
# | ...
# `---data was truncated (10240/18669) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632d932515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005632d93220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005632d932589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc48c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc48c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc48c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc48c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005632d92bae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005632d92bac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005632d929fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005632d8f4f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005632d8f4edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc48c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc48c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc48c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005632d8f4ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c (2795 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_u8m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_u8m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr 
# | ...
# `---data was truncated (10240/26240) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624d78ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005624d78a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005624d78ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6240333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f624038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6240333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f624031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624d7840e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005624d7840c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005624d7825b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005624d74d50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005624d74d4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f624031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f624031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f624031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624d74d4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c (2796 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> %0, <16 x i8> %1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16> %0, <8 x i16> %1)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %0, <4 x i32> %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.qrdmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.qrdmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = call <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> %0, <16 x i8> %.splat)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = call <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16> %0, <8 x i16> %.splat)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %0, <4 x i32> %.splat)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 
# | ...
# `---data was truncated (10240/11881) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055860b4cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055860b4c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055860b4cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6ceae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6ceae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6ceae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6ceae03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055860b460e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055860b460c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055860b445b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055860b0f50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055860b0f4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6ceae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6ceae050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6ceae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055860b0f4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c (2797 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056131977015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056131976d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056131977089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2bf7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2bf758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2bf7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2bf751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561319705e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561319705c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005613196eab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056131939a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561319399dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2bf751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2bf751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2bf751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561319399cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c (2798 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.5a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg  | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.5a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint32zf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint32z.i = call float @llvm.aarch64.frint32z.f32(float %1)
# |   ret float %frint32z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint32z(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint32z.i = call double @llvm.aarch64.frint32z.f64(double %1)
# |   ret double %frint32z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint64zf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint64z.i = call float @llvm.aarch64.frint64z.f32(float %1)
# |   ret float %frint64z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint64z(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint64z.i = call double @llvm.aarch64.frint64z.f64(double %1)
# |   ret double %frint64z.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint32xf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint32x.i = call float @llvm.aarch64.frint32x.f32(float %1)
# |   ret float %frint32x.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint32x(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint32x.i = call double @llvm.aarch64.frint32x.f64(double %1)
# |   ret double %frint32x.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_rint64xf(float noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca float, align 4
# |   %a.addr = alloca float, align 4
# |   store float %a, ptr %a.addr, align 4
# |   %0 = load float, ptr %a.addr, align 4
# |   store float %0, ptr %__a.addr.i, align 4
# |   %1 = load float, ptr %__a.addr.i, align 4
# |   %frint64x.i = call float @llvm.aarch64.frint64x.f32(float %1)
# |   ret float %frint64x.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local double @test_rint64x(double noundef %a) #0 {
# | entry:
# |   %__a.addr.i = alloca double, align 8
# |   %a.addr = alloca double, align 8
# |   store double %a, ptr %a.addr, align 8
# |   %0 = load double, ptr %a.addr, align 8
# |   store double %0, ptr %__a.addr.i, align 8
# |   %1 = load double, ptr %__a.addr.i, align 8
# |   %frint64x.i = call double @llvm.aarch64.frint64x.f64(double %1)
# |   ret double %frint64x.i
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint32z.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint32z.f64(double) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint64z.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint64z.f64(double) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint32x.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint32x.f64(double) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.aarch64.frint64x.f32(float) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.aarch64.frint64x.f64(double) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055adb904615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055adb90430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055adb904689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3710c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3710c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3710c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3710c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055adb8fdbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055adb8fdbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055adb8fc0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055adb8c700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055adb8c6fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3710c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3710c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3710c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055adb8c6fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c (2799 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr
# | ...
# `---data was truncated (10240/14461) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d05c0915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561d05c060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561d05c0989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1cbcc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1cbcca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1cbcc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1cbcc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d05b9ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561d05b9ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561d05b83b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561d058330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561d05832dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1cbcc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1cbcc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1cbcc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d05832cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c (2800 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none)
# | ...
# `---data was truncated (10240/30609) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b30fef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562b30fec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562b30fef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d6fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d6faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d6fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d6fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b30f84e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562b30f84c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562b30f69b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562b30c190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562b30c18dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2d6fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d6fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d6fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b30c18cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c (2801 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_i32m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_i32m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_u32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 nounde
# | ...
# `---data was truncated (10240/31748) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055910a9c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055910a9c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055910a9c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a0f105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a0f15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a0f105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a0f0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055910a95ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055910a95ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055910a93fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055910a5ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055910a5eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6a0f0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a0f0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a0f0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055910a5eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c (2802 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f16m1x6(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei32_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f32m1x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei32_v_f64m1x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei32_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei32_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d57ef8a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d57ef870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d57ef8a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6950333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f695038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6950333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f695031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d57ef1fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d57ef1fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d57ef04b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d57ebb40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d57ebb3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f695031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f695031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f695031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d57ebb3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c (2803 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff
# | ...
# `---data was truncated (10240/54702) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b7f63f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562b7f63c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562b7f63f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5856449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58564a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5856449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5856431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b7f5d4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562b7f5d4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562b7f5b9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562b7f2690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562b7f268dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5856432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58564330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58564330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b7f268cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c (2804 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei32_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f16m1x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f16m2x4(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei32_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f32m1x4(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei32_v_f32m2x4(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei32_v_f64m1x4(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/87884) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec9a8b815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ec9a8b50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ec9a8b889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe902c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe902c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe902c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe902c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec9a84de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ec9a84dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ec9a832b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ec9a4e20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ec9a4e1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe902c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe902c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe902c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec9a4e1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c (2805 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e88064915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e8806460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e88064989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5302c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5302ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5302c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5302c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8805dee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e8805dec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e8805c3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e8802730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e880272dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5302c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5302c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5302c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e880272cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c (2806 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmin_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmin_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmin_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmin_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmin_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>
# | ...
# `---data was truncated (10240/29062) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c3c56ae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c3c56ab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c3c56ae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ad2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ad258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ad2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ad251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c3c5643e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c3c5643c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c3c5628b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c3c52d80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c3c52d7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4ad251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ad251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ad251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c3c52d7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c (2807 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f768a315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564f768a00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564f768a389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fac2421bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fac242725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fac2421ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fac24203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f76838e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564f76838c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564f7681db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564f764cd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564f764ccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fac24204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fac242050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fac242050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f764cccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c (2808 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e10fe7315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e10fe700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e10fe7389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29d7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29d74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29d7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29d7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e10fe08e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e10fe08c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e10fdedb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e10fa9d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e10fa9cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f29d7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29d74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29d74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e10fa9ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c (2809 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec10c3e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ec10c3b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ec10c3e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fae7841bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fae784725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fae7841ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fae78403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec10bd3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ec10bd3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ec10bb8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ec108680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ec10867dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fae78404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fae784050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fae784050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec10867cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c (2810 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i8 @subscript_int8(<vscale x 8 x i8> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i8> %0, i64 %1
# |   ret i8 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local zeroext i8 @subscript_uint8(<vscale x 8 x i8> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <32 x i8> %0, i64 %1
# |   ret i8 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i16 @subscript_int16(<vscale x 4 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local zeroext i16 @subscript_uint16(<vscale x 4 x i16> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <16 x i16> %0, i64 %1
# |   ret i16 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i32 @subscript_int32(<vscale x 2 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local signext i32 @subscript_uint32(<vscale x 2 x i32> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x i32> %0, i64 %1
# |   ret i32 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_int64(<vscale x 1 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <4 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local i64 @subscript_uint64(<vscale x 1 x i64> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <4 x i64> %0, i64 %1
# |   ret i64 %vecext
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local float @subscript_float32(<vscale x 2 x float> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x float>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %a.coerce, i64 0)
# |   store <8 x float> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <8 x float>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <8 x float> %0, i64 %1
# |   ret float %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local double @subscript_float64(<vscale x 1 x double> noundef %a.coerce, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x double>, align 8
# |   %b.addr = alloca i64, align 8
# |   %a = call <4 x double> @llvm.vector.extract.v4f64.nxv1f64(<vscale x 1 x double> %a.coerce, i64 0)
# |   store <4 x double> %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load <4 x double>, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   %vecext = extractelement <4 x double> %0, i64 %1
# |   ret double %vecext
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x double> @llvm.vector.extract.v4f64.nxv1f64(<vscale x 1 x double>, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,4) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055716bb2915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055716bb260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055716bb2989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2400449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24004a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2400449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2400431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055716babee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055716babec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055716baa3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055716b7530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055716b752dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2400432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24004330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24004330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055716b752cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c (2811 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c  -check-prefix=RV64ZKND-ZKNE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64ks1i(i64 noundef %rs1) #0 {
# | entry:
# |   %rs1.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = call i64 @llvm.riscv.aes64ks1i(i64 %0, i32 0)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64ks1i(i64, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @aes64ks2(i64 noundef %rs1, i64 noundef %rs2) #0 {
# | entry:
# |   %__x.addr.i = alloca i64, align 8
# |   %__y.addr.i = alloca i64, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %rs2.addr = alloca i64, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   %0 = load i64, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   store i64 %0, ptr %__x.addr.i, align 8
# |   store i64 %1, ptr %__y.addr.i, align 8
# |   %2 = load i64, ptr %__x.addr.i, align 8
# |   %3 = load i64, ptr %__y.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.aes64ks2(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.riscv.aes64ks2(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknd" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zknd1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d3f335f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d3f335c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d3f335f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a6e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a6e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a6e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a6e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3f32f4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d3f32f4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d3f32d9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d3f2f890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d3f2f88dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7a6e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a6e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a6e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3f2f88cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c (2812 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vloxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e09d6c815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e09d6c50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e09d6c889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc8f6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc8f618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc8f6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc8f611b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e09d65de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e09d65dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e09d642b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e09d2f20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e09d2f1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc8f611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc8f611d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc8f611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e09d2f1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c (2813 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvtbf16_f_f_v_f32m8_tu(<vscale x 16 x float> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvtbf16_f_f_v_f32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvtbf16_f_f_v_f32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvtbf16_f_f_v_f32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvtbf16_f_f_v_f32m4_tum(<vscale x 8 x i1> %vm, <vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 8 x bfloat>, ptr %v
# | ...
# `---data was truncated (10240/23064) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557f4552a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557f455270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557f4552a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f60f8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60f8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f60f8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60f8a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557f454bfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557f454bfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557f454a4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557f451540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557f45153dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f60f8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60f8a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60f8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557f45153cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c (2814 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x i1> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i1> %vs1, ptr %vs1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055debee3315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055debee300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055debee3389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4ea3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4ea30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4ea3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4ea3031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055debedc8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055debedc8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055debedadb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055debea5d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055debea5cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4ea3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4ea30330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4ea30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055debea5ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c (2815 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_
# | ...
# `---data was truncated (10240/10440) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d848eb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556d848e80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556d848eb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4488305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f448835c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4488305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44882ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d84880e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556d84880c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556d84865b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556d845150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556d84514dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f44882eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44882ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44882ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d84514cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c (2816 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d114b8715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d114b840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d114b8789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5bd041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5bd04725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5bd041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5bd0403507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d114b1ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d114b1cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d114b01b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d1147b10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d1147b0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5bd0404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5bd04050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5bd04050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d1147b0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c (2817 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vcpop_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/11958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd4006c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fd400690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fd4006c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdcd9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdcd9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdcd9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdcd9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd40001e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fd40001c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fd3ffe6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fd3fc960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fd3fc95dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdcd9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdcd9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdcd9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd3fc95cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c (2818 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055587622a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005558762270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055587622a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb37ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb37cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb37ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb37ce31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558761bfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005558761bfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005558761a4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555875e540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555875e53dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb37ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb37ce330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb37ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555875e53cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-cde-reinterpret.c (2819 of 27911)
******************** TEST 'Clang :: CodeGen/arm-cde-reinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +mve.fp    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_s8(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_u16(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x i16>
# |   ret <8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_s32(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_u32(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x i32>
# |   ret <4 x i32> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_s64(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <2 x i64>
# |   ret <2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_u64(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <2 x i64>
# |   ret <2 x i64> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_f16(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <8 x half>
# |   ret <8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_f32(<16 x i8> noundef %x) #0 {
# | entry:
# |   %x.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %x, ptr %x.addr, align 8
# |   %0 = load <16 x i8>, ptr %x.addr, align 8
# |   %1 = bitcast <16 x i8> %0 to <4 x float>
# |   ret <4 x float> %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+mve.fp,+thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e7fa1115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560e7fa0e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560e7fa1189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff192133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff19218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff192133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff19211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e7f9a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560e7f9a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560e7f98bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560e7f63b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560e7f63add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff19211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff19211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff19211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e7f63acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/builtin-cpu-is.c (2820 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/builtin-cpu-is.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c -o -    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-unknown-linux-gnu"
# | 
# | @__riscv_cpu_model = external dso_local global { i32, i64, i64 }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @test_cpu_is_spacemit_x60() #0 {
# | entry:
# |   %0 = load i32, ptr @__riscv_cpu_model, align 4
# |   %1 = icmp eq i32 %0, 1808
# |   %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
# |   %3 = icmp eq i64 %2, -9223372035378380799
# |   %4 = and i1 %1, %3
# |   %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
# |   %6 = icmp eq i64 %5, 1152921505839391232
# |   %7 = and i1 %4, %6
# |   %conv = zext i1 %7 to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @test_cpu_is_sifive_p550() #0 {
# | entry:
# |   %0 = load i32, ptr @__riscv_cpu_model, align 4
# |   %1 = icmp eq i32 %0, 1161
# |   %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
# |   %3 = icmp eq i64 %2, -9223372036854775800
# |   %4 = and i1 %1, %3
# |   %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
# |   %6 = icmp eq i64 %5, 102892581
# |   %7 = and i1 %4, %6
# |   %conv = zext i1 %7 to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @test_cpu_is_sifive_p870_d() #0 {
# | entry:
# |   %0 = load i32, ptr @__riscv_cpu_model, align 4
# |   %1 = icmp eq i32 %0, 1161
# |   %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
# |   %3 = icmp eq i64 %2, -9223372036854775543
# |   %4 = and i1 %1, %3
# |   %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
# |   %6 = icmp eq i64 %5, 337970694
# |   %7 = and i1 %4, %6
# |   %conv = zext i1 %7 to i32
# |   ret i32 %conv
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562e56bb215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562e56baf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562e56bb289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f045bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f045bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f045bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f045bc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562e56b47e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562e56b47c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562e56b2cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562e567dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562e567dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f045bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f045bc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f045bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562e567dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c (2821 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/13031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056203a65815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056203a6550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056203a65889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e42c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e42ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e42c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e42c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056203a5ede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056203a5edc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056203a5d2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056203a2820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056203a281dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4e42c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e42c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e42c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056203a281cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c (2822 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vlsseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/48313) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8db3c215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e8db3bf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e8db3c289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7820449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78204a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7820449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7820431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8db357e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e8db357c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e8db33cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e8dafec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e8dafebdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7820432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78204330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78204330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8dafebcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c (2823 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64
# | ...
# `---data was truncated (10240/14036) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625393d115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005625393ce0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005625393d189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f932e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f932e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f932e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f932e631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562539366e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562539366c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056253934bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562538ffb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562538ffadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f932e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f932e6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f932e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562538ffacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c (2824 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4
# | ...
# `---data was truncated (10240/25575) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563d778c715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563d778c40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563d778c789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa0b1d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0b1d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa0b1d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa0b1ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563d7785ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563d7785cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563d77841b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563d774f10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563d774f0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa0b1ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0b1cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0b1cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563d774f0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c (2825 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590b76dc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005590b76d90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005590b76dc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe239c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe239ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe239c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe239c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590b7671e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005590b7671c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005590b7656b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005590b73060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005590b7305dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe239c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe239c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe239c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590b7305cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c (2826 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4(<vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2(<vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1(<vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2(<vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4(<vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2(<vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1(<vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2(<vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4(<vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1(<vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vunzipo_v_f64m2(<vscale x 4 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 2 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(<vscale x 2 x double>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vunzipo_v_f64m4(<vscale x 8 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %vs.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 4 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(<vscale x 4 x double>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @
# | ...
# `---data was truncated (10240/35774) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b8bbb715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561b8bbb40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561b8bbb789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8687133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f868718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8687133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f868711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b8bb4ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561b8bb4cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561b8bb31b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561b8b7e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561b8b7e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f868711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f868711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f868711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b8b7e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c (2827 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558274cc415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558274cc10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558274cc489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2779333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f277938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2779333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f277931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558274c59e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558274c59c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558274c3eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005582748ee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005582748eddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f277931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f277931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f277931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005582748edcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c (2828 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpaire.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpaire_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpaire.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpaire_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpaire.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpaire_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpaire.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpaire_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpaire.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpaire_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpaire.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpaire_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.add
# | ...
# `---data was truncated (10240/15312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f3799b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f3799b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f3799b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb086d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb086d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb086d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb086d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f37994ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f37994cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f379931b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f3795e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f3795e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb086d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb086d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb086d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3795e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c (2829 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_
# | ...
# `---data was truncated (10240/63061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e57076f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e57076c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e57076f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff04f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff04f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff04f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff04f71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e570704e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e570704c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e5706e9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e5703990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e570398dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff04f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff04f71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff04f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e570398cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c (2830 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2(ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2(ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f32m1x2(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f32m2x2(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple
# | ...
# `---data was truncated (10240/108848) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a594b6315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a594b600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a594b6389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcf30f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcf30f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcf30f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcf30f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a594af8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a594af8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a594addb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a59478d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a59478cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcf30f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcf30f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcf30f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a59478ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c (2831 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_u16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_u16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, pt
# | ...
# `---data was truncated (10240/24016) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df6797a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055df679770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055df6797a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f222ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f222aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f222ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f222ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df6790fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055df6790fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055df678f4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055df675a40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055df675a3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f222ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f222ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f222ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df675a3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c (2832 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwadd_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwadd_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwadd_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# | 
# | ...
# `---data was truncated (10240/86100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056382dd0315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056382dd000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056382dd0389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe825c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe825ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe825c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe825c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056382dc98e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056382dc98c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056382dc7db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056382d92d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056382d92cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe825c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe825c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe825c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056382d92ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c (2833 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8_tu(<vscale x 32 x half> %maskedoff, <vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %2 = load half, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %2 = load float, ptr %op2.addr, align 4
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: 
# | ...
# `---data was truncated (10240/22367) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557fbb2c215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557fbb2bf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557fbb2c289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f26b4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f26b4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f26b4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f26b4b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fbb257e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557fbb257c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557fbb23cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557fbaeec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557fbaeebdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f26b4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f26b4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f26b4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fbaeebcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c (2834 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005594d73c915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005594d73c60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005594d73c989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f881d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f881d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f881d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f881d631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005594d735ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005594d735ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005594d7343b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005594d6ff30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005594d6ff2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f881d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f881d6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f881d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005594d6ff2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c (2835 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8_tu(<vscale x 16 x float> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2_tu(<vscale x 2 x double> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4_tu(<vscale x 4 x double> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8_tu(<vscale x 8 x double> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = al
# | ...
# `---data was truncated (10240/41670) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559fe24bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559fe24ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559fe24bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd10bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd10bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd10bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd10bf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559fe2452e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559fe2452c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559fe2437b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559fe20e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559fe20e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd10bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd10bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd10bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559fe20e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c (2836 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_f32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_f32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_f32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e32_v_i32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e32_v_i32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e32_v_i32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e32_v_i32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.
# | ...
# `---data was truncated (10240/15486) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ab76c915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562ab76c60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562ab76c989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa85ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa85ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa85ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa85ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ab765ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562ab765ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562ab7643b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562ab72f30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562ab72f2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa85ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa85ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa85ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ab72f2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c (2837 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563aa4d8015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563aa4d7d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563aa4d8089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f744de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f744dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f744de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f744de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563aa4d15e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563aa4d15c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563aa4cfab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563aa49aa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563aa49a9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f744de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f744de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f744de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563aa49a9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c (2838 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_bf16m4x2_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4840c415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d4840c10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d4840c489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5fd0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5fd06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5fd0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5fd0631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d484059e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d484059c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d48403eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d483cee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d483ceddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5fd0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5fd06330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5fd06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d483cedcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c (2839 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %m
# | ...
# `---data was truncated (10240/160133) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da49cc415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055da49cc10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055da49cc489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe333049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe3330a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe333049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe333031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da49c59e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055da49c59c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055da49c3eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055da498ee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055da498eddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe333032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe3330330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe3330330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da498edcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c (2840 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsleu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsleu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsleu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsleu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad9e04915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ad9e0460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ad9e04989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fed7321bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fed732725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fed7321ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fed73203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad9dfdee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ad9dfdec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ad9dfc3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ad9dc730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ad9dc72dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fed73204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fed732050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fed732050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad9dc72cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c (2841 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c00eaf415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c00eaf10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c00eaf489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5460d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5460d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5460d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5460ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c00ea89e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c00ea89c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c00ea6eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c00e71e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c00e71ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5460ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5460cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5460cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c00e71dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c (2842 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056112c7e115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056112c7de0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056112c7e189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbbc2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbbc28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbbc2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbbc2831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056112c776e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056112c776c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056112c75bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056112c40b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056112c40add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbbc2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbbc28330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbbc28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056112c40acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c (2843 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e49158115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e49157e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e49158189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90a3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90a3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90a3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90a3c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e491516e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e491516c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e4914fbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e4911ab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e4911aadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f90a3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90a3c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90a3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e4911aacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c (2844 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16ff_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16ff_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16ff_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da91e8115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055da91e7e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055da91e8189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1438249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14382a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1438249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1438231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da91e16e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055da91e16c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055da91dfbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055da91aab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055da91aaadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1438232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14382330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14382330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da91aaacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c (2845 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wv_u8mf8(<vscale x 1 x i16> %op1, <vscale x 1 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vnsrl_wx_u8mf8(<vscale x 1 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(<vscale x 1 x i8>, <vscale x 1 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wv_u8mf4(<vscale x 2 x i16> %op1, <vscale x 2 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vnsrl_wx_u8mf4(<vscale x 2 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(<vscale x 2 x i8>, <vscale x 2 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wv_u8mf2(<vscale x 4 x i16> %op1, <vscale x 4 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vnsrl_wx_u8mf2(<vscale x 4 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(<vscale x 4 x i8>, <vscale x 4 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wv_u8m1(<vscale x 8 x i16> %op1, <vscale x 8 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vnsrl_wx_u8m1(<vscale x 8 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(<vscale x 8 x i8>, <vscale x 8 x i16>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wv_u8m2(<vscale x 16 x i16> %op1, <vscale x 16 x i8> %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x i8> %shift, ptr %shift.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %shift.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vnsrl_wx_u8m2(<vscale x 16 x i16> %op1, i64 noundef %shift, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %shift.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %shift, ptr %shift.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %shift.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i16> %0, i64 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(<vscale x 16 x i8>, <vs
# | ...
# `---data was truncated (10240/68517) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb60c4715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fb60c440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fb60c4789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6b1b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6b1b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6b1b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6b1b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb60bdce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fb60bdcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fb60bc1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fb608710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fb60870dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6b1b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6b1b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6b1b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb60870cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c (2846 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslideup_vx_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslideup.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslideup_vx_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslideup.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslideup_vx_bf16m4(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslideup.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslideup_vx_bf16m8(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2, i64 %3, i64 3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslideup.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslideup_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslideup.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslideup_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %rs1.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslideup.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x 
# | ...
# `---data was truncated (10240/16529) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560c7397a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560c739770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560c7397a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4795733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f479578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4795733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f479571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560c7390fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560c7390fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560c738f4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560c735a40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560c735a3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f479571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f479571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f479571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560c735a3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c (2847 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8_tu(<vscale x 16 x float> %maskedoff, <vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2_tu(<vscale x 2 x double> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4_tu(<vscale x 4 x double> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8_tu(<vscale x 8 x double> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x float> %maskedoff, <vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.a
# | ...
# `---data was truncated (10240/41678) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd8bdd415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dd8bdd10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dd8bdd489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7102b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7102b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7102b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7102b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd8bd69e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dd8bd69c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dd8bd4eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dd8b9fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dd8b9fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7102b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7102b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7102b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd8b9fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c (2848 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_m(<vscale x 16 x i1> %vm, <vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bf
# | ...
# `---data was truncated (10240/13040) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561e1e2515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005561e1e220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005561e1e2589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9ce305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9ce35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9ce305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9ce2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561e1dbae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005561e1dbac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005561e1d9fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005561e1a4f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005561e1a4edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb9ce2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9ce2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9ce2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561e1a4ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c (2849 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4a_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4a_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4a_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4a_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4a_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# | 
# | ...
# `---data was truncated (10240/26460) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601b8bf115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005601b8bee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005601b8bf189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78bd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78bd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78bd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78bd31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601b8b86e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005601b8b86c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005601b8b6bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005601b881b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005601b881add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f78bd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78bd31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78bd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601b881acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c (2850 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559648c6e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559648c6b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559648c6e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff0e6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0e62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff0e6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff0e6231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559648c03e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559648c03c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559648be8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005596488980b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559648897dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff0e6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0e62330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0e62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559648897cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c (2851 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_viota_m_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_viota_m_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_viota_m_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_viota_m_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_viota_m_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_viota_m_u8m4_tu(<vscale x 32 x i8> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_viota_m_u8m8_tu(<vscale x 64 x i8> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_viota_m_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_viota_m_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_viota_m_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_viota
# | ...
# `---data was truncated (10240/94681) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055718111215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055718110f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055718111289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff463449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff4634a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff463449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff463431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571810a7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005571810a7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055718108cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557180d3c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557180d3bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff463432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff4634330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff4634330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557180d3bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c (2852 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.
# | ...
# `---data was truncated (10240/24951) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055744ed7815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055744ed750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055744ed7889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f134db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f134db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f134db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f134db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055744ed0de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055744ed0dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055744ecf2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055744e9a20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055744e9a1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f134db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f134db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f134db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055744e9a1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c (2853 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vtdiscard() #0 {
# | entry:
# |   call void @llvm.riscv.sf.vtdiscard()
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vtdiscard() #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056211ae7915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056211ae760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056211ae7989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facdc533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facdc58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facdc533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facdc51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056211ae0ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056211ae0ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056211adf3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056211aaa30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056211aaa2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007facdc51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facdc51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facdc51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056211aaa2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c (2854 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f80ee9115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f80ee8e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f80ee9189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b9b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b9b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b9b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b9b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f80ee26e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f80ee26c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f80ee0bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f80eabb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f80eabadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8b9b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b9b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b9b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f80eabacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c (2855 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4_tu(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2_tu(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1_tu(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2_tu(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4_tu(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8_tu(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2_tu(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1_tu(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2_tu(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.a
# | ...
# `---data was truncated (10240/73947) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005630a5c3a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005630a5c370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005630a5c3a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa89fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa89fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa89fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa89fb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005630a5bcfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005630a5bcfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005630a5bb4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005630a58640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005630a5863dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa89fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa89fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa89fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005630a5863cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-crc32.c (2856 of 27911)
******************** TEST 'Clang :: CodeGen/arm-crc32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +crc   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8-none-linux-gnueabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32b(i32 noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32b(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32b(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cb(i32 noundef %a, i8 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32cb(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32cb(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32h(i32 noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32h(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32h(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32ch(i32 noundef %a, i16 noundef signext %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.arm.crc32ch(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32ch(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32w(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.arm.crc32w(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32w(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cw(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.arm.crc32cw(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.crc32cw(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32d(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = trunc i64 %1 to i32
# |   %3 = lshr i64 %1, 32
# |   %4 = trunc i64 %3 to i32
# |   %5 = call i32 @llvm.arm.crc32w(i32 %0, i32 %2)
# |   %6 = call i32 @llvm.arm.crc32w(i32 %5, i32 %4)
# |   ret i32 %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cd(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = trunc i64 %1 to i32
# |   %3 = lshr i64 %1, 32
# |   %4 = trunc i64 %3 to i32
# |   %5 = call i32 @llvm.arm.crc32cw(i32 %0, i32 %2)
# |   %6 = call i32 @llvm.arm.crc32cw(i32 %5, i32 %4)
# |   ret i32 %6
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8-a,+crc,-thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1}
# | !llvm.ident = !{!2}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs-linux"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005620cc86015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005620cc85d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005620cc86089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18f841bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18f84725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18f841ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18f8403507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005620cc7f5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005620cc7f5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005620cc7dab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005620cc48a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005620cc489dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f18f8404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18f84050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18f84050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005620cc489cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c (2857 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005602aff3a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005602aff370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005602aff3a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe984b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe984b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe984b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe984b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005602afecfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005602afecfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005602afeb4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005602afb640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005602afb63dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe984b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe984b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe984b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005602afb63cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c (2858 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vcpop_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vcpop_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vcpop_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vcpopv.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Fun
# | ...
# `---data was truncated (10240/40883) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ff4ee015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557ff4edd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557ff4ee089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f842a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f842a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f842a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f842a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ff4e75e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557ff4e75c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557ff4e5ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557ff4b0a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557ff4b09dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f842a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f842a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f842a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ff4b09cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c (2859 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmerge_vfm_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmerge_vfm_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmerge_vfm_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmerge_vfm_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, bfloat noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfmerge_vfm_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, bfloat noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, <vscale x 16 x i1> %3, i64 %4)
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfmerge_vfm_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, bfloat noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load bfloat, ptr %op2.addr, align 2
# |   %3 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, <vscale x 32 x i1> %3, i64 %4)
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, <vscale x 32 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653d6dbb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005653d6db80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005653d6dbb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1635933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f163598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1635933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f163591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005653d6d50e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005653d6d50c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005653d6d35b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005653d69e50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005653d69e4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f163591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f163591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f163591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005653d69e4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c (2860 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f857c0015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f857bfd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f857c0089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4b3d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4b3d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4b3d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4b3d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f857b95e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f857b95c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f857b7ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f85782a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f857829dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4b3d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4b3d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4b3d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f857829cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c (2861 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfwma -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vv_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x float> @test_vfwmaccbf16_vf_f32mf2_tu(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vv_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x float> @test_vfwmaccbf16_vf_f32m1_tu(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vv_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x float> @test_vfwmaccbf16_vf_f32m2_tu(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vv_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x float> @test_vfwmaccbf16_vf_f32m4_tu(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x
# | ...
# `---data was truncated (10240/101475) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b7793315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562b779300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562b7793389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff080449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff0804a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff080449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff080431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b778c8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562b778c8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562b778adb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562b7755d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562b7755cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff080432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff0804330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff0804330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b7755ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c (2862 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ca3206915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ca320660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ca3206989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f62cfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f62cfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f62cfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f62cfd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ca31ffee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ca31ffec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ca31fe3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ca31c930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ca31c92dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f62cfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f62cfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f62cfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ca31c92cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c (2863 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_i8m2_i8m1(<vscale x 16 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_i8m4_i8m1(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_i8m8_i8m1(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_i8m4_i8m2(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_i8m8_i8m2(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vget_v_i8m8_i8m4(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 32 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_u8m2_u8m1(<vscale x 16 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_u8m4_u8m1(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vget_v_u8m8_u8m1(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 8 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_u8m4_u8m2(<vscale x 32 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vget_v_u8m8_u8m2(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 16 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vget_v_u8m8_u8m4(<vscale x 64 x i8> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   %1 = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> %0, i64 0)
# |   ret <vscale x 32 x i8> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vget_v_i16m2_i16m1(<vscale x 8 x i16> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> %0, i64 0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vget_v_i16m4_i16m1(<vscale x 16 x i16> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> %0, i64 0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vget_v_i16m8_i16m1(<vscale x 32 x i16> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> %0, i64 0)
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale
# | ...
# `---data was truncated (10240/40902) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fed1bf915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fed1bf60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fed1bf989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff5a1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff5a178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff5a1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff5a171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fed1b8ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fed1b8ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fed1b73b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fed18230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fed1822dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff5a171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff5a171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff5a171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fed1822cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c (2864 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbrsrq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32> %0, i32 %1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbrsrq_n_f16(<8 x half> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half> %0, i32 %1)
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbrsrq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %1 = load <16 x i8>, ptr %a.addr, align 8
# |   %2 = load i32, ptr %b.addr, align 4
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4)
# |   %6 = call <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 %2, <16 x i1> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbrsrq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %a.addr, align 8
# |   %2 = load i32, ptr %b.addr, align 4
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 %2, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbrsrq_x_n_u16(<8 x i16> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16> undef, <8 x i16> %0, i32 %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbrsrq_x_n_f16(<8 x half> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca i32, align 4
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half> undef, <8 x half> %0, i32 %1, <8 x i1> %4)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624aadff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005624aadfc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005624aadff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4490905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f449095c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4490905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44908ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005624aad94e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005624aad94c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005624aad79b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005624aaa290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005624aaa28dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f44908eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44908ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44908ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005624aaa28cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c (2865 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.v
# | ...
# `---data was truncated (10240/23413) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564ab4c2415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564ab4c210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564ab4c2489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1b29b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1b29b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1b29b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1b29b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564ab4bb9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564ab4bb9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564ab4b9eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564ab484e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564ab484ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1b29b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1b29b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1b29b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564ab484dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c (2866 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesz_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesz_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesz_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesz_vs_u32m1_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(<vscale x 16 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesz_vs_u32m2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree n
# | ...
# `---data was truncated (10240/15237) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629cb6be15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005629cb6bb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005629cb6be89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce48133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce4818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce48133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce4811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005629cb653e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005629cb653c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005629cb638b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005629cb2e80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005629cb2e7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fce4811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce4811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce4811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005629cb2e7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c (2867 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_i8mf8_u8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_i8mf4_u8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_i8mf2_u8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i8m1_u8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i8m2_u8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i8m4_u8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i8m8_u8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_i8mf8(<vscale x 1 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i8>, align 1
# |   store <vscale x 1 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 1 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 1 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_i8mf4(<vscale x 2 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i8>, align 1
# |   store <vscale x 2 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 2 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 2 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_i8mf2(<vscale x 4 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i8>, align 1
# |   store <vscale x 4 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 4 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 4 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_i8m1(<vscale x 8 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i8>, align 1
# |   store <vscale x 8 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 8 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 8 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_i8m2(<vscale x 16 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i8>, align 1
# |   store <vscale x 16 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 16 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 16 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_i8m4(<vscale x 32 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i8>, align 1
# |   store <vscale x 32 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 32 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 32 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_i8m8(<vscale x 64 x i8> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 64 x i8>, align 1
# |   store <vscale x 64 x i8> %src, ptr %src.addr, align 1
# |   %0 = load <vscale x 64 x i8>, ptr %src.addr, align 1
# |   ret <vscale x 64 x i8> %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_i16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_i16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_i16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_i16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_i16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_i16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x half>
# |   ret <vscale x 32 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vreinterpret_v_u16mf4_f16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x half>
# |   ret <vscale x 1 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vreinterpret_v_u16mf2_f16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x half>
# |   ret <vscale x 2 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vreinterpret_v_u16m1_f16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x half>
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vreinterpret_v_u16m2_f16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x half>
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vreinterpret_v_u16m4_f16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x half>
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vreinterpret_v_u16m8_f16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bi
# | ...
# `---data was truncated (10240/136481) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d828c2415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d828c210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d828c2489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd1b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd1b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd1b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd1b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d828bb9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d828bb9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d828b9eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d82884e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d82884ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efd1b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd1b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd1b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d82884dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c (2868 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ea9bae315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ea9bae00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ea9bae389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1430333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f143038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1430333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f143031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ea9ba78e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ea9ba78c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ea9ba5db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ea9b70d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ea9b70cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f143031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f143031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f143031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea9b70ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c (2869 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettm.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettm_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fde1efb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fde1ef80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fde1efb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94a3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94a3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94a3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94a3a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fde1e90e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fde1e90c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fde1e75b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fde1b250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fde1b24dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f94a3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94a3a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94a3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fde1b24cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c (2870 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d46abbe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d46abbb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d46abbe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27bbc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27bbca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27bbc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27bbc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d46ab53e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d46ab53c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d46ab38b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d46a7e80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d46a7e7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f27bbc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27bbc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27bbc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d46a7e7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c (2871 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load bfloat, ptr %rs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x floa
# | ...
# `---data was truncated (10240/199588) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c63119115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c63118e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c63119189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06a0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06a058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06a0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06a051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c631126e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c631126c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c63110bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c630dbb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c630dbadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f06a051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06a051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06a051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c630dbacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c (2872 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_f32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_i32m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e32_v_u32m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | 
# | ...
# `---data was truncated (10240/26984) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ff5207815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ff520750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ff5207889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29d7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29d74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29d7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29d7431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ff5200de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ff5200dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ff51ff2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ff51ca20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ff51ca1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f29d7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29d74330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29d74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ff51ca1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c (2873 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei16_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei16_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei16_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555f91b7915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555f91b760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555f91b7989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82b9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82b9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82b9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82b9a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555f91b0ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555f91b0ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555f91af3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555f917a30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555f917a2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f82b9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82b9a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82b9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555f917a2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c (2874 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i6
# | ...
# `---data was truncated (10240/25511) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558b366315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005558b36600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005558b366389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff92b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff92b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff92b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff92b231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558b35f8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005558b35f8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005558b35ddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005558b328d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005558b328cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff92b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff92b2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff92b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558b328ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c (2875 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vsc
# | ...
# `---data was truncated (10240/41579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1ed1c315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e1ed1c00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e1ed1c389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1a66e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1a66ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1a66e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1a66e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1ed158e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e1ed158c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e1ed13db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e1ecded0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e1ecdecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1a66e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1a66e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1a66e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1ecdeccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c (2876 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf8_i16m1(<vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> poison, <vscale x 1 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf4_i16m1(<vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> poison, <vscale x 2 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8mf2_i16m1(<vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m1_i16m1(<vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> poison, <vscale x 8 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m2_i16m1(<vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> poison, <vscale x 16 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m4_i16m1(<vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> poison, <vscale x 32 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsum_vs_i8m8_i16m1(<vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> poison, <vscale x 64 x i8> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf4_i32m1(<vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> poison, <vscale x 1 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32>, <vscale x 1 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16mf2_i32m1(<vscale x 2 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsum_vs_i16m1_i32m1(<vscale x 4 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/43515) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642ad58f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005642ad58c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005642ad58f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f199621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f19962725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f199621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1996203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642ad524e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005642ad524c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005642ad509b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005642ad1b90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005642ad1b8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1996204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f19962050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f19962050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642ad1b8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c (2877 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4
# | ...
# `---data was truncated (10240/47636) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d5046ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d5046a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d5046ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f641cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f641cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f641cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f641cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d504640e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d504640c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d504625b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d5042d50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d5042d4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f641cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f641cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f641cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d5042d4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c (2878 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmorn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmorn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmorn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmorn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmorn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmorn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmorn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eafb02d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eafb02a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eafb02d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb428849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4288a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb428849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb428831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eafafc2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eafafc2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eafafa7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eafac570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eafac56dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb428832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4288330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4288330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eafac56cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c (2879 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei32_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei32_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei32_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei32_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056299560915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005629956060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056299560989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9535b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9535b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9535b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9535aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056299559ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056299559ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562995583b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005629952330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562995232dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9535aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9535aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9535aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562995232cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c (2880 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsub_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsub_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsub_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsub_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsub_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   stor
# | ...
# `---data was truncated (10240/29518) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ef347f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563ef347c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563ef347f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f498c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f498c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f498c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f498c51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ef3414e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563ef3414c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563ef33f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563ef30a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563ef30a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f498c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f498c51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f498c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ef30a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c (2881 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055809dcbe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055809dcbb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055809dcbe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c0c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c0c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c0c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c0c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055809dc53e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055809dc53c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055809dc38b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055809d8e80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055809d8e7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9c0c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c0c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c0c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055809d8e7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c (2882 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vv_i8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vor_vx_i8mf8(<vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vv_i8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vor_vx_i8mf4(<vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vv_i8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vor_vx_i8mf2(<vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vv_i8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vor_vx_i8m1(<vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vv_i8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vor_vx_i8m2(<vscale x 16 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i8, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i8 %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vor_vv_i8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %op2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, pt
# | ...
# `---data was truncated (10240/174721) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d89fc6d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d89fc6a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d89fc6d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e98a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e98aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e98a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e98a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d89fc02e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d89fc02c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d89fbe7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d89f8970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d89f896dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3e98a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e98a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e98a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d89f896cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c (2883 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -target-feature +zve64d    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vtmv_v_t_bf16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vtmv.v.t.nxv32bf16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vtmv.v.t.nxv32bf16.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vtmv_v_t_f16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.sf.vtmv.v.t.nxv32f16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 32 x half> @llvm.riscv.sf.vtmv.v.t.nxv32f16.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vtmv_v_t_f32m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 16 x float> @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x double> @test_sf_vtmv_v_t_f64m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x double> @llvm.riscv.sf.vtmv.v.t.nxv8f64.i64(i64 %0, i64 %1)
# |   ret <vscale x 8 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 8 x double> @llvm.riscv.sf.vtmv.v.t.nxv8f64.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_i8m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_sf_vtmv_v_t_i16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 32 x i16> @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vtmv_v_t_i32m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vtmv_v_t_i64m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_u8m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_sf_vtmv_v_t_u16m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vtmv_v_t_u32m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vtmv_v_t_u64m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_f8e4m3m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_sf_vtmv_v_t_f8e5m2m8(i64 noundef %tss, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfofp8min,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvfhmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfhmin1p0_zvfofp8min0p9_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056146bdb115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056146bdae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056146bdb189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80cb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80cb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80cb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80cb431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056146bd46e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056146bd46c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056146bd2bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056146b9db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056146b9dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f80cb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80cb4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80cb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056146b9dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c (2884 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_u32m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_u32m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_u32m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   
# | ...
# `---data was truncated (10240/23061) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562a371e715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562a371e40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562a371e789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff82d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff82d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff82d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff82d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562a3717ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562a3717cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562a37161b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562a36e110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562a36e10dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff82d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff82d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff82d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562a36e10cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c (2885 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1
# | ...
# `---data was truncated (10240/26772) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1c7e4115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a1c7e3e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a1c7e4189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcfed249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcfed2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcfed249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcfed231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1c7dd6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a1c7dd6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a1c7dbbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a1c7a6b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a1c7a6add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcfed232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcfed2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcfed2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1c7a6acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c (2886 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg7e8_v_i8mf8x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/21566) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055772b70e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055772b70b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055772b70e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdffb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdffb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdffb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdffb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055772b6a3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055772b6a3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055772b688b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055772b3380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055772b337dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdffb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdffb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdffb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055772b337cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c (2887 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf8x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf4x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8mf2x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_u8m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564738b3d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564738b3a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564738b3d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f76e1a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f76e1a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f76e1a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f76e1a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564738ad2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564738ad2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564738ab7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005647387670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564738766dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f76e1a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f76e1a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f76e1a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564738766cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c (2888 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m1x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_u64m2x4(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tu
# | ...
# `---data was truncated (10240/14044) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056310497615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005631049730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056310497689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f247b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f247b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f247b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f247b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056310490be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056310490bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005631048f0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005631045a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056310459fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f247b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f247b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f247b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056310459fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c (2889 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale
# | ...
# `---data was truncated (10240/10790) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c92a22d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c92a22a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c92a22d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f06d9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f06d90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f06d9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f06d9031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c92a1c2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c92a1c2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c92a1a7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c929e570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c929e56dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f06d9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f06d90330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f06d90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c929e56cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c (2890 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a936d6715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a936d640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a936d6789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdd83d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdd83d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdd83d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdd83d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a936cfce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a936cfcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a936ce1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a9369910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a936990dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdd83d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdd83d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdd83d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a936990cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c (2891 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_i16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_i16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_i16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_i16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_i16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_i16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vreinterpret_v_u16mf4_bf16mf4(<vscale x 1 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x i16>, align 2
# |   store <vscale x 1 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x i16> %0 to <vscale x 1 x bfloat>
# |   ret <vscale x 1 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vreinterpret_v_u16mf2_bf16mf2(<vscale x 2 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x i16>, align 2
# |   store <vscale x 2 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x i16> %0 to <vscale x 2 x bfloat>
# |   ret <vscale x 2 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vreinterpret_v_u16m1_bf16m1(<vscale x 4 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x i16>, align 2
# |   store <vscale x 4 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x i16> %0 to <vscale x 4 x bfloat>
# |   ret <vscale x 4 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vreinterpret_v_u16m2_bf16m2(<vscale x 8 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x i16>, align 2
# |   store <vscale x 8 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x i16> %0 to <vscale x 8 x bfloat>
# |   ret <vscale x 8 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vreinterpret_v_u16m4_bf16m4(<vscale x 16 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x i16>, align 2
# |   store <vscale x 16 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x i16> %0 to <vscale x 16 x bfloat>
# |   ret <vscale x 16 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vreinterpret_v_u16m8_bf16m8(<vscale x 32 x i16> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x i16>, align 2
# |   store <vscale x 32 x i16> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x i16>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x i16> %0 to <vscale x 32 x bfloat>
# |   ret <vscale x 32 x bfloat> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_i16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_i16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_i16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_i16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_i16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 to <vscale x 16 x i16>
# |   ret <vscale x 16 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i16> @test_vreinterpret_v_bf16m8_i16m8(<vscale x 32 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 32 x bfloat> %0 to <vscale x 32 x i16>
# |   ret <vscale x 32 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i16> @test_vreinterpret_v_bf16mf4_u16mf4(<vscale x 1 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 1 x bfloat> %0 to <vscale x 1 x i16>
# |   ret <vscale x 1 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i16> @test_vreinterpret_v_bf16mf2_u16mf2(<vscale x 2 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 2 x bfloat> %0 to <vscale x 2 x i16>
# |   ret <vscale x 2 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i16> @test_vreinterpret_v_bf16m1_u16m1(<vscale x 4 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 4 x bfloat> %0 to <vscale x 4 x i16>
# |   ret <vscale x 4 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i16> @test_vreinterpret_v_bf16m2_u16m2(<vscale x 8 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 8 x bfloat> %0 to <vscale x 8 x i16>
# |   ret <vscale x 8 x i16> %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i16> @test_vreinterpret_v_bf16m4_u16m4(<vscale x 16 x bfloat> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = bitcast <vscale x 16 x bfloat> %0 to <vsca
# | ...
# `---data was truncated (10240/11229) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593201be15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005593201bb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005593201be89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f285b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f285b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f285b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f285b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559320153e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559320153c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559320138b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055931fde80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055931fde7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f285b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f285b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f285b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055931fde7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c (2892 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_i16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e1
# | ...
# `---data was truncated (10240/63053) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f89c71615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f89c7130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f89c71689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e93b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e93b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e93b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e93aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f89c6abe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f89c6abc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f89c690b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f89c3400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f89c33fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1e93aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e93aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e93aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f89c33fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c (2893 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056101ddf415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056101ddf10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056101ddf489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4696649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f46966a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4696649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4696631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056101dd89e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056101dd89c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056101dd6eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056101da1e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056101da1ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4696632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f46966330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f46966330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056101da1dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c (2894 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.vlte64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vlte64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556739b5115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556739b4e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556739b5189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c9441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c944725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c9441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c94403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556739ae6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556739ae6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556739acbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055673977b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055673977add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3c94404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c944050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c944050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055673977acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c (2895 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f16m1x6(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f32m1x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_f64m1x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei8_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vsca
# | ...
# `---data was truncated (10240/61665) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d32e69515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d32e6920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d32e69589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98a9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98a978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98a9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98a971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d32e62ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d32e62ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d32e60fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d32e2bf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d32e2bedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f98a971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98a971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98a971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d32e2becc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c (2896 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/61937) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560920a0a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560920a070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560920a0a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe51e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe51ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe51e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe51e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056092099fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056092099fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560920984b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005609206340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560920633dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbe51e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe51e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe51e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560920633cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c (2897 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005632533fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005632533f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005632533fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61f4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61f478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61f4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61f471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563253391e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563253391c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563253376b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005632530260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563253025dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f61f471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61f471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61f471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563253025cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c (2898 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005559766ef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005559766ec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005559766ef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd3c9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd3c9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd3c9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd3c9f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555976684e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555976684c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555976669b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005559763190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555976318dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd3c9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd3c9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd3c9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555976318cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c (2899 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b9d90c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561b9d9090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561b9d90c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6089533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f608958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6089533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f608951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b9d8a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561b9d8a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561b9d886b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561b9d5360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561b9d535dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f608951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f608951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f608951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b9d535cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c (2900 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f91cc1715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f91cc140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f91cc1789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8f72933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8f7298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8f72933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8f7291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f91cbace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f91cbacc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f91cb91b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f91c8410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f91c840dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8f7291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8f7291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8f7291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f91c840cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c (2901 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_i32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_i32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_u32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_u32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32ff_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32ff_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 7), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560bd921415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560bd92110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560bd921489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f178b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f178b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f178b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f178b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560bd91a9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560bd91a9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560bd918eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560bd8e3e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560bd8e3ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f178b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f178b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f178b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560bd8e3dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c (2902 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8(<vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4(<vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2(<vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1(<vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_x_f_qf_i8m2(<vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load float, ptr %rs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> poison, <vscale x 16 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_x_f_qf_i8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_x_f_qf_i8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_x_f_qf_i8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_x_f_qf_i8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> poison, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %0, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocall
# | ...
# `---data was truncated (10240/12425) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584c784a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005584c78470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005584c784a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f685df05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f685df5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f685df05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f685deed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584c77dfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005584c77dfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005584c77c4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005584c74740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005584c7473dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f685deeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f685deef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f685deef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584c7473cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c (2903 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf4(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16mf2(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m1(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m2(ptr noundef %base, <vscale x 8 x i8> %bindex, <vscale x 8 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i8>, align 1
# |   %value.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 8 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m4(ptr noundef %base, <vscale x 16 x i8> %bindex, <vscale x 16 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i8>, align 1
# |   %value.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 16 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 16 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f16m8(ptr noundef %base, <vscale x 32 x i8> %bindex, <vscale x 32 x half> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 32 x i8>, align 1
# |   %value.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 32 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 32 x half> %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 32 x half>, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32mf2(ptr noundef %base, <vscale x 1 x i8> %bindex, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(<vscale x 1 x float>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m1(ptr noundef %base, <vscale x 2 x i8> %bindex, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(<vscale x 2 x float>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsuxei8_v_f32m2(ptr noundef %base, <vscale x 4 x i8> %bindex, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i8.i64(<vscale x 4 x float> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory
# | ...
# `---data was truncated (10240/135997) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584b237015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005584b236d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005584b237089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcadb333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcadb38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcadb333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcadb31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005584b2305e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005584b2305c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005584b22eab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005584b1f9a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005584b1f99dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcadb31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcadb31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcadb31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584b1f99cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c (2904 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055559b51215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055559b50f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055559b51289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6855049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f68550a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6855049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6855031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055559b4a7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055559b4a7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055559b48cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055559b13c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055559b13bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6855032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f68550330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f68550330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055559b13bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c (2905 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsca
# | ...
# `---data was truncated (10240/15622) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac6391615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ac639130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ac6391689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7c0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7c0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7c0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7c0a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac638abe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ac638abc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ac63890b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ac635400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ac6353fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe7c0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7c0a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7c0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac6353fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c (2906 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmul_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmul_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmul_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmul_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, a
# | ...
# `---data was truncated (10240/18875) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f41c8a415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f41c8a10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f41c8a489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2946649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29466a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2946649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2946631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f41c839e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f41c839c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f41c81eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f41c4ce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f41c4cddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2946632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29466330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29466330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f41c4cdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c (2907 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560475be215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560475bdf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560475be289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa840b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa840b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa840b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa840b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560475b77e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560475b77c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560475b5cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056047580c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056047580bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa840b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa840b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa840b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056047580bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c (2908 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <v
# | ...
# `---data was truncated (10240/16552) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f4b7e4615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f4b7e430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f4b7e4689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f58cc905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f58cc95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f58cc905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f58cc8ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f4b7ddbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f4b7ddbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f4b7dc0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f4b7a700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f4b7a6fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f58cc8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f58cc8ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f58cc8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f4b7a6fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c (2909 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e64_v_f64m2x4_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 
# | ...
# `---data was truncated (10240/32125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005589dd7c915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005589dd7c60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005589dd7c989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2eccf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2eccf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2eccf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2eccf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589dd75ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005589dd75ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005589dd743b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005589dd3f30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005589dd3f2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2eccf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2eccf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2eccf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005589dd3f2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c (2910 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.
# | ...
# `---data was truncated (10240/16808) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8cc54915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d8cc5460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d8cc54989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde23d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde23d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde23d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde23d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8cc4dee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d8cc4dec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d8cc4c3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d8cc1730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d8cc172dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fde23d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde23d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde23d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8cc172cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c (2911 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf26f0c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cf26f090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cf26f0c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6059849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60598a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6059849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6059831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf26ea1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cf26ea1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cf26e86b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cf26b360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cf26b35dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6059832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60598330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60598330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf26b35cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c (2912 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vluxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056202aca815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056202aca50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056202aca889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc725649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7256a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc725649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc725631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056202ac3de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056202ac3dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056202ac22b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056202a8d20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056202a8d1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc725632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7256330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7256330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056202a8d1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c (2913 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df5c4eb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055df5c4e80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055df5c4eb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0ab933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0ab98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0ab933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0ab91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df5c480e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055df5c480c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055df5c465b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055df5c1150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055df5c114dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd0ab91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0ab91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0ab91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df5c114cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c (2914 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d728fbe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d728fbb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d728fbe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fead401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fead40725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fead401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fead4003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d728f53e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d728f53c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d728f38b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d728be80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d728be7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fead4004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fead40050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fead40050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d728be7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c (2915 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/25817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e7a09515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556e7a0920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556e7a09589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa2fdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa2fdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa2fdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa2fdd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e7a02ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556e7a02ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556e7a00fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556e79cbf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556e79cbedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa2fdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa2fdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa2fdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e79cbecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c (2916 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c -o -    -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_fcvt_s_bf16(bfloat noundef %bf) #0 {
# | entry:
# |   %bf.addr.i = alloca bfloat, align 2
# |   %bf.addr = alloca bfloat, align 2
# |   store bfloat %bf, ptr %bf.addr, align 2
# |   %0 = load bfloat, ptr %bf.addr, align 2
# |   store bfloat %0, ptr %bf.addr.i, align 2
# |   %1 = load bfloat, ptr %bf.addr.i, align 2
# |   %2 = fpext bfloat %1 to float
# |   ret float %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_fcvt_bf16_s(float noundef %sf) #0 {
# | entry:
# |   %sf.addr.i = alloca float, align 4
# |   %sf.addr = alloca float, align 4
# |   store float %sf, ptr %sf.addr, align 4
# |   %0 = load float, ptr %sf.addr, align 4
# |   store float %0, ptr %sf.addr.i, align 4
# |   %1 = load float, ptr %sf.addr.i, align 4
# |   %2 = fptrunc float %1 to bfloat
# |   ret bfloat %2
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+f,+i,+xandesbfhcvt,+zicsr" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d26b4b215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d26b4af0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d26b4b289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f39b6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f39b6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f39b6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f39b6e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d26b447e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d26b447c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d26b42cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d26b0dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d26b0dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f39b6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f39b6e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f39b6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d26b0dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c (2917 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_f32mf2(<vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_f32mf2(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(<vscale x 1 x float>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_f32mf2(<vscale x 1 x float> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_f32mf2(<vscale x 1 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(<vscale x 1 x float>, <vscale x 1 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_f32m1(<vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_f32m1(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_f32m1(<vscale x 2 x float> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_f32m1(<vscale x 2 x float> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(<vscale x 2 x float>, <vscale x 2 x float>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_f32m2(<vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(<vscale x 4 x float>, <vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_f32m2(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, a
# | ...
# `---data was truncated (10240/151903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581cea0a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005581cea070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005581cea0a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda9a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda9a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda9a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda9a003507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581ce99fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005581ce99fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005581ce984b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005581ce6340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005581ce633dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fda9a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda9a0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda9a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581ce633cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c (2918 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac8eac315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ac8eac00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ac8eac389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f61df133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f61df18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f61df133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f61df11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac8ea58e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ac8ea58c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ac8ea3db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ac8e6ed0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ac8e6ecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f61df11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f61df11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f61df11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac8e6eccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c (2919 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e64_v_f64m1x3_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e64_v_f64m2x3_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 
# | ...
# `---data was truncated (10240/32125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056167073f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056167073c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056167073f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f47fe933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f47fe98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f47fe933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f47fe91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005616706d4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005616706d4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005616706b9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005616703690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561670368dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f47fe91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f47fe91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f47fe91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561670368cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c (2920 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055df11ea715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055df11ea40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055df11ea789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56f081bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56f08725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56f081ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56f0803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055df11e3ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055df11e3cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055df11e21b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055df11ad10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055df11ad0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f56f0804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56f08050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56f08050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055df11ad0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c (2921 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 
# | ...
# `---data was truncated (10240/14824) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8fdbd915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a8fdbd60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a8fdbd989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8e01d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8e01d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8e01d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8e01d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8fdb6ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a8fdb6ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a8fdb53b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a8fd8030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a8fd802dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8e01d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8e01d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8e01d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8fd802cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c (2922 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f16m1x8(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f32m1x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_f64m1x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei8_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb464e315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cb464e00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cb464e389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd96a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd96aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd96a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd96a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb46478e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cb46478c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cb4645db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cb4610d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cb4610cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcd96a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd96a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd96a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb4610ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c (2923 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_f16mf4x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_f16mf2x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_f16m1x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556632da615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556632da30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556632da689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e3201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e320725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e3201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e32003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556632d3be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556632d3bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556632d20b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005566329d00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005566329cfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4e32004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e320050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e320050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005566329cfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c (2924 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056335047e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056335047b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056335047e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007eff3fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007eff3faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007eff3fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007eff3fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563350413e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563350413c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005633503f8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005633500a80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005633500a7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007eff3fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007eff3fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007eff3fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633500a7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c (2925 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei8_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei8_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei8_v_bf16m1x
# | ...
# `---data was truncated (10240/25695) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ec9950c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ec995090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ec9950c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff241649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2416a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff241649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff241631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ec994a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ec994a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ec99486b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ec991360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ec99135dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff241632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2416330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2416330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ec99135cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c (2926 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmulh_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmulh_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmulh_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmulh_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vmulh_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i8> %op
# | ...
# `---data was truncated (10240/222917) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562226b2f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562226b2c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562226b2f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd042b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd042b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd042b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd042b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562226ac4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562226ac4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562226aa9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005622267590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562226758dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd042b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd042b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd042b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562226758cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c (2927 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("ri
# | ...
# `---data was truncated (10240/32023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b89b84e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b89b84b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b89b84e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdea6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdea6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdea6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdea6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b89b7e3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b89b7e3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b89b7c8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b89b4780b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b89b477dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdea6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdea6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdea6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b89b477cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c (2928 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 7), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsoxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %v_tuple, i64 noundef
# | ...
# `---data was truncated (10240/69988) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056414b5af15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056414b5ac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056414b5af89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd9d61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd9d6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd9d61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd9d603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056414b544e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056414b544c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056414b529b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056414b1d90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056414b1d8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efd9d604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd9d6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd9d6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056414b1d8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c (2929 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b7910115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555b790fe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555b7910189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf90133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf9018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf90133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf9011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b79096e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555b79096c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555b7907bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555b78d2b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555b78d2add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faf9011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf9011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf9011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b78d2acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c (2930 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %
# | ...
# `---data was truncated (10240/13690) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1d71ae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e1d71ab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e1d71ae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa84c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa84c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa84c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa84c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1d7143e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e1d7143c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e1d7128b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e1d6dd80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e1d6dd7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa84c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa84c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa84c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1d6dd7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c (2931 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a1f555c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a1f55590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a1f555c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee91449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee914a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee91449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee91431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a1f54f1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a1f54f1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a1f54d6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a1f51860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a1f5185dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fee91432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee914330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee914330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a1f5185cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c (2932 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfneg_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfneg_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfneg_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfneg_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfneg_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfneg_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfneg_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfneg_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfneg_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfneg_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfneg_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfneg_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.
# | ...
# `---data was truncated (10240/30869) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e02bab615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e02bab30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e02bab689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d34e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d34ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d34e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d34e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e02ba4be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e02ba4bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e02ba30b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e02b6e00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e02b6dfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9d34e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d34e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d34e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e02b6dfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c (2933 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555f0ae215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005555f0adf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005555f0ae289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c27f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c27f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c27f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c27f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005555f0a77e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005555f0a77c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005555f0a5cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005555f070c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005555f070bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1c27f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c27f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c27f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005555f070bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c (2934 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/23365) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e08c4615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559e08c430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559e08c4689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007febc701bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007febc70725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007febc701ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007febc7003507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e08bdbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559e08bdbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559e08bc0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559e088700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559e0886fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007febc7004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007febc70050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007febc70050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e0886fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c (2935 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb6873b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eb687380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eb6873b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f13c2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f13c22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f13c2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f13c2231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb686d0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eb686d0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eb686b5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eb683650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eb68364dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f13c2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f13c22330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f13c22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb68364cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c (2936 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.
# | ...
# `---data was truncated (10240/18498) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e89750215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e8974ff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e89750289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6c4d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6c4d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6c4d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6c4d831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e897497e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e897497c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e89747cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e89712c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e89712bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6c4d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6c4d8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6c4d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e89712bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c (2937 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnot_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnot_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnot_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnot_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnot_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnot_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnot_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564dc4b4515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564dc4b420f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564dc4b4589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9cbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9cbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9cbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9cbb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564dc4adae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564dc4adac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564dc4abfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564dc476f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564dc476edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb9cbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9cbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9cbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564dc476ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c (2938 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e676d815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559e676d50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559e676d889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1eb8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1eb898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1eb8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1eb891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e6766de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559e6766dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559e67652b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559e673020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559e67301dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1eb891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1eb891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1eb891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e67301cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c (2939 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d8d78bb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d8d78b80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d8d78bb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2e57533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2e5758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2e57533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2e5751b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d8d7850e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d8d7850c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d8d7835b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d8d74e50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d8d74e4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2e5751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2e5751d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2e5751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d8d74e4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c (2940 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564be70b015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564be70ad0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564be70b089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f27ae849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f27ae8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f27ae849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f27ae831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564be7045e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564be7045c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564be702ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564be6cda0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564be6cd9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f27ae832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f27ae8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f27ae8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564be6cd9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c (2941 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d3dff5a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d3dff570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d3dff5a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3f39533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3f3958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3f39533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3f3951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d3dfeefe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d3dfeefc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d3dfed4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d3dfb840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d3dfb83dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3f3951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3f3951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3f3951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d3dfb83cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c (2942 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64
# | ...
# `---data was truncated (10240/32709) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649f230715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005649f23040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005649f230789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effe9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effe918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effe9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effe911b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649f229ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005649f229cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005649f2281b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005649f1f310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005649f1f30dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007effe911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effe911d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effe911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649f1f30cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c (2943 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnot_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnot_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnot_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnot_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnot_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnot_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnot_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573a7a4415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005573a7a410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005573a7a4489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f60ec449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60ec4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f60ec449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60ec431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005573a79d9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005573a79d9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005573a79beb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005573a766e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005573a766ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f60ec432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60ec4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60ec4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005573a766dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c (2944 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005618c841b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005618c84180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005618c841b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f29c1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f29c178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f29c1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29c171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005618c83b0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005618c83b0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005618c8395b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005618c80450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005618c8044dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f29c171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29c171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29c171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005618c8044cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c (2945 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %maskedoff, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %m
# | ...
# `---data was truncated (10240/41661) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055faece6015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055faece5d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055faece6089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d88649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d886a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d88649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d88631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055faecdf5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055faecdf5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055faecddab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055faeca8a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055faeca89dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8d88632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d886330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d886330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055faeca89cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c (2946 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei64_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei64_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei64_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557a76ee415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557a76ee10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557a76ee489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd686049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6860a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd686049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd686031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557a76e79e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557a76e79c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557a76e5eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557a76b0e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557a76b0ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd686032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6860330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6860330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557a76b0dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c (2947 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4(<vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2(<vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1(<vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2(<vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4(<vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8(<vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2(<vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1(<vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vcompress_vm_f32m2(<vscale x 4 x float> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vcompress_vm_f32m4(<vscale x 8 x float> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 
# | ...
# `---data was truncated (10240/62956) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055de397aa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055de397a70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055de397aa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa9ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa9baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa9ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa9ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055de3973fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055de3973fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055de39724b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055de393d40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055de393d3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faa9ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa9ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa9ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055de393d3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c (2948 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <
# | ...
# `---data was truncated (10240/34430) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555b6bcb715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555b6bcb40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555b6bcb789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3710d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3710d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3710d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3710ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555b6bc4ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555b6bc4cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555b6bc31b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555b6b8e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555b6b8e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3710ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3710cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3710cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555b6b8e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c (2949 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |  
# | ...
# `---data was truncated (10240/26713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb5fd9915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bb5fd960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bb5fd9989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f827d61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f827d6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f827d61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f827d603507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb5fd2ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bb5fd2ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bb5fd13b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bb5f9c30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bb5f9c2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f827d604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f827d6050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f827d6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb5f9c2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c (2950 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559f46d6115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559f46d5e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559f46d6189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f709221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f70922725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f709221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7092203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559f46cf6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559f46cf6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559f46cdbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559f4698b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559f4698add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7092204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f70922050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f70922050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559f4698acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c (2951 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmacc_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmacc_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmacc_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmacc_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmacc.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | ...
# `---data was truncated (10240/34356) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562fd00f015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562fd00ed0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562fd00f089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f74f8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f74f878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f74f8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f74f871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562fd0085e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562fd0085c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562fd006ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562fcfd1a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562fcfd19dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f74f871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f74f871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f74f871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562fcfd19cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c (2952 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %
# | ...
# `---data was truncated (10240/201226) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f6eac2d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f6eac2a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f6eac2d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb96c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb96c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb96c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb96c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f6eabc2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f6eabc2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f6eaba7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f6ea8570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f6ea856dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb96c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb96c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb96c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f6ea856cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c (2953 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vv_u64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vclmulh_vx_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vv_u64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vclmulh_vx_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vv_u64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 8 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i64> @test_vclmulh_vx_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vclmulh_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   
# | ...
# `---data was truncated (10240/18925) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d5688315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556d568800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556d5688389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe7b6e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe7b6e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe7b6e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe7b6e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d56818e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556d56818c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556d567fdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556d564ad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556d564acdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe7b6e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe7b6e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe7b6e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d564accc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c (2954 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dbe095715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dbe09540f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dbe095789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa239733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa23978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa239733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa23971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dbe08ece2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dbe08ecc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dbe08d1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dbe05810b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dbe0580dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa23971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa23971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa23971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dbe0580cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c (2955 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vlse8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vlse8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, i64 %2, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vlse8_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, i64 %2, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 32 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vlse8_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, i64 %2, <vscale x 64 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 64 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vlse8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vlse8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vlse8_v_
# | ...
# `---data was truncated (10240/15323) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a91492c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a9149290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a91492c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fde4e105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fde4e15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fde4e105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fde4e0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9148c1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a9148c1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a9148a6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a9145560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a914555dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fde4e0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fde4e0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fde4e0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a914555cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c (2956 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560bba57815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560bba5750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560bba57889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34ba733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34ba78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34ba733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34ba71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560bba50de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560bba50dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560bba4f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560bba1a20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560bba1a1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f34ba71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34ba71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34ba71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560bba1a1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c (2957 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/15944) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056039067515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005603906720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056039067589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb96f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb96f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb96f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb96f631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056039060ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056039060ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005603905efb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056039029f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056039029edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb96f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb96f6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb96f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056039029ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c (2958 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f32.p0.i64(<vscale x 1 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f32.p0.i64(<vscale x 2 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f32.p0.i64(<vscale x 4 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f32.p0.i64(<vscale x 8 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x float> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x float> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x float>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16f32.p0.i64(<vscale x 16 x float>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i32.p0.i64(<vscale x 2 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i32.p0.i64(<vscale x 4 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i32.p0.i64(<vscale x 8 x i32>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i32> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i32> %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %value.addr, align 4
# |   %3 = load i64, ptr %vl.a
# | ...
# `---data was truncated (10240/33190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560cafddb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560cafdd80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560cafddb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fea67849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fea678a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fea67849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fea67831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560cafd70e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560cafd70c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560cafd55b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560cafa050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560cafa04dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fea67832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fea678330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fea678330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560cafa04cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c (2959 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vloxei8_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vloxei8_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vloxei8_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i8> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vloxei8_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i8> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vloxei8_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vloxei8_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Fu
# | ...
# `---data was truncated (10240/30423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fdeeda115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fdeed9e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fdeeda189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2944905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f294495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2944905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f29448ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fdeed36e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fdeed36c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fdeed1bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fdee9cb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fdee9cadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f29448eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f29448ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f29448ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fdee9cacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c (2960 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vvm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vmerge_vxm_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vvm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vmerge_vxm_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vvm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vmerge_vxm_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4)
# |   ret <vscale x 4 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vmerge_vvm_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4)
# |   ret <vscale x 8 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | de
# | ...
# `---data was truncated (10240/148020) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557fdb86b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557fdb8680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557fdb86b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5826f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5826f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5826f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5826f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557fdb800e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557fdb800c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557fdb7e5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557fdb4950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557fdb494dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5826f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5826f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5826f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557fdb494cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c (2961 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/23357) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557da165315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557da16500f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557da165389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd684449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6844a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd684449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd684431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557da15e8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557da15e8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557da15cdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557da127d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557da127cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd684432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6844330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6844330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557da127ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c (2962 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesef_vs_u32mf2_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32mf2_u32m1(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32mf2_u32m2(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32mf2_u32m4(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesef_vs_u32mf2_u32m8(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesef_vs_u32m1_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesef_vs_u32m1_u32m2(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesef_vs_u32m1_u32m4(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | ...
# `---data was truncated (10240/20149) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d8e85e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562d8e85b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562d8e85e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f18ced33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f18ced8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f18ced33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f18ced1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d8e7f3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562d8e7f3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562d8e7d8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562d8e4880b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562d8e487dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f18ced1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f18ced1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f18ced1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d8e487cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c (2963 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005642fb3d515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005642fb3d20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005642fb3d589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4486649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44866a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4486649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4486631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005642fb36ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005642fb36ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005642fb34fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005642fafff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005642faffedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4486632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44866330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44866330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005642faffecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c (2964 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f82d62c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f82d6290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f82d62c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d32733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d3278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d32733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d3271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f82d5c1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f82d5c1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f82d5a6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f82d2560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f82d255dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2d3271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d3271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d3271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f82d255cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c (2965 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg
# | ...
# `---data was truncated (10240/20483) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd37d6515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fd37d620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fd37d6589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa9e9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa9e92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa9e9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa9e9231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd37cfae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fd37cfac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fd37cdfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fd3798f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fd3798edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa9e9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa9e92330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa9e92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd3798ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c (2966 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> %1, ptr %2, <vscale x 4 x i1> %0, i64 %3,
# | ...
# `---data was truncated (10240/29443) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f1e7bf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558f1e7bc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558f1e7bf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0f8f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0f8f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0f8f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0f8f11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f1e754e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558f1e754c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558f1e739b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558f1e3e90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558f1e3e8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0f8f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0f8f11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0f8f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f1e3e8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c (2967 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfeq_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfeq_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c17b7e515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c17b7e20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c17b7e589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa276c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa276ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa276c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa276c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c17b77ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c17b77ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c17b75fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c17b40f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c17b40edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa276c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa276c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa276c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c17b40ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c (2968 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_u32m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0
# | ...
# `---data was truncated (10240/14010) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f6ab4315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556f6ab400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556f6ab4389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efdfd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efdfd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efdfd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efdfd231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f6aad8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556f6aad8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556f6aabdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556f6a76d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556f6a76cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efdfd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efdfd2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efdfd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f6a76ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c (2969 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 8 x i64>, ptr %
# | ...
# `---data was truncated (10240/20631) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bafb24f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bafb24c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bafb24f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7188f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7188f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7188f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7188f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bafb1e4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bafb1e4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bafb1c9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bafae790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bafae78dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7188f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7188f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7188f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bafae78cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/attr-counted-by-issue200014.c (2970 of 27911)
******************** TEST 'Clang :: CodeGen/attr-counted-by-issue200014.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 11
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -O0 -Wno-missing-declarations    -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c    | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -O0 -Wno-missing-declarations -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.annotated_flex = type { i64, i8, [0 x i8] }
# | 
# | @gaf = global { i64, i8, [15 x i8] } { i64 10, i8 0, [15 x i8] c"i am very long\00" }, align 8
# | @sink = external global i64, align 8
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @local_fam(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %af = alloca %struct.annotated_flex, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0
# |   %0 = load i64, ptr %n.addr, align 8
# |   store i64 %0, ptr %count, align 8
# |   %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1
# |   store i8 0, ptr %induce_padding, align 8
# |   %1 = getelementptr i8, ptr %af, i64 9
# |   call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false)
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arraydecay = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 0
# |   %2 = ptrtoint ptr %arraydecay to i64
# |   store i64 %2, ptr @sink, align 8
# |   %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arraydecay2 = getelementptr inbounds [0 x i8], ptr %fam1, i64 0, i64 0
# |   %counted_by.gep = getelementptr inbounds i8, ptr %af, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %3 = icmp sgt i64 %flexible_array_member_size, -1
# |   %4 = select i1 %3, i64 %flexible_array_member_size, i64 0
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @local_subscript(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %af = alloca %struct.annotated_flex, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0
# |   %0 = load i64, ptr %n.addr, align 8
# |   store i64 %0, ptr %count, align 8
# |   %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1
# |   store i8 0, ptr %induce_padding, align 8
# |   %1 = getelementptr i8, ptr %af, i64 9
# |   call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false)
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arrayidx = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 2
# |   %2 = ptrtoint ptr %arrayidx to i64
# |   store i64 %2, ptr @sink, align 8
# |   %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %arrayidx2 = getelementptr inbounds [0 x i8], ptr %fam1, i64 0, i64 2
# |   %counted_by.gep = getelementptr inbounds i8, ptr %af, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %result = sub nuw i64 %flexible_array_member_size, 2
# |   %3 = icmp sgt i64 %result, -1
# |   %4 = and i1 true, %3
# |   %5 = select i1 %4, i64 %result, i64 0
# |   ret i64 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @local_addrof(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %af = alloca %struct.annotated_flex, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0
# |   %0 = load i64, ptr %n.addr, align 8
# |   store i64 %0, ptr %count, align 8
# |   %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1
# |   store i8 0, ptr %induce_padding, align 8
# |   %1 = getelementptr i8, ptr %af, i64 9
# |   call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false)
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %2 = ptrtoint ptr %fam to i64
# |   store i64 %2, ptr @sink, align 8
# |   %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2
# |   %3 = call i64 @llvm.objectsize.i64.p0(ptr %fam1, i1 false, i1 true, i1 true)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.objectsize.i64.p0(ptr, i1 immarg, i1 immarg, i1 immarg) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @global_fam() #0 {
# | entry:
# |   %counted_by.load = load i64, ptr @gaf, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %0 = icmp sgt i64 %flexible_array_member_size, -1
# |   %1 = select i1 %0, i64 %flexible_array_member_size, i64 0
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @global_subscript() #0 {
# | entry:
# |   %counted_by.load = load i64, ptr @gaf, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %result = sub nuw i64 %flexible_array_member_size, 3
# |   %0 = icmp sgt i64 %result, -1
# |   %1 = and i1 true, %0
# |   %2 = select i1 %1, i64 %result, i64 0
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @global_addrof() #0 {
# | entry:
# |   %0 = call i64 @llvm.objectsize.i64.p0(ptr getelementptr inbounds nuw (i8, ptr @gaf, i64 9), i1 false, i1 true, i1 true)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @ptr_fam(ptr noundef %p) #0 {
# | entry:
# |   %p.addr = alloca ptr, align 8
# |   store ptr %p, ptr %p.addr, align 8
# |   %0 = load ptr, ptr %p.addr, align 8
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2
# |   %arraydecay = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 0
# |   %1 = load ptr, ptr %p.addr, align 8
# |   %counted_by.gep = getelementptr inbounds i8, ptr %1, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %2 = icmp sgt i64 %flexible_array_member_size, -1
# |   %3 = select i1 %2, i64 %flexible_array_member_size, i64 0
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @ptr_subscript(ptr noundef %p) #0 {
# | entry:
# |   %p.addr = alloca ptr, align 8
# |   store ptr %p, ptr %p.addr, align 8
# |   %0 = load ptr, ptr %p.addr, align 8
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2
# |   %arrayidx = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 3
# |   %1 = load ptr, ptr %p.addr, align 8
# |   %counted_by.gep = getelementptr inbounds i8, ptr %1, i64 0
# |   %counted_by.load = load i64, ptr %counted_by.gep, align 4
# |   %flexible_array_member_size = mul nuw i64 %counted_by.load, 1
# |   %result = sub nuw i64 %flexible_array_member_size, 3
# |   %2 = icmp sgt i64 %result, -1
# |   %3 = and i1 true, %2
# |   %4 = select i1 %3, i64 %result, i64 0
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @ptr_addrof(ptr noundef %p) #0 {
# | entry:
# |   %p.addr = alloca ptr, align 8
# |   store ptr %p, ptr %p.addr, align 8
# |   %0 = load ptr, ptr %p.addr, align 8
# |   %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2
# |   %1 = call i64 @llvm.objectsize.i64.p0(ptr %fam, i1 false, i1 true, i1 true)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.ident = !{!0}
# | 
# | !0 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000565348adb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000565348ad80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000565348adb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1fd1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1fd1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1fd1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1fd1e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565348a70e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565348a70c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565348a55b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005653487050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000565348704dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1fd1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1fd1e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1fd1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565348704cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c (2971 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vv_bf16mf4(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmadd_vf_bf16mf4(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vv_bf16mf2(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmadd_vf_bf16mf2(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vv_bf16m1(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmadd_vf_bf16m1(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vv_bf16m2(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmadd_vf_bf16m2(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# | ...
# `---data was truncated (10240/34438) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5be66b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f5be6680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f5be66b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0497733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f049778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0497733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f049771b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5be600e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f5be600c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f5be5e5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f5be2950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f5be294dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f049771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f049771d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f049771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5be294cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c (2972 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e32_v_f32mf2x6_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscal
# | ...
# `---data was truncated (10240/35921) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b6a04d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556b6a04a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556b6a04d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f093c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f093c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f093c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f093c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b69fe2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556b69fe2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556b69fc7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556b69c770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556b69c76dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f093c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f093c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f093c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b69c76cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c (2973 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/14613) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590e2abf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005590e2abc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005590e2abf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa562d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa562d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa562d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa562d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590e2a54e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005590e2a54c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005590e2a39b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005590e26e90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005590e26e8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa562d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa562d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa562d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590e26e8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c (2974 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <
# | ...
# `---data was truncated (10240/48305) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601d781315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005601d78100f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005601d781389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b91f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b91f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b91f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b91f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601d77a8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005601d77a8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005601d778db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005601d743d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005601d743cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9b91f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b91f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b91f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601d743ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c (2975 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4(<vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2(<vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1(<vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2(<vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4(<vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561e4448115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561e4447e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561e4448189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc733f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc733f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc733f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc733f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561e44416e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561e44416c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561e443fbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561e440ab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561e440aadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc733f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc733f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc733f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561e440aacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/2008-07-17-no-emit-on-error.c (2976 of 27911)
******************** TEST 'Clang :: CodeGen/2008-07-17-no-emit-on-error.c' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 1
rm -f /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# executed command: rm -f /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DPASS /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2008-07-17-no-emit-on-error.c -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DPASS /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2008-07-17-no-emit-on-error.c -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output
# |  #0 0x00005593c761915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005593c76160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005593c761989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6a45449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6a454a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6a45449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6a45431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593c75aee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005593c75aec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005593c7593b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005593c72430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005593c7242dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6a45432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6a454330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6a454330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593c7242cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c (2977 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558d22a4615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558d22a430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558d22a4689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42e8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42e878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42e8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42e871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558d229dbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558d229dbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558d229c0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558d226700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558d2266fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f42e871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42e871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42e871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558d2266fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c (2978 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16mf4_f16(<vscale x 1 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16mf2_f16(<vscale x 2 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv2f16(<vscale x 2 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv2f16(<vscale x 2 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m1_f16(<vscale x 4 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv4f16(<vscale x 4 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv4f16(<vscale x 4 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m2_f16(<vscale x 8 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv8f16(<vscale x 8 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv8f16(<vscale x 8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m4_f16(<vscale x 16 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv16f16(<vscale x 16 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv16f16(<vscale x 16 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local half @test_vfmv_f_s_f16m8_f16(<vscale x 32 x half> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call half @llvm.riscv.vfmv.f.s.nxv32f16(<vscale x 32 x half> %0)
# |   ret half %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.riscv.vfmv.f.s.nxv32f16(<vscale x 32 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32mf2_f32(<vscale x 1 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m1_f32(<vscale x 2 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv2f32(<vscale x 2 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv2f32(<vscale x 2 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m2_f32(<vscale x 4 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv4f32(<vscale x 4 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv4f32(<vscale x 4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m4_f32(<vscale x 8 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv8f32(<vscale x 8 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv8f32(<vscale x 8 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local float @test_vfmv_f_s_f32m8_f32(<vscale x 16 x float> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call float @llvm.riscv.vfmv.f.s.nxv16f32(<vscale x 16 x float> %0)
# |   ret float %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.riscv.vfmv.f.s.nxv16f32(<vscale x 16 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m1_f64(<vscale x 1 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m2_f64(<vscale x 2 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv2f64(<vscale x 2 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv2f64(<vscale x 2 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m4_f64(<vscale x 4 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv4f64(<vscale x 4 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv4f64(<vscale x 4 x double>) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local double @test_vfmv_f_s_f64m8_f64(<vscale x 8 x double> %src) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = call double @llvm.riscv.vfmv.f.s.nxv8f64(<vscale x 8 x double> %0)
# |   ret double %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.riscv.vfmv.f.s.nxv8f64(<vscale x 8 x double>) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560d13d0f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560d13d0c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560d13d0f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe87c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe87c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe87c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe87c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560d13ca4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560d13ca4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560d13c89b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560d139390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560d13938dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe87c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe87c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe87c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560d13938cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c (2979 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfabs_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfabs_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfabs_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfabs_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfabs_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfabs_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfabs_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfabs_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfabs_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfabs_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfabs_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfabs_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, al
# | ...
# `---data was truncated (10240/30861) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593a1d7c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005593a1d790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005593a1d7c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f02d3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f02d378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f02d3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f02d371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593a1d11e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005593a1d11c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005593a1cf6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005593a19a60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005593a19a5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f02d371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f02d371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f02d371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593a19a5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c (2980 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c19e47f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c19e47c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c19e47f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a0ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a0ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a0ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a0ed1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c19e414e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c19e414c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c19e3f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c19e0a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c19e0a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3a0ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a0ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a0ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c19e0a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c (2981 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559ad9eef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559ad9eec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559ad9eef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4400333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f440038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4400333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f440031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559ad9e84e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559ad9e84c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559ad9e69b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559ad9b190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559ad9b18dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f440031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f440031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f440031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559ad9b18cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c (2982 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005627a08ce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005627a08cb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005627a08ce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3b61a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3b61aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3b61a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3b61a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005627a0863e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005627a0863c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005627a0848b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005627a04f80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005627a04f7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3b61a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3b61a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3b61a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005627a04f7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c (2983 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64) #1
# | 
# | 
# | ...
# `---data was truncated (10240/63571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556fd25e315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556fd25e00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556fd25e389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5974a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5974aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5974a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5974a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556fd2578e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556fd2578c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556fd255db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556fd220d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556fd220cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5974a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5974a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5974a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556fd220ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c (2984 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh    -target-feature +xsfvfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.sf.vfexp.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x half> @test_sf_vfexp_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 16 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs2.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.sf.vfexp.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x half> @test_sf_vfexp_v_f16m8_tu(<vscale x 32 x half> %vd, <vscale x 32 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x half>, align 2
# |   %vs2.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.sf.vfexp.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x half> @test_sf_vfexp_v_f16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x half> %vd, <vscale x 1 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x half> @test_sf_vfexp_v_f16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x half> %vd, <vscale x 2 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x half> @test_sf_vfexp_v_f16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x half> %vd, <vscale x 4 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x half> @test_sf_vfexp_v_f16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x half> %vd, <vscale x 8 x half> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 
# | ...
# `---data was truncated (10240/26333) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eaa017c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eaa01790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eaa017c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc476d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc476d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc476d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc476d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eaa0111e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eaa0111c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eaa00f6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ea9fda60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ea9fda5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc476d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc476d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc476d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ea9fda5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c (2985 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste64.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056254869d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056254869a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056254869d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb605649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6056a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb605649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb605631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562548632e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562548632c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562548617b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005625482c70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005625482c6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb605632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6056330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6056330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625482c6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c (2986 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vv_bf16mf4_f32mf2(<vscale x 1 x float> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwnmsac_vf_bf16mf4_f32mf2(<vscale x 1 x float> %vd, bfloat noundef %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(<vscale x 1 x float>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vv_bf16mf2_f32m1(<vscale x 2 x float> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwnmsac_vf_bf16mf2_f32m1(<vscale x 2 x float> %vd, bfloat noundef %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(<vscale x 2 x float>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vv_bf16m1_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwnmsac_vf_bf16m1_f32m2(<vscale x 4 x float> %vd, bfloat noundef %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(<vscale x 4 x float>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vv_bf16m2_f32m4(<vscale x 8 x float> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 3)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfwnmsac_vf_bf16m2_f32m4(<vscale x 8 x float> %vd, bfloat noundef %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store bfloat %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load bfloat, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.
# | ...
# `---data was truncated (10240/51804) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056259e05015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056259e04d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056259e05089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd778533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd77858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd778533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd77851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056259dfe5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056259dfe5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056259dfcab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056259dc7a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056259dc79dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd77851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd77851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd77851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056259dc79cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c (2987 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_f16mf4x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f16mf2x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f16m1x6(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei64_v_f32mf2x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f32m1x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei64_v_f64m1x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vluxseg6ei64_v_i8mf8x6(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei64_v_i8mf4x6(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ade7cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557ade7cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557ade7cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5124c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5124ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5124c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5124c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ade764e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557ade764c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557ade749b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557ade3f90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557ade3f8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5124c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5124c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5124c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ade3f8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c (2988 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055997929e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055997929b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055997929e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b5f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b5f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b5f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b5f431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559979233e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559979233c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559979218b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559978ec80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559978ec7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9b5f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b5f4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b5f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559978ec7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c (2989 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e36361915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e3636160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e36361989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0b36533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0b3658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0b36533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0b3651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3635aee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e3635aec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e363593b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e3632430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e363242dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0b3651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0b3651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0b3651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e363242cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c (2990 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_x_f_v_i16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_x_f_v_i16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_x_f_v_i16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_x_f_v_i16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_x_f_v_i16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_x_f_v_i16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfcvt_rtz_xu_f_v_u16mf4(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfcvt_rtz_xu_f_v_u16mf2(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfcvt_rtz_xu_f_v_u16m1(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfcvt_rtz_xu_f_v_u16m2(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfcvt_rtz_xu_f_v_u16m4(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfcvt_rtz_xu_f_v_u16m8(<vscale x 32 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.v
# | ...
# `---data was truncated (10240/58683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557cec86a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557cec8670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557cec86a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ddfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ddfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ddfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ddfb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557cec7ffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557cec7ffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557cec7e4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557cec4940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557cec493dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7ddfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ddfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ddfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557cec493cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c (2991 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i64> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> %3, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-feature
# | ...
# `---data was truncated (10240/10692) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc942b915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dc942b60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dc942b989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f918c505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f918c55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f918c505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f918c4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc9424ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dc9424ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dc94233b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dc93ee30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dc93ee2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f918c4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f918c4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f918c4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc93ee2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c (2992 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vslidedown_vx_f16mf4(<vscale x 1 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vslidedown_vx_f16mf2(<vscale x 2 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vslidedown_vx_f16m1(<vscale x 4 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vslidedown_vx_f16m2(<vscale x 8 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vslidedown_vx_f16m4(<vscale x 16 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vslidedown_vx_f16m8(<vscale x 32 x half> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vslidedown_vx_f32mf2(<vscale x 1 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vslidedown_vx_f32m1(<vscale x 2 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vslidedown_vx_f32m2(<vscale x 4 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vslidedown_vx_f32m4(<vscale x 8 x float> %src, i64 noundef %offset, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %offset.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %offset, ptr %offset.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %offset.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i
# | ...
# `---data was truncated (10240/120468) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056064c32815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056064c3250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056064c32889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd302f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd302f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd302f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd302f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056064c2bde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056064c2bdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056064c2a2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056064bf520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056064bf51dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd302f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd302f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd302f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056064bf51cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c (2993 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsgeu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsgeu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsgeu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsgeu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5d585a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c5d58570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c5d585a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff86dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff86dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff86dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff86dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5d57efe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c5d57efc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c5d57d4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c5d54840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c5d5483dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff86dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff86dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff86dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5d5483cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c (2994 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync 
# | ...
# `---data was truncated (10240/62063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005649f9ea615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005649f9ea30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005649f9ea689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5c78733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5c7878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5c78733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5c7871b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005649f9e3be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005649f9e3bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005649f9e20b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005649f9ad00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005649f9acfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5c7871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5c7871d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5c7871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005649f9acfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c (2995 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ac754915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562ac75460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562ac754989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbbf1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbbf1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbbf1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbbf1c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ac74dee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562ac74dec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562ac74c3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562ac71730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562ac7172dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbbf1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbbf1c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbbf1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ac7172cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c (2996 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjx_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjx_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjx_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjx_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjx_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr 
# | ...
# `---data was truncated (10240/29202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055980f82615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055980f8230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055980f82689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fccf8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fccf84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fccf8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fccf8431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055980f7bbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055980f7bbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055980f7a0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055980f4500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055980f44fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fccf8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fccf84330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fccf84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055980f44fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c (2997 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), pt
# | ...
# `---data was truncated (10240/19484) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e8df0af15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e8df0ac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e8df0af89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ec5b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ec5b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ec5b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ec5aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e8df044e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e8df044c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e8df029b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e8decd90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e8decd8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1ec5aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ec5aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ec5aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e8decd8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c (2998 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vrga
# | ...
# `---data was truncated (10240/28435) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556480e8115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556480e7e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556480e8189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe5acd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe5acd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe5acd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe5acd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556480e16e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556480e16c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556480dfbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556480aab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556480aaadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe5acd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe5acd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe5acd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556480aaacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c (2999 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vundefined_f16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vundefined_f16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vundefined_f16m1() #0 {
# | entry:
# |   ret <vscale x 4 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vundefined_f16m2() #0 {
# | entry:
# |   ret <vscale x 8 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vundefined_f16m4() #0 {
# | entry:
# |   ret <vscale x 16 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vundefined_f16m8() #0 {
# | entry:
# |   ret <vscale x 32 x half> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vundefined_f32mf2() #0 {
# | entry:
# |   ret <vscale x 1 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vundefined_f32m1() #0 {
# | entry:
# |   ret <vscale x 2 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vundefined_f32m2() #0 {
# | entry:
# |   ret <vscale x 4 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vundefined_f32m4() #0 {
# | entry:
# |   ret <vscale x 8 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vundefined_f32m8() #0 {
# | entry:
# |   ret <vscale x 16 x float> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vundefined_f64m1() #0 {
# | entry:
# |   ret <vscale x 1 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vundefined_f64m2() #0 {
# | entry:
# |   ret <vscale x 2 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vundefined_f64m4() #0 {
# | entry:
# |   ret <vscale x 4 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vundefined_f64m8() #0 {
# | entry:
# |   ret <vscale x 8 x double> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vundefined_i8mf8() #0 {
# | entry:
# |   ret <vscale x 1 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vundefined_i8mf4() #0 {
# | entry:
# |   ret <vscale x 2 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vundefined_i8mf2() #0 {
# | entry:
# |   ret <vscale x 4 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vundefined_i8m1() #0 {
# | entry:
# |   ret <vscale x 8 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vundefined_i8m2() #0 {
# | entry:
# |   ret <vscale x 16 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vundefined_i8m4() #0 {
# | entry:
# |   ret <vscale x 32 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vundefined_i8m8() #0 {
# | entry:
# |   ret <vscale x 64 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vundefined_i16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vundefined_i16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vundefined_i16m1() #0 {
# | entry:
# |   ret <vscale x 4 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vundefined_i16m2() #0 {
# | entry:
# |   ret <vscale x 8 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vundefined_i16m4() #0 {
# | entry:
# |   ret <vscale x 16 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vundefined_i16m8() #0 {
# | entry:
# |   ret <vscale x 32 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vundefined_i32mf2() #0 {
# | entry:
# |   ret <vscale x 1 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vundefined_i32m1() #0 {
# | entry:
# |   ret <vscale x 2 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vundefined_i32m2() #0 {
# | entry:
# |   ret <vscale x 4 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vundefined_i32m4() #0 {
# | entry:
# |   ret <vscale x 8 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vundefined_i32m8() #0 {
# | entry:
# |   ret <vscale x 16 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vundefined_i64m1() #0 {
# | entry:
# |   ret <vscale x 1 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vundefined_i64m2() #0 {
# | entry:
# |   ret <vscale x 2 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vundefined_i64m4() #0 {
# | entry:
# |   ret <vscale x 4 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vundefined_i64m8() #0 {
# | entry:
# |   ret <vscale x 8 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vundefined_u8mf8() #0 {
# | entry:
# |   ret <vscale x 1 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vundefined_u8mf4() #0 {
# | entry:
# |   ret <vscale x 2 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vundefined_u8mf2() #0 {
# | entry:
# |   ret <vscale x 4 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vundefined_u8m1() #0 {
# | entry:
# |   ret <vscale x 8 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vundefined_u8m2() #0 {
# | entry:
# |   ret <vscale x 16 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vundefined_u8m4() #0 {
# | entry:
# |   ret <vscale x 32 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vundefined_u8m8() #0 {
# | entry:
# |   ret <vscale x 64 x i8> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vundefined_u16mf4() #0 {
# | entry:
# |   ret <vscale x 1 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vundefined_u16mf2() #0 {
# | entry:
# |   ret <vscale x 2 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vundefined_u16m1() #0 {
# | entry:
# |   ret <vscale x 4 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vundefined_u16m2() #0 {
# | entry:
# |   ret <vscale x 8 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vundefined_u16m4() #0 {
# | entry:
# |   ret <vscale x 16 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vundefined_u16m8() #0 {
# | entry:
# |   ret <vscale x 32 x i16> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vundefined_u32mf2() #0 {
# | entry:
# |   ret <vscale x 1 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vundefined_u32m1() #0 {
# | entry:
# |   ret <vscale x 2 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vundefined_u32m2() #0 {
# | entry:
# |   ret <vscale x 4 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vundefined_u32m4() #0 {
# | entry:
# |   ret <vscale x 8 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vundefined_u32m8() #0 {
# | entry:
# |   ret <vscale x 16 x i32> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vundefined_u64m1() #0 {
# | entry:
# |   ret <vscale x 1 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vundefined_u64m2() #0 {
# | entry:
# |   ret <vscale x 2 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vundefined_u64m4() #0 {
# | entry:
# |   ret <vscale x 4 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vundefined_u64m8() #0 {
# | entry:
# |   ret <vscale x 8 x i64> poison
# | }
# | 
# | ; Function Attrs: noinline nounwind vsca
# | ...
# `---data was truncated (10240/63140) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e77999915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e7799960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e77999989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f10d6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10d678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f10d6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10d671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e77992ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e77992ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e779913b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e7795c30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e7795c2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f10d671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10d671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10d671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e7795c2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c (3000 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559e9ad1a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559e9ad170f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559e9ad1a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5de9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5de9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5de9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5de9e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559e9acafe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559e9acafc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559e9ac94b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559e9a9440b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559e9a943dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5de9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5de9e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5de9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559e9a943cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/builtins-loongarch.c (3001 of 27911)
******************** TEST 'Clang :: CodeGen/builtins-loongarch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple loongarch32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple loongarch32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "loongarch32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_eh_return_data_regno() #0 {
# | entry:
# |   %res = alloca i32, align 4
# |   store volatile i32 4, ptr %res, align 4
# |   store volatile i32 5, ptr %res, align 4
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit" }
# | 
# | !llvm.module.flags = !{!0}
# | !llvm.ident = !{!1}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32d"}
# | !1 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556fc1af215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556fc1aef0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556fc1af289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff2aed05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff2aed5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff2aed05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff2aeced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556fc1a87e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556fc1a87c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556fc1a6cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556fc171c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556fc171bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff2aeceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff2aecef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff2aecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556fc171bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c (3002 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 
# | ...
# `---data was truncated (10240/17523) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564fed0e315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564fed0e00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564fed0e389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff7b5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7b5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff7b5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff7b5c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564fed078e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564fed078c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564fed05db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564fecd0d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564fecd0cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff7b5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7b5c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7b5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564fecd0ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c (3003 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei8_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei8_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei8_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6f320615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b6f32030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b6f320689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff293a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff293aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff293a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff293a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6f319be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b6f319bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b6f3180b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b6f2e300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b6f2e2fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff293a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff293a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff293a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6f2e2fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c (3004 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_f16mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_f16mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_f16m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_f16m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_f16m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_i16mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_i16mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_i16m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align
# | ...
# `---data was truncated (10240/39416) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d20efb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556d20ef80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556d20efb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f337c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f337c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f337c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f337c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d20e90e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556d20e90c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556d20e75b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556d20b250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556d20b24dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f337c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f337c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f337c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d20b24cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c (3005 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639988ce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005639988cb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005639988ce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9841133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f984118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9841133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f984111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563998863e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563998863c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563998848b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005639984f80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005639984f7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f984111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f984111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f984111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639984f7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c (3006 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vpairo.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vpairo_vv_bf16m2(<vscale x 8 x bfloat> %vs2, <vscale x 8 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vpairo.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vpairo_vv_bf16m4(<vscale x 16 x bfloat> %vs2, <vscale x 16 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vpairo.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vpairo_vv_bf16m8(<vscale x 32 x bfloat> %vs2, <vscale x 32 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vpairo.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vpairo_vv_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vpairo.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vpairo_vv_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vpairo.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vpairo_vv_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.add
# | ...
# `---data was truncated (10240/15312) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633f331f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005633f331c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005633f331f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff420933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff42098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff420933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff42091b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633f32b4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005633f32b4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005633f3299b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005633f2f490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005633f2f48dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff42091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff42091d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff42091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633f2f48cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c (3007 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4
# | ...
# `---data was truncated (10240/12740) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005558d4fd215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005558d4fcf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005558d4fd289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5b78649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5b786a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5b78649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5b78631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005558d4f67e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005558d4f67c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005558d4f4cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005558d4bfc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005558d4bfbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5b78632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5b786330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5b786330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005558d4bfbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c (3008 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce21bb415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ce21bb10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ce21bb489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6df7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6df7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6df7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6df7e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce21b49e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ce21b49c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ce21b2eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ce217de0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ce217dddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6df7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6df7e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6df7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce217ddcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c (3009 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_f32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_f32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_i32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_i32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_i32m2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e32_v_u32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e32_v_u32m1x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e32_v_u3
# | ...
# `---data was truncated (10240/11880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e90db5a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e90db570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e90db5a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff22ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff22baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff22ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff22ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e90daefe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e90daefc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e90dad4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e90d7840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e90d783dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff22ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff22ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff22ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e90d783cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c (3010 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvlimax.i64(i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0df31715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d0df3140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d0df31789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba63d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba63d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba63d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba63d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0df2ace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d0df2acc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d0df291b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d0def410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d0def40dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fba63d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba63d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba63d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0def40cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c (3011 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 16 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei32_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei32_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i
# | ...
# `---data was truncated (10240/32100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bec1a2015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bec1a1d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bec1a2089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f14bd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f14bd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f14bd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f14bd91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bec19b5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bec19b5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bec199ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bec164a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bec1649dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f14bd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f14bd91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f14bd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bec1649cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c (3012 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat> %0, ptr %1, i64 %3)
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 2
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 0
# |   %7 = extractvalue { <vscale x 1 x bfloat>, i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret <vscale x 1 x bfloat> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vs
# | ...
# `---data was truncated (10240/32206) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005560fffca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005560fffc70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005560fffca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8388905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f838895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8388905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f83888ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560fff5fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005560fff5fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005560fff44b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005560ffbf40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005560ffbf3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f83888eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f83888ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f83888ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005560ffbf3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c (3013 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2ch_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2ch_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2ch_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2ch_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2ch_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2ch_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2ch_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2ch_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | 
# | ...
# `---data was truncated (10240/12216) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005576f976815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005576f97650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005576f976889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fddf5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fddf578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fddf5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fddf571b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005576f96fde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005576f96fdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005576f96e2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005576f93920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005576f9391dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fddf571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fddf571d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fddf571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005576f9391cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c (3014 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnjn_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnjn_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnjn_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnjn_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnjn_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr 
# | ...
# `---data was truncated (10240/29202) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558bc347115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558bc346e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558bc347189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f737e505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f737e55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f737e505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f737e4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558bc3406e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558bc3406c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558bc33ebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558bc309b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558bc309add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f737e4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f737e4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f737e4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558bc309acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c (3015 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i64> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i64> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i64> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i64> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei64_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei64_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei64_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei64_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i64>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e9908415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556e990810f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556e9908489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb1d9705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1d975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb1d9705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb1d96ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e99019e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556e99019c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556e98ffeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556e98cae0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556e98caddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb1d96eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1d96ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1d96ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e98cadcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c (3016 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vle64_v_f64m1_tu(<vscale x 1 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x double> @llvm.riscv.vle.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x double> @test_vle64_v_f64m2_tu(<vscale x 2 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x double> @llvm.riscv.vle.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x double> @test_vle64_v_f64m4_tu(<vscale x 4 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x double> @llvm.riscv.vle.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x double> @test_vle64_v_f64m8_tu(<vscale x 8 x double> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x double>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x double> @llvm.riscv.vle.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_i64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_i64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_i64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vle64_v_i64m8_tu(<vscale x 8 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vle64_v_u64m1_tu(<vscale x 1 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.p0.i64(<vscale x 1 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vle64_v_u64m2_tu(<vscale x 2 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64.p0.i64(<vscale x 2 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vle64_v_u64m4_tu(<vscale x 4 x i64> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64.p0.i64(<vscale x 4 x i64> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | defi
# | ...
# `---data was truncated (10240/48385) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f5a56b415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f5a56b10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f5a56b489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d78933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d7898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d78933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d7891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5a5649e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f5a5649c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f5a562eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f5a52de0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f5a52dddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0d7891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d7891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d7891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f5a52ddcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c (3017 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettnt.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettn_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e69063115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e69062e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e69063189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8790449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f87904a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8790449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8790431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e6905c6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e6905c6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e6905abb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e69025b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e69025add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8790432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f87904330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f87904330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e69025acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vsubq.c (3018 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vsubq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = sub <4 x i32> %0, %1
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = fsub <8 x half> %0, %1
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsubq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> undef)
# |   ret <8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load i32, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0
# |   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
# |   %2 = sub <4 x i32> %0, %.splat
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_n_f16(<8 x half> noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca half, align 2
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load half, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x half> poison, half %1, i64 0
# |   %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer
# |   %2 = fsub <8 x half> %0, %.splat
# |   ret <8 x half> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca i8, align 1
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i8 %b, ptr %b.addr, align 1
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i8, ptr %b.addr, align 1
# |   %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0
# |   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsubq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, float noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x float>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca float, align 4
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store float %b, ptr %b.addr, align 4
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load float, ptr %b.addr, align 4
# |   %.splatinsert = insertelement <4 x float> poison, float %1, i64 0
# |   %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x float>, ptr %inactive.addr, align 8
# |   %6 = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %.splat, <4 x i1> %4, <4 x float> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca i16, align 2
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %b, ptr %b.addr, align 2
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %b.addr, align 2
# |   %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0
# |   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x half> @t
# | ...
# `---data was truncated (10240/11617) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x00005595e41ba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005595e41b70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005595e41ba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb27d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb27d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb27d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb27d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595e414fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005595e414fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005595e4134b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005595e3de40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005595e3de3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feb27d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb27d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb27d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595e3de3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c (3019 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i64> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# | ...
# `---data was truncated (10240/12732) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055722023f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055722023c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055722023f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7caa649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7caa6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7caa649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7caa631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005572201d4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005572201d4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005572201b9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055721fe690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055721fe68dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7caa632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7caa6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7caa6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055721fe68cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c (3020 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_i32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_u32m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e32_v_f32mf2x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void
# | ...
# `---data was truncated (10240/20489) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005633cea5c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005633cea590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005633cea5c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb721733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb72178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb721733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb72171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633ce9f1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005633ce9f1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005633ce9d6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005633ce6860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005633ce685dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb72171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb72171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb72171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005633ce685cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c (3021 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=' @llvm.fma.' --implicit-check-not=' @llvm.sqrt.'
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local half @test_vsqrth_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vsqrt = call half @llvm.experimental.constrained.sqrt.f16(half %1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store half %vsqrt, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata) #1
# | 
# | ; Function Attrs: noinline nounwind strictfp
# | define dso_local half @test_vfmah_f16(half noundef %a, half noundef %b, half noundef %c) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %c.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %__s2 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   store half %c, ptr %c.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %c.addr, align 2
# |   store half %2, ptr %__s2, align 2
# |   %3 = load half, ptr %__s0, align 2
# |   %4 = load half, ptr %__s1, align 2
# |   %5 = load half, ptr %__s2, align 2
# |   %6 = call half @llvm.experimental.constrained.fma.f16(half %4, half %5, half %3, metadata !"round.tonearest", metadata !"fpexcept.strict") #2
# |   store half %6, ptr %ref.tmp, align 2
# |   %7 = load half, ptr %ref.tmp, align 2
# |   store half %7, ptr %__ret, align 2
# |   %8 = load half, ptr %__ret, align 2
# |   store half %8, ptr %tmp, align 2
# |   %9 = load half, ptr %tmp, align 2
# |   ret half %9
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite)
# | declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata) #1
# | 
# | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" }
# | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
# | attributes #2 = { strictfp }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg
# |  #0 0x0000563eea6f615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563eea6f30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563eea6f689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4575d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4575d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4575d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4575d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563eea68be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563eea68bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563eea670b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563eea3200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563eea31fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4575d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4575d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4575d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563eea31fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM '--implicit-check-not= @llvm.fma.' '--implicit-check-not= @llvm.sqrt.'
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not= @llvm.fma. --implicit-check-not= @llvm.sqrt.
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c (3022 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eb66e1415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eb66e110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eb66e1489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5eb8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5eb82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5eb8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5eb8231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eb66da9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eb66da9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eb66d8eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eb66a3e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eb66a3ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5eb8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5eb82330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5eb82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eb66a3dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c (3023 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaeskf1_vi_u32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaeskf1.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaeskf1_vi_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaeskf1.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaeskf1_vi_u32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaeskf1_vi_u32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaeskf1_vi_u32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d06a9a415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d06a9a10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d06a9a489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faee1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faee118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faee1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faee111b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d06a939e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d06a939c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d06a91eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d06a5ce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d06a5cddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faee111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faee111d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faee111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d06a5cdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c (3024 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | ...
# `---data was truncated (10240/12958) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556e6feba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556e6feb70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556e6feba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f69de305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f69de35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f69de305a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f69de2ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556e6fe4fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556e6fe4fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556e6fe34b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556e6fae40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556e6fae3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f69de2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f69de2ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f69de2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556e6fae3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c (3025 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_f32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_i32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_i32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_u32mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e32ff_v_u32m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e32ff_v_f32mf2x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 4
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple,
# | ...
# `---data was truncated (10240/40726) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005597fd02b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005597fd0280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005597fd02b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efcb2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efcb2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efcb2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efcb2a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005597fcfc0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005597fcfc0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005597fcfa5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005597fcc550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005597fcc54dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efcb2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efcb2a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efcb2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005597fcc54cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c (3026 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 1 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(<vscale x 4 x half>, <vscale x 1 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16mf2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 2 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(<vscale x 4 x half>, <vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m1_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m2_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 8 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m4_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 16 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(<vscale x 4 x half>, <vscale x 16 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfredmax_vs_f16m8_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 32 x half> %vector, <vscale x 4 x half> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x half> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x half>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(<vscale x 4 x half>, <vscale x 32 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float>, <vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfredmax_vs_f32m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x float> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff
# | ...
# `---data was truncated (10240/44185) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bd2b28515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bd2b2820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bd2b28589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12da533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12da58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12da533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12da51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bd2b21ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bd2b21ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bd2b1ffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bd2aeaf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bd2aeaedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f12da51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12da51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12da51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bd2aeaecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c (3027 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_u64m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e64_v_i64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tu
# | ...
# `---data was truncated (10240/14044) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005639c1e6c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005639c1e690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005639c1e6c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe0fcc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe0fcca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe0fcc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe0fcc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005639c1e01e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005639c1e01c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005639c1de6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005639c1a960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005639c1a95dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe0fcc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe0fcc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe0fcc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005639c1a95cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c (3028 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558b5c24315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558b5c2400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558b5c24389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba8f705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba8f75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba8f705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba8f6ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558b5c1d8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558b5c1d8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558b5c1bdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558b5be6d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558b5be6cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fba8f6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba8f6ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba8f6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558b5be6ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c (3029 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vluxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, <vscale x 16 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei16_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, ali
# | ...
# `---data was truncated (10240/14621) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ecc777515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ecc77720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ecc777589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5673933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f567398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5673933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f567391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ecc770ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ecc770ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ecc76efb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ecc739f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ecc739edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f567391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f567391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f567391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ecc739ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c (3030 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = call <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = call <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0)
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = call <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1)
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f3653715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560f365340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560f3653789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f039b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f039b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f039b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f039b031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f364cce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560f364ccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560f364b1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560f361610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560f36160dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f039b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f039b0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f039b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f36160cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c (3031 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %
# | ...
# `---data was truncated (10240/29809) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad4616f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ad4616c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ad4616f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9d81f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9d81f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9d81f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9d81f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad46104e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ad46104c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ad460e9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ad45d990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ad45d98dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9d81f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9d81f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9d81f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad45d98cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c (3032 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_u64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %2, i64 6)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_u64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %ba
# | ...
# `---data was truncated (10240/24100) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fba7d4915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fba7d460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fba7d4989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a6a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a6a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a6a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a6a003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fba7cdee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fba7cdec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fba7cc3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fba79730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fba7972dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7a6a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a6a0050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a6a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fba7972cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c (3033 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m2_f16m1(<vscale x 8 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m4_f16m1(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vget_v_f16m8_f16m1(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 4 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m4_f16m2(<vscale x 16 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vget_v_f16m8_f16m2(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 8 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vget_v_f16m8_f16m4(<vscale x 32 x half> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = call <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> %0, i64 0)
# |   ret <vscale x 16 x half> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m2_f32m1(<vscale x 4 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m4_f32m1(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vget_v_f32m8_f32m1(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 2 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m4_f32m2(<vscale x 8 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vget_v_f32m8_f32m2(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 4 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vget_v_f32m8_f32m4(<vscale x 16 x float> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = call <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> %0, i64 0)
# |   ret <vscale x 8 x float> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vget_v_f64m2_f64m1(<vscale x 2 x double> %src, i64 noundef %index) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %index.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %index, ptr %index.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> %0, i64 0)
# |   ret <vscale x 1 x double> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounw
# | ...
# `---data was truncated (10240/246606) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055acf148f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055acf148c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055acf148f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdeb6f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdeb6f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdeb6f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdeb6eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055acf1424e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055acf1424c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055acf1409b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055acf10b90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055acf10b8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdeb6eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdeb6eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdeb6eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055acf10b8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c (3034 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs
# | ...
# `---data was truncated (10240/15978) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055db3fc1915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055db3fc160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055db3fc1989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f553a505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f553a55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f553a505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f553a4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055db3fbaee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055db3fbaec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055db3fb93b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055db3f8430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055db3f842dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f553a4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f553a4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f553a4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055db3f842cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c (3035 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 %3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("r
# | ...
# `---data was truncated (10240/36023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056231f68b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056231f6880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056231f68b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07d0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07d00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07d0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07d0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056231f620e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056231f620c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056231f605b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056231f2b50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056231f2b4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f07d0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07d00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07d00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056231f2b4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c (3036 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfrdiv_vf_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfrdiv_vf_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfrdiv.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfrdiv_vf_f16m1(<vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfrdiv.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfrdiv_vf_f16m2(<vscale x 8 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfrdiv.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfrdiv_vf_f16m4(<vscale x 16 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfrdiv.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfrdiv_vf_f16m8(<vscale x 32 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 7, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfrdiv.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfrdiv_vf_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfrdiv.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfrdiv_vf_f32m1(<vscale x 2 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfrdiv.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfrdiv_vf_f32m2(<vscale x 4 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfrdiv_vf_f32m4(<vscale x 8 x float> %op1, float noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 7, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfrdiv.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @
# | ...
# `---data was truncated (10240/61058) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b13da4315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b13da400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b13da4389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1a6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1a6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1a6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1a6b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b13d9d8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b13d9d8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b13d9bdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b13d66d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b13d66cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc1a6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1a6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1a6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b13d66ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c (3037 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei8_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei8_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei8_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005586297e815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005586297e50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005586297e889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0ac6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0ac6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0ac6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0ac6a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055862977de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055862977dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558629762b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005586294120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558629411dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0ac6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0ac6a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0ac6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558629411cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c (3038 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call
# | ...
# `---data was truncated (10240/39914) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b0061a415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b0061a10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b0061a489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1609933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f160998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1609933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f160991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b006139e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b006139c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b00611eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b005dce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b005dcddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f160991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f160991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f160991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b005dcdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c (3039 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ba0ed915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560ba0ed60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560ba0ed989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7e49b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7e49b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7e49b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7e49b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ba0e6ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560ba0e6ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560ba0e53b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560ba0b030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560ba0b02dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7e49b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7e49b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7e49b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ba0b02cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c (3040 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_f64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_f64m2x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e64_v_i64m1x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e64_v_i64m2x3_m(<vscale x 2 x i1
# | ...
# `---data was truncated (10240/14031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3396fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e3396f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e3396fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5038933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f503898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5038933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f503891b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e339690e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e339690c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e339675b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e3393250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e339324dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f503891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f503891d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f503891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e339324cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c (3041 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055afd3e8c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055afd3e890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055afd3e8c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf46533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf4658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf46533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf4651b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055afd3e21e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055afd3e21c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055afd3e06b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055afd3ab60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055afd3ab5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdf4651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf4651d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf4651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055afd3ab5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-cde-gpr.c (3042 of 27911)
******************** TEST 'Clang :: CodeGen/arm-cde-gpr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +cdecp1    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx1() #0 {
# | entry:
# |   %0 = call i32 @llvm.arm.cde.cx1(i32 0, i32 123)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx1(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx1a(i32 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = call i32 @llvm.arm.cde.cx1a(i32 0, i32 %0, i32 345)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx1a(i32 immarg, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx1d() #0 {
# | entry:
# |   %0 = call { i32, i32 } @llvm.arm.cde.cx1d(i32 1, i32 567)
# |   %1 = extractvalue { i32, i32 } %0, 1
# |   %2 = zext i32 %1 to i64
# |   %3 = shl i64 %2, 32
# |   %4 = extractvalue { i32, i32 } %0, 0
# |   %5 = zext i32 %4 to i64
# |   %6 = or i64 %3, %5
# |   ret i64 %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx1d(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx1da(i64 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = call { i32, i32 } @llvm.arm.cde.cx1da(i32 0, i32 %3, i32 %2, i32 789)
# |   %5 = extractvalue { i32, i32 } %4, 1
# |   %6 = zext i32 %5 to i64
# |   %7 = shl i64 %6, 32
# |   %8 = extractvalue { i32, i32 } %4, 0
# |   %9 = zext i32 %8 to i64
# |   %10 = or i64 %7, %9
# |   ret i64 %10
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx1da(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx2(i32 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = call i32 @llvm.arm.cde.cx2(i32 0, i32 %0, i32 11)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx2(i32 immarg, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx2a(i32 noundef %acc, i32 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = load i32, ptr %n.addr, align 4
# |   %2 = call i32 @llvm.arm.cde.cx2a(i32 1, i32 %0, i32 %1, i32 22)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx2a(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx2d(i32 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = call { i32, i32 } @llvm.arm.cde.cx2d(i32 1, i32 %0, i32 33)
# |   %2 = extractvalue { i32, i32 } %1, 1
# |   %3 = zext i32 %2 to i64
# |   %4 = shl i64 %3, 32
# |   %5 = extractvalue { i32, i32 } %1, 0
# |   %6 = zext i32 %5 to i64
# |   %7 = or i64 %4, %6
# |   ret i64 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx2d(i32 immarg, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx2da(i64 noundef %acc, i32 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i32, align 4
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %n.addr, align 4
# |   %5 = call { i32, i32 } @llvm.arm.cde.cx2da(i32 0, i32 %3, i32 %2, i32 %4, i32 44)
# |   %6 = extractvalue { i32, i32 } %5, 1
# |   %7 = zext i32 %6 to i64
# |   %8 = shl i64 %7, 32
# |   %9 = extractvalue { i32, i32 } %5, 0
# |   %10 = zext i32 %9 to i64
# |   %11 = or i64 %8, %10
# |   ret i64 %11
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx2da(i32 immarg, i32, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx3(i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = load i32, ptr %m.addr, align 4
# |   %2 = call i32 @llvm.arm.cde.cx3(i32 0, i32 %0, i32 %1, i32 1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx3(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_cx3a(i32 noundef %acc, i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = load i32, ptr %n.addr, align 4
# |   %2 = load i32, ptr %m.addr, align 4
# |   %3 = call i32 @llvm.arm.cde.cx3a(i32 1, i32 %0, i32 %1, i32 %2, i32 2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.arm.cde.cx3a(i32 immarg, i32, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx3d(i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = load i32, ptr %m.addr, align 4
# |   %2 = call { i32, i32 } @llvm.arm.cde.cx3d(i32 1, i32 %0, i32 %1, i32 3)
# |   %3 = extractvalue { i32, i32 } %2, 1
# |   %4 = zext i32 %3 to i64
# |   %5 = shl i64 %4, 32
# |   %6 = extractvalue { i32, i32 } %2, 0
# |   %7 = zext i32 %6 to i64
# |   %8 = or i64 %5, %7
# |   ret i64 %8
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx3d(i32 immarg, i32, i32, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_cx3da(i64 noundef %acc, i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = lshr i64 %0, 32
# |   %2 = trunc i64 %1 to i32
# |   %3 = trunc i64 %0 to i32
# |   %4 = load i32, ptr %n.addr, align 4
# |   %5 = load i32, ptr %m.addr, align 4
# |   %6 = call { i32, i32 } @llvm.arm.cde.cx3da(i32 0, i32 %3, i32 %2, i32 %4, i32 %5, i32 4)
# |   %7 = extractvalue { i32, i32 } %6, 1
# |   %8 = zext i32 %7 to i64
# |   %9 = shl i64 %8, 32
# |   %10 = extractvalue { i32, i32 } %6, 0
# |   %11 = zext i32 %10 to i64
# |   %12 = or i64 %9, %11
# |   ret i64 %12
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare { i32, i32 } @llvm.arm.cde.cx3da(i32 immarg, i32, i32, i32, i32, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+cdecp1,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562ad270b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562ad27080f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562ad270b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c87d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c87d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c87d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c87ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ad26a0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562ad26a0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562ad2685b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562ad23350b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562ad2334dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1c87ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c87cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c87cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ad2334cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c (3043 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8(<vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> poison, <vscale x 1 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4(<vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> poison, <vscale x 2 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2(<vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> poison, <vscale x 4 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1(<vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> poison, <vscale x 8 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2(<vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> poison, <vscale x 16 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> poison, <vscale x 32 x bfloat> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_sat_f_f_w_bf16m8_f8e4m3m4(<vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <
# | ...
# `---data was truncated (10240/84810) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625f0c6515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005625f0c620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005625f0c6589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1bf9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1bf978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1bf9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1bf971b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625f0bfae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005625f0bfac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005625f0bdfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005625f088f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005625f088edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1bf971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1bf971d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1bf971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625f088ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c (3044 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +xandesvbfhcvt -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf4_rm(<vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_nds_vfncvt_bf16_s_bf16mf2_rm(<vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_nds_vfncvt_bf16_s_bf16m1_rm(<vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_nds_vfncvt_bf16_s_bf16m2_rm(<vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_nds_vfncvt_bf16_s_bf16m4_rm(<vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x float> %0, i64 0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005622bb32c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005622bb3290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005622bb32c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8a9d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8a9d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8a9d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8a9d11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005622bb2c1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005622bb2c1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005622bb2a6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005622baf560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005622baf55dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8a9d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8a9d11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8a9d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005622baf55cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c (3045 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | 
# | ...
# `---data was truncated (10240/31868) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056314153f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056314153c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056314153f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f974cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f974cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f974cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f974cf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631414d4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005631414d4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005631414b9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005631411690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563141168dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f974cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f974cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f974cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563141168cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c (3046 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vv_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmulu_vx_u16mf4_tu(<vscale x 1 x i16> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i16>, align 2
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vv_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmulu_vx_u16mf2_tu(<vscale x 2 x i16> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i16>, align 2
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vv_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmulu_vx_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vv_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmulu_vx_u16m2_tu(<vscale x 8 x i16> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i16>, align 2
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i8, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmulu_vv_u16m4_tu(<vscale x 16 x i16> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i16>, align 2
# |   %op1.addr = alloca <vscale x 16 x i8>,
# | ...
# `---data was truncated (10240/154207) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c5bb49f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c5bb49c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c5bb49f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb68d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb68d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb68d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb68ced507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c5bb434e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c5bb434c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c5bb419b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c5bb0c90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c5bb0c8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdb68ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb68cef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb68cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c5bb0c8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c (3047 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccus_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccus_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccus_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccus_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc11af615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dc11af30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dc11af689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f54d8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f54d858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f54d8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f54d851b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc11a8be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dc11a8bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dc11a70b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dc117200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dc1171fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f54d851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f54d851d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f54d851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc1171fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/atomic-hint-template.cpp (3048 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/atomic-hint-template.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple aarch64-none-elf -target-feature +v9.4a -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple aarch64-none-elf -target-feature +v9.4a -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "aarch64-unknown-none-elf"
# | 
# | $_Z37test_atomic_store_hint_template_orderILj3EEvPii = comdat any
# | 
# | $_Z36test_atomic_store_hint_template_hintILj1EEvPii = comdat any
# | 
# | $_Z37test_atomic_fetch_hint_template_orderILj2EEiPii = comdat any
# | 
# | $_Z36test_atomic_fetch_hint_template_hintILj4EEiPii = comdat any
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr void @_Z37test_atomic_store_hint_template_orderILj3EEvPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   store atomic i32 %1, ptr %0 release, align 4, !mem.cache_hint !4
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr void @_Z36test_atomic_store_hint_template_hintILj1EEvPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   store atomic i32 %1, ptr %0 seq_cst, align 4, !mem.cache_hint !6
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local void @_Z43test_atomic_store_hint_array_consexpr_orderPii(ptr noundef %ptr, i32 noundef %value) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %value.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %value.addr, align 4
# |   store atomic i32 %1, ptr %0 monotonic, align 4, !mem.cache_hint !4
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define dso_local void @_Z42test_atomic_store_hint_array_consexpr_hintPii(ptr noundef %ptr, i32 noundef %value) #0 {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %value.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %value, ptr %value.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %value.addr, align 4
# |   store atomic i32 %1, ptr %0 monotonic, align 4, !mem.cache_hint !6
# |   ret void
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr noundef i32 @_Z37test_atomic_fetch_hint_template_orderILj2EEiPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   %2 = atomicrmw add ptr %0, i32 %1 acquire, align 4, !mem.cache_hint !8
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16)
# | define weak_odr noundef i32 @_Z36test_atomic_fetch_hint_template_hintILj4EEiPii(ptr noundef %ptr, i32 noundef %val) #0 comdat {
# | entry:
# |   %ptr.addr = alloca ptr, align 8
# |   %val.addr = alloca i32, align 4
# |   store ptr %ptr, ptr %ptr.addr, align 8
# |   store i32 %val, ptr %val.addr, align 4
# |   %0 = load ptr, ptr %ptr.addr, align 8
# |   %1 = load i32, ptr %val.addr, align 4
# |   %2 = atomicrmw xor ptr %0, i32 %1 seq_cst, align 4, !mem.cache_hint !10
# |   ret i32 %2
# | }
# | 
# | attributes #0 = { mustprogress noinline nounwind vscale_range(1,16) "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+cssc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+hbc,+i8mm,+jsconv,+lse,+mec,+mops,+neon,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9a,+wfxt" }
# | 
# | !llvm.module.flags = !{!0, !1, !2}
# | !llvm.ident = !{!3}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{!"clang version 24.0.0"}
# | !4 = !{i32 1, !5}
# | !5 = !{!"aarch64.mem_hint", i32 0}
# | !6 = !{i32 1, !7}
# | !7 = !{!"aarch64.mem_hint", i32 1}
# | !8 = !{i32 0, !9}
# | !9 = !{!"aarch64.mem_hint", i32 3}
# | !10 = !{i32 0, !11}
# | !11 = !{!"aarch64.mem_hint", i32 4}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005648b023615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005648b02330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005648b023689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9c1af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9c1af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9c1af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9c1af1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005648b01cbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005648b01cbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005648b01b0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005648afe600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005648afe5fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9c1af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9c1af1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9c1af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648afe5fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c (3049 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vcompress_vm_f16mf4(<vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vcompress_vm_f16mf2(<vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vcompress_vm_f16m1(<vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vcompress_vm_f16m2(<vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vcompress_vm_f16m4(<vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vcompress_vm_f16m8(<vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vcompress_vm_f32mf2(<vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vcompress_vm_f32m1(<vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vcompress_vm_f32m2(<vscale x 4 x float> %src, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vcompress_vm_f32m4(<vscale x 8 x float> %src, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load <v
# | ...
# `---data was truncated (10240/62964) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555da3f0415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555da3f010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555da3f0489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd483b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd483b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd483b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd483aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555da3e99e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555da3e99c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555da3e7eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555da3b2e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555da3b2ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd483aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd483aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd483aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555da3b2dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c (3050 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesdf_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesdf_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesdf_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesdf_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesdf_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind w
# | ...
# `---data was truncated (10240/20198) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555d4743515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555d474320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555d4743589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f905cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f905cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f905cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f905cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555d473cae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555d473cac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555d473afb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555d4705f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555d4705edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f905cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f905cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f905cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555d4705ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c (3051 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), i64, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), i64, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), i64, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsse16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, <vscale x 8 x bfloat> %vs3
# | ...
# `---data was truncated (10240/14330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6f7f9615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b6f7f930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b6f7f9689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fa3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fa3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fa3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fa3f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6f7f2be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b6f7f2bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b6f7f10b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b6f7bc00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b6f7bbfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3fa3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fa3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fa3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6f7bbfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c (3052 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b7399e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557b7399b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557b7399e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f66c1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f66c1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f66c1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f66c1f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b73933e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557b73933c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557b73918b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557b735c80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557b735c7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f66c1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f66c1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f66c1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b735c7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c (3053 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vv_bf16mf4(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfsgnj_vf_bf16mf4(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vv_bf16mf2(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfsgnj_vf_bf16mf2(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vv_bf16m1(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfsgnj_vf_bf16m1(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vv_bf16m2(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfsgnj_vf_bf16m2(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vv_bf16m4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfsgnj_vf_bf16m4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0
# | ...
# `---data was truncated (10240/29136) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056256e87415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056256e8710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056256e87489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b00133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b0018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b00133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b0011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056256e809e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056256e809c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056256e7eeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056256e49e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056256e49ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9b0011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b0011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b0011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056256e49dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-poly-add.c (3054 of 27911)
******************** TEST 'Clang :: CodeGen/arm-poly-add.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi    -target-feature +neon    -mfloat-abi hard  -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa   | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.2a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i8> @test_vadd_p8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i8>, align 8
# |   %__p1.addr.i = alloca <8 x i8>, align 8
# |   %__ret.i = alloca <8 x i8>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <8 x i8>, align 8
# |   %b.addr = alloca <8 x i8>, align 8
# |   store <8 x i8> %a, ptr %a.addr, align 8
# |   store <8 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i8>, ptr %a.addr, align 8
# |   %1 = load <8 x i8>, ptr %b.addr, align 8
# |   store <8 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <8 x i8> %2, %3
# |   store <8 x i8> %4, ptr %ref.tmp.i, align 8
# |   %5 = load <8 x i8>, ptr %ref.tmp.i, align 8
# |   store <8 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <8 x i8>, ptr %__ret.i, align 8
# |   ret <8 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i16> @test_vadd_p16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x i16>, align 8
# |   %__p1.addr.i = alloca <4 x i16>, align 8
# |   %__ret.i = alloca <4 x i16>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x i16>, align 8
# |   %b.addr = alloca <4 x i16>, align 8
# |   store <4 x i16> %a, ptr %a.addr, align 8
# |   store <4 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i16>, ptr %a.addr, align 8
# |   %1 = load <4 x i16>, ptr %b.addr, align 8
# |   store <4 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <4 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <8 x i8> %2, %3
# |   %5 = bitcast <8 x i8> %4 to <4 x i16>
# |   store <4 x i16> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <4 x i16>, ptr %ref.tmp.i, align 8
# |   store <4 x i16> %6, ptr %__ret.i, align 8
# |   %7 = load <4 x i16>, ptr %__ret.i, align 8
# |   ret <4 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <1 x i64> @test_vadd_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <1 x i64>, align 8
# |   %__p1.addr.i = alloca <1 x i64>, align 8
# |   %__ret.i = alloca <1 x i64>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <1 x i64>, align 8
# |   %b.addr = alloca <1 x i64>, align 8
# |   store <1 x i64> %a, ptr %a.addr, align 8
# |   store <1 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <1 x i64>, ptr %a.addr, align 8
# |   %1 = load <1 x i64>, ptr %b.addr, align 8
# |   store <1 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <1 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <8 x i8> %2, %3
# |   %5 = bitcast <8 x i8> %4 to <1 x i64>
# |   store <1 x i64> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <1 x i64>, ptr %ref.tmp.i, align 8
# |   store <1 x i64> %6, ptr %__ret.i, align 8
# |   %7 = load <1 x i64>, ptr %__ret.i, align 8
# |   ret <1 x i64> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_p8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <16 x i8>, align 8
# |   %__p1.addr.i = alloca <16 x i8>, align 8
# |   %__ret.i = alloca <16 x i8>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   store <16 x i8> %0, ptr %__p0.addr.i, align 8
# |   store <16 x i8> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <16 x i8> %2, %3
# |   store <16 x i8> %4, ptr %ref.tmp.i, align 8
# |   %5 = load <16 x i8>, ptr %ref.tmp.i, align 8
# |   store <16 x i8> %5, ptr %__ret.i, align 8
# |   %6 = load <16 x i8>, ptr %__ret.i, align 8
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x i16>, align 8
# |   %__p1.addr.i = alloca <8 x i16>, align 8
# |   %__ret.i = alloca <8 x i16>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   store <8 x i16> %0, ptr %__p0.addr.i, align 8
# |   store <8 x i16> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <16 x i8> %2, %3
# |   %5 = bitcast <16 x i8> %4 to <8 x i16>
# |   store <8 x i16> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <8 x i16>, ptr %ref.tmp.i, align 8
# |   store <8 x i16> %6, ptr %__ret.i, align 8
# |   %7 = load <8 x i16>, ptr %__ret.i, align 8
# |   ret <8 x i16> %7
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vaddq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x i64>, align 8
# |   %__p1.addr.i = alloca <2 x i64>, align 8
# |   %__ret.i = alloca <2 x i64>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <2 x i64>, align 8
# |   %b.addr = alloca <2 x i64>, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   store <2 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   %1 = load <2 x i64>, ptr %b.addr, align 8
# |   store <2 x i64> %0, ptr %__p0.addr.i, align 8
# |   store <2 x i64> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %4 = xor <16 x i8> %2, %3
# |   %5 = bitcast <16 x i8> %4 to <2 x i64>
# |   store <2 x i64> %5, ptr %ref.tmp.i, align 8
# |   %6 = load <2 x i64>, ptr %ref.tmp.i, align 8
# |   store <2 x i64> %6, ptr %__ret.i, align 8
# |   %7 = load <2 x i64>, ptr %__ret.i, align 8
# |   ret <2 x i64> %7
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.2-a,+neon,+v8.1a,+v8.2a,-thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000558971a6515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558971a620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558971a6589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3c55649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3c556a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3c55649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3c55631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005589719fae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005589719fac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005589719dfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055897168f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055897168edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3c55632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3c556330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3c556330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055897168ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c (3055 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vv_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmslt_vx_i8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vv_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmslt_vx_i8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vv_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmslt_vx_i8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmslt_vv_i8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i
# | ...
# `---data was truncated (10240/63579) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb5fd3515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fb5fd320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fb5fd3589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ffb5b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ffb5b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ffb5b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ffb5b631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb5fccae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fb5fccac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fb5fcafb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fb5f95f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fb5f95edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ffb5b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ffb5b6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ffb5b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb5f95ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm64-crc32.c (3056 of 27911)
******************** TEST 'Clang :: CodeGen/arm64-crc32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +crc   -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32b(i32 noundef %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32b(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32b(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cb(i32 noundef %a, i8 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i8, align 1
# |   store i32 %a, ptr %a.addr, align 4
# |   store i8 %b, ptr %b.addr, align 1
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i8, ptr %b.addr, align 1
# |   %2 = zext i8 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32cb(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32cb(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32h(i32 noundef %a, i16 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32h(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32h(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32ch(i32 noundef %a, i16 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i16, align 2
# |   store i32 %a, ptr %a.addr, align 4
# |   store i16 %b, ptr %b.addr, align 2
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i16, ptr %b.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call i32 @llvm.aarch64.crc32ch(i32 %0, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32ch(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32w(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.aarch64.crc32w(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32w(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cw(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   %2 = call i32 @llvm.aarch64.crc32cw(i32 %0, i32 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32cw(i32, i32) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32d(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.aarch64.crc32x(i32 %0, i64 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32x(i32, i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @crc32cd(i32 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i64, align 8
# |   store i32 %a, ptr %a.addr, align 4
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i64, ptr %b.addr, align 8
# |   %2 = call i32 @llvm.aarch64.crc32cx(i32 %0, i64 %1)
# |   ret i32 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i32 @llvm.aarch64.crc32cx(i32, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
# | !llvm.ident = !{!6}
# | 
# | !0 = !{i32 1, !"ptrauth-elf-got", i32 0}
# | !1 = !{i32 1, !"ptrauth-init-fini", i32 0}
# | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0}
# | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0}
# | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458}
# | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0}
# | !6 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dfcb04215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dfcb03f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dfcb04289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5953933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f595398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5953933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f595391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dfcafd7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dfcafd7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dfcafbcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dfcac6c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dfcac6bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f595391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f595391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f595391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dfcac6bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c (3057 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmaxu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmaxu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, pt
# | ...
# `---data was truncated (10240/52733) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555950eeb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555950ee80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555950eeb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc74a41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc74a4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc74a41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc74a403507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555950e80e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555950e80c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555950e65b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555950b150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555950b14dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc74a404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc74a4050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc74a4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555950b14cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c (3058 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_f64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_f64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_f64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_i64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64ff_v_i64m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64ff_v_i64m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64ff_v_u64m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale 
# | ...
# `---data was truncated (10240/60817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005569dc04415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005569dc0410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005569dc04489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff92eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff92eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff92eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff92eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005569dbfd9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005569dbfd9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005569dbfbeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005569dbc6e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005569dbc6ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff92eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff92eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff92eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005569dbc6dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c (3059 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vle16ff_v_f16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0(<vscale x 1 x half> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x half>, i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0(<vscale x 1 x half>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vle16ff_v_f16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0(<vscale x 2 x half> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x half>, i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0(<vscale x 2 x half>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vle16ff_v_f16m1_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0(<vscale x 4 x half> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x half>, i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0(<vscale x 4 x half>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vle16ff_v_f16m2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0(<vscale x 8 x half> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x half>, i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0(<vscale x 8 x half>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vle16ff_v_f16m4_m(<vscale x 16 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0(<vscale x 16 x half> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x half>, i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0(<vscale x 16 x half>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vle16ff_v_f16m8_m(<vscale x 32 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0(<vscale x 32 x half> poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 32 x half>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x half>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 32 x half> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x half>, i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0(<vscale x 32 x half>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vle16ff_v_i16mf4_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(<vscale x 1 x i16> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x i16>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x i16>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i16>, i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(<vscale x 1 x i16>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vle16ff_v_i16mf2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x i16>, i64 } @llvm.riscv.vleff.mask.nxv2i16.i64.p0(<vscale x 2 x i16> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractva
# | ...
# `---data was truncated (10240/22708) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056059127e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056059127b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056059127e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f784b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f784b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f784b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f784b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560591213e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560591213c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005605911f8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560590ea80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560590ea7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f784b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f784b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f784b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560590ea7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c (3060 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3me_vv_u32mf2(<vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3me_vv_u32m1(<vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3me_vv_u32m2(<vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3me_vv_u32m4(<vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3me_vv_u32m8(<vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a9b6e4f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a9b6e4c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a9b6e4f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c7c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c7c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c7c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c7c71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a9b6de4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a9b6de4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a9b6dc9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a9b6a790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a9b6a78dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1c7c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c7c71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c7c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a9b6a78cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c (3061 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c -o -      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i32 @test_vlenb() #0 {
# | entry:
# |   %0 = call i32 @llvm.read_register.i32(metadata !4)
# |   ret i32 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare i32 @llvm.read_register.i32(metadata) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"vlenb"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2
# |  #0 0x000055f3ed7c915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f3ed7c60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f3ed7c989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3b1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3b158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3b1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3b151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3ed75ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f3ed75ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f3ed743b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f3ed3f30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f3ed3f2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc3b151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3b151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3b151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f3ed3f2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c (3062 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfsqrt_v_f16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfsqrt_v_f16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfsqrt_v_f16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfsqrt_v_f16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfsqrt_v_f16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfsqrt_v_f16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, i64 7, i64 %1)
# |   ret <vscale x 32 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfsqrt_v_f32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfsqrt_v_f32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfsqrt_v_f32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfsqrt_v_f32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfsqrt_v_f32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float> poison, <vscale x 16 x float> %0, i64 7, i64 %1)
# |   ret <vscale x 16 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfsqrt_v_f64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> %0, i64 7, i64 %1)
# |   ret <vscale x 1 x double> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local
# | ...
# `---data was truncated (10240/51412) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556fb97cc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556fb97c90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556fb97cc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f88a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f88aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f88a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f88a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556fb9761e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556fb9761c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556fb9746b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556fb93f60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556fb93f5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4f88a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f88a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f88a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556fb93f5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c (3063 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6),
# | ...
# `---data was truncated (10240/53330) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ac759e415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ac759e10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ac759e489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa716733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa71678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa716733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa71671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ac75979e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ac75979c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ac7595eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ac7560e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ac7560ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa71671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa71671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa71671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ac7560dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c (3064 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vsmul_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vsmul_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vsmul_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vsmul_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vsmul_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   
# | ...
# `---data was truncated (10240/225205) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055caa123615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055caa12330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055caa123689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2f7e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2f7e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2f7e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2f7e231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055caa11cbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055caa11cbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055caa11b0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055caa0e600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055caa0e5fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2f7e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2f7e2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2f7e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055caa0e5fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c (3065 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cf6065015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cf6064d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cf6065089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3d40a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3d40aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3d40a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3d40a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cf605e5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cf605e5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cf605cab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cf6027a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cf60279dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3d40a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3d40a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3d40a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cf60279cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c (3066 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16.p0.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16.p0.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16.p0.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16.p0.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16.p0.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vle.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vle.mask.nxv32bf16.p0.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056275ab3b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056275ab380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056275ab3b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0aaaa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0aaaaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0aaaa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0aaaa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056275aad0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056275aad0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056275aab5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056275a7650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056275a764dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0aaaa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0aaaa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0aaaa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056275a764cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c (3067 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %1, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005626400d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005626400d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005626400d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff7c4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff7c438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff7c4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff7c431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562640069e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562640069c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056264004eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056263fcfe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056263fcfddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff7c431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff7c431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff7c431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056263fcfdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c (3068 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_f16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_f16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_f16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_i16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_i16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_i16m1x7_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlsseg7e16_v_u16mf4x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlsseg7e16_v_u16mf2x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlsseg7e16_v_u16m1x7_m(<vs
# | ...
# `---data was truncated (10240/11851) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005571ccf7c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005571ccf790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005571ccf7c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc22b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc22b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc22b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc22b71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005571ccf11e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005571ccf11c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005571ccef6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005571ccba60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005571ccba5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc22b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc22b71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc22b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005571ccba5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c (3069 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vwmaccus_vx_i16mf4(<vscale x 1 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(<vscale x 1 x i16>, i8, <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vwmaccus_vx_i16mf2(<vscale x 2 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(<vscale x 2 x i16>, i8, <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwmaccus_vx_i16m1(<vscale x 4 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(<vscale x 4 x i16>, i8, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vwmaccus_vx_i16m2(<vscale x 8 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(<vscale x 8 x i16>, i8, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vwmaccus_vx_i16m4(<vscale x 16 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(<vscale x 16 x i16>, i8, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vwmaccus_vx_i16m8(<vscale x 32 x i16> %vd, i8 noundef zeroext %rs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i16>, align 2
# |   %rs1.addr = alloca i8, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vd, ptr %vd.addr, align 2
# |   store i8 %rs1, ptr %rs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vd.addr, align 2
# |   %1 = load i8, ptr %rs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 32 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(<vscale x 32 x i16>, i8, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vwmaccus_vx_i32mf2(<vscale x 1 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(<vscale x 1 x i32>, i16, <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwmaccus_vx_i32m1(<vscale x 2 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(<vscale x 2 x i32>, i16, <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vwmaccus_vx_i32m2(<vscale x 4 x i32> %vd, i16 noundef zeroext %rs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i16, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store i16 %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load i16, ptr %rs1.addr, align 
# | ...
# `---data was truncated (10240/39226) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562f8345a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562f834570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562f8345a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec1fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec1fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec1fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec1fd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562f833efe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562f833efc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562f833d4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562f830840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562f83083dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fec1fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec1fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec1fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562f83083cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c (3070 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, <vscale x 8 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_v
# | ...
# `---data was truncated (10240/228865) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ffaddb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563ffadd80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563ffaddb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efca2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efca258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efca2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efca251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ffad70e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563ffad70c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563ffad55b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563ffaa050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563ffaa04dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efca251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efca251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efca251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ffaa04cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c (3071 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b7c6c015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562b7c6bd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562b7c6c089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6639333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f663938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6639333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f663931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b7c655e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562b7c655c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562b7c63ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562b7c2ea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562b7c2e9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f663931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f663931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f663931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b7c2e9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c (3072 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nx
# | ...
# `---data was truncated (10240/18660) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dd0859a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dd085970f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dd0859a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f05c1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f05c10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f05c1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f05c1031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dd0852fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dd0852fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dd08514b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dd081c40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dd081c3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f05c1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f05c10330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f05c10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dd081c3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c (3073 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c58edc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557c58ed90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557c58edc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3e41e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3e41ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3e41e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3e41e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c58e71e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557c58e71c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557c58e56b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557c58b060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557c58b05dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3e41e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3e41e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3e41e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c58b05cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c (3074 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vluxseg2ei64_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vluxseg2ei64_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vluxseg2ei64_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vluxseg2ei64_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564c1533a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564c153370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564c1533a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f23d4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f23d4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f23d4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f23d4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564c152cfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564c152cfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564c152b4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564c14f640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564c14f63dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f23d4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f23d4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f23d4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564c14f63cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-cde-vfp.c (3075 of 27911)
******************** TEST 'Clang :: CodeGen/arm-cde-vfp.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +cdecp1    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx1_u32() #0 {
# | entry:
# |   %0 = call float @llvm.arm.cde.vcx1.f32(i32 0, i32 11)
# |   %1 = bitcast float %0 to i32
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx1.f32(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx1a_u32(i32 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = call float @llvm.arm.cde.vcx1a.f32(i32 1, float %1, i32 12)
# |   %3 = bitcast float %2 to i32
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx1a.f32(i32 immarg, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx2_u32(i32 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = call float @llvm.arm.cde.vcx2.f32(i32 0, float %1, i32 21)
# |   %3 = bitcast float %2 to i32
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx2.f32(i32 immarg, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx2a_u32(i32 noundef %acc, i32 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = load i32, ptr %n.addr, align 4
# |   %3 = bitcast i32 %2 to float
# |   %4 = call float @llvm.arm.cde.vcx2a.f32(i32 0, float %1, float %3, i32 22)
# |   %5 = bitcast float %4 to i32
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx2a.f32(i32 immarg, float, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx3_u32(i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %n.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = load i32, ptr %m.addr, align 4
# |   %3 = bitcast i32 %2 to float
# |   %4 = call float @llvm.arm.cde.vcx3.f32(i32 1, float %1, float %3, i32 3)
# |   %5 = bitcast float %4 to i32
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx3.f32(i32 immarg, float, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i32 @test_vcx3a_u32(i32 noundef %acc, i32 noundef %n, i32 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i32, align 4
# |   %n.addr = alloca i32, align 4
# |   %m.addr = alloca i32, align 4
# |   store i32 %acc, ptr %acc.addr, align 4
# |   store i32 %n, ptr %n.addr, align 4
# |   store i32 %m, ptr %m.addr, align 4
# |   %0 = load i32, ptr %acc.addr, align 4
# |   %1 = bitcast i32 %0 to float
# |   %2 = load i32, ptr %n.addr, align 4
# |   %3 = bitcast i32 %2 to float
# |   %4 = load i32, ptr %m.addr, align 4
# |   %5 = bitcast i32 %4 to float
# |   %6 = call float @llvm.arm.cde.vcx3a.f32(i32 0, float %1, float %3, float %5, i32 5)
# |   %7 = bitcast float %6 to i32
# |   ret i32 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare float @llvm.arm.cde.vcx3a.f32(i32 immarg, float, float, float, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx1d_u64() #0 {
# | entry:
# |   %0 = call double @llvm.arm.cde.vcx1.f64(i32 0, i32 11)
# |   %1 = bitcast double %0 to i64
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx1.f64(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx1da_u64(i64 noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = call double @llvm.arm.cde.vcx1a.f64(i32 1, double %1, i32 12)
# |   %3 = bitcast double %2 to i64
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx1a.f64(i32 immarg, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx2d_u64(i64 noundef %n) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %0 = load i64, ptr %n.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = call double @llvm.arm.cde.vcx2.f64(i32 0, double %1, i32 21)
# |   %3 = bitcast double %2 to i64
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx2.f64(i32 immarg, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx2da_u64(i64 noundef %acc, i64 noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = load i64, ptr %n.addr, align 8
# |   %3 = bitcast i64 %2 to double
# |   %4 = call double @llvm.arm.cde.vcx2a.f64(i32 0, double %1, double %3, i32 22)
# |   %5 = bitcast double %4 to i64
# |   ret i64 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx2a.f64(i32 immarg, double, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx3d_u64(i64 noundef %n, i64 noundef %m) #0 {
# | entry:
# |   %n.addr = alloca i64, align 8
# |   %m.addr = alloca i64, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   store i64 %m, ptr %m.addr, align 8
# |   %0 = load i64, ptr %n.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = load i64, ptr %m.addr, align 8
# |   %3 = bitcast i64 %2 to double
# |   %4 = call double @llvm.arm.cde.vcx3.f64(i32 1, double %1, double %3, i32 3)
# |   %5 = bitcast double %4 to i64
# |   ret i64 %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx3.f64(i32 immarg, double, double, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc i64 @test_vcx3da_u64(i64 noundef %acc, i64 noundef %n, i64 noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca i64, align 8
# |   %n.addr = alloca i64, align 8
# |   %m.addr = alloca i64, align 8
# |   store i64 %acc, ptr %acc.addr, align 8
# |   store i64 %n, ptr %n.addr, align 8
# |   store i64 %m, ptr %m.addr, align 8
# |   %0 = load i64, ptr %acc.addr, align 8
# |   %1 = bitcast i64 %0 to double
# |   %2 = load i64, ptr %n.addr, align 8
# |   %3 = bitcast i64 %2 to double
# |   %4 = load i64, ptr %m.addr, align 8
# |   %5 = bitcast i64 %4 to double
# |   %6 = call double @llvm.arm.cde.vcx3a.f64(i32 0, double %1, double %3, double %5, i32 5)
# |   %7 = bitcast double %6 to i64
# |   ret i64 %7
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare double @llvm.arm.cde.vcx3a.f64(i32 immarg, double, double, double, i32 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+cdecp1,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a4120bf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a4120bc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a4120bf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faf15133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faf1518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faf15133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faf1511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a412054e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a412054c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a412039b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a411ce90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a411ce8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faf1511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faf1511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faf1511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a411ce8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c (3076 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmandn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmandn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmandn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmandn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmandn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmandn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmandn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005591dfe6b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005591dfe680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005591dfe6b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe6d4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe6d438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe6d4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe6d431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005591dfe00e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005591dfe00c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005591dfde5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005591dfa950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005591dfa94dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe6d431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe6d431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe6d431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591dfa94cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c (3077 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e32_v_u32m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i6
# | ...
# `---data was truncated (10240/47604) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560e591a315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560e591a00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560e591a389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efef6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efef66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efef6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efef6631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560e59138e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560e59138c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560e5911db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560e58dcd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560e58dccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efef6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efef66330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efef66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560e58dcccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c (3078 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfne_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfne_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfne_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfne_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560ff826515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560ff82620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560ff826589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb9f3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9f378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb9f3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb9f371b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560ff81fae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560ff81fac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560ff81dfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560ff7e8f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560ff7e8edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb9f371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9f371d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9f371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560ff7e8ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c (3079 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_f16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_f16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_f16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_i16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_i16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_i16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_u16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %base.addr = alloca ptr, ali
# | ...
# `---data was truncated (10240/60543) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055818a91d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055818a91a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055818a91d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7a8eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7a8eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7a8eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7a8eb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055818a8b2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055818a8b2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055818a897b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055818a5470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055818a546dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7a8eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7a8eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7a8eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055818a546cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c (3080 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 3, i64 31, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 immarg, i64 immarg, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 3, i64 31, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 immarg, i64 immarg, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 3, i64 31, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 immarg, i64 immarg, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_sf_vc_xv_se_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 3, i64 31, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nounwind
# | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 immarg, i64 immarg, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xv_se_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_xv_se_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_xv_se_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_xv_se_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind
# | declare <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 immarg, <vscale x 8 x i64>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_sf_vc_v_xv_u64m1(<vscale x 1 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.nxv1i64.i64.i64(i64 immarg, <vscale x 1 x i64>, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_sf_vc_v_xv_u64m2(<vscale x 2 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.nxv2i64.i64.i64(i64 immarg, <vscale x 2 x i64>, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_sf_vc_v_xv_u64m4(<vscale x 4 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> %0, i64 %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nounwind memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.nxv4i64.i64.i64(i64 immarg, <vscale x 4 x i64>, i64, i64) #2
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_sf_vc_v_xv_u64m8(<vscale x 8 x i64> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %rs1.addr = alloca i64, align 8
# |   %vl.
# | ...
# `---data was truncated (10240/11504) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aa401f015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aa401ed0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aa401f089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdefb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdefb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdefb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdefb031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa40185e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aa40185c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aa4016ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aa3fe1a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aa3fe19dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdefb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdefb0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdefb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa3fe19cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c (3081 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f    -target-feature +experimental-zvfofp8min -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %tm.addr = alloca i64, align 8
# |   %tn.addr = alloca i64, align 8
# |   %tk.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store i64 %tm, ptr %tm.addr, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   store i64 %tk, ptr %tk.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load i64, ptr %tm.addr, align 8
# |   %3 = load i64, ptr %tn.addr, align 8
# |   %4 = load i64, ptr %tk.addr, align 8
# |   call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2, i64 %3, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 immarg, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8f0abb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a8f0ab80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a8f0abb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff338b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff338b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff338b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff338b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8f0a50e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a8f0a50c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a8f0a35b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a8f06e50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a8f06e4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff338b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff338b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff338b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8f06e4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c (3082 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_f64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_i64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg6e64_v_u64m1x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a8d915415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a8d91510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a8d915489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007feb3c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007feb3c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007feb3c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007feb3c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a8d90e9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a8d90e9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a8d90ceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a8d8d7e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a8d8d7ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007feb3c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007feb3c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007feb3c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a8d8d7dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c (3083 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i
# | ...
# `---data was truncated (10240/51295) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ebcf5b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563ebcf580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563ebcf5b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f414e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f414e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f414e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f414e831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ebcef0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563ebcef0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563ebced5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563ebcb850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563ebcb84dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f414e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f414e8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f414e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ebcb84cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c (3084 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4(<vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2(<vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1(<vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2(<vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4(<vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8(<vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %1 = load bfloat, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vsc
# | ...
# `---data was truncated (10240/14832) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055af1e86715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055af1e8640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055af1e86789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb08fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb08faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb08fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb08fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055af1e7fce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055af1e7fcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055af1e7e1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055af1e4910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055af1e490dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb08fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb08fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb08fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055af1e490cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c (3085 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565205b9615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000565205b930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000565205b9689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5d47f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5d47f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5d47f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5d47f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565205b2be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565205b2bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565205b10b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005652057c00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005652057bfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5d47f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5d47f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5d47f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652057bfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c (3086 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target
# | ...
# `---data was truncated (10240/23439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563e46f1415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563e46f110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563e46f1489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007effde933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007effde98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007effde933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007effde91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563e46ea9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563e46ea9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563e46e8eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563e46b3e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563e46b3ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007effde91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007effde91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007effde91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563e46b3dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c (3087 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4
# | ...
# `---data was truncated (10240/17503) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619d08ad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005619d08aa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005619d08ad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc6b9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc6b958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc6b9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc6b951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619d0842e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005619d0842c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005619d0827b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005619d04d70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005619d04d6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc6b951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc6b951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc6b951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619d04d6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c (3088 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 5)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs:
# | ...
# `---data was truncated (10240/16382) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005581e9ce615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005581e9ce30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005581e9ce689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc7e1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc7e1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc7e1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc7e1a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005581e9c7be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005581e9c7bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005581e9c60b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005581e99100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005581e990fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc7e1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc7e1a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc7e1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005581e990fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c (3089 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = c
# | ...
# `---data was truncated (10240/16451) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005614211ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005614211a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005614211ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f80a4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f80a478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f80a4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f80a471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561421140e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561421140c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561421125b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561420dd50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561420dd4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f80a471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f80a471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f80a471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561420dd4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c (3090 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfnmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfnmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfnmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfnmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7
# | ...
# `---data was truncated (10240/64374) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056090178715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005609017840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056090178789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd1e1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd1e158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd1e1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd1e151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056090171ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056090171cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560901701b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005609013b10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005609013b0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd1e151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd1e151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd1e151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005609013b0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c (3091 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f55767415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f5576710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f55767489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe8dc049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe8dc0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe8dc049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe8dc031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f557609e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f557609c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f5575eeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f55729e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f55729ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe8dc032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe8dc0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe8dc0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f55729dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c (3092 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple
# | ...
# `---data was truncated (10240/20903) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559d705e815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559d705e50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559d705e889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb402049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb4020a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb402049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb402031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559d7057de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559d7057dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559d70562b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559d702120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559d70211dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb402032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb4020330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb4020330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559d70211cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c (3093 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsm3c_vi_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsm3c.nxv1i32.i64.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsm3c_vi_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsm3c.nxv2i32.i64.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsm3c_vi_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsm3c.nxv4i32.i64.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsm3c_vi_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsm3c.nxv8i32.i64.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsm3c_vi_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 0, i64 %2, i64 3)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsm3c.nxv16i32.i64.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i64 immarg, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b83621115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b83620e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b83621189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2f7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2f7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2f7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2f7f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b8361a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b8361a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b83618bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b835e3b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b835e3add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd2f7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2f7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2f7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b835e3acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c (3094 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree no
# | ...
# `---data was truncated (10240/13023) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f0d75d815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f0d75d50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f0d75d889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9e29649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9e296a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9e29649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9e29631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f0d756de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f0d756dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f0d7552b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f0d72020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f0d7201dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9e29632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9e296330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9e296330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f0d7201cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-bf16-params-returns.c (3095 of 27911)
******************** TEST 'Clang :: CodeGen/arm-bf16-params-returns.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.6a-arm-none-eabi"
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
# | define dso_local arm_aapcs_vfpcc noundef bfloat @test_ret_bf16(bfloat noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret bfloat %v
# | }
# | 
# | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
# | define dso_local arm_aapcs_vfpcc noundef <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> noundef returned %v) local_unnamed_addr #0 {
# | entry:
# |   ret <4 x bfloat> %v
# | }
# | 
# | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.6-a,+bf16,+neon,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,-thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | !llvm.errno.tbaa = !{!6}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# | !6 = !{!7, !8, i64 0}
# | !7 = !{!"__libc_errno", !8, i64 0}
# | !8 = !{!"int", !9, i64 0}
# | !9 = !{!"omnipotent char", !10, i64 0}
# | !10 = !{!"Simple C/C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa
# |  #0 0x0000562ec62b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562ec62b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562ec62b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdf68e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdf68ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdf68e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdf68e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562ec624be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562ec624bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562ec6230b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562ec5ee00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562ec5edfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdf68e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdf68e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdf68e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562ec5edfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c (3096 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb6430d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fb6430a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fb6430d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4e0c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4e0c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4e0c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4e0c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb642a2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fb642a2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fb64287b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fb63f370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fb63f36dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4e0c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4e0c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4e0c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb63f36cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c (3097 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055791dbf815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055791dbf50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055791dbf889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdb23649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdb236a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdb23649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdb23631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055791db8de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055791db8dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055791db72b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055791d8220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055791d821dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdb23632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdb236330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdb236330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055791d821cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c (3098 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055993b60015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055993b5fd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055993b60089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4374733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f437478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4374733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f437471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055993b595e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055993b595c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055993b57ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055993b22a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055993b229dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f437471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f437471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f437471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055993b229cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c (3099 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei16_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei16_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei16_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ba8480e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ba8480b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ba8480e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faceb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faceb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faceb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faceb831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ba847a3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ba847a3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ba84788b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ba844380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ba84437dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faceb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faceb8330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faceb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ba84437cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c (3100 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vle32ff_v_f32mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(<vscale x 1 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vle32ff_v_f32m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x float>, i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(<vscale x 2 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vle32ff_v_f32m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x float>, i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(<vscale x 4 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vle32ff_v_f32m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x float>, i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(<vscale x 8 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vle32ff_v_f32m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 16 x float>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 16 x float>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x float>, i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(<vscale x 16 x float>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vle32ff_v_i32mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 1 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 1 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(<vscale x 1 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vle32ff_v_i32m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 2 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 2 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(<vscale x 2 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vle32ff_v_i32m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 4 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 4 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x i32>, i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(<vscale x 4 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vle32ff_v_i32m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32.i64.p0(<vscale x 8 x i32> poison, ptr %0, i64 %2)
# |   %4 = extractvalue { <vscale x 8 x i32>, i64 } %3, 0
# |   %5 = extractvalue { <vscale x 8 x i32>, i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x i32>, i64 } @llvm.riscv.vleff.nxv8i32.i64.p0(<vscale x 8 x i32>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vle32ff_v_i32m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { <vscale x 16 x i32>, i64 } @llvm.riscv.vleff.nxv16i32.i64.p0(<vscale x 16 x i32> poison, ptr %0, i64 %2)
# |   %4 =
# | ...
# `---data was truncated (10240/33471) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565380c5515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000565380c520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000565380c5589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8d19f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8d19f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8d19f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8d19f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565380beae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565380beac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565380bcfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056538087f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056538087edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8d19f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8d19f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8d19f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056538087ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c (3101 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e64_v_f64m1x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e64_v_f64m2x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e64_v_f64m4x2_m(<vscale x 4
# | ...
# `---data was truncated (10240/17583) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d13a2b515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d13a2b20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d13a2b589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007febe8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007febe8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007febe8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007febe8c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d13a24ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d13a24ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d13a22fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d139edf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d139ededd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007febe8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007febe8c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007febe8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d139edecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmovl.c (3102 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmovl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
# |   %2 = sext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
# |   %2 = sext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
# |   %2 = zext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
# |   %2 = zext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_s8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
# |   %2 = sext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_s16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
# |   %2 = sext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_u8(<16 x i8> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
# |   %2 = zext <8 x i8> %1 to <8 x i16>
# |   ret <8 x i16> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_u16(<8 x i16> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
# |   %2 = zext <4 x i16> %1 to <4 x i32>
# |   ret <4 x i32> %2
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 0, i32 0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 0, i32 0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_u8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 1, i32 0, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 1, i32 0, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 0, i32 1, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
# |   %4 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 0, i32 1, <4 x i1> %3, <4 x i32> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_u8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 1, i32 1, <8 x i1> %3, <8 x i16> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %p.ad
# | ...
# `---data was truncated (10240/16274) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a77b0d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555a77b0a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555a77b0d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9bf6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9bf678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9bf6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9bf671b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a77aa2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555a77aa2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555a77a87b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555a777370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555a77736dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9bf671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9bf671d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9bf671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a77736cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/AArch64/neon/fullfp16.c (3103 of 27911)
******************** TEST 'Clang :: CodeGen/AArch64/neon/fullfp16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16           -emit-llvm  /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg             | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
# | target triple = "arm64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vaddh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vaddh = fadd half %2, %3
# |   store half %vaddh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vsubh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vsubh = fsub half %2, %3
# |   store half %vsubh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vmulh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmulh = fmul half %2, %3
# |   store half %vmulh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vdivh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vdivh = fdiv half %2, %3
# |   store half %vdivh, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vmaxh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmax = call half @llvm.aarch64.neon.fmax.f16(half %2, half %3)
# |   store half %vmax, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fmax.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vmaxnmh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmaxnm = call half @llvm.aarch64.neon.fmaxnm.f16(half %2, half %3)
# |   store half %vmaxnm, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fmaxnm.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vminh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vmin = call half @llvm.aarch64.neon.fmin.f16(half %2, half %3)
# |   store half %vmin, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fmin.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vminnmh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   store half %b, ptr %b.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %b.addr, align 2
# |   store half %1, ptr %__s1, align 2
# |   %2 = load half, ptr %__s0, align 2
# |   %3 = load half, ptr %__s1, align 2
# |   %vminnm = call half @llvm.aarch64.neon.fminnm.f16(half %2, half %3)
# |   store half %vminnm, ptr %ref.tmp, align 2
# |   %4 = load half, ptr %ref.tmp, align 2
# |   store half %4, ptr %__ret, align 2
# |   %5 = load half, ptr %__ret, align 2
# |   store half %5, ptr %tmp, align 2
# |   %6 = load half, ptr %tmp, align 2
# |   ret half %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare half @llvm.aarch64.neon.fminnm.f16(half, half) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i16 @test_vceqzh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca i16, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca i16, align 2
# |   %tmp = alloca i16, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %2 = fcmp oeq half %1, 0.000000e+00
# |   %vceqz = sext i1 %2 to i16
# |   store i16 %vceqz, ptr %ref.tmp, align 2
# |   %3 = load i16, ptr %ref.tmp, align 2
# |   store i16 %3, ptr %__ret, align 2
# |   %4 = load i16, ptr %__ret, align 2
# |   store i16 %4, ptr %tmp, align 2
# |   %5 = load i16, ptr %tmp, align 2
# |   ret i16 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vabsh_f16(half noundef %a) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %ref.tmp = alloca half, align 2
# |   %tmp = alloca half, align 2
# |   store half %a, ptr %a.addr, align 2
# |   %0 = load half, ptr %a.addr, align 2
# |   store half %0, ptr %__s0, align 2
# |   %1 = load half, ptr %__s0, align 2
# |   %vabs = call half @llvm.fabs.f16(half %1)
# |   store half %vabs, ptr %ref.tmp, align 2
# |   %2 = load half, ptr %ref.tmp, align 2
# |   store half %2, ptr %__ret, align 2
# |   %3 = load half, ptr %__ret, align 2
# |   store half %3, ptr %tmp, align 2
# |   %4 = load half, ptr %tmp, align 2
# |   ret half %4
# | }
# | 
# | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none)
# | declare half @llvm.fabs.f16(half) #2
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local half @test_vabdh_f16(half noundef %a, half noundef %b) #0 {
# | entry:
# |   %a.addr = alloca half, align 2
# |   %b.addr = alloca half, align 2
# |   %__ret = alloca half, align 2
# |   %__s0 = alloca half, align 2
# |   %__s1 = all
# | ...
# `---data was truncated (10240/27802) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a65cbc015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a65cbbd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a65cbc089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe23ef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe23ef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe23ef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe23eeed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a65cb55e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a65cb55c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a65cb3ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a65c7ea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a65c7e9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe23eeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe23eeef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe23eeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a65c7e9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c (3104 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_bf16mf2x5_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_bf16m1x5_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, i64 %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_bf16mf4x5_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %rs1.addr = alloca ptr, align 8
# | ...
# `---data was truncated (10240/18506) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562dcdbcc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562dcdbc90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562dcdbcc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc596f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc596f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc596f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc596f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562dcdb61e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562dcdb61c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562dcdb46b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562dcd7f60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562dcd7f5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc596f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc596f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc596f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562dcd7f5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c (3105 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, <vscale x 16 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 16 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 16 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, <vscale x 32 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 32 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 32 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, <vscale x 64 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 64 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 64 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i8.p0.i64(<vscale x 1 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i8.p0.i64(<vscale x 2 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i8> %value, ptr %value.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %value.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i8.p0.i64(<vscale x 4 x i8> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i8> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %bas
# | ...
# `---data was truncated (10240/29817) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005583e9eda15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005583e9ed70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005583e9eda89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe355b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe355b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe355b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe355b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005583e9e6fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005583e9e6fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005583e9e54b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005583e9b040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005583e9b03dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe355b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe355b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe355b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005583e9b03cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c (3106 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vfclass_v_u16mf4(<vscale x 1 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vfclass_v_u16mf2(<vscale x 2 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vfclass_v_u16m1(<vscale x 4 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vfclass_v_u16m2(<vscale x 8 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vfclass_v_u16m4(<vscale x 16 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vfclass_v_u16m8(<vscale x 32 x half> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> poison, <vscale x 32 x half> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfclass_v_u32mf2(<vscale x 1 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfclass_v_u32m1(<vscale x 2 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfclass_v_u32m2(<vscale x 4 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfclass_v_u32m4(<vscale x 8 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfclass_v_u32m8(<vscale x 16 x float> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfclass_v_u64m1(<vscale x 1 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfclass_v_u64m2(<vscale x 2 x double> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %op1, ptr %op1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 
# | ...
# `---data was truncated (10240/28683) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557c8782b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557c878280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557c8782b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d34333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d3438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d34333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d3431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557c877c0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557c877c0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557c877a5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557c874550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557c87454dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1d3431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d3431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d3431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557c87454cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c (3107 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i16> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i16> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c04730715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c0473040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c04730789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff951c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff951c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff951c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff951c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c04729ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c04729cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c047281b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c046f310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c046f30dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff951c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff951c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff951c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c046f30cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c (3108 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc7ae2315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dc7ae200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dc7ae2389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc977a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc977aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc977a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc977a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc7adb8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dc7adb8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dc7ad9db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dc7aa4d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dc7aa4cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc977a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc977a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc977a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc7aa4ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c (3109 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmerge_vfm_f16mf4(<vscale x 1 x half> %op1, half noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmerge_vfm_f16mf2(<vscale x 2 x half> %op1, half noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmerge_vfm_f16m1(<vscale x 4 x half> %op1, half noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, <vscale x 4 x i1> %2, i64 %3)
# |   ret <vscale x 4 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmerge_vfm_f16m2(<vscale x 8 x half> %op1, half noundef %op2, <vscale x 8 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, <vscale x 8 x i1> %2, i64 %3)
# |   ret <vscale x 8 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmerge_vfm_f16m4(<vscale x 16 x half> %op1, half noundef %op2, <vscale x 16 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, <vscale x 16 x i1> %2, i64 %3)
# |   ret <vscale x 16 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmerge_vfm_f16m8(<vscale x 32 x half> %op1, half noundef %op2, <vscale x 32 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %op1.addr, align 2
# |   %1 = load half, ptr %op2.addr, align 2
# |   %2 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, <vscale x 32 x i1> %2, i64 %3)
# |   ret <vscale x 32 x half> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmerge_vfm_f32mf2(<vscale x 1 x float> %op1, float noundef %op2, <vscale x 1 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, <vscale x 1 x i1> %2, i64 %3)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmerge_vfm_f32m1(<vscale x 2 x float> %op1, float noundef %op2, <vscale x 2 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %op1, ptr %op1.addr, align 4
# |   store float %op2, ptr %op2.addr, align 4
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %op1.addr, align 4
# |   %1 = load float, ptr %op2.addr, align 4
# |   %2 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, <vscale x 2 x i1> %2, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmerge_vfm_f32m2(<vscale x 4 x float> %op1, float noundef %op2, <vscale x 4 x i1> %mask, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x float>, align 4
# |   %op2.addr = alloca float, align 4
# |   %mask.addr = alloca <vscale x 4 x i1
# | ...
# `---data was truncated (10240/19049) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f51876315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f5187600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f51876389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0409533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f040958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0409533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f040951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f5186f8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f5186f8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f5186ddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f51838d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f51838cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f040951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f040951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f040951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f51838ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c (3110 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16ff_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16ff_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16ff_v_bf16m1x2_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16ff_v_bf16m2x2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16ff_v_bf16m4x2_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056531157315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005653115700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056531157389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe899c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe899ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe899c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe899c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565311508e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565311508c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005653114edb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056531119d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056531119cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe899c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe899c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe899c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056531119ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c (3111 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_i8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_i8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_i8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_i8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e8_v_i8m2x3_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlseg3e8_v_u8mf8x3_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e8_v_u8mf4x3_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e8_v_u8mf2x3_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e8_v_u8m1x3_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x 
# | ...
# `---data was truncated (10240/11943) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563c8cb3615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563c8cb330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563c8cb3689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2217b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2217b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2217b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2217b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563c8cacbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563c8cacbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563c8cab0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563c8c7600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563c8c75fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2217b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2217b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2217b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563c8c75fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c (3112 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vzext_vf4_u32m4(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vzext_vf4_u32m8(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf4_u64m1(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf4_u64m2(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf4_u64m4(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf4_u64m8(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vzext_vf4_u32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vzext_vf4_u32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vzext_vf4_u32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i8.i64(<
# | ...
# `---data was truncated (10240/17495) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f9cd54915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f9cd5460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f9cd54989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f608db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f608db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f608db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f608db1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9cd4dee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f9cd4dec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f9cd4c3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f9cd1730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f9cd172dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f608db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f608db1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f608db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f9cd172cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c (3113 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i64> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b2111215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559b2110f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559b2111289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e89533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e8958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e89533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e8951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b210a7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559b210a7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559b2108cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559b20d3c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559b20d3bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6e8951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e8951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e8951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b20d3bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c (3114 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f16m1x7(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f32m1x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_f64m1x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei32_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607cea4715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005607cea440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005607cea4789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4f6c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4f6c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4f6c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4f6c91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607ce9dce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005607ce9dcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005607ce9c1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005607ce6710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005607ce670dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4f6c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4f6c91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4f6c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607ce670cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c (3115 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vsca
# | ...
# `---data was truncated (10240/63705) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556c8186415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556c818610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556c8186489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9a5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9a52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9a5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9a5231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556c817f9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556c817f9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556c817deb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556c8148e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556c8148ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc9a5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9a52330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9a52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556c8148dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c (3116 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563ac68c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563ac68c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563ac68c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc4c0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc4c018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc4c0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc4c011b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563ac685ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563ac685ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563ac683fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563ac64ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563ac64eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc4c011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc4c011d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc4c011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563ac64eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c (3117 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 8 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 16 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 16 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 16 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, <vscale x 16 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 
# | ...
# `---data was truncated (10240/284344) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596723e115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005596723de0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005596723e189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9cc6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9cc66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9cc6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9cc6631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559672376e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559672376c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055967235bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055967200b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055967200add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9cc6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9cc66330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9cc66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055967200acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c (3118 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vv_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_vf_bf16mf4_f32mf2(<vscale x 1 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(<vscale x 1 x float>, <vscale x 1 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wv_bf16mf4_f32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfwsub_wf_bf16_f32mf2(<vscale x 1 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(<vscale x 1 x float>, <vscale x 1 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vv_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_vf_bf16mf2_f32m1(<vscale x 2 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x bfloat> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(<vscale x 2 x float>, <vscale x 2 x bfloat>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wv_bf16mf2_f32m1(<vscale x 2 x float> %vs2, <vscale x 2 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwsub_wf_bf16_f32m1(<vscale x 2 x float> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, bfloat %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(<vscale x 2 x float>, <vscale x 2 x float>, bfloat, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vv_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, <vscale x 4 x bfloat> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> poison, <vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfwsub_vf_bf16m1_f32m2(<vscale x 4 x bfloat> %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.a
# | ...
# `---data was truncated (10240/86092) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c73cfa815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c73cfa50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c73cfa889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe283933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe28398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe283933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe28391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c73cf3de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c73cf3dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c73cf22b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c73cbd20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c73cbd1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe28391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe28391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe28391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c73cbd1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c (3119 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vv.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vaesem_vs_u32mf2_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32mf2_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(<vscale x 2 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32mf2_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(<vscale x 4 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32mf2_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(<vscale x 8 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vaesem_vs_u32mf2_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 1 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(<vscale x 16 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vv.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vaesem_vs_u32m1_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vaesem_vs_u32m1_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(<vscale x 4 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vaesem_vs_u32m1_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 2 x i32> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64(<vscale x 8 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretur
# | ...
# `---data was truncated (10240/20190) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005646a7a1d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005646a7a1a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005646a7a1d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4a09249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4a092a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4a09249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4a09231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005646a79b2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005646a79b2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005646a7997b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005646a76470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005646a7646dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4a09232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4a092330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4a092330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005646a7646cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c (3120 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_f16mf4x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f16mf2x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f16m1x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f16m2x4(ptr noundef %base, <vscale x 8 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_f32mf2x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f32m1x4(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_f32m2x4(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_f64m1x4(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.
# | ...
# `---data was truncated (10240/82975) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055aea58d015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aea58cd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aea58d089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3131049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f31310a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3131049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3131031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aea5865e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aea5865c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aea584ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aea54fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aea54f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3131032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f31310330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f31310330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aea54f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c (3121 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555bd745a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555bd74570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555bd745a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fce8b21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fce8b2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fce8b21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fce8b203507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555bd73efe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555bd73efc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555bd73d4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555bd70840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555bd7083dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fce8b204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fce8b2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fce8b2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555bd7083cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c (3122 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettk.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettk_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005580fd06b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005580fd0680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005580fd06b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fe6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fe6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fe6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fe6a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005580fd000e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005580fd000c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005580fcfe5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005580fcc950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005580fcc94dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9fe6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fe6a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fe6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005580fcc94cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c (3123 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vluxseg6ei32_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vluxseg6ei32_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vluxseg6ei32_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556497c3815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556497c350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556497c3889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f55c1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f55c18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f55c1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f55c1831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556497bcde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556497bcdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556497bb2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005564978620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556497861dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f55c1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f55c18330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f55c18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556497861cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c (3124 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfle_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfle_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 32 x bflo
# | ...
# `---data was truncated (10240/27786) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562bea21e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562bea21b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562bea21e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5967449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f59674a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5967449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5967431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562bea1b3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562bea1b3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562bea198b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562be9e480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562be9e47dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5967432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f59674330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f59674330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562be9e47cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c (3125 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c  -check-prefix=RV64XTHEADBB
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clz_32(i32 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 false)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clo_32(i32 noundef signext %a) #0 {
# | entry:
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %not = xor i32 %0, -1
# |   %1 = call i32 @llvm.ctlz.i32(i32 %not, i1 false)
# |   ret i32 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clz_64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = call i64 @llvm.ctlz.i64(i64 %0, i1 false)
# |   %cast = trunc i64 %1 to i32
# |   ret i32 %cast
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare i64 @llvm.ctlz.i64(i64, i1 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local signext i32 @clo_64(i64 noundef %a) #0 {
# | entry:
# |   %a.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %not = xor i64 %0, -1
# |   %1 = call i64 @llvm.ctlz.i64(i64 %not, i1 false)
# |   %cast = trunc i64 %1 to i32
# |   ret i32 %cast
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xtheadbb" }
# | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_xtheadbb1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055575077815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005557507750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055575077889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1872933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f187298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1872933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f187291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055575070de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055575070dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005557506f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005557503a20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005557503a1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f187291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f187291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f187291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557503a1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c (3126 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i16> @test_vsext_vf2_i16mf4(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i16> @test_vsext_vf2_i16mf2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vsext_vf2_i16m1(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i16> @test_vsext_vf2_i16m2(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i16> @test_vsext_vf2_i16m4(<vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i16> @test_vsext_vf2_i16m8(<vscale x 32 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf2_i32mf2(<vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf2_i32m1(<vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf2_i32m2(<vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf2_i32m4(<vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf2_i32m8(<vscale x 16 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf2_i64m1(<vscale x 1 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %op1.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> poison, <vscale x 1 x i32> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf2_i64m2(<vscale x 2 x i32> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %op1, ptr %op1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>,
# | ...
# `---data was truncated (10240/28571) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ec304c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555ec30490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555ec304c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd0a5505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd0a555c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd0a5505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd0a54ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ec2fe1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555ec2fe1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555ec2fc6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555ec2c760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555ec2c75dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd0a54eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd0a54ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd0a54ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ec2c75cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c (3127 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4asu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4asu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4asu_vv_i32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4asu_vv_i32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4asu_vv_i32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 =
# | ...
# `---data was truncated (10240/26564) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005604d09b215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005604d09af0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005604d09b289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3d2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3d278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3d2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3d271b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005604d0947e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005604d0947c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005604d092cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005604d05dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005604d05dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff3d271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3d271d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3d271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005604d05dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c (3128 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_f16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_f16mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_f16m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_f16m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_i16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_i16mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_i16m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_i16m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, i64 %2, i64 4)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_u16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | ent
# | ...
# `---data was truncated (10240/31706) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641d168e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005641d168b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005641d168e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f98c9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f98c958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f98c9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f98c951b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641d1623e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005641d1623c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005641d1608b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005641d12b80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005641d12b7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f98c951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f98c951d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f98c951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641d12b7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c (3129 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgatherei16_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgatherei16_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgatherei16_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i16> %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vrgatherei16_vv_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, <vscale x 32 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 32 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 32 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i16> %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgatherei16_vv_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgatherei16_vv_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, pt
# | ...
# `---data was truncated (10240/32701) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055610f38915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055610f3860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055610f38989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff3c1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff3c158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff3c1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff3c151b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055610f31ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055610f31ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055610f303b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055610efb30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055610efb2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff3c151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff3c151d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff3c151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055610efb2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c (3130 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vv_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfle_vf_bf16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(<vscale x 1 x i1>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vv_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfle_vf_bf16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1> %1, <vscale x 2 x bfloat> %2, bfloat %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(<vscale x 2 x i1>, <vscale x 2 x bfloat>, bfloat, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vv_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfle_vf_bf16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load bfloat, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1> %1, <vscale x 4 x bfloat> %2, bfloat %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(<vscale x 4 x i1>, <vscale x 4 x bfloat>, bfloat, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfle_vv_bf16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfle
# | ...
# `---data was truncated (10240/18668) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d238e1b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d238e180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d238e1b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f22eea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22eeaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f22eea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f22eea31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d238db0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d238db0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d238d95b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d238a450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d238a44dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f22eea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22eea330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22eea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d238a44cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c (3131 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, i64 %1, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8
# | ...
# `---data was truncated (10240/12059) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559a0512c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559a051290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559a0512c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f294e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f294e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f294e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f294e51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559a050c1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559a050c1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559a050a6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559a04d560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559a04d55dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f294e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f294e51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f294e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559a04d55cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c (3132 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vv_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vasub_vx_i8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vv_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vasub_vx_i8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vv_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vasub_vx_i8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vv_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vasub_vx_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %op1, i8 noundef signext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i8, ptr %op2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, i64 0, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i8, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vasub_vv_i8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %op2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, al
# | ...
# `---data was truncated (10240/225213) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557dadee515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557dadee20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557dadee589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f122e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f122e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f122e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f122e71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557dade7ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557dade7ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557dade5fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557dadb0f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557dadb0edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f122e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f122e71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f122e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557dadb0ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c (3133 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 %3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e32_v_f32mf2x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 4
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %bstride.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, i64 %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple"
# | ...
# `---data was truncated (10240/35929) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056110040915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005611004060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056110040989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2420249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f24202a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2420249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2420231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056110039ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056110039ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561100383b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005611000330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561100032dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2420232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f24202330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f24202330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561100032cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c (3134 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @
# | ...
# `---data was truncated (10240/60228) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056307da6f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056307da6c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056307da6f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbe9dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbe9dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbe9dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbe9dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056307da04e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056307da04c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056307d9e9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056307d6990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056307d698dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbe9dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbe9dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbe9dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056307d698cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c (3135 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_i8mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_i8mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_i8m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_u8mf8x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8ff_v_u8mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8ff_v_u8mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8ff_v_u8m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8ff_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %m
# | ...
# `---data was truncated (10240/22258) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562b0d15f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562b0d15c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562b0d15f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff374e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff374ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff374e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff374e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562b0d0f4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562b0d0f4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562b0d0d9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562b0cd890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562b0cd88dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff374e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff374e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff374e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562b0cd88cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c (3136 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i8> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs
# | ...
# `---data was truncated (10240/15504) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558fd03a215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558fd039f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558fd03a289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3503a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3503aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3503a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3503a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558fd0337e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558fd0337c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558fd031cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558fcffcc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558fcffcbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3503a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3503a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3503a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558fcffcbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c (3137 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_i8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_i8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_i8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_i8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlsseg8e8_v_u8mf8x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlsseg8e8_v_u8mf4x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlsseg8e8_v_u8mf2x8_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlsseg8e8_v_u8m1x8_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556ce004915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556ce00460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556ce004989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8064d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8064d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8064d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8064d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556cdffdee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556cdffdec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556cdffc3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556cdfc730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556cdfc72dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8064d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8064d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8064d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556cdfc72cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c (3138 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale
# | ...
# `---data was truncated (10240/15707) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056149698715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005614969840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056149698789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f42a1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f42a178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f42a1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f42a171b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056149691ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056149691cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561496901b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005614965b10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005614965b0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f42a171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f42a171d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f42a171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005614965b0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c (3139 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_f32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_f32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_f32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_i32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_i32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_i32m2x4_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e32_v_u32mf2x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e32_v_u32m1x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e32_v_u3
# | ...
# `---data was truncated (10240/11880) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b23d12a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b23d1270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b23d12a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f94a9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f94a9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f94a9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f94a9d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b23d0bfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b23d0bfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b23d0a4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b23cd540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b23cd53dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f94a9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f94a9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f94a9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b23cd53cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c (3140 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vle.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vle.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vle.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <v
# | ...
# `---data was truncated (10240/13125) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005596f53d315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005596f53d00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005596f53d389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff8afa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff8afaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff8afa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff8afa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005596f5368e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005596f5368c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005596f534db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005596f4ffd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005596f4ffcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff8afa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff8afa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff8afa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005596f4ffccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c (3141 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e32_v_f32mf2x7_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e32_v_f32m1x7_tum(<vscale x 2 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 4
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 5)
# |   ret ta
# | ...
# `---data was truncated (10240/32031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b503f1b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b503f180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b503f1b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2e7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2e798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2e7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2e791b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b503eb0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b503eb0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b503e95b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b503b450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b503b44dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc2e791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2e791d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2e791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b503b44cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c (3142 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv
# | ...
# `---data was truncated (10240/47720) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560cb57af15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560cb57ac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560cb57af89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc04c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc04c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc04c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc04c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560cb5744e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560cb5744c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560cb5729b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560cb53d90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560cb53d8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc04c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc04c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc04c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560cb53d8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c (3143 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sle(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = icmp sle i32 %2, %3
# |   %sle.i = zext i1 %4 to i32
# |   ret i32 %sle.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_sleu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = icmp ule i32 %2, %3
# |   %sleu.i = zext i1 %4 to i32
# |   ret i32 %sleu.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_min(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.min.i = call i32 @llvm.smin.i32(i32 %2, i32 %3)
# |   ret i32 %elt.min.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_minu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.min.i = call i32 @llvm.umin.i32(i32 %2, i32 %3)
# |   ret i32 %elt.min.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_max(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.max.i = call i32 @llvm.smax.i32(i32 %2, i32 %3)
# |   ret i32 %elt.max.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_maxu(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %elt.max.i = call i32 @llvm.umax.i32(i32 %2, i32 %3)
# |   ret i32 %elt.max.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exths(i16 noundef signext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i16, align 2
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %a.addr.i, align 2
# |   %1 = load i16, ptr %a.addr.i, align 2
# |   %conv.i = sext i16 %1 to i32
# |   %exths.i = sext i16 %1 to i32
# |   ret i32 %exths.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_exthz(i16 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i16, align 2
# |   %a.addr = alloca i16, align 2
# |   store i16 %a, ptr %a.addr, align 2
# |   %0 = load i16, ptr %a.addr, align 2
# |   store i16 %0, ptr %a.addr.i, align 2
# |   %1 = load i16, ptr %a.addr.i, align 2
# |   %conv.i = zext i16 %1 to i32
# |   %exthz.i = zext i16 %1 to i32
# |   ret i32 %exthz.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbs(i8 noundef signext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i8, align 1
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   store i8 %0, ptr %a.addr.i, align 1
# |   %1 = load i8, ptr %a.addr.i, align 1
# |   %conv.i = sext i8 %1 to i32
# |   %extbs.i = sext i8 %1 to i32
# |   ret i32 %extbs.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_extbz(i8 noundef zeroext %a) #0 {
# | entry:
# |   %a.addr.i = alloca i8, align 1
# |   %a.addr = alloca i8, align 1
# |   store i8 %a, ptr %a.addr, align 1
# |   %0 = load i8, ptr %a.addr, align 1
# |   store i8 %0, ptr %a.addr.i, align 1
# |   %1 = load i8, ptr %a.addr.i, align 1
# |   %conv.i = zext i8 %1 to i32
# |   %extbz.i = zext i8 %1 to i32
# |   ret i32 %extbz.i
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clip(i32 noundef %a) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 0, ptr %b.addr.i, align 4
# |   %1 = load i32, ptr %a.addr.i, align 4
# |   %2 = load i32, ptr %b.addr.i, align 4
# |   %3 = call i32 @llvm.riscv.cv.alu.clip(i32 %1, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_clipu(i32 noundef %a) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %a.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 0, ptr %b.addr.i, align 4
# |   %1 = load i32, ptr %a.addr.i, align 4
# |   %2 = load i32, ptr %b.addr.i, align 4
# |   %3 = call i32 @llvm.riscv.cv.alu.clipu(i32 %1, i32 %2)
# |   ret i32 %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.addN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.adduN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_addRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.addRN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_adduRN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   store i32 %b, ptr %b.addr, align 4
# |   %0 = load i32, ptr %a.addr, align 4
# |   %1 = load i32, ptr %b.addr, align 4
# |   store i32 %0, ptr %a.addr.i, align 4
# |   store i32 %1, ptr %b.addr.i, align 4
# |   store i8 0, ptr %shft.addr.i, align 1
# |   %2 = load i32, ptr %a.addr.i, align 4
# |   %3 = load i32, ptr %b.addr.i, align 4
# |   %4 = load i8, ptr %shft.addr.i, align 1
# |   %conv.i = zext i8 %4 to i32
# |   %5 = call i32 @llvm.riscv.cv.alu.adduRN(i32 %2, i32 %3, i32 %conv.i)
# |   ret i32 %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @test_alu_subN(i32 noundef %a, i32 noundef %b) #0 {
# | entry:
# |   %a.addr.i = alloca i32, align 4
# |   %b.addr.i = alloca i32, align 4
# |   %shft.addr.i = alloca i8, align 1
# |   %a.addr = alloca i32, align 4
# |   %b.addr = alloca i32, align 4
# |   store i32 %a, ptr %a.addr, align 4
# |   st
# | ...
# `---data was truncated (10240/15696) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fba9fa215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fba9f9f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fba9fa289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb282849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb2828a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb282849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb282831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fba9f37e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fba9f37c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fba9f1cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fba9bcc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fba9bcbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb282832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb2828330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb2828330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fba9bcbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c (3144 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_f16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_i16m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e16_v_u16mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_
# | ...
# `---data was truncated (10240/26936) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a37f13415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a37f1310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a37f13489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe675933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe67598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe675933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe67591b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a37f0c9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a37f0c9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a37f0aeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a37ed5e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a37ed5ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe67591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe67591d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe67591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a37ed5dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c (3145 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f16m1x5(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei8_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f32m1x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei8_v_f64m1x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei8_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei8_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560bce3ca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560bce3c70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560bce3ca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa1b8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa1b8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa1b8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa1b8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560bce35fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560bce35fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560bce344b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560bcdff40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560bcdff3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa1b8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa1b8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa1b8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560bcdff3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-neon-endianness.c (3146 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-endianness.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8a-arm-none-eabihf -target-cpu generic -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c -disable-O0-optnone |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8a-arm-none-eabihf -target-cpu generic -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8a-arm-none-eabihf"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_0(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_1(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_2(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 2
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x4_t_lane_3(<4 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <4 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   store <4 x i32> %0, ptr %__s0, align 8
# |   %1 = load <4 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <4 x i32> %1, i32 3
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x2_t_lane_0(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 0
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i32 @int32x2_t_lane_1(<2 x i32> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i32>, align 8
# |   %__ret = alloca i32, align 4
# |   %__s0 = alloca <2 x i32>, align 8
# |   %ref.tmp = alloca i32, align 4
# |   %tmp = alloca i32, align 4
# |   store <2 x i32> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i32>, ptr %a.addr, align 8
# |   store <2 x i32> %0, ptr %__s0, align 8
# |   %1 = load <2 x i32>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i32> %1, i32 1
# |   store i32 %vget_lane, ptr %ref.tmp, align 4
# |   %2 = load i32, ptr %ref.tmp, align 4
# |   store i32 %2, ptr %__ret, align 4
# |   %3 = load i32, ptr %__ret, align 4
# |   store i32 %3, ptr %tmp, align 4
# |   %4 = load i32, ptr %tmp, align 4
# |   ret i32 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @int64x2_t_lane_0(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <2 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   store <2 x i64> %0, ptr %__s0, align 8
# |   %1 = load <2 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i64> %1, i32 0
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @int64x2_t_lane_1(<2 x i64> noundef %a) #0 {
# | entry:
# |   %a.addr = alloca <2 x i64>, align 8
# |   %__ret = alloca i64, align 8
# |   %__s0 = alloca <2 x i64>, align 8
# |   %ref.tmp = alloca i64, align 8
# |   %tmp = alloca i64, align 8
# |   store <2 x i64> %a, ptr %a.addr, align 8
# |   %0 = load <2 x i64>, ptr %a.addr, align 8
# |   store <2 x i64> %0, ptr %__s0, align 8
# |   %1 = load <2 x i64>, ptr %__s0, align 8
# |   %vget_lane = extractelement <2 x i64> %1, i32 1
# |   store i64 %vget_lane, ptr %ref.tmp, align 8
# |   %2 = load i64, ptr %ref.tmp, align 8
# |   store i64 %2, ptr %__ret, align 8
# |   %3 = load i64, ptr %__ret, align 8
# |   store i64 %3, ptr %tmp, align 8
# |   %4 = load i64, ptr %tmp, align 8
# |   ret i64 %4
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp,-thumb-mode" }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"aapcs"}
# | !1 = !{i32 1, !"min_enum_size", i32 4}
# | !2 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !3 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o -
# |  #0 0x000055c2d4d6d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c2d4d6a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c2d4d6d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3a52a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3a52a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3a52a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3a52a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c2d4d02e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c2d4d02c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c2d4ce7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c2d49970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c2d4996dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3a52a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3a52a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3a52a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c2d4996cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c (3147 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfmv_v_f_f16mf4_tu(<vscale x 1 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.i64(<vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfmv_v_f_f16mf2_tu(<vscale x 2 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.i64(<vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfmv_v_f_f16m1_tu(<vscale x 4 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.i64(<vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfmv_v_f_f16m2_tu(<vscale x 8 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.i64(<vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfmv_v_f_f16m4_tu(<vscale x 16 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.i64(<vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfmv_v_f_f16m8_tu(<vscale x 32 x half> %maskedoff, half noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x half>, align 2
# |   %src.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store half %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load half, ptr %src.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.i64(<vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfmv_v_f_f32mf2_tu(<vscale x 1 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfmv_v_f_f32m1_tu(<vscale x 2 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.i64(<vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfmv_v_f_f32m2_tu(<vscale x 4 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.i64(<vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfmv_v_f_f32m4_tu(<vscale x 8 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load float, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.i64(<vscale x 8 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_vfmv_v_f_f32m8_tu(<vscale x 16 x float> %maskedoff, float noundef %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x float>, align 4
# |   %src.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store float %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr
# | ...
# `---data was truncated (10240/29319) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a0e78b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a0e78ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a0e78b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbfe0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbfe038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbfe0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbfe031b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a0e7846e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a0e7846c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a0e782bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a0e74db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a0e74dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbfe031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbfe031d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbfe031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a0e74dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c (3148 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d05e76515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d05e7620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d05e76589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efcb2c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efcb2c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efcb2c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efcb2c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d05e6fae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d05e6fac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d05e6dfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d05e38f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d05e38edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efcb2c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efcb2c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efcb2c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d05e38ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c (3149 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tu(<vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vsext_vf4_i32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vsext_vf4_i32m2_tu(<vscale x 4 x i32> %maskedoff, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i32>, align 4
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vsext_vf4_i32m4_tu(<vscale x 8 x i32> %maskedoff, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i32>, align 4
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vsext_vf4_i32m8_tu(<vscale x 16 x i32> %maskedoff, <vscale x 16 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i32>, align 4
# |   %op1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x i32> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsext_vf4_i64m1_tu(<vscale x 1 x i64> %maskedoff, <vscale x 1 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i64>, align 8
# |   %op1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> %0, <vscale x 1 x i16> %1, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsext_vf4_i64m2_tu(<vscale x 2 x i64> %maskedoff, <vscale x 2 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i64>, align 8
# |   %op1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 2 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> %0, <vscale x 2 x i16> %1, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsext_vf4_i64m4_tu(<vscale x 4 x i64> %maskedoff, <vscale x 4 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i64>, align 8
# |   %op1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 4 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsext_vf4_i64m8_tu(<vscale x 8 x i64> %maskedoff, <vscale x 8 x i16> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i64>, align 8
# |   %op1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 8 x i16> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vsext_vf4_i32mf2_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %maskedoff, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i32>, align 4
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %maskedoff.addr, align 4
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %
# | ...
# `---data was truncated (10240/39922) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dc4c19015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dc4c18d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dc4c19089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa426b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa426b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa426b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa426b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dc4c125e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dc4c125c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dc4c10ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dc4bdba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dc4bdb9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa426b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa426b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa426b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dc4bdb9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c (3150 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i8> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i8> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i8> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vluxei8_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i8> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vluxei8_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat> poison, ptr %0, <vscale x 32 x i8> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vluxei8_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vluxei8_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vluxei8_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vluxei8_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vs
# | ...
# `---data was truncated (10240/14201) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056107174c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005610717490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056107174c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f45d3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f45d398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f45d3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f45d391b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610716e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005610716e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005610716c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005610713760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561071375dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f45d391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f45d391d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f45d391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561071375cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c (3151 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055995c32515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055995c3220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055995c32589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c1ea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c1ea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c1ea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c1ea03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055995c2bae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055995c2bac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055995c29fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055995bf4f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055995bf4edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8c1ea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c1ea050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c1ea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055995bf4ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c (3152 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561ef6b9c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561ef6b990f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561ef6b9c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faeb7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faeb7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faeb7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faeb7b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561ef6b31e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561ef6b31c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561ef6b16b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561ef67c60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561ef67c5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faeb7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faeb7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faeb7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561ef67c5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c (3153 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1(ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m2(ptr noundef %base, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m4(ptr noundef %base, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m8(ptr noundef %base, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_i64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m1(ptr noundef %base, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv1i64.p0.i64(<vscale x 1 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m2(ptr noundef %base, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv2i64.p0.i64(<vscale x 2 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m4(ptr noundef %base, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv4i64.p0.i64(<vscale x 4 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_u64m8(ptr noundef %base, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vse.nxv8i64.p0.i64(<vscale x 8 x i64> %1, ptr %0, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vse64_v_f64m1_m(<vscale x 1 x i1> %mask, ptr noundef %base, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %value.addr = alloca <vscale x 1 x double>
# | ...
# `---data was truncated (10240/22898) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056330665715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005633066540f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056330665789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc3b0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc3b058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc3b0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc3b051b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005633065ece2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005633065ecc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005633065d1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005633062810b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563306280dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc3b051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc3b051d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc3b051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563306280cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c (3154 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_f32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_f32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_i32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_i32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e32_v_u32mf2x8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e32_v_u32m1x8_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d0b576a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d0b57670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d0b576a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5321905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f532195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5321905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f53218ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d0b56ffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d0b56ffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d0b56e4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d0b53940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d0b5393dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f53218eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53218ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53218ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d0b5393cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c (3155 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_i8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_i8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_i8mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e8ff_v_i8m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vlseg8e8ff_v_u8mf8x8_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e8ff_v_u8mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 3)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e8ff_v_u8mf2
# | ...
# `---data was truncated (10240/54694) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557b7bcce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557b7bccb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557b7bcce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2257049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f22570a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2257049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2257031507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557b7bc63e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557b7bc63c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557b7bc48b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557b7b8f80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557b7b8f7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2257032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f22570330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f22570330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557b7b8f7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c (3156 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %2, ptr %0, <vscale x 1 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2(ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %2, ptr %0, <vscale x 2 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1(ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 4 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat> %2, ptr %0, <vscale x 4 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m2(ptr noundef %rs1, <vscale x 8 x i16> %rs2, <vscale x 8 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 8 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat> %2, ptr %0, <vscale x 8 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m4(ptr noundef %rs1, <vscale x 16 x i16> %rs2, <vscale x 16 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 16 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat> %2, ptr %0, <vscale x 16 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m8(ptr noundef %rs1, <vscale x 32 x i16> %rs2, <vscale x 32 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 32 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 32 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 32 x i16>, ptr %rs2.addr, align 2
# |   %2 = load <vscale x 32 x bfloat>, ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat> %2, ptr %0, <vscale x 32 x i16> %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, <vscale x 1 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 1 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 1 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat> %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, <vscale x 2 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store <vscale x 2 x bfloat> %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load <vscale x 2 x bfloat>, ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat> %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxei16_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, <vscale x 4 x bfloat> %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vsca
# | ...
# `---data was truncated (10240/15622) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cbec29b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cbec2980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cbec29b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcd0ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcd0eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcd0ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcd0ec31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbec230e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cbec230c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cbec215b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cbebec50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cbebec4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcd0ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcd0ec330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcd0ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbebec4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c (3157 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vv_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vv_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vv_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vv_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vv_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>
# | ...
# `---data was truncated (10240/26512) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564890bb115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564890bae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564890bb189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f736a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f736a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f736a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f736a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564890b46e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564890b46c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564890b2bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005648907db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005648907dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f736a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f736a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f736a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005648907dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c (3158 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfeq_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfeq_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfeq_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfeq_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwi
# | ...
# `---data was truncated (10240/44369) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557ba5e5715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557ba5e540f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557ba5e5789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1598e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1598ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1598e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1598e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557ba5dece2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557ba5decc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557ba5dd1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557ba5a810b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557ba5a80dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1598e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1598e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1598e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557ba5a80cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c (3159 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store tar
# | ...
# `---data was truncated (10240/30818) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056374d27815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056374d2750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056374d27889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0efb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0efb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0efb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0efb11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056374d20de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056374d20dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056374d1f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056374cea20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056374cea1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0efb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0efb11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0efb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056374cea1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c (3160 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei32_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei32_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei32_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i32> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056374333c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005637433390f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056374333c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd977d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd977d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd977d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd977d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005637432d1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005637432d1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005637432b6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563742f660b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563742f65dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd977d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd977d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd977d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563742f65cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c (3161 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c -o -    -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c"
# | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
# | target triple = "riscv32"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local float @test_fcvt_s_bf16(bfloat noundef %bf) #0 {
# | entry:
# |   %bf.addr = alloca bfloat, align 2
# |   store bfloat %bf, ptr %bf.addr, align 2
# |   %0 = load bfloat, ptr %bf.addr, align 2
# |   %1 = fpext bfloat %0 to float
# |   ret float %1
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local bfloat @test_fcvt_bf16_s(float noundef %sf) #0 {
# | entry:
# |   %sf.addr = alloca float, align 4
# |   store float %sf, ptr %sf.addr, align 4
# |   %0 = load float, ptr %sf.addr, align 4
# |   %1 = fptrunc float %0 to bfloat
# |   ret bfloat %1
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+f,+i,+xandesbfhcvt,+zicsr" }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"ilp32f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555a8108d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555a8108a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555a8108d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8b34849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8b348a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8b34849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8b34831507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555a81022e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555a81022c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555a81007b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555a80cb70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555a80cb6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8b34832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8b348330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8b348330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555a80cb6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c (3162 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_sf_vfwmacc_4x4x4_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(<vscale x 1 x float>, <vscale x 4 x bfloat>, <vscale x 1 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_sf_vfwmacc_4x4x4_f32m1(<vscale x 2 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(<vscale x 2 x float>, <vscale x 4 x bfloat>, <vscale x 2 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_sf_vfwmacc_4x4x4_f32m2(<vscale x 4 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(<vscale x 4 x float>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_sf_vfwmacc_4x4x4_f32m4(<vscale x 8 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(<vscale x 8 x float>, <vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x float> @test_sf_vfwmacc_4x4x4_f32m8(<vscale x 16 x float> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x float>, align 4
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(<vscale x 16 x float>, <vscale x 4 x bfloat>, <vscale x 16 x bfloat>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562db7e1d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562db7e1a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562db7e1d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3be1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3be14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3be1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3be1431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562db7db2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562db7db2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562db7d97b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562db7a470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562db7a46dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3be1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3be14330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3be14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562db7a46cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c (3163 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_f64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_i64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg7e64_v_u64m1x7_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed6093115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ed6092e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ed6093189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f262b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f262b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f262b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f262b91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed608c6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ed608c6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ed608abb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ed6055b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ed6055add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f262b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f262b91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f262b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed6055acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c (3164 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmandn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmandn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmandn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmandn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmandn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmandn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmandn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmandn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmandn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmandn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmandn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmandn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmandn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e1d5c9415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e1d5c910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e1d5c9489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdee8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdee80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdee8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdee8031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e1d5c29e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e1d5c29c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e1d5c0eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e1d58be0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e1d58bddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdee8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdee80330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdee80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e1d58bdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c (3165 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone    -target-feature +zve64x    -target-feature +zvfbfmin    -target-feature +experimental-zvzip    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 2 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 4 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 8 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 16 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 32 x bfloat> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005652cee7b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005652cee780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005652cee7b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1c0a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1c0a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1c0a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1c0a431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005652cee10e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005652cee10c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005652cedf5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005652ceaa50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005652ceaa4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1c0a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1c0a4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1c0a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005652ceaa4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c (3166 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vloxseg4ei64_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vloxseg4ei64_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vloxseg4ei64_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vloxseg4ei64_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005595d3de115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005595d3dde0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005595d3de189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f12b861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f12b86725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f12b861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f12b8603507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005595d3d76e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005595d3d76c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005595d3d5bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005595d3a0b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005595d3a0add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f12b8604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f12b86050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f12b86050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005595d3a0acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c (3167 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlsseg5e16_v_f16mf4x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.v
# | ...
# `---data was truncated (10240/20439) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c36b36115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c36b35e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c36b36189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8ff6b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8ff6b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8ff6b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8ff6aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c36b2f6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c36b2f6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c36b2dbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c36af8b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c36af8add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8ff6aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8ff6aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8ff6aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c36af8acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c (3168 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_bf16mf4_b64(<vscale x 1 x bfloat> %op1, <vscale x 1 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_bf16mf4_b64(<vscale x 1 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_bf16mf2_b32(<vscale x 2 x bfloat> %op1, <vscale x 2 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_bf16mf2_b32(<vscale x 2 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_bf16m1_b16(<vscale x 4 x bfloat> %op1, <vscale x 4 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_bf16m1_b16(<vscale x 4 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_bf16m2_b8(<vscale x 8 x bfloat> %op1, <vscale x 8 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vf_bf16m2_b8(<vscale x 8 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vv_bf16m4_b4(<vscale x 16 x bfloat> %op1, <vscale x 16 x bfloat> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store <vscale x 16 x bfloat> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmfgt_vf_bf16m4_b4(<vscale x 16 x bfloat> %op1, bfloat noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op2.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store bfloat %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load bfloat, ptr %op2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, bfloat %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmfgt_vv_bf16m8_b2(<vscale x 32 x bfloat> %op1, <vscale x 3
# | ...
# `---data was truncated (10240/27794) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c7be3a015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c7be39d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c7be3a089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facc4705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facc475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facc4705a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facc46ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c7be335e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c7be335c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c7be31ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c7bdfca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c7bdfc9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007facc46eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facc46ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facc46ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c7bdfc9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c (3169 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ce0701f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ce0701c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ce0701f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb109049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1090a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb109049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb109031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ce06fb4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ce06fb4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ce06f99b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ce06c490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ce06c48dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb109032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1090330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1090330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ce06c48cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c (3170 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmmv_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmmv_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmmv_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmmv_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmmv_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmmv_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmmv_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561b7b67315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561b7b6700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561b7b67389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007faa26449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007faa264a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007faa26449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007faa26431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561b7b608e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561b7b608c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561b7b5edb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561b7b29d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561b7b29cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007faa26432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007faa264330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007faa264330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561b7b29ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c (3171 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret <vscale x 64 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret <vscale x 32 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret <vscale x 16 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret <vscale x 8 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret <vscale x 4 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsif_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret <vscale x 2 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsif_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret <vscale x 1 x i1> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsif_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> poison, <vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsif_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> poison, <vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsif_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> poison, <vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsif_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> poison, <vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsif_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> poison, <vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback n
# | ...
# `---data was truncated (10240/13031) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e0e29dd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e0e29da0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e0e29dd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0eb9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0eb998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0eb9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0eb991b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e0e2972e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e0e2972c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e0e2957b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e0e26070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e0e2606dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0eb991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0eb991d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0eb991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e0e2606cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c (3172 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb001fa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fb001f70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fb001fa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc9d081bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc9d08725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc9d081ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc9d0803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb0018fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fb0018fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fb00174b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055faffe240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055faffe23dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc9d0804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc9d08050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc9d08050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055faffe23cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c (3173 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmxor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmxor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmxor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmxor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmxor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmxor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmxor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562c663a715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562c663a40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562c663a789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7047c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7047ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7047c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7047c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562c6633ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562c6633cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562c66321b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562c65fd10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562c65fd0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7047c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7047c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7047c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562c65fd0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c (3174 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vle16ff_v_bf16mf4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat> poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 1 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 1 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(<vscale x 1 x bfloat>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vle16ff_v_bf16mf2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat> poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 2 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 2 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 2 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(<vscale x 2 x bfloat>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vle16ff_v_bf16m1_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0(<vscale x 4 x bfloat> poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 4 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 4 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 4 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0(<vscale x 4 x bfloat>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vle16ff_v_bf16m2_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64.p0(<vscale x 8 x bfloat> poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 8 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 8 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 8 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64.p0(<vscale x 8 x bfloat>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vle16ff_v_bf16m4_m(<vscale x 16 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 16 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64.p0(<vscale x 16 x bfloat> poison, ptr %1, <vscale x 16 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 16 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 16 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 16 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64.p0(<vscale x 16 x bfloat>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vle16ff_v_bf16m8_m(<vscale x 32 x i1> %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 32 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64.p0(<vscale x 32 x bfloat> poison, ptr %1, <vscale x 32 x i1> %0, i64 %3, i64 3)
# |   %5 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 0
# |   %6 = extractvalue { <vscale x 32 x bfloat>, i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret <vscale x 32 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { <vscale x 32 x bfloat>, i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64.p0(<vscale x 32 x bfloat>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e3d1d3d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e3d1d3a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e3d1d3d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa202933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa20298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa202933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa20291b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e3d1cd2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e3d1cd2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e3d1cb7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e3d19670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e3d1966dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa20291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa20291d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa20291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e3d1966cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c (3175 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlsseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlsseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %0, i64 %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlsseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlsseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 
# | ...
# `---data was truncated (10240/19037) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005631a163a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005631a16370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005631a163a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7985d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7985d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7985d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7985d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005631a15cfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005631a15cfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005631a15b4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005631a12640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005631a1263dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7985d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7985d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7985d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005631a1263cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c (3176 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotu_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotu_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotu_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotu_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotu_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotu_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotu_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotu_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv
# | ...
# `---data was truncated (10240/25519) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559b48e4115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559b48e3e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559b48e4189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8c6d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f8c6d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8c6d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f8c6d431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559b48dd6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559b48dd6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559b48dbbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559b48a6b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559b48a6add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f8c6d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f8c6d4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f8c6d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559b48a6acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c (3177 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | 
# | ...
# `---data was truncated (10240/11938) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005561f406615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005561f40630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005561f406689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2d4ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2d4ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2d4ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2d4ad1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005561f3ffbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005561f3ffbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005561f3fe0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005561f3c900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005561f3c8fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2d4ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2d4ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2d4ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005561f3c8fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c (3178 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_m(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_m(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_m(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 3)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | ...
# `---data was truncated (10240/13625) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed30c9f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ed30c9c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ed30c9f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7136449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f71364a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7136449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7136431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed30c34e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ed30c34c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ed30c19b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ed308c90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ed308c8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7136432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f71364330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f71364330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed308c8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c (3179 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tu(<vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x half>, align 2
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> %0, <vscale x 1 x float> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_tu(<vscale x 2 x half> %maskedoff, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x half>, align 2
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1_tu(<vscale x 4 x half> %maskedoff, <vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x half>, align 2
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2_tu(<vscale x 8 x half> %maskedoff, <vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x half>, align 2
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4_tu(<vscale x 16 x half> %maskedoff, <vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x half>, align 2
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2_tu(<vscale x 1 x float> %maskedoff, <vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x float>, align 4
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2_tu(<vscale x 4 x float> %maskedoff, <vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x float>, align 4
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4_tu(<vscale x 8 x float> %maskedoff, <vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x float>, align 4
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x half> %maskedoff, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, alig
# | ...
# `---data was truncated (10240/41926) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564e3813a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564e381370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564e3813a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f07e3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f07e358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f07e3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f07e351b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564e380cfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564e380cfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564e380b4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564e37d640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564e37d63dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f07e351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f07e351d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f07e351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564e37d63cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c (3180 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvdot -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i32> @test_nds_vd4dotsu_vv_i32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 4 x i8> %vs1, <vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32>, <vscale x 4 x i8>, <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i32> @test_nds_vd4dotsu_vv_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i32> @test_nds_vd4dotsu_vv_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 16 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 16 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i32> @test_nds_vd4dotsu_vv_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 32 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 32 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 32 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 32 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i32> @test_nds_vd4dotsu_vv_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 64 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 64 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 64 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 64 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i64> @test_nds_vd4dotsu_vv_i64m1_tu(<vscale x 1 x i64> %vd, <vscale x 4 x i16> %vs1, <vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(<vscale x 1 x i64>, <vscale x 4 x i16>, <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i64> @test_nds_vd4dotsu_vv_i64m2_tu(<vscale x 2 x i64> %vd, <vscale x 8 x i16> %vs1, <vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(<vscale x 2 x i64>, <vscale x 8 x i16>, <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i64> @test_nds_vd4dotsu_vv_i64m4_tu(<vscale x 4 x i64> %vd, <vscale x 16 x i16> %vs1, <vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 16 x i16>, align 2
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 16 x i16> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 16 x i16>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @ll
# | ...
# `---data was truncated (10240/47728) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bca6e1815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bca6e150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bca6e1889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2de0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2de00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2de0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2de0031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bca6dade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bca6dadc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bca6d92b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bca6a420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bca6a41dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2de0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2de00330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2de00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bca6a41cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c (3181 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f16m1x8(ptr noundef %base, <vscale x 4 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei32_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f32m1x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei32_v_f64m1x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei32_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei32_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i32> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i32> %bindex, ptr %bindex.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %bindex.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555e9ae8a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555e9ae870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555e9ae8a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc58f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc58f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc58f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc58f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555e9ae1fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555e9ae1fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555e9ae04b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555e9aab40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555e9aab3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc58f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc58f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc58f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555e9aab3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c (3182 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zvfhmin -target-feature +zvfbfmin    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.sf.vste16.i64(i64, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local void @test_sf_vste16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %tss.addr = alloca i64, align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store i64 %tss, ptr %tss.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %tss.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560bc3e7f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560bc3e7c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560bc3e7f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f32e9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f32e9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f32e9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f32e9a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560bc3e14e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560bc3e14c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560bc3df9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560bc3aa90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560bc3aa8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f32e9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f32e9a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f32e9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560bc3aa8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c (3183 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfabs_v_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfabs_v_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfabs_v_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfabs_v_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfabs_v_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfabs_v_bf16m1_tum(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store
# | ...
# `---data was truncated (10240/29296) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bb35f5015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bb35f4d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bb35f5089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb909249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb9092a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb909249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb909231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bb35ee5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bb35ee5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bb35ecab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bb35b7a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bb35b79dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb909232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb9092330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb9092330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bb35b79cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c (3184 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlseg3e16ff_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlseg3e16ff_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlseg3e16ff_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlseg3e16ff_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { ta
# | ...
# `---data was truncated (10240/27858) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000565280f7c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000565280f790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000565280f7c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5622133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f562218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5622133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f562211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000565280f11e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000565280f11c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000565280ef6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000565280ba60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000565280ba5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f562211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f562211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f562211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000565280ba5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c (3185 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei8_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei8_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei8_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005644bcede15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005644bcedb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005644bcede89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f142a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f142a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f142a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f142a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005644bce73e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005644bce73c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005644bce58b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005644bcb080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005644bcb07dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f142a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f142a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f142a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005644bcb07cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c (3186 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlsseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlsseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlsseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlsseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlsseg2e16_v_i16m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.r
# | ...
# `---data was truncated (10240/33423) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605bafa415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005605bafa10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005605bafa489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96b7905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96b795c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96b7905a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96b78ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605baf39e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005605baf39c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005605baf1eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005605babce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005605babcddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f96b78eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96b78ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96b78ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605babcdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c (3187 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i8> @test_vcpop_v_u8mf8(<vscale x 1 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vcpopv.nxv1i8.i64(<vscale x 1 x i8>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i8> @test_vcpop_v_u8mf4(<vscale x 2 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vcpopv.nxv2i8.i64(<vscale x 2 x i8>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i8> @test_vcpop_v_u8mf2(<vscale x 4 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vcpopv.nxv4i8.i64(<vscale x 4 x i8>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i8> @test_vcpop_v_u8m1(<vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vcpopv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i8> @test_vcpop_v_u8m2(<vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %0, i64 %1)
# |   ret <vscale x 16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vcpopv.nxv16i8.i64(<vscale x 16 x i8>, <vscale x 16 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i8> @test_vcpop_v_u8m4(<vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %0, i64 %1)
# |   ret <vscale x 32 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vcpopv.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 64 x i8> @test_vcpop_v_u8m8(<vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %0, i64 %1)
# |   ret <vscale x 64 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i8> @llvm.riscv.vcpopv.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i16> @test_vcpop_v_u16mf4(<vscale x 1 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %0, i64 %1)
# |   ret <vscale x 1 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i16> @llvm.riscv.vcpopv.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i16> @test_vcpop_v_u16mf2(<vscale x 2 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %0, i64 %1)
# |   ret <vscale x 2 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i16> @llvm.riscv.vcpopv.nxv2i16.i64(<vscale x 2 x i16>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i16> @test_vcpop_v_u16m1(<vscale x 4 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %0, i64 %1)
# |   ret <vscale x 4 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vcpopv.nxv4i16.i64(<vscale x 4 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i16> @test_vcpop_v_u16m2(<vscale x 8 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %0, i64 %1)
# |   ret <vscale x 8 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i16> @llvm.riscv.vcpopv.nxv8i16.i64(<vscale x 8 x i16>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i16> @test_vcpop_v_u16m4(<vscale x 16 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %0, i64 %1)
# |   ret <vscale x 16 x i16> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i16> @llvm.riscv.vcpopv.nxv16i16.i64(<vscale x 16 x i16>, <vscale x 16 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 32 x i16> @test_vcpop_v_u16m8(<vscale x 32 x i16> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i16> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i16>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x i16> @llvm.riscv.vcpopv.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %0, i64 %1)
# |   ret <vscale x 32 x i16> %2
# | 
# | ...
# `---data was truncated (10240/40891) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568be03215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005568be02f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005568be03289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9fea733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9fea78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9fea733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9fea71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568bdfc7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005568bdfc7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005568bdfacb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005568bdc5c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005568bdc5bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9fea71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9fea71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9fea71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568bdc5bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c (3188 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_f16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_f16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_f16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_i16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e16ff_v_i16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e16ff_v_i16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e16ff_v_u16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %base.addr = alloca 
# | ...
# `---data was truncated (10240/60551) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000557e78f9715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000557e78f940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000557e78f9789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd42cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd42cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd42cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd42cd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557e78f2ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557e78f2cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557e78f11b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557e78bc10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557e78bc0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd42cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd42cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd42cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557e78bc0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c (3189 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4(<vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1)
# |   ret <vscale x 1 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2(<vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1)
# |   ret <vscale x 2 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1(<vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1)
# |   ret <vscale x 4 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2(<vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1)
# |   ret <vscale x 8 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4(<vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1)
# |   ret <vscale x 16 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfrsqrt7_v_bf16m8(<vscale x 32 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %op1.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1)
# |   ret <vscale x 32 x bfloat> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfrsqrt7_v_bf16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfrsqrt7_v_bf16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfrsqrt7_v_bf16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfrsqrt7_v_bf16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %op1.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfrsqrt7_v_bf16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x bfloat> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x bfloat> %op1, ptr %op1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16
# | ...
# `---data was truncated (10240/12536) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a5dcf0715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a5dcf040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a5dcf0789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0a10249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0a102a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0a10249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0a10231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a5dce9ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a5dce9cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a5dce81b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a5dcb310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a5dcb30dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0a10232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0a102330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0a102330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a5dcb30cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c (3190 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vlseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vlseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %maskedoff_tuple.addr, align 2
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vlseg7e16_v_u16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ta
# | ...
# `---data was truncated (10240/47488) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055646689b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005564668980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055646689b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5e49f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5e49f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5e49f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5e49eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556466830e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556466830c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556466815b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005564664c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005564664c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5e49eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5e49eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5e49eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005564664c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c (3191 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cbe9f0515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cbe9f020f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cbe9f0589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5932533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f593258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5932533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f593251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cbe9e9ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cbe9e9ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cbe9e7fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cbe9b2f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cbe9b2edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f593251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f593251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f593251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cbe9b2ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c (3192 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlsseg4e16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlsseg4e16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tup
# | ...
# `---data was truncated (10240/11051) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fb4286315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fb428600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fb4286389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff990849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff9908a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff990849a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff990831507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fb427f8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fb427f8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fb427ddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fb4248d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fb4248cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff990832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff9908330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff9908330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fb4248ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c (3193 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vv_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, <vscale x 1 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 1 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 1 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmfgt_vf_f16mf4_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1> %1, <vscale x 1 x half> %2, half %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(<vscale x 1 x i1>, <vscale x 1 x half>, half, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vv_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, <vscale x 2 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 2 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 2 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmfgt_vf_f16mf2_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1> %1, <vscale x 2 x half> %2, half %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(<vscale x 2 x i1>, <vscale x 2 x half>, half, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vv_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, <vscale x 4 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 4 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 4 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmfgt_vf_f16m1_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x half> %op1, half noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x half>, align 2
# |   %op2.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x half> %op1, ptr %op1.addr, align 2
# |   store half %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x half>, ptr %op1.addr, align 2
# |   %3 = load half, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1> %1, <vscale x 4 x half> %2, half %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(<vscale x 4 x i1>, <vscale x 4 x half>, half, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmfgt_vv_f16m2_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x half>, align 2
# |   %op2.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x half> %op1, ptr %op1.addr, align 2
# |   store <vscale x 8 x half> %op2, ptr %op2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x half>, ptr %op1.addr, align 2
# |   %3 = load <vscale x 8 x half>, ptr %op2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x i1> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willr
# | ...
# `---data was truncated (10240/44361) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e53bc8d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e53bc8a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e53bc8d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3fc3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f3fc3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3fc3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f3fc3a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e53bc22e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e53bc22c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e53bc07b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e53b8b70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e53b8b6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f3fc3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f3fc3a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f3fc3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e53b8b6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c (3194 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16>, <vscale x 1 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16>, <vscale x 2 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8mf2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>, <vscale x 4 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m1_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16>, <vscale x 8 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m2_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16>, <vscale x 16 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m4_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16>, <vscale x 32 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vwredsumu_vs_u8m8_u16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16>, <vscale x 64 x i8>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vwredsumu_vs_u16mf4_u32m1_tu(<vscale x 2 x i32> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 2 x i32> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i32>, align 4
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x i32> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x i32>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i
# | ...
# `---data was truncated (10240/51303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559977b7a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559977b770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559977b7a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1ce8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1ce818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1ce8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1ce811b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559977b0fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559977b0fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559977af4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005599777a40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005599777a3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1ce811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1ce811d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1ce811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599777a3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c (3195 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, <vscale x 1 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 1 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 1 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vrgather_vx_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, <vscale x 2 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 2 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 2 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vrgather_vx_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, <vscale x 4 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 4 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vrgather_vx_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, <vscale x 8 x i16> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store <vscale x 8 x i16> %vs1, ptr %vs1.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load <vscale x 8 x i16>, ptr %vs1.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vrgather_vx_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vrgather_vv_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, <vscale x 16 x i16
# | ...
# `---data was truncated (10240/62095) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005578dd2ed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005578dd2ea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005578dd2ed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2b1b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2b1b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2b1b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2b1b51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005578dd282e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005578dd282c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005578dd267b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005578dcf170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005578dcf16dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2b1b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2b1b51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2b1b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005578dcf16cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c (3196 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16_v_bf16mf4x8_tumu(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", 
# | ...
# `---data was truncated (10240/16800) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005599c4e9815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005599c4e950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005599c4e9889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4955449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f49554a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4955449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4955431507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005599c4e2de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005599c4e2dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005599c4e12b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005599c4ac20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005599c4ac1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4955432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f49554330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f49554330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005599c4ac1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminq.c (3197 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = icmp ule <16 x i8> %0, %1
# |   %3 = select <16 x i1> %2, <16 x i8> %0, <16 x i8> %1
# |   ret <16 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = icmp sle <8 x i16> %0, %1
# |   %3 = select <8 x i1> %2, <8 x i16> %0, <8 x i16> %1
# |   ret <8 x i16> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = icmp ule <4 x i32> %0, %1
# |   %3 = select <4 x i1> %2, <4 x i32> %0, <4 x i32> %1
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <16 x i8>, align 8
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %inactive, ptr %inactive.addr, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = load <16 x i8>, ptr %inactive.addr, align 8
# |   %6 = call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5)
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %6 = call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5)
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %6 = call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef)
# |   ret <4 x i32> %5
# | }
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564d9cdd915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564d9cdd60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564d9cdd989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2514f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2514f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2514f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2514f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564d9cd6ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564d9cd6ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564d9cd53b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564d9ca030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564d9ca02dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2514f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2514f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2514f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564d9ca02cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c (3198 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i8> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei8_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei8_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei8_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i8> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %rs2, ptr %rs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i8>, ptr %rs2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>
# | ...
# `---data was truncated (10240/19492) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ba89f315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555ba89f00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555ba89f389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5349333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f534938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5349333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f534931b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ba8988e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555ba8988c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555ba896db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555ba861d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555ba861cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f534931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f534931d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f534931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ba861ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c (3199 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   s
# | ...
# `---data was truncated (10240/30826) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005593f6ac215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005593f6abf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005593f6ac289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb241933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb24198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb241933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb24191b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005593f6a57e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005593f6a57c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005593f6a3cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005593f66ec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005593f66ebdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb24191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb24191d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb24191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005593f66ebcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c (3200 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32ff_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32ff_v_u32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 6), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563055e0b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563055e080f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563055e0b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb166649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb1666a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb166649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb166631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563055da0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563055da0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563055d85b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563055a350b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563055a34dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb166632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb1666330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb1666330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563055a34cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c (3201 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +xandesvsintload -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_m(<vscale x 16 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr %1, <vscale x 16 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), <vscale x 16 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_m(<vscale x 32 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr %1, <vscale x 32 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), <vscale x 32 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_m(<vscale x 64 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr %1, <vscale x 64 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), <vscale x 64 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesvsintload,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvsintload5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c82915315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c8291500f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c82915389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee60733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee6078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee60733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee6071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c8290e8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c8290e8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c8290cdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c828d7d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c828d7cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fee6071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee6071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee6071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c828d7ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c (3202 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, pt
# | ...
# `---data was truncated (10240/52733) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d44cc215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562d44cbf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562d44cc289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7ed2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7ed2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7ed2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7ed2b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d44c57e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562d44c57c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562d44c3cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562d448ec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562d448ebdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7ed2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7ed2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7ed2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d448ebcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c (3203 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b78f1a415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b78f1a10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b78f1a489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f10f2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f10f2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f10f2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f10f2e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b78f139e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b78f139c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b78f11eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b78edce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b78edcddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f10f2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f10f2e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f10f2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b78edcdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c (3204 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vluxseg4ei16_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vluxseg4ei16_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vluxseg4ei16_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vluxseg4ei16_v_bf16m2x4_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee90de815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ee90de50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ee90de889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fec87d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fec87d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fec87d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fec87d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee90d7de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ee90d7dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ee90d62b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ee90a120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ee90a11dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fec87d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fec87d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fec87d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee90a11cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c (3205 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5(ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %2, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsseg5e16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562599a0015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005625999fd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562599a0089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f00f3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f00f34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f00f3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f00f3431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562599995e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562599995c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056259997ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056259962a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562599629dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f00f3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f00f34330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f00f34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562599629cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c (3206 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %3, i64 6)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %6
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64ff_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 6)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 5), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vsca
# | ...
# `---data was truncated (10240/20895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ab255e715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ab255e40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ab255e789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1120249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f11202a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1120249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1120231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ab2557ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ab2557cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ab25561b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ab252110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ab25210dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1120232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f11202330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f11202330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ab25210cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c (3207 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f16m1x8(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f32m1x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_f64m1x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vluxseg8ei16_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005654be3de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005654be3db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005654be3de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd2f6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd2f6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd2f6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd2f6f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005654be373e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005654be373c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005654be358b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005654be0080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005654be007dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd2f6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd2f6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd2f6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005654be007cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c (3208 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm,
# | ...
# `---data was truncated (10240/11871) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556074a0c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556074a090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556074a0c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6dda649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6dda6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6dda649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6dda631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005560749a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005560749a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556074986b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005560746360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556074635dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6dda632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6dda6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6dda6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556074635cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c (3209 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d  -target-feature +f -target-feature +d -disable-O0-optnone  -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64-none-linux-gnu"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @add_i8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %add = add <32 x i8> %0, %1
# |   store <32 x i8> %add, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8>, <32 x i8>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @add_i16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %add = add <16 x i16> %0, %1
# |   store <16 x i16> %add, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16>, <16 x i16>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @add_i32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %add = add <8 x i32> %0, %1
# |   store <8 x i32> %add, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @add_i64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %add = add <4 x i64> %0, %1
# |   store <4 x i64> %add, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64>, <4 x i64>, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 8 x i8> @add_u8(<vscale x 8 x i8> noundef %a.coerce, <vscale x 8 x i8> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <32 x i8>, align 8
# |   %a.addr = alloca <32 x i8>, align 8
# |   %b.addr = alloca <32 x i8>, align 8
# |   %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %a.coerce, i64 0)
# |   %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(<vscale x 8 x i8> %b.coerce, i64 0)
# |   store <32 x i8> %a, ptr %a.addr, align 8
# |   store <32 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <32 x i8>, ptr %a.addr, align 8
# |   %1 = load <32 x i8>, ptr %b.addr, align 8
# |   %add = add <32 x i8> %0, %1
# |   store <32 x i8> %add, ptr %retval, align 8
# |   %2 = load <32 x i8>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v32i8(<vscale x 8 x i8> poison, <32 x i8> %2, i64 0)
# |   ret <vscale x 8 x i8> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 4 x i16> @add_u16(<vscale x 4 x i16> noundef %a.coerce, <vscale x 4 x i16> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <16 x i16>, align 8
# |   %a.addr = alloca <16 x i16>, align 8
# |   %b.addr = alloca <16 x i16>, align 8
# |   %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %a.coerce, i64 0)
# |   %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(<vscale x 4 x i16> %b.coerce, i64 0)
# |   store <16 x i16> %a, ptr %a.addr, align 8
# |   store <16 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i16>, ptr %a.addr, align 8
# |   %1 = load <16 x i16>, ptr %b.addr, align 8
# |   %add = add <16 x i16> %0, %1
# |   store <16 x i16> %add, ptr %retval, align 8
# |   %2 = load <16 x i16>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v16i16(<vscale x 4 x i16> poison, <16 x i16> %2, i64 0)
# |   ret <vscale x 4 x i16> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x i32> @add_u32(<vscale x 2 x i32> noundef %a.coerce, <vscale x 2 x i32> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x i32>, align 8
# |   %a.addr = alloca <8 x i32>, align 8
# |   %b.addr = alloca <8 x i32>, align 8
# |   %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %a.coerce, i64 0)
# |   %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(<vscale x 2 x i32> %b.coerce, i64 0)
# |   store <8 x i32> %a, ptr %a.addr, align 8
# |   store <8 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i32>, ptr %a.addr, align 8
# |   %1 = load <8 x i32>, ptr %b.addr, align 8
# |   %add = add <8 x i32> %0, %1
# |   store <8 x i32> %add, ptr %retval, align 8
# |   %2 = load <8 x i32>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> poison, <8 x i32> %2, i64 0)
# |   ret <vscale x 2 x i32> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 1 x i64> @add_u64(<vscale x 1 x i64> noundef %a.coerce, <vscale x 1 x i64> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <4 x i64>, align 8
# |   %a.addr = alloca <4 x i64>, align 8
# |   %b.addr = alloca <4 x i64>, align 8
# |   %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %a.coerce, i64 0)
# |   %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(<vscale x 1 x i64> %b.coerce, i64 0)
# |   store <4 x i64> %a, ptr %a.addr, align 8
# |   store <4 x i64> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i64>, ptr %a.addr, align 8
# |   %1 = load <4 x i64>, ptr %b.addr, align 8
# |   %add = add <4 x i64> %0, %1
# |   store <4 x i64> %add, ptr %retval, align 8
# |   %2 = load <4 x i64>, ptr %retval, align 8
# |   %cast.scalable = call <vscale x 1 x i64> @llvm.vector.insert.nxv1i64.v4i64(<vscale x 1 x i64> poison, <4 x i64> %2, i64 0)
# |   ret <vscale x 1 x i64> %cast.scalable
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(4,4)
# | define dso_local <vscale x 2 x float> @add_f32(<vscale x 2 x float> noundef %a.coerce, <vscale x 2 x float> noundef %b.coerce) #0 {
# | entry:
# |   %retval = alloca <8 x float>, align 8
# |   %a.addr = alloca <8 x float>, align 8
# |   %b.addr = alloca <8 x float>, align 8
# |   %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %a.coerce, i64 0)
# |   %b = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32(<vscale x 2 x float> %b.coerce, i64 0)
# |   store <8 x float> %a, ptr %a.addr, align 8
# |   store <8 x float> %b, ptr %b.addr, align 8
# |   %0 = load <8 x float>, ptr %a.addr, align 8
# |   %1 = load <8 x float>, ptr %b.addr, align 8
# |   %add = fadd <8 x float> %0, %1
# |   store <8 x float> %add, ptr %retval, align 8
# |   %2 = load <8 x float>, ptr %retval,
# | ...
# `---data was truncated (10240/145303) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa
# |  #0 0x000055aa4176915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055aa417660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055aa4176989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc1da505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc1da55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc1da505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc1da4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055aa416fee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055aa416fec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055aa416e3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055aa413930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055aa41392dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc1da4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc1da4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc1da4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055aa41392cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c (3210 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf8x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf4x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8mf2x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_u8m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf8x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e8_v_i8mf4x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, pt
# | ...
# `---data was truncated (10240/18980) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005577cef8015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005577cef7d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005577cef8089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc5a3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5a338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc5a3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc5a331b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005577cef15e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005577cef15c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005577ceefab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005577cebaa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005577ceba9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc5a331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5a331d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5a331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005577ceba9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c (3211 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c -o -      -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg      | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c -o - -disable-O0-optnone
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffb(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.ffb.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffzmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.ffzmism.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_ffmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.ffmism.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local i64 @test_flmism(i64 noundef %a, i64 noundef %b) #0 {
# | entry:
# |   %__a.addr.i = alloca i64, align 8
# |   %__b.addr.i = alloca i64, align 8
# |   %a.addr = alloca i64, align 8
# |   %b.addr = alloca i64, align 8
# |   store i64 %a, ptr %a.addr, align 8
# |   store i64 %b, ptr %b.addr, align 8
# |   %0 = load i64, ptr %a.addr, align 8
# |   %1 = load i64, ptr %b.addr, align 8
# |   store i64 %0, ptr %__a.addr.i, align 8
# |   store i64 %1, ptr %__b.addr.i, align 8
# |   %2 = load i64, ptr %__a.addr.i, align 8
# |   %3 = load i64, ptr %__b.addr.i, align 8
# |   %4 = call i64 @llvm.riscv.nds.flmism.i64(i64 %2, i64 %3)
# |   ret i64 %4
# | }
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffb.i64(i64, i64) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffzmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.ffmism.i64(i64, i64) #1
# | 
# | ; Function Attrs: nounwind speculatable memory(none)
# | declare i64 @llvm.riscv.nds.flmism.i64(i64, i64) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesperf" }
# | attributes #1 = { nounwind speculatable memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_xandesperf5p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005573958f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005573958f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005573958f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007febca133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007febca18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007febca133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007febca11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055739588de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055739588dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000557395872b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005573955220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557395521dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007febca11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007febca11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007febca11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557395521cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c (3212 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase    -target-feature +zve64x    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c -o - |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e8w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.sf.vsettnt.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e8w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e8w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e16w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e16w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e16w4(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 3)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e32w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 1)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e32w2(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 2)
# |   ret i64 %1
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local i64 @test_sf_vsettnt_e64w1(i64 noundef %tn) #0 {
# | entry:
# |   %tn.addr = alloca i64, align 8
# |   store i64 %tn, ptr %tn.addr, align 8
# |   %0 = load i64, ptr %tn.addr, align 8
# |   %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 3, i64 1)
# |   ret i64 %1
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005625c457815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005625c45750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005625c457889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa649249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa6492a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa649249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa649231507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005625c450de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005625c450dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005625c44f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005625c41a20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005625c41a1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa649232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa6492330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa6492330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005625c41a1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c (3213 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_f16mf4x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f16mf2x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f16m1x8(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vloxseg8ei64_v_f32mf2x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f32m1x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vloxseg8ei64_v_f64m1x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @test_vloxseg8ei64_v_i8mf8x8(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vloxseg8ei64_v_i8mf4x8(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.
# | ...
# `---data was truncated (10240/62079) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005568c32de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005568c32db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005568c32de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f37c821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f37c82725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f37c821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f37c8203507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005568c3273e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005568c3273c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005568c3258b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005568c2f080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005568c2f07dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f37c8204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f37c82050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f37c82050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005568c2f07cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c (3214 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1_tu(<vscale x 2 x float> %maskedoff, <vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x float>, align 4
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %maskedoff, ptr %maskedoff.addr, align 4
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %maskedoff.addr, align 4
# |   %1 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 7, i64 %3)
# |   ret <vscale x 2 x float> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %maskedoff, ptr %maskedoff.addr, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %maskedoff.addr, align 8
# |   %1 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %2 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 7, i64 %3)
# |   ret <vscale x 1 x double> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1_tu(<vscale x 1 x double> %maskedoff, <vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x double>, align 8
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca 
# | ...
# `---data was truncated (10240/60342) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005557b7a1115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005557b7a0e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005557b7a1189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb082533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb08258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb082533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb08251b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005557b79a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005557b79a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005557b798bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005557b763b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005557b763add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb08251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb08251d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb08251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005557b763acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c (3215 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b    -target-feature +zvbb    -target-feature +zvbc    -target-feature +zvkb    -target-feature +zvkg    -target-feature +zvkned    -target-feature +zvknhb    -target-feature +zvksed    -target-feature +zvksh    -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i32> @test_vsha2cl_vv_u32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 1 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i32> @test_vsha2cl_vv_u32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 2 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i32> @test_vsha2cl_vv_u32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 4 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 8 x i32> @test_vsha2cl_vv_u32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 8 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 8 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 16 x i32> @test_vsha2cl_vv_u32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 16 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store <vscale x 16 x i32> %vs1, ptr %vs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load <vscale x 16 x i32>, ptr %vs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 1 x i64> @test_vsha2cl_vv_u64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 1 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 1 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 2 x i64> @test_vsha2cl_vv_u64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 2 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define dso_local <vscale x 4 x i64> @test_vsha2cl_vv_u64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vs1.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %vd, ptr %vd.addr, align 8
# |   store <vscale x 4 x i64> %vs2, ptr %vs2.addr, align 8
# |   store <vscale x 4 x i64> %vs1, ptr %vs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %vs2.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %vs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(8,1024)
# | define d
# | ...
# `---data was truncated (10240/12208) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055e69d4ff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055e69d4fc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055e69d4ff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6eea249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6eea2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6eea249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6eea231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055e69d494e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055e69d494c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055e69d479b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055e69d1290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055e69d128dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6eea232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6eea2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6eea2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055e69d128cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c (3216 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %0, i64 %2, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_f64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_i64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg5e64_v_u64m1x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %2, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562d2137e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562d2137b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562d2137e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0fee105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0fee15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0fee105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0fee0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562d21313e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562d21313c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562d212f8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562d20fa80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562d20fa7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0fee0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0fee0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0fee0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562d20fa7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c (3217 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, <vscale x 1 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, <vscale x 2 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, <vscale x 4 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 8 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 8 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, <vscale x 8 x i32> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei32_v_bf16mf4x3_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %2, <vscale x 1 x i32> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei32_v_bf16mf2x3_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %2, <vscale x 2 x i32> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.t
# | ...
# `---data was truncated (10240/25825) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638a26ac15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005638a26a90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005638a26ac89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa848f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa848f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa848f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa848f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638a2641e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005638a2641c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005638a2626b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005638a22d60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005638a22d5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa848f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa848f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa848f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638a22d5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c (3218 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vlseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e8_v_u8m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vlseg5e8_v_i8mf8x5_tum(<vscale x 1 x 
# | ...
# `---data was truncated (10240/43119) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005601f791e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005601f791b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005601f791e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc057133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc05718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc057133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc05711b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005601f78b3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005601f78b3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005601f7898b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005601f75480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005601f7547dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc05711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc05711d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc05711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005601f7547cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c (3219 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e16_v_bf16mf4x4_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e16_v_bf16mf2x4_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e16_v_bf16m1x4_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %1, ptr %2, <vscale x 4 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function 
# | ...
# `---data was truncated (10240/22115) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556f4127915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556f412760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556f4127989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa630a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa630aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa630a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa630a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556f4120ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556f4120ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556f411f3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556f40ea30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556f40ea2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa630a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa630a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa630a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556f40ea2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c (3220 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %3, i64 4)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vlseg8e16ff_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vlseg8e16ff_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 0
# |   %7 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } %5, 1
# |   store i64 %7, ptr %3, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e16ff_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load ptr, ptr %new_vl.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call { target("risc
# | ...
# `---data was truncated (10240/21103) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555c3c57f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555c3c57c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555c3c57f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f78e3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f78e3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f78e3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f78e3b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555c3c514e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555c3c514c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555c3c4f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555c3c1a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555c3c1a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f78e3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f78e3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f78e3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555c3c1a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c (3221 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055614a33c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055614a3390f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055614a33c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fad79449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fad794a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fad79449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fad79431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055614a2d1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055614a2d1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055614a2b6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556149f660b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556149f65dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fad79432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fad794330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fad794330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556149f65cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c (3222 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c1fa0415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558c1fa010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558c1fa0489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f4fd4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f4fd4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f4fd4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f4fd4a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c1f999e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558c1f999c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558c1f97eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558c1f62e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558c1f62ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f4fd4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f4fd4a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f4fd4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c1f62dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c (3223 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vlsseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vlsseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vlsseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @test_vlsseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, ptr %1, i64 %2, i64 %3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vlsseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %maskedoff_tuple.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.ris
# | ...
# `---data was truncated (10240/60220) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555922d3d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555922d3a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555922d3d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f28fe649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f28fe6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f28fe649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f28fe631507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555922cd2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555922cd2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555922cb7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005559229670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555922966dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f28fe632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f28fe6330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f28fe6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555922966cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c (3224 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmclr_m_b1(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1.i64(i64 %0)
# |   ret <vscale x 64 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmclr_m_b2(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1.i64(i64 %0)
# |   ret <vscale x 32 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmclr_m_b4(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1.i64(i64 %0)
# |   ret <vscale x 16 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmclr_m_b8(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1.i64(i64 %0)
# |   ret <vscale x 8 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmclr_m_b16(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1.i64(i64 %0)
# |   ret <vscale x 4 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmclr_m_b32(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1.i64(i64 %0)
# |   ret <vscale x 2 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1.i64(i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmclr_m_b64(i64 noundef %vl) #0 {
# | entry:
# |   %vl.addr = alloca i64, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load i64, ptr %vl.addr, align 8
# |   %1 = call <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1.i64(i64 %0)
# |   ret <vscale x 1 x i1> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1.i64(i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed4de3f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ed4de3c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ed4de3f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9da4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9da4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9da4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9da4f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed4ddd4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ed4ddd4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ed4ddb9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ed4da690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ed4da68dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9da4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9da4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9da4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed4da68cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c (3225 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m2x4(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounw
# | ...
# `---data was truncated (10240/12658) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005653914f515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005653914f20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005653914f589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe95c21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe95c2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe95c21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe95c203507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056539148ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056539148ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056539146fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056539111f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056539111edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe95c204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe95c2050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe95c2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056539111ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c (3226 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m1x2(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m2x2(ptr noundef %rs1, <vscale x 8 x i32> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2, ptr %0, <vscale x 8 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 8 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16m4x2(ptr noundef %rs1, <vscale x 16 x i32> %vs2, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2, ptr %0, <vscale x 16 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 16 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i
# | ...
# `---data was truncated (10240/15699) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558f07b7d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558f07b7a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558f07b7d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa543249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa5432a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa543249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa543231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558f07b12e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558f07b12c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558f07af7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558f077a70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558f077a6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa543232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa5432330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa5432330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558f077a6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c (3227 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfncvt_rod_f_f_w_f16m1(<vscale x 4 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> %0, i64 %1)
# |   ret <vscale x 4 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfncvt_rod_f_f_w_f16m2(<vscale x 8 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> %0, i64 %1)
# |   ret <vscale x 8 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfncvt_rod_f_f_w_f16m4(<vscale x 16 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %0, i64 %1)
# |   ret <vscale x 16 x half> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfncvt_rod_f_f_w_f32mf2(<vscale x 1 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> %0, i64 %1)
# |   ret <vscale x 1 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float>, <vscale x 1 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfncvt_rod_f_f_w_f32m1(<vscale x 2 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> %0, i64 %1)
# |   ret <vscale x 2 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float>, <vscale x 2 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfncvt_rod_f_f_w_f32m2(<vscale x 4 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> %0, i64 %1)
# |   ret <vscale x 4 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float>, <vscale x 4 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfncvt_rod_f_f_w_f32m4(<vscale x 8 x double> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x double> %src, ptr %src.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x double>, ptr %src.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> %0, i64 %1)
# |   ret <vscale x 8 x float> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float>, <vscale x 8 x double>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfncvt_rod_f_f_w_f16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half>, <vscale x 1 x float>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfncvt_rod_f_f_w_f16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half>, <vscale x 2 x float>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define 
# | ...
# `---data was truncated (10240/18595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055dda427d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055dda427a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055dda427d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f88fa333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f88fa38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f88fa333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f88fa31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055dda4212e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055dda4212c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055dda41f7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055dda3ea70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055dda3ea6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f88fa31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f88fa31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f88fa31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055dda3ea6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c (3228 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declar
# | ...
# `---data was truncated (10240/44434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005570f1b7c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005570f1b790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005570f1b7c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efca0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efca06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efca0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efca0631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005570f1b11e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005570f1b11c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005570f1af6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005570f17a60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005570f17a5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efca0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efca06330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efca06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005570f17a5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c (3229 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4(<vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2(<vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1(<vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2(<vscale x 8 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vslidedown_vx_bf16m4(<vscale x 16 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vslidedown_vx_bf16m8(<vscale x 32 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %1 = load i64, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> %0, i64 %1, i64 %2, i64 3)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vslidedown.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vslidedown_vx_bf16mf4_m(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vslidedown_vx_bf16mf2_m(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vslidedown_vx_bf16m1_m(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vs2, i64 noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> %1, i64 %2, <vscale x 4 x i1> %0, i64 %3, i64 3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vslidedown_vx_bf16m2_m(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vs2, i64 noundef
# | ...
# `---data was truncated (10240/14333) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005607e48eb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005607e48e80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005607e48eb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1d67c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1d67c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1d67c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1d67c03507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005607e4880e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005607e4880c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005607e4865b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005607e45150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005607e4514dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1d67c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1d67c050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1d67c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005607e4514cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c (3230 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf8_u8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf4_u8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8mf2_u8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m1_u8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m2_u8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m4_u8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredminu_vs_u8m8_u8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf4_u16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16mf2_u16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredminu_vs_u16m1_u16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %sc
# | ...
# `---data was truncated (10240/52741) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558c4453515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558c445320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558c4453589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f90e3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f90e3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f90e3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f90e3c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558c444cae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558c444cac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558c444afb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000558c4415f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000558c4415edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f90e3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f90e3c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f90e3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000558c4415ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c (3231 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmsof_m_b1_mu(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %maskedoff, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %2, <vscale x 64 x i1> %0, i64 %3)
# |   ret <vscale x 64 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmsof_m_b2_mu(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %maskedoff, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %2, <vscale x 32 x i1> %0, i64 %3)
# |   ret <vscale x 32 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmsof_m_b4_mu(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %maskedoff, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %2, <vscale x 16 x i1> %0, i64 %3)
# |   ret <vscale x 16 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsof_m_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %2, <vscale x 8 x i1> %0, i64 %3)
# |   ret <vscale x 8 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsof_m_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %2, <vscale x 4 x i1> %0, i64 %3)
# |   ret <vscale x 4 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsof_m_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %2, <vscale x 2 x i1> %0, i64 %3)
# |   ret <vscale x 2 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsof_m_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1> %1, <vscale x 1 x i1> %2, <vscale x 1 x i1> %0, i64 %3)
# |   ret <vscale x 1 x i1> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056235fcaa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056235fca70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056235fcaa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdaafb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdaafb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdaafb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdaafb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056235fc3fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056235fc3fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056235fc24b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056235f8d40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056235f8d3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdaafb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdaafb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdaafb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056235f8d3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c (3232 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei16_v_bf16mf4x8_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei16_v_bf16mf2x8_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei16_v_bf16m1x8_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nx
# | ...
# `---data was truncated (10240/19590) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f38a75b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f38a7580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f38a75b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f070b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f070b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f070b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f070b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f38a6f0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f38a6f0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f38a6d5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f38a3850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f38a384dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f070b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f070b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f070b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f38a384cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c (3233 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg8e16_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055577c2a015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055577c29d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055577c2a089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0823b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0823b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0823b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0823b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055577c235e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055577c235c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055577c21ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055577beca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055577bec9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0823b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0823b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0823b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055577bec9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c (3234 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1f64.p0.i64(<vscale x 1 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2f64.p0.i64(<vscale x 2 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4f64.p0.i64(<vscale x 4 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x double> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x double> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x double>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8f64.p0.i64(<vscale x 8 x double>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, <vscale x 4 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 4 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv4i64.p0.i64(<vscale x 4 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, <vscale x 8 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 8 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 8 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsse.nxv8i64.p0.i64(<vscale x 8 x i64>, ptr captures(none), i64, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, <vscale x 1 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 1 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv1i64.p0.i64(<vscale x 1 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, <vscale x 2 x i64> %value, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %value.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store <vscale x 2 x i64> %value, ptr %value.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %value.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsse.nxv2i64.p0.i64(<vscale x 2 x i64> %2, ptr %0, i64 %1, i64 %3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | def
# | ...
# `---data was truncated (10240/26764) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f8df5415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564f8df510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564f8df5489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f52e1f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f52e1f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f52e1f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f52e1eed507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f8dee9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564f8dee9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564f8deceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564f8db7e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564f8db7ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f52e1eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f52e1eef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f52e1eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f8db7dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c (3235 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f16m1x5(ptr noundef %base, <vscale x 4 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f32m1x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_f64m1x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei16_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i16> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i16> %bindex, ptr %bindex.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %bindex.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d4af21815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d4af2150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d4af21889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8195133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f819518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8195133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f819511b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d4af1ade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d4af1adc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d4af192b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d4aee420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d4aee41dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f819511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f819511d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f819511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d4aee41cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c (3236 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_u64m1x8_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_f64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vlseg8e64_v_i64m1x8_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 8), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055fd8583915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055fd858360f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055fd8583989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f093a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f093a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f093a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f093a11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055fd857cee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055fd857cec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055fd857b3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055fd854630b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055fd85462dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f093a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f093a11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f093a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055fd85462cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c (3237 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declar
# | ...
# `---data was truncated (10240/44434) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000558544b5115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000558544b4e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000558544b5189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0dddc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0dddca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0dddc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0dddc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558544ae6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558544ae6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558544acbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055854477b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055854477add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0dddc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0dddc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0dddc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055854477acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c (3238 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vv_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 1 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmsltu_vx_u8mf8_b64_mu(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %maskedoff, <vscale x 1 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> %1, <vscale x 1 x i8> %2, i8 %3, <vscale x 1 x i1> %0, i64 %4)
# |   ret <vscale x 1 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1>, <vscale x 1 x i8>, i8, <vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vv_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 2 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmsltu_vx_u8mf4_b32_mu(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %maskedoff, <vscale x 2 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1> %1, <vscale x 2 x i8> %2, i8 %3, <vscale x 2 x i1> %0, i64 %4)
# |   ret <vscale x 2 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(<vscale x 2 x i1>, <vscale x 2 x i8>, i8, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vv_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 4 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmsltu_vx_u8mf2_b16_mu(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %maskedoff, <vscale x 4 x i8> %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %op2.addr = alloca i8, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i8 %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %3 = load i8, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1> %1, <vscale x 4 x i8> %2, i8 %3, <vscale x 4 x i1> %0, i64 %4)
# |   ret <vscale x 4 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(<vscale x 4 x i1>, <vscale x 4 x i8>, i8, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmsltu_vv_u8m1_b8_mu(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %maskedoff, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %op2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i8> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %3 = load <vscale x 8 x i8>, ptr %op2.addr, align 1
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, <vscale x 8 x i1> %0, i64 %4)
# |   ret <vscale x 8 x i1> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8
# | ...
# `---data was truncated (10240/63713) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6b66fe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c6b66fb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c6b66fe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fcb04249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fcb042a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fcb04249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fcb04231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6b6693e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c6b6693c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c6b6678b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c6b63280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c6b6327dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fcb04232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fcb042330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fcb042330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6b6327cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c (3239 of 27911)
******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   %0 = load <16 x i8>, ptr %b.addr, align 8
# |   %1 = icmp slt <16 x i8> %0, zeroinitializer
# |   %2 = sub <16 x i8> zeroinitializer, %0
# |   %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0
# |   %4 = load <16 x i8>, ptr %a.addr, align 8
# |   %5 = icmp uge <16 x i8> %4, %3
# |   %6 = select <16 x i1> %5, <16 x i8> %4, <16 x i8> %3
# |   ret <16 x i8> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   %0 = load <8 x i16>, ptr %b.addr, align 8
# |   %1 = icmp slt <8 x i16> %0, zeroinitializer
# |   %2 = sub <8 x i16> zeroinitializer, %0
# |   %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0
# |   %4 = load <8 x i16>, ptr %a.addr, align 8
# |   %5 = icmp uge <8 x i16> %4, %3
# |   %6 = select <8 x i1> %5, <8 x i16> %4, <8 x i16> %3
# |   ret <8 x i16> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   %0 = load <4 x i32>, ptr %b.addr, align 8
# |   %1 = icmp slt <4 x i32> %0, zeroinitializer
# |   %2 = sub <4 x i32> zeroinitializer, %0
# |   %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0
# |   %4 = load <4 x i32>, ptr %a.addr, align 8
# |   %5 = icmp uge <4 x i32> %4, %3
# |   %6 = select <4 x i1> %5, <4 x i32> %4, <4 x i32> %3
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_m_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <16 x i8>, align 8
# |   %b.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %a, ptr %a.addr, align 8
# |   store <16 x i8> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %a.addr, align 8
# |   %1 = load <16 x i8>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3)
# |   %5 = call <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_m_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <8 x i16>, align 8
# |   %b.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %a, ptr %a.addr, align 8
# |   store <8 x i16> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %a.addr, align 8
# |   %1 = load <8 x i16>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
# |   %5 = call <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4)
# |   ret <8 x i16> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_m_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 {
# | entry:
# |   %a.addr = alloca <4 x i32>, align 8
# |   %b.addr = alloca <4 x i32>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %a, ptr %a.addr, align 8
# |   store <4 x i32> %b, ptr %b.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %a.addr, align 8
# |   %1 = load <4 x i32>, ptr %b.addr, align 8
# |   %2 = load i16, ptr %p.addr, align 2
# |   %3 = zext i16 %2 to i32
# |   %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3)
# |   %5 = call <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4)
# |   ret <4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #1
# | 
# | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !2, !3, !4}
# | !llvm.ident = !{!5}
# | 
# | !0 = !{i32 1, !"float-abi", !"hard"}
# | !1 = !{i32 1, !"target-abi", !"aapcs"}
# | !2 = !{i32 1, !"min_enum_size", i32 4}
# | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1}
# | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3}
# | !5 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055763b2cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055763b2cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055763b2cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f966b81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f966b8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f966b81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f966b803507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055763b264e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055763b264c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055763b249b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055763aef90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055763aef8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f966b804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f966b8050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f966b8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055763aef8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c (3240 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f16m1x7(ptr noundef %base, <vscale x 4 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i8> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vluxseg7ei8_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f32m1x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vluxseg7ei8_v_f64m1x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vluxseg7ei8_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vluxseg7ei8_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i8> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i8> %bindex, ptr %bindex.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %bindex.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i8> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none
# | ...
# `---data was truncated (10240/61673) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056522ad9115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056522ad8e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056522ad9189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fba2b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fba2b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fba2b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fba2b11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056522ad26e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056522ad26c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056522ad0bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056522a9bb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056522a9badd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fba2b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fba2b11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fba2b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056522a9bacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-cde-vec.c (3241 of 27911)
******************** TEST 'Clang :: CodeGen/arm-cde-vec.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi    -target-feature +cdecp0 -target-feature +cdecp1    -target-feature +mve.fp    -mfloat-abi hard -O0 -disable-O0-optnone    -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "thumbv8.1m.main-none-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1q_u8() #0 {
# | entry:
# |   %0 = call <16 x i8> @llvm.arm.cde.vcx1q(i32 0, i32 1111)
# |   ret <16 x i8> %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx1q(i32 immarg, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1qa_1(<16 x i8> noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca <16 x i8>, align 8
# |   store <16 x i8> %acc, ptr %acc.addr, align 8
# |   %0 = load <16 x i8>, ptr %acc.addr, align 8
# |   %1 = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 1, <16 x i8> %0, i32 1112)
# |   ret <16 x i8> %1
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx1qa(i32 immarg, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcx1qa_2(<4 x i32> noundef %acc) #0 {
# | entry:
# |   %acc.addr = alloca <4 x i32>, align 8
# |   store <4 x i32> %acc, ptr %acc.addr, align 8
# |   %0 = load <4 x i32>, ptr %acc.addr, align 8
# |   %1 = bitcast <4 x i32> %0 to <16 x i8>
# |   %2 = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 0, <16 x i8> %1, i32 1113)
# |   %3 = bitcast <16 x i8> %2 to <4 x i32>
# |   ret <4 x i32> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx2q_u8(<8 x half> noundef %n) #0 {
# | entry:
# |   %n.addr = alloca <8 x half>, align 8
# |   store <8 x half> %n, ptr %n.addr, align 8
# |   %0 = load <8 x half>, ptr %n.addr, align 8
# |   %1 = bitcast <8 x half> %0 to <16 x i8>
# |   %2 = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> %1, i32 111)
# |   ret <16 x i8> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx2q(i32 immarg, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2q(<4 x float> noundef %n) #0 {
# | entry:
# |   %n.addr = alloca <4 x float>, align 8
# |   store <4 x float> %n, ptr %n.addr, align 8
# |   %0 = load <4 x float>, ptr %n.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <16 x i8>
# |   %2 = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> %1, i32 112)
# |   %3 = bitcast <16 x i8> %2 to <4 x float>
# |   ret <4 x float> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2qa(<4 x float> noundef %acc, <2 x i64> noundef %n) #0 {
# | entry:
# |   %acc.addr = alloca <4 x float>, align 8
# |   %n.addr = alloca <2 x i64>, align 8
# |   store <4 x float> %acc, ptr %acc.addr, align 8
# |   store <2 x i64> %n, ptr %n.addr, align 8
# |   %0 = load <4 x float>, ptr %acc.addr, align 8
# |   %1 = bitcast <4 x float> %0 to <16 x i8>
# |   %2 = load <2 x i64>, ptr %n.addr, align 8
# |   %3 = bitcast <2 x i64> %2 to <16 x i8>
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx2qa(i32 0, <16 x i8> %1, <16 x i8> %3, i32 113)
# |   %5 = bitcast <16 x i8> %4 to <4 x float>
# |   ret <4 x float> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx2qa(i32 immarg, <16 x i8>, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx3q_u8(<8 x i16> noundef %n, <4 x i32> noundef %m) #0 {
# | entry:
# |   %n.addr = alloca <8 x i16>, align 8
# |   %m.addr = alloca <4 x i32>, align 8
# |   store <8 x i16> %n, ptr %n.addr, align 8
# |   store <4 x i32> %m, ptr %m.addr, align 8
# |   %0 = load <8 x i16>, ptr %n.addr, align 8
# |   %1 = bitcast <8 x i16> %0 to <16 x i8>
# |   %2 = load <4 x i32>, ptr %m.addr, align 8
# |   %3 = bitcast <4 x i32> %2 to <16 x i8>
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx3q(i32 0, <16 x i8> %1, <16 x i8> %3, i32 11)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx3q(i32 immarg, <16 x i8>, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcx3q(<2 x i64> noundef %n, <4 x float> noundef %m) #0 {
# | entry:
# |   %n.addr = alloca <2 x i64>, align 8
# |   %m.addr = alloca <4 x float>, align 8
# |   store <2 x i64> %n, ptr %n.addr, align 8
# |   store <4 x float> %m, ptr %m.addr, align 8
# |   %0 = load <2 x i64>, ptr %n.addr, align 8
# |   %1 = bitcast <2 x i64> %0 to <16 x i8>
# |   %2 = load <4 x float>, ptr %m.addr, align 8
# |   %3 = bitcast <4 x float> %2 to <16 x i8>
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx3q(i32 1, <16 x i8> %1, <16 x i8> %3, i32 12)
# |   %5 = bitcast <16 x i8> %4 to <2 x i64>
# |   ret <2 x i64> %5
# | }
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx3qa(<16 x i8> noundef %acc, <8 x i16> noundef %n, <4 x float> noundef %m) #0 {
# | entry:
# |   %acc.addr = alloca <16 x i8>, align 8
# |   %n.addr = alloca <8 x i16>, align 8
# |   %m.addr = alloca <4 x float>, align 8
# |   store <16 x i8> %acc, ptr %acc.addr, align 8
# |   store <8 x i16> %n, ptr %n.addr, align 8
# |   store <4 x float> %m, ptr %m.addr, align 8
# |   %0 = load <16 x i8>, ptr %acc.addr, align 8
# |   %1 = load <8 x i16>, ptr %n.addr, align 8
# |   %2 = bitcast <8 x i16> %1 to <16 x i8>
# |   %3 = load <4 x float>, ptr %m.addr, align 8
# |   %4 = bitcast <4 x float> %3 to <16 x i8>
# |   %5 = call <16 x i8> @llvm.arm.cde.vcx3qa(i32 1, <16 x i8> %0, <16 x i8> %2, <16 x i8> %4, i32 13)
# |   ret <16 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx3qa(i32 immarg, <16 x i8>, <16 x i8>, <16 x i8>, i32 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcx1q_m(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <8 x i16>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <8 x i16> %inactive, ptr %inactive.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <8 x i16>, ptr %inactive.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
# |   %4 = call <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 0, <8 x i16> %0, i32 1111, <8 x i1> %3)
# |   ret <8 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 immarg, <8 x i16>, i32 immarg, <8 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1qa_m(<16 x i8> noundef %acc, i16 noundef zeroext %p) #0 {
# | entry:
# |   %acc.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <16 x i8> %acc, ptr %acc.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <16 x i8>, ptr %acc.addr, align 8
# |   %1 = load i16, ptr %p.addr, align 2
# |   %2 = zext i16 %1 to i32
# |   %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2)
# |   %4 = call <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 1, <16 x i8> %0, i32 1112, <16 x i1> %3)
# |   ret <16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 immarg, <16 x i8>, i32 immarg, <16 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcx2q_m(<4 x i32> noundef %inactive, <4 x float> noundef %n, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <4 x i32>, align 8
# |   %n.addr = alloca <4 x float>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x i32> %inactive, ptr %inactive.addr, align 8
# |   store <4 x float> %n, ptr %n.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x i32>, ptr %inactive.addr, align 8
# |   %1 = load <4 x float>, ptr %n.addr, align 8
# |   %2 = bitcast <4 x float> %1 to <16 x i8>
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 0, <4 x i32> %0, <16 x i8> %2, i32 111, <4 x i1> %5)
# |   ret <4 x i32> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 immarg, <4 x i32>, <16 x i8>, i32 immarg, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2qa_m(<4 x float> noundef %acc, <8 x half> noundef %n, i16 noundef zeroext %p) #0 {
# | entry:
# |   %acc.addr = alloca <4 x float>, align 8
# |   %n.addr = alloca <8 x half>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <4 x float> %acc, ptr %acc.addr, align 8
# |   store <8 x half> %n, ptr %n.addr, align 8
# |   store i16 %p, ptr %p.addr, align 2
# |   %0 = load <4 x float>, ptr %acc.addr, align 8
# |   %1 = load <8 x half>, ptr %n.addr, align 8
# |   %2 = bitcast <8 x half> %1 to <16 x i8>
# |   %3 = load i16, ptr %p.addr, align 2
# |   %4 = zext i16 %3 to i32
# |   %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4)
# |   %6 = call <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <16 x i8> %2, i32 112, <4 x i1> %5)
# |   ret <4 x float> %6
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 immarg, <4 x float>, <16 x i8>, i32 immarg, <4 x i1>) #1
# | 
# | ; Function Attrs: noinline nounwind
# | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcx3q_m(<2 x i64> noundef %inactive, <4 x float> noundef %n, <16 x i8> noundef %m, i16 noundef zeroext %p) #0 {
# | entry:
# |   %inactive.addr = alloca <2 x i64>, align 8
# |   %n.addr = alloca <4 x float>, align 8
# |   %m.addr = alloca <16 x i8>, align 8
# |   %p.addr = alloca i16, align 2
# |   store <2 x i64> %inactive, ptr %inactive.addr, align 8
# | ...
# `---data was truncated (10240/13030) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005598023a015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055980239d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005598023a089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1836f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1836f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1836f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1836f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559802335e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559802335c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055980231ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559801fca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559801fc9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1836f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1836f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1836f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559801fc9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c (3242 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmnor_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmnor_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmnor_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmnor_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmnor_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmnor_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmnor_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561d92d0715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561d92d040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561d92d0789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fca43f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fca43f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fca43f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fca43f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561d92c9ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561d92c9cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561d92c81b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561d929310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561d92930dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fca43f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fca43f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fca43f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561d92930cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c (3243 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1(<vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2(<vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4(<vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8(<vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16(<vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32(<vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b64(<vscale x 1 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1> %0, i64 %1)
# |   ret i64 %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b1_m(<vscale x 64 x i1> %mask, <vscale x 64 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 64 x i1>, align 1
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1> %1, <vscale x 64 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b2_m(<vscale x 32 x i1> %mask, <vscale x 32 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 32 x i1>, align 1
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1> %1, <vscale x 32 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 16 x i1>, align 1
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1> %1, <vscale x 16 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1> %1, <vscale x 8 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b16_m(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1> %1, <vscale x 4 x i1> %0, i64 %2)
# |   ret i64 %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vfirst_m_b32_m(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call i64 @llvm.riscv.vfirst.mask.nxv2i1.i64(<vscale x 2 x i1> %1, <vscale x 2 x i1> %0, i64 %2)
# |   ret i6
# | ...
# `---data was truncated (10240/11946) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005590c412515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005590c41220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005590c412589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f34c4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f34c4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f34c4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f34c4d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005590c40bae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005590c40bac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005590c409fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005590c3d4f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005590c3d4edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f34c4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f34c4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f34c4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005590c3d4ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c (3244 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 3)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005610e873215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005610e872f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005610e873289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fee8ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fee8baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fee8ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fee8ba31507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005610e86c7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005610e86c7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005610e86acb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005610e835c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005610e835bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fee8ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fee8ba330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fee8ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005610e835bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c (3245 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000555ae46f215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000555ae46ef0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000555ae46f289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f82af933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f82af98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f82af933a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f82af91b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000555ae4687e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000555ae4687c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000555ae466cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000555ae431c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000555ae431bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f82af91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f82af91d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f82af91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000555ae431bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c (3246 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, a
# | ...
# `---data was truncated (10240/26721) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005605f5ab715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005605f5ab40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005605f5ab789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fa095649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fa0956a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fa095649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fa095631507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005605f5a4ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005605f5a4cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005605f5a31b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005605f56e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005605f56e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fa095632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fa0956330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fa0956330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005605f56e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c (3247 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %2, ptr %0, <vscale x 1 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %2, ptr %0, <vscale x 2 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7(ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %2, ptr %0, <vscale x 4 x i32> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055eead54115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055eead53e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055eead54189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5a94e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5a94e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5a94e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5a94e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055eead4d6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055eead4d6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055eead4bbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055eead16b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055eead16add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5a94e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5a94e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5a94e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055eead16acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c (3248 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_f16mf4x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f16mf2x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f16m1x7(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_f32mf2x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f32m1x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_f64m1x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @test_vloxseg7ei64_v_i8mf8x7(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_i8mf4x7(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ad3dbe415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ad3dbe10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ad3dbe489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2997333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f299738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2997333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f299731b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ad3db79e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ad3db79c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ad3db5eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ad3d80e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ad3d80ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f299731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f299731d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f299731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ad3d80dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c (3249 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 5)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/23405) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556b93e9015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556b93e8d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556b93e9089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efd92133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efd9218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efd92133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efd9211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556b93e25e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556b93e25c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556b93e0ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556b93aba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556b93ab9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efd9211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efd9211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efd9211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556b93ab9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c (3250 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e16_v_bf16mf4x2_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e16_v_bf16mf2x2_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %2, <vscale x 2 x i1> %0, i64 %3, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e16_v_bf16m1x2_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %vd, ptr noundef %rs1, i64 nou
# | ...
# `---data was truncated (10240/27442) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c6eee1d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c6eee1a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c6eee1d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0d7c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0d7c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0d7c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0d7c11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c6eedb2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c6eedb2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c6eed97b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c6eea470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c6eea46dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0d7c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0d7c11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0d7c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c6eea46cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c (3251 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i32> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vluxseg5ei32_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vluxseg5ei32_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i32>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vluxseg5ei32_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i32> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i32> %rs2, ptr %rs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i32>, ptr %rs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i32>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f31171415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f3117110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f31171489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f8750733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f875078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f8750733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f875071b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f3116a9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f3116a9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f31168eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f31133e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f31133ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f875071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f875071d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f875071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f31133dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c (3252 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %2, ptr %0, <vscale x 1 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %2, ptr %0, <vscale x 2 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6(ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %2, ptr %0, <vscale x 4 x i16> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %vs2, ptr %vs2.addr, align 2
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %vs2.addr, align 2
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562267f6315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562267f600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562267f6389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff6c4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff6c4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff6c4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff6c4e31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562267ef8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562267ef8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562267eddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562267b8d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562267b8cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff6c4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff6c4e330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff6c4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562267b8ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c (3253 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @test_vlseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @test_vlseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e8_v_u8mf2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e8_v_u8m1x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e8_v_u8m2x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %0, i64 %1, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %2
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e8_v_u8m4x2(ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call target("riscv.vect
# | ...
# `---data was truncated (10240/24229) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005555897e515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005555897e20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005555897e589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f1e92049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f1e920a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f1e92049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f1e92031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055558977ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055558977ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055558975fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055558940f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055558940edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f1e92032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f1e920330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f1e920330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055558940ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c (3254 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1(<vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vv_i64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 2 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vsmul_vx_i64m2(<vscale x 2 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64.i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vv_i64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 4 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vsmul_vx_i64m4(<vscale x 4 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64.i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vv_i64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca <vscale x 8 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 8 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load <vscale x 8 x i64>, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vsmul_vx_i64m8(<vscale x 8 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i64>, ptr %op1.addr, align 8
# |   %1 = load i64, ptr %op2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %0, i64 %1, i64 0, i64 %2)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64.i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i64, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vv_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store <vscale x 1 x i64> %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr %op1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %op2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 0, i64 %3, i64 3)
# |   ret <vscale x 1 x i64> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vsmul_vx_i64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 noundef %op2, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i64>, align 8
# |   %op2.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i64> %op1, ptr %op1.addr, align 8
# |   store i64 %op2, ptr %op2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i64>, ptr 
# | ...
# `---data was truncated (10240/18895) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559168bc815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559168bc50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559168bc889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb672b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb672b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb672b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb672b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559168b5de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559168b5dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559168b42b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005591687f20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005591687f1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb672b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb672b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb672b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005591687f1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c (3255 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %0, ptr %1, <vscale x 1 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, ptr %1, <vscale x 2 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %0, ptr %1, <vscale x 4 x i16> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vloxseg6ei16_v_bf16mf4x6_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %1, ptr %2, <vscale x 1 x i16> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vloxseg6ei16_v_bf16mf2x6_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %1, ptr %2, <vscale x 2 x i16> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vloxseg6ei16_v_bf16m1x6_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 6), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %1, ptr %2, <vscale x 4 x i16> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055f90352f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055f90352c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055f90352f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f44c7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f44c72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f44c7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f44c7231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055f9034c4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055f9034c4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055f9034a9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055f9031590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055f903158dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f44c7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f44c72330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f44c72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055f903158cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c (3256 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/52607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055d41facc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d41fac90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d41facc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f96a7a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f96a7a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f96a7a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f96a7a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d41fa61e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d41fa61c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d41fa46b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d41f6f60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d41f6f5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f96a7a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f96a7a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f96a7a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d41f6f5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c (3257 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8(ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @test_vluxseg8ei64_v_bf16mf4x8_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) poison, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @test_vluxseg8ei64_v_bf16mf2x8_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @test_vluxseg8ei64_v_bf16m1x8_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) poison, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr captures(none), <vscale x 4 x i64>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056493e4a915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056493e4a60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056493e4a989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fefad505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fefad55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fefad505a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fefad4ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056493e43ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056493e43ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056493e423b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056493e0d30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056493e0d2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fefad4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fefad4ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fefad4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056493e0d2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/distributed-thin-lto/cfi.ll (3258 of 27911)
******************** TEST 'Clang :: CodeGen/distributed-thin-lto/cfi.ll' FAILED ********************
Exit Code: -6

Command Output (stdout):
--
# RUN: at line 5
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll
# |  #0 0x00005636fdf0415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005636fdf010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005636fdf0489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff10a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff10a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff10a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff10a31b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005636fde99e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005636fde99c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005636fde7eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005636fdb2e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005636fdb2ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff10a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff10a31d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff10a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005636fdb2dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c (3259 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %0, ptr %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_u64m1x5_tum(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_f64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %maskedoff_tuple.addr, align 8
# |   %2 = load ptr, ptr %base.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %1, ptr %2, <vscale x 1 x i1> %0, i64 %3, i64 0, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlseg5e64_v_i64m1x5_tumu(<vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 8
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load target("riscv.vector.tu
# | ...
# `---data was truncated (10240/16560) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560b5e0b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560b5e0b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560b5e0b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f129ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f129ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f129ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f129ab1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560b5e04be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560b5e04bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560b5e030b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560b5dce00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560b5dcdfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f129ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f129ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f129ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560b5dcdfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c (3260 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_x_f_w_bf16m2_i8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(<vscale x 8 x i8>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vfncvt_rtz_x_f_w_bf16m4_i8m2_tu(<vscale x 16 x i8> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(<vscale x 16 x i8>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vfncvt_rtz_x_f_w_bf16m8_i8m4_tu(<vscale x 32 x i8> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(<vscale x 32 x i8>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8_tu(<vscale x 1 x i8> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(<vscale x 1 x i8>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4_tu(<vscale x 2 x i8> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(<vscale x 2 x i8>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2_tu(<vscale x 4 x i8> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(<vscale x 4 x i8>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1_tu(<vscale x 8 x i8> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vd, ptr %vd.addr, align 1
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vd.addr, align 1
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.v
# | ...
# `---data was truncated (10240/53192) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056372e29e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056372e29b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056372e29e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fe50dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fe50dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fe50dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fe50dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056372e233e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056372e233c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056372e218b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056372dec80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056372dec7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fe50dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fe50dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fe50dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056372dec7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c (3261 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_i8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_i8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_i8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_i8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @test_vlseg6e8_v_u8mf8x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @test_vlseg6e8_v_u8mf4x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e8_v_u8mf2x6_m(<vscale x 4 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 4 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e8_v_u8m1x6_m(<vscale x 8 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 8 x i1> %0, i64 %2, i64 3, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b64798315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b6479800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b64798389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5387049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53870a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5387049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5387031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b647918e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b647918c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b6478fdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b6475ad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b6475acdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5387032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53870330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53870330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6475accc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c (3262 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf   -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - |   /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tu(<vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 1 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tu(<vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 2 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tu(<vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 4 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(<vscale x 4 x i8>, <vscale x 4 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_sf_vfnrclip_xu_f_qf_u8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(<vscale x 8 x i8>, <vscale x 8 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_sf_vfnrclip_xu_f_qf_u8m2_tu(<vscale x 16 x i8> %maskedoff, <vscale x 16 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load float, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, i64 7, i64 %3)
# |   ret <vscale x 16 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(<vscale x 16 x i8>, <vscale x 16 x float>, float, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf8_tum(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %maskedoff, <vscale x 1 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> %1, <vscale x 1 x float> %2, float %3, <vscale x 1 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 1 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(<vscale x 1 x i8>, <vscale x 1 x float>, float, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf4_tum(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %maskedoff, <vscale x 2 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load float, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> %1, <vscale x 2 x float> %2, float %3, <vscale x 2 x i1> %0, i64 7, i64 %4, i64 2)
# |   ret <vscale x 2 x i8> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(<vscale x 2 x i8>, <vscale x 2 x float>, float, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_sf_vfnrclip_xu_f_qf_u8mf2_tum(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %maskedoff, <vscale x 4 x float> %vs2, float noundef %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %rs1.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store float %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, al
# | ...
# `---data was truncated (10240/26756) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561064f5d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561064f5a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561064f5d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f51a5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f51a5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f51a5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f51a5b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561064ef2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561064ef2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561064ed7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000561064b870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561064b86dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f51a5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f51a5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f51a5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561064b86cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c (3263 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %2, ptr %0, i64 %1, i64 %3, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vssseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 4), align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %v_tuple, ptr %v_tuple.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr %v_tuple.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 6)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Functi
# | ...
# `---data was truncated (10240/15986) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ef5432515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ef543220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ef5432589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f53caf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f53caf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f53caf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f53caf1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ef542bae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ef542bac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ef5429fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ef53f4f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ef53f4edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f53caf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f53caf1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f53caf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ef53f4ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c (3264 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_i8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_i8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_i8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_i8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_i8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 16 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8.p0.i64(<vscale x 16 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i8> @test_vle8_v_i8m4_tu(<vscale x 32 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 32 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8.p0.i64(<vscale x 32 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i8> @test_vle8_v_i8m8_tu(<vscale x 64 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 64 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 64 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8.p0.i64(<vscale x 64 x i8>, ptr captures(none), i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i8> @test_vle8_v_u8mf8_tu(<vscale x 1 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.p0.i64(<vscale x 1 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 1 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i8> @test_vle8_v_u8mf4_tu(<vscale x 2 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8.p0.i64(<vscale x 2 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 2 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i8> @test_vle8_v_u8mf2_tu(<vscale x 4 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8.p0.i64(<vscale x 4 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 4 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vle8_v_u8m1_tu(<vscale x 8 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8.p0.i64(<vscale x 8 x i8> %0, ptr %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i8> @test_vle8_v_u8m2_tu(<vscale x 16 x i8> %maskedoff, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x i8>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = l
# | ...
# `---data was truncated (10240/54480) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056020ec4315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056020ec400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056020ec4389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fdbed133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fdbed18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fdbed133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fdbed11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056020ebd8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056020ebd8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056020ebbdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056020e86d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056020e86cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fdbed11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fdbed11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fdbed11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056020e86ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c (3265 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_f64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_f64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_i64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_i64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlsseg4e64_v_u64m1x4_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlsseg4e64_v_u64m2x4_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ed1893615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ed189330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ed1893689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f56bf449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f56bf4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f56bf449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f56bf431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ed188cbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ed188cbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ed188b0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ed185600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ed1855fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f56bf432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f56bf4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f56bf4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ed1855fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c (3266 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(<vscale x 8 x bfloat>, <vscale x 8 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfncvtbf16_f_f_w_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x float>, ptr %vs2.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(<vscale x 16 x bfloat>, <vscale x 16 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(<vscale x 1 x bfloat>, <vscale x 1 x float>, <vscale x 1 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfncvtbf16_f_f_w_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(<vscale x 2 x bfloat>, <vscale x 2 x float>, <vscale x 2 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfncvtbf16_f_f_w_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x float> %vs2, ptr %vs2.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x float>, ptr %vs2.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %0, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(<vscale x 4 x bfloat>, <vscale x 4 x float>, <vscale x 4 x i1>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfncvtbf16_f_f_w_bf16m2_tum(<vscale x 8 x i1> %vm, <vscale x 8 x bfloat> %vd, <vscale x 8 x float> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x float> %vs2, ptr %vs2.addr, align 4
# |  
# | ...
# `---data was truncated (10240/43478) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005619e875815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005619e87550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005619e875889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff384333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff38438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff384333a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff38431b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005619e86ede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005619e86edc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005619e86d2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005619e83820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005619e8381dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff38431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff38431d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff38431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005619e8381cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/arm-neon-vcadd.c (3267 of 27911)
******************** TEST 'Clang :: CodeGen/arm-neon-vcadd.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 2
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.3a-arm-none-eabi -target-cpu generic  -target-feature +fullfp16 -mfloat-abi soft -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c |  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.3a-arm-none-eabi -target-cpu generic -target-feature +fullfp16 -mfloat-abi soft -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c"
# | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
# | target triple = "armv8.3a-arm-none-eabi"
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x4_rot90(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %result = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot90_f16.i = bitcast <8 x i8> %2 to <4 x half>
# |   %vcadd_rot90_f161.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcadd_rot90_f162.i = call <4 x half> @llvm.arm.neon.vcadd.rot90.v4f16(<4 x half> %vcadd_rot90_f16.i, <4 x half> %vcadd_rot90_f161.i)
# |   %vcadd_rot90_f163.i = bitcast <4 x half> %vcadd_rot90_f162.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot90_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x2_rot90(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %result = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot90_f32.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vcadd_rot90_f321.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vcadd_rot90_f322.i = call <2 x float> @llvm.arm.neon.vcadd.rot90.v2f32(<2 x float> %vcadd_rot90_f32.i, <2 x float> %vcadd_rot90_f321.i)
# |   %vcadd_rot90_f323.i = bitcast <2 x float> %vcadd_rot90_f322.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot90_f323.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x8_rot90(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 8
# |   %__p1.addr.i = alloca <8 x half>, align 8
# |   %__ret.i = alloca <8 x half>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %result = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 8
# |   store <8 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vcaddq_rot90_f16.i = bitcast <16 x i8> %2 to <8 x half>
# |   %vcaddq_rot90_f161.i = bitcast <16 x i8> %3 to <8 x half>
# |   %vcaddq_rot90_f162.i = call <8 x half> @llvm.arm.neon.vcadd.rot90.v8f16(<8 x half> %vcaddq_rot90_f16.i, <8 x half> %vcaddq_rot90_f161.i)
# |   %vcaddq_rot90_f163.i = bitcast <8 x half> %vcaddq_rot90_f162.i to <16 x i8>
# |   store <16 x i8> %vcaddq_rot90_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x half>, ptr %ref.tmp.i, align 8
# |   store <8 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x half>, ptr %__ret.i, align 8
# |   store <8 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x4_rot90(<4 x float> noundef %a, <4 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x float>, align 8
# |   %__p1.addr.i = alloca <4 x float>, align 8
# |   %__ret.i = alloca <4 x float>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <4 x float>, align 8
# |   %b.addr = alloca <4 x float>, align 8
# |   %result = alloca <4 x float>, align 8
# |   store <4 x float> %a, ptr %a.addr, align 8
# |   store <4 x float> %b, ptr %b.addr, align 8
# |   %0 = load <4 x float>, ptr %a.addr, align 8
# |   %1 = load <4 x float>, ptr %b.addr, align 8
# |   store <4 x float> %0, ptr %__p0.addr.i, align 8
# |   store <4 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vcaddq_rot90_f32.i = bitcast <16 x i8> %2 to <4 x float>
# |   %vcaddq_rot90_f321.i = bitcast <16 x i8> %3 to <4 x float>
# |   %vcaddq_rot90_f322.i = call <4 x float> @llvm.arm.neon.vcadd.rot90.v4f32(<4 x float> %vcaddq_rot90_f32.i, <4 x float> %vcaddq_rot90_f321.i)
# |   %vcaddq_rot90_f323.i = bitcast <4 x float> %vcaddq_rot90_f322.i to <16 x i8>
# |   store <16 x i8> %vcaddq_rot90_f323.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x float>, ptr %ref.tmp.i, align 8
# |   store <4 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x float>, ptr %__ret.i, align 8
# |   store <4 x float> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x4_rot270(<4 x half> noundef %a, <4 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <4 x half>, align 8
# |   %__p1.addr.i = alloca <4 x half>, align 8
# |   %__ret.i = alloca <4 x half>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <4 x half>, align 8
# |   %b.addr = alloca <4 x half>, align 8
# |   %result = alloca <4 x half>, align 8
# |   store <4 x half> %a, ptr %a.addr, align 8
# |   store <4 x half> %b, ptr %b.addr, align 8
# |   %0 = load <4 x half>, ptr %a.addr, align 8
# |   %1 = load <4 x half>, ptr %b.addr, align 8
# |   store <4 x half> %0, ptr %__p0.addr.i, align 8
# |   store <4 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot270_f16.i = bitcast <8 x i8> %2 to <4 x half>
# |   %vcadd_rot270_f161.i = bitcast <8 x i8> %3 to <4 x half>
# |   %vcadd_rot270_f162.i = call <4 x half> @llvm.arm.neon.vcadd.rot270.v4f16(<4 x half> %vcadd_rot270_f16.i, <4 x half> %vcadd_rot270_f161.i)
# |   %vcadd_rot270_f163.i = bitcast <4 x half> %vcadd_rot270_f162.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot270_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <4 x half>, ptr %ref.tmp.i, align 8
# |   store <4 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <4 x half>, ptr %__ret.i, align 8
# |   store <4 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x2_rot270(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <2 x float>, align 8
# |   %__p1.addr.i = alloca <2 x float>, align 8
# |   %__ret.i = alloca <2 x float>, align 8
# |   %ref.tmp.i = alloca <8 x i8>, align 8
# |   %a.addr = alloca <2 x float>, align 8
# |   %b.addr = alloca <2 x float>, align 8
# |   %result = alloca <2 x float>, align 8
# |   store <2 x float> %a, ptr %a.addr, align 8
# |   store <2 x float> %b, ptr %b.addr, align 8
# |   %0 = load <2 x float>, ptr %a.addr, align 8
# |   %1 = load <2 x float>, ptr %b.addr, align 8
# |   store <2 x float> %0, ptr %__p0.addr.i, align 8
# |   store <2 x float> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <8 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <8 x i8>, ptr %__p1.addr.i, align 8
# |   %vcadd_rot270_f32.i = bitcast <8 x i8> %2 to <2 x float>
# |   %vcadd_rot270_f321.i = bitcast <8 x i8> %3 to <2 x float>
# |   %vcadd_rot270_f322.i = call <2 x float> @llvm.arm.neon.vcadd.rot270.v2f32(<2 x float> %vcadd_rot270_f32.i, <2 x float> %vcadd_rot270_f321.i)
# |   %vcadd_rot270_f323.i = bitcast <2 x float> %vcadd_rot270_f322.i to <8 x i8>
# |   store <8 x i8> %vcadd_rot270_f323.i, ptr %ref.tmp.i, align 8
# |   %4 = load <2 x float>, ptr %ref.tmp.i, align 8
# |   store <2 x float> %4, ptr %__ret.i, align 8
# |   %5 = load <2 x float>, ptr %__ret.i, align 8
# |   store <2 x float> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo16x8_rot270(<8 x half> noundef %a, <8 x half> noundef %b) #0 {
# | entry:
# |   %__p0.addr.i = alloca <8 x half>, align 8
# |   %__p1.addr.i = alloca <8 x half>, align 8
# |   %__ret.i = alloca <8 x half>, align 8
# |   %ref.tmp.i = alloca <16 x i8>, align 8
# |   %a.addr = alloca <8 x half>, align 8
# |   %b.addr = alloca <8 x half>, align 8
# |   %result = alloca <8 x half>, align 8
# |   store <8 x half> %a, ptr %a.addr, align 8
# |   store <8 x half> %b, ptr %b.addr, align 8
# |   %0 = load <8 x half>, ptr %a.addr, align 8
# |   %1 = load <8 x half>, ptr %b.addr, align 8
# |   store <8 x half> %0, ptr %__p0.addr.i, align 8
# |   store <8 x half> %1, ptr %__p1.addr.i, align 8
# |   %2 = load <16 x i8>, ptr %__p0.addr.i, align 8
# |   %3 = load <16 x i8>, ptr %__p1.addr.i, align 8
# |   %vcaddq_rot270_f16.i = bitcast <16 x i8> %2 to <8 x half>
# |   %vcaddq_rot270_f161.i = bitcast <16 x i8> %3 to <8 x half>
# |   %vcaddq_rot270_f162.i = call <8 x half> @llvm.arm.neon.vcadd.rot270.v8f16(<8 x half> %vcaddq_rot270_f16.i, <8 x half> %vcaddq_rot270_f161.i)
# |   %vcaddq_rot270_f163.i = bitcast <8 x half> %vcaddq_rot270_f162.i to <16 x i8>
# |   store <16 x i8> %vcaddq_rot270_f163.i, ptr %ref.tmp.i, align 8
# |   %4 = load <8 x half>, ptr %ref.tmp.i, align 8
# |   store <8 x half> %4, ptr %__ret.i, align 8
# |   %5 = load <8 x half>, ptr %__ret.i, align 8
# |   store <8 x half> %5, ptr %result, align 8
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind optnone
# | define dso_local void @foo32x4_rot270(<4 x float> noundef %a, <4 
# | ...
# `---data was truncated (10240/13572) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o -
# |  #0 0x000055d291bc315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055d291bc00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055d291bc389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f647c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f647c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f647c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f647c231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055d291b58e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055d291b58c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055d291b3db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055d2917ed0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055d2917ecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f647c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f647c2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f647c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055d2917eccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c (3268 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_f32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_f32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_f32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) poison, ptr %1, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32ff_v_f32m4x2_m(<vscale x 8 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %1, <vscale x 8 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), <vscale x 8 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32ff_v_i32mf2x2_m(<vscale x 1 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %1, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32ff_v_i32m1x2_m(<vscale x 2 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %1, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 0
# |   %6 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64 } %4, 1
# |   store i64 %6, ptr %2, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %5
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32ff_v_i32m2x2_m(<vscale x 4 x i1> %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load ptr, ptr %new_vl.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call { target("riscv.
# | ...
# `---data was truncated (10240/17879) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056427e81015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056427e80d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056427e81089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f3532133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f353218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f3532133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f353211b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056427e7a5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056427e7a5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056427e78ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056427e43a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056427e439dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f353211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f353211d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f353211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056427e439cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c (3269 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_x_f_v_i32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_x_f_v_i32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_x_f_v_i32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_x_f_v_i32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_x_f_v_i32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vfwcvt_rtz_xu_f_v_u32mf2(<vscale x 1 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> poison, <vscale x 1 x half> %0, i64 %1)
# |   ret <vscale x 1 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32>, <vscale x 1 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vfwcvt_rtz_xu_f_v_u32m1(<vscale x 2 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> poison, <vscale x 2 x half> %0, i64 %1)
# |   ret <vscale x 2 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vfwcvt_rtz_xu_f_v_u32m2(<vscale x 4 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> poison, <vscale x 4 x half> %0, i64 %1)
# |   ret <vscale x 4 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vfwcvt_rtz_xu_f_v_u32m4(<vscale x 8 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> poison, <vscale x 8 x half> %0, i64 %1)
# |   ret <vscale x 8 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vfwcvt_rtz_xu_f_v_u32m8(<vscale x 16 x half> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> poison, <vscale x 16 x half> %0, i64 %1)
# |   ret <vscale x 16 x i32> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vfwcvt_rtz_x_f_v_i64m1(<vscale x 1 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> poison, <vscale x 1 x float> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64>, <vscale x 1 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vfwcvt_rtz_x_f_v_i64m2(<vscale x 2 x float> %src, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> poison, <vscale x 2 x float> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i6
# | ...
# `---data was truncated (10240/35605) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000562aae76c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000562aae7690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000562aae76c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f2ce4a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f2ce4a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f2ce4a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f2ce4a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562aae701e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562aae701c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562aae6e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562aae3960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562aae395dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f2ce4a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f2ce4a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f2ce4a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562aae395cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c (3270 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tu(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 1 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tu(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tu(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_vdot4au_vx_u32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 8 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.vdot4au.nxv8i32.i32.i64(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_vdot4au_vx_u32m8_tu(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 16 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x i32>, ptr %vs2.addr, align 4
# |   %2 = load i32, ptr %rs1.addr, align 4
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.vdot4au.nxv16i32.i32.i64(<vscale x 16 x i32>, <vscale x 16 x i32>, i32, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i32> @test_vdot4au_vx_u32mf2_tum(<vscale x 1 x i1> %vm, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 1 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 1 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 1 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i32> @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i32, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_vdot4au_vx_u32m1_tum(<vscale x 2 x i1> %vm, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 2 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 2 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3, <vscale x 2 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 2 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_vdot4au_vx_u32m2_tum(<vscale x 4 x i1> %vm, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs2.addr = alloca <vscale x 4 x i32>, align 4
# |   %rs1.addr = alloca i32, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x i32> %vs2, ptr %vs2.addr, align 4
# |   store i32 %rs1, ptr %rs1.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %2 = load <vscale x 4 x i32>, ptr %vs2.addr, align 4
# |   %3 = load i32, ptr %rs1.addr, align 4
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3, <vscale x 4 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 4 x i32> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nou
# | ...
# `---data was truncated (10240/25034) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005647658a415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005647658a10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005647658a489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0672a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0672a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0672a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0672a03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564765839e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564765839c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056476581eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005647654ce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005647654cddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0672a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0672a050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0672a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005647654cdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c (3271 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvlimax.i64(i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e8m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e16m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32mf2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e32m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m1() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m2() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m4() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
# |   ret i64 %0
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local i64 @test_vsetvlmax_e64m8() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3)
# |   ret i64 %0
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b7ceb7b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b7ceb780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b7ceb7b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f130ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f130aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f130ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f130ae31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b7ceb10e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b7ceb10c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b7ceaf5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b7ce7a50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b7ce7a4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f130ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f130ae330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f130ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b7ce7a4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c (3272 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tu(<vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tu(<vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfslide1up_vf_bf16m1_tu(<vscale x 4 x bfloat> %maskedoff, <vscale x 4 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 4 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfslide1up_vf_bf16m2_tu(<vscale x 8 x bfloat> %maskedoff, <vscale x 8 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 8 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x bfloat> @test_vfslide1up_vf_bf16m4_tu(<vscale x 16 x bfloat> %maskedoff, <vscale x 16 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 16 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 16 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x bfloat> @test_vfslide1up_vf_bf16m8_tu(<vscale x 32 x bfloat> %maskedoff, <vscale x 32 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 32 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %src.addr, align 2
# |   %2 = load bfloat, ptr %value.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, i64 %3)
# |   ret <vscale x 32 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, bfloat, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfslide1up_vf_bf16mf4_tum(<vscale x 1 x i1> %mask, <vscale x 1 x bfloat> %maskedoff, <vscale x 1 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %maskedoff.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %src.addr, align 2
# |   %3 = load bfloat, ptr %value.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, bfloat %3, <vscale x 1 x i1> %0, i64 %4, i64 2)
# |   ret <vscale x 1 x bfloat> %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, bfloat, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfslide1up_vf_bf16mf2_tum(<vscale x 2 x i1> %mask, <vscale x 2 x bfloat> %maskedoff, <vscale x 2 x bfloat> %src, bfloat noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %maskedoff.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %src.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %value.addr = alloca bfloat, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x bfloat> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 2 x bfloat> %src, ptr %src.addr, align 2
# |   store bfloat %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %maskedoff.addr, alig
# | ...
# `---data was truncated (10240/32578) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056322f39b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056322f3980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056322f39b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc2d4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2d478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc2d4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc2d471b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056322f330e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056322f330c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056322f315b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056322efc50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056322efc4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc2d471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2d471d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2d471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056322efc4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c (3273 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf8_i8m1(<vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> poison, <vscale x 1 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf4_i8m1(<vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> poison, <vscale x 2 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8mf2_i8m1(<vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m1_i8m1(<vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m2_i8m1(<vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m4_i8m1(<vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> poison, <vscale x 32 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmax_vs_i8m8_i8m1(<vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> poison, <vscale x 64 x i8> %0, <vscale x 8 x i8> %1, i64 %2)
# |   ret <vscale x 8 x i8> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf4_i16m1(<vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> poison, <vscale x 1 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(<vscale x 4 x i16>, <vscale x 1 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16mf2_i16m1(<vscale x 2 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i16>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> %0, <vscale x 4 x i16> %1, i64 %2)
# |   ret <vscale x 4 x i16> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(<vscale x 4 x i16>, <vscale x 2 x i16>, <vscale x 4 x i16>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmax_vs_i16m1_i16m1(<vscale x 4 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 
# | ...
# `---data was truncated (10240/52607) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000564f6451115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000564f6450e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000564f6451189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb26a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb26a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb26a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb26a71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000564f644a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000564f644a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000564f6448bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000564f6413b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000564f6413add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb26a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb26a71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb26a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000564f6413acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c (3274 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vluxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vluxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vluxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vluxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556d6575915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556d657560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556d6575989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb7f7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb7f7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb7f7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb7f7c31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556d656eee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556d656eec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556d656d3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556d653830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556d65382dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb7f7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb7f7c330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb7f7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556d65382cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c (3275 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod    -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1_tu(<vscale x 2 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 8 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 2 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2_tu(<vscale x 4 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 16 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 16 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 16 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 16 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 4 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32>, <vscale x 8 x i8>, <vscale x 16 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4_tu(<vscale x 8 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 32 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 32 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 32 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 32 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 8 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32>, <vscale x 8 x i8>, <vscale x 32 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8_tu(<vscale x 16 x i32> %vd, <vscale x 8 x i8> %vs1, <vscale x 64 x i8> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x i32>, align 4
# |   %vs1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs2.addr = alloca <vscale x 64 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i32> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x i8> %vs1, ptr %vs1.addr, align 1
# |   store <vscale x 64 x i8> %vs2, ptr %vs2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i32>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x i8>, ptr %vs1.addr, align 1
# |   %2 = load <vscale x 64 x i8>, ptr %vs2.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, i64 %3, i64 2)
# |   ret <vscale x 16 x i32> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32>, <vscale x 8 x i8>, <vscale x 64 x i8>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055791637015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055791636d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055791637089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5029d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5029d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5029d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5029d1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000557916305e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000557916305c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005579162eab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000557915f9a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000557915f99dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5029d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5029d1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5029d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000557915f99cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c (3276 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_f32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr captures(none), <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_f32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr captures(none), <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_i32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_i32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @test_vlseg6e32_v_u32mf2x6_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %1, <vscale x 1 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @test_vlseg6e32_v_u32m1x6_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) poison, ptr %1, <vscale x 2 x i1> %0, i64 %2, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %3
# | }
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c72f14415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c72f1410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c72f14489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007facf8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007facf8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007facf8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007facf8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c72f0d9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c72f0d9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c72f0beb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c72ed6e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c72ed6ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007facf8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007facf8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007facf8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c72ed6dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c (3277 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local signext i32 @test() #0 {
# | entry:
# |   %0 = call i64 @llvm.riscv.vsetvli.i64(i64 1, i64 0, i64 0)
# |   %conv = trunc i64 %0 to i32
# |   ret i32 %conv
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000559afbc8515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000559afbc820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000559afbc8589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f6e9cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f6e9cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f6e9cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f6e9cb1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000559afbc1ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000559afbc1ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000559afbbffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000559afb8af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000559afb8aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f6e9cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f6e9cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f6e9cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000559afb8aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c (3278 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf4_f32m1(<vscale x 1 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> poison, <vscale x 1 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(<vscale x 2 x float>, <vscale x 1 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16mf2_f32m1(<vscale x 2 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(<vscale x 2 x float>, <vscale x 2 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m1_f32m1(<vscale x 4 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> poison, <vscale x 4 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(<vscale x 2 x float>, <vscale x 4 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m2_f32m1(<vscale x 8 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 8 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> poison, <vscale x 8 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(<vscale x 2 x float>, <vscale x 8 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m4_f32m1(<vscale x 16 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 16 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> poison, <vscale x 16 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(<vscale x 2 x float>, <vscale x 16 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfwredosum_vs_f16m8_f32m1(<vscale x 32 x half> %vector, <vscale x 2 x float> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 32 x half>, align 2
# |   %scalar.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %vector, ptr %vector.addr, align 2
# |   store <vscale x 2 x float> %scalar, ptr %scalar.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %vector.addr, align 2
# |   %1 = load <vscale x 2 x float>, ptr %scalar.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> poison, <vscale x 32 x half> %0, <vscale x 2 x float> %1, i64 7, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(<vscale x 2 x float>, <vscale x 32 x half>, <vscale x 2 x float>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32mf2_f64m1(<vscale x 1 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 1 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double>, <vscale x 1 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m1_f64m1(<vscale x 2 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 2 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> poison, <vscale x 2 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(<vscale x 1 x double>, <vscale x 2 x float>, <vscale x 1 x double>, i64 immarg, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vfwredosum_vs_f32m2_f64m1(<vscale x 4 x float> %vector, <vscale x 1 x double> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %vector.addr = alloca <vscale x 4 x float>, align 4
# |   %scalar.addr = alloca <vscale x 1 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vector, ptr %vector.addr, align 4
# |   store <vscale x 1 x double> %scalar, ptr %scalar.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vector.addr, align 4
# |   %1 = load <vscale x 1 x double>, ptr %scalar.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> poison, <vscale x 4 x float> %0, <vscale x 1 x double> %1, i64 7, i64 %2)
# |   ret 
# | ...
# `---data was truncated (10240/50516) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000556475fb315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000556475fb00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000556475fb389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc98f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc98f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc98f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc98f231507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000556475f48e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000556475f48c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000556475f2db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000556475bdd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000556475bdcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc98f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc98f2330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc98f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000556475bdccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c (3279 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_i8mf8x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_i8mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_i8mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 4) @test_vlseg4e8ff_v_i8m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 8 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 4) @test_vlseg4e8ff_v_i8m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn
# | declare { target("riscv.vector.tuple", <vscale x 16 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @test_vlseg4e8ff_v_u8mf8x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 1 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @test_vlseg4e8ff_v_u8mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 2 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @test_vlseg4e8ff_v_u8mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %new_vl.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store ptr %new_vl, ptr %new_vl.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load ptr, ptr %new_vl.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %0, i64 %2, i64 3)
# |   %4 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 0
# |   %5 = extractvalue { target("riscv.vector.tuple", <vscale x 4 x i8>, 4), i64 } %3, 1
# |   store i64 %5, ptr %1, align 8
# |   ret target("riscv.vec
# | ...
# `---data was truncated (10240/27595) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005624493e915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005624493e60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005624493e989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc275249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc2752a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc275249a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc275231507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056244937ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056244937ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000562449363b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005624490130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562449012dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc275232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc2752330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc2752330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562449012cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c (3280 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, <vscale x 1 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, <vscale x 2 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, <vscale x 4 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i8> %vs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 8 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i8>, ptr %vs2.addr, align 1
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, <vscale x 8 x i8> %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i8>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i8> %vs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 1 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i8> %vs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 2 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i8> %vs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %vs2.addr = alloca <vscale x 4 x i8>, align 1
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i8> %vs2, ptr %vs2.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i8>, ptr %vs2.addr, align 1
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosy
# | ...
# `---data was truncated (10240/12666) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056164e37115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056164e36e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056164e37189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f5bb8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f5bb8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f5bb8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f5bb8b1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056164e306e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056164e306c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056164e2ebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056164df9b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056164df9add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f5bb8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f5bb8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f5bb8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056164df9acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c (3281 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfhmin -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_f16mf4x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f16mf2x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f16m1x5(ptr noundef %base, <vscale x 4 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 4 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 4 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i64> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei64_v_f32mf2x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f32m1x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei64_v_f64m1x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 6)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @test_vloxseg5ei64_v_i8mf8x5(ptr noundef %base, <vscale x 1 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 1 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 1 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) poison, ptr %0, <vscale x 1 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei64_v_i8mf4x5(ptr noundef %base, <vscale x 2 x i64> %bindex, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bindex.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store <vscale x 2 x i64> %bindex, ptr %bindex.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load <vscale x 2 x i64>, ptr %bindex.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 2 x i64> %1, i64 %2, i64 3)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(targ
# | ...
# `---data was truncated (10240/62071) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000560f7e52515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000560f7e5220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000560f7e52589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f590fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f590faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f590fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f590fa31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000560f7e4bae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000560f7e4bac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000560f7e49fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000560f7e14f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000560f7e14edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f590fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f590fa330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f590fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000560f7e14ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c (3282 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f    -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, i64 %2)
# |   ret <vscale x 1 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, i64 %2)
# |   ret <vscale x 2 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, i64 %2)
# |   ret <vscale x 4 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 8 x bfloat> @test_sf_vfexp_v_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, i64 %2)
# |   ret <vscale x 8 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.sf.vfexp.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 16 x bfloat> @test_sf_vfexp_v_bf16m4_tu(<vscale x 16 x bfloat> %vd, <vscale x 16 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 16 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, i64 %2)
# |   ret <vscale x 16 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x bfloat> @llvm.riscv.sf.vfexp.nxv16bf16.i64(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 32 x bfloat> @test_sf_vfexp_v_bf16m8_tu(<vscale x 32 x bfloat> %vd, <vscale x 32 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 32 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x bfloat>, ptr %vs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, i64 %2)
# |   ret <vscale x 32 x bfloat> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x bfloat> @llvm.riscv.sf.vfexp.nxv32bf16.i64(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 1 x bfloat> @test_sf_vfexp_v_bf16mf4_tum(<vscale x 1 x i1> %vm, <vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 2 x bfloat> @test_sf_vfexp_v_bf16mf2_tum(<vscale x 2 x i1> %vm, <vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local <vscale x 4 x bfloat> @test_sf_vfexp_v_bf16m1_tum(<vscale x 4 x i1> %vm, <vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %0, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i64, i64 
# | ...
# `---data was truncated (10240/27063) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055ee7edf315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055ee7edf00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055ee7edf389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fc570449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fc5704a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fc570449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fc570431507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055ee7ed88e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055ee7ed88c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055ee7ed6db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055ee7ea1d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055ee7ea1cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fc570432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fc5704330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fc5704330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055ee7ea1ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c (3283 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma    -target-feature +zve64x -target-feature +zve64d    -target-feature +experimental-zvzip -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4_tu(<vscale x 1 x half> %vd, <vscale x 2 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x half>, align 2
# |   %vs.addr = alloca <vscale x 2 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half> %0, <vscale x 2 x half> %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(<vscale x 1 x half>, <vscale x 2 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2_tu(<vscale x 2 x half> %vd, <vscale x 4 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x half>, align 2
# |   %vs.addr = alloca <vscale x 4 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half> %0, <vscale x 4 x half> %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(<vscale x 2 x half>, <vscale x 4 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1_tu(<vscale x 4 x half> %vd, <vscale x 8 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x half>, align 2
# |   %vs.addr = alloca <vscale x 8 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half> %0, <vscale x 8 x half> %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(<vscale x 4 x half>, <vscale x 8 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2_tu(<vscale x 8 x half> %vd, <vscale x 16 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x half>, align 2
# |   %vs.addr = alloca <vscale x 16 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 16 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 16 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half> %0, <vscale x 16 x half> %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(<vscale x 8 x half>, <vscale x 16 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4_tu(<vscale x 16 x half> %vd, <vscale x 32 x half> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 16 x half>, align 2
# |   %vs.addr = alloca <vscale x 32 x half>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %vd, ptr %vd.addr, align 2
# |   store <vscale x 32 x half> %vs, ptr %vs.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 32 x half>, ptr %vs.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half> %0, <vscale x 32 x half> %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(<vscale x 16 x half>, <vscale x 32 x half>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2_tu(<vscale x 1 x float> %vd, <vscale x 2 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x float>, align 4
# |   %vs.addr = alloca <vscale x 2 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 2 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 2 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float> %0, <vscale x 2 x float> %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(<vscale x 1 x float>, <vscale x 2 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1_tu(<vscale x 2 x float> %vd, <vscale x 4 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x float>, align 4
# |   %vs.addr = alloca <vscale x 4 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 4 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 4 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float> %0, <vscale x 4 x float> %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(<vscale x 2 x float>, <vscale x 4 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2_tu(<vscale x 4 x float> %vd, <vscale x 8 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x float>, align 4
# |   %vs.addr = alloca <vscale x 8 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 8 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 8 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float> %0, <vscale x 8 x float> %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(<vscale x 4 x float>, <vscale x 8 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4_tu(<vscale x 8 x float> %vd, <vscale x 16 x float> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x float>, align 4
# |   %vs.addr = alloca <vscale x 16 x float>, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %vd, ptr %vd.addr, align 4
# |   store <vscale x 16 x float> %vs, ptr %vs.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %vd.addr, align 4
# |   %1 = load <vscale x 16 x float>, ptr %vs.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float> %0, <vscale x 16 x float> %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(<vscale x 8 x float>, <vscale x 16 x float>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1_tu(<vscale x 1 x double> %vd, <vscale x 2 x double> %vs, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x double>, align 8
# |   %vs.addr = alloca <vscale x 2 x double>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x double> %vd, ptr %vd.addr, align 8
# |   store <vscale x 2 x double> %vs, ptr %vs.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x double>, ptr %vd.addr, align 8
# |   %1 = load <vscale x 2 x double>, ptr %vs.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x double> @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, i64 %2)
# |   ret <vscale x 1 x double> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscal
# | ...
# `---data was truncated (10240/44426) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055c334cee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055c334ceb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055c334cee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f7bc801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f7bc80725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f7bc801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f7bc8003507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055c334c83e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055c334c83c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055c334c68b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055c3349180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055c334917dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f7bc8004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f7bc80050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f7bc80050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055c334917cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c (3284 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %0, ptr %1, <vscale x 1 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, ptr %1, <vscale x 2 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %0, ptr %1, <vscale x 4 x i64> %2, i64 %3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr captures(none), <vscale x 4 x i64>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @test_vloxseg7ei64_v_bf16mf4x7_tum(<vscale x 1 x i1> %vm, target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 1 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 1 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %1, ptr %2, <vscale x 1 x i64> %3, <vscale x 1 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr captures(none), <vscale x 1 x i64>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @test_vloxseg7ei64_v_bf16mf2x7_tum(<vscale x 2 x i1> %vm, target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 2 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 2 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %1, ptr %2, <vscale x 2 x i64> %3, <vscale x 2 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr captures(none), <vscale x 2 x i64>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @test_vloxseg7ei64_v_bf16m1x7_tum(<vscale x 4 x i1> %vm, target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr noundef %rs1, <vscale x 4 x i64> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %vd.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 7), align 2
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i64>, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %vd, ptr %vd.addr, align 2
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i64> %rs2, ptr %rs2.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr %vd.addr, align 2
# |   %2 = load ptr, ptr %rs1.addr, align 8
# |   %3 = load <vscale x 4 x i64>, ptr %rs2.addr, align 8
# |   %4 = load i64, ptr %vl.addr, align 8
# |   %5 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %1, ptr %2, <vscale x 4 x i64> %3, <vscale x 4 x i1> %0, i64 %4, i64 2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %5
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64
# | ...
# `---data was truncated (10240/19582) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055da0ddd015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055da0ddcd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055da0ddd089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f483c105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f483c15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f483c105a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f483c0ed507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055da0dd65e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055da0dd65c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055da0dd4ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055da0d9fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055da0d9f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f483c0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f483c0ef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f483c0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055da0d9f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c (3285 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v    -target-feature +experimental-zvfbfa -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vv_bf16mf4_tu(<vscale x 1 x bfloat> %vd, <vscale x 1 x bfloat> %vs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 1 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 1 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x bfloat> @test_vfmsac_vf_bf16mf4_tu(<vscale x 1 x bfloat> %vd, bfloat noundef %rs1, <vscale x 1 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 1 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 1 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 1 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 1 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(<vscale x 1 x bfloat>, bfloat, <vscale x 1 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vv_bf16mf2_tu(<vscale x 2 x bfloat> %vd, <vscale x 2 x bfloat> %vs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 2 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 2 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x bfloat> @test_vfmsac_vf_bf16mf2_tu(<vscale x 2 x bfloat> %vd, bfloat noundef %rs1, <vscale x 2 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 2 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 2 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 2 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 2 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(<vscale x 2 x bfloat>, bfloat, <vscale x 2 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vv_bf16m1_tu(<vscale x 4 x bfloat> %vd, <vscale x 4 x bfloat> %vs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 4 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 4 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x bfloat> @test_vfmsac_vf_bf16m1_tu(<vscale x 4 x bfloat> %vd, bfloat noundef %rs1, <vscale x 4 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 4 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 4 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 4 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 4 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(<vscale x 4 x bfloat>, bfloat, <vscale x 4 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vv_bf16m2_tu(<vscale x 8 x bfloat> %vd, <vscale x 8 x bfloat> %vs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs1.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store <vscale x 8 x bfloat> %vs1, ptr %vs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load <vscale x 8 x bfloat>, ptr %vs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 8 x bfloat> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i64 immarg, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x bfloat> @test_vfmsac_vf_bf16m2_tu(<vscale x 8 x bfloat> %vd, bfloat noundef %rs1, <vscale x 8 x bfloat> %vs2, i64 noundef %vl) #0 {
# | entry:
# |   %vd.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %rs1.addr = alloca bfloat, align 2
# |   %vs2.addr = alloca <vscale x 8 x bfloat>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x bfloat> %vd, ptr %vd.addr, align 2
# |   store bfloat %rs1, ptr %rs1.addr, align 2
# |   store <vscale x 8 x bfloat> %vs2, ptr %vs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x bfloat>, ptr %vd.addr, align 2
# |   %1 = load bfloat, ptr %rs1.addr, align 2
# |   %2 = load <vscale x 8 x bfloat>, ptr %vs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16.i64(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, i64 7, i64 %3, i64 2)
# |   ret <vscale x 
# | ...
# `---data was truncated (10240/64244) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055b6c05dd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b6c05da0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b6c05dd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fabba133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fabba18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fabba133a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fabba11b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b6c0572e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b6c0572c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b6c0557b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b6c02070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b6c0206dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fabba11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fabba11d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fabba11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b6c0206cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c (3286 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_i8m4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf8x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf4x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8mf2x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg2e8_v_u8m1x2(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %
# | ...
# `---data was truncated (10240/27994) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000561396aee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000561396aeb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000561396aee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f60a3e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f60a3e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f60a3e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f60a3e03507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000561396a83e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000561396a83c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000561396a68b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005613967180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000561396717dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f60a3e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f60a3e050d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f60a3e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000561396717cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c (3287 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
# | declare target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @test_vlseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @test_vlseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @test_vlseg2e32_v_i32m4x2_tu(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 4
# |   %base.addr = alloca ptr, align 8
# |   %vl.addr = alloca i64, align 8
# |   store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %maskedoff_tuple.addr, align 4
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x
# | ...
# `---data was truncated (10240/63177) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005641e265815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005641e26550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005641e265889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f780dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f780dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f780dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f780dd1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005641e25ede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005641e25edc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005641e25d2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005641e22820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005641e2281dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f780dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f780dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f780dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005641e2281cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGenCXX/virtual-base-ctor.cpp (3288 of 27911)
******************** TEST 'Clang :: CodeGenCXX/virtual-base-ctor.cpp' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 1
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp -emit-llvm -triple x86_64-unknown-linux-gnu -o - -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp -emit-llvm -triple x86_64-unknown-linux-gnu -o - -O2
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp"
# | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
# | target triple = "x86_64-unknown-linux-gnu"
# | 
# | %struct.B = type { ptr, ptr, %struct.A }
# | %struct.A = type { i32 }
# | 
# | $_ZTV1B = comdat any
# | 
# | $_ZTI1B = comdat any
# | 
# | $_ZTS1B = comdat any
# | 
# | $_ZTI1A = comdat any
# | 
# | $_ZTS1A = comdat any
# | 
# | @y = local_unnamed_addr global i8 2, align 1
# | @x = local_unnamed_addr global %struct.B { ptr getelementptr inbounds inrange(-24, 0) (i8, ptr @_ZTV1B, i64 24), ptr null, %struct.A zeroinitializer }, align 8
# | @_ZTV1B = linkonce_odr constant { [3 x ptr] } { [3 x ptr] [ptr inttoptr (i64 16 to ptr), ptr null, ptr @_ZTI1B] }, comdat, align 8
# | @_ZTI1B = linkonce_odr constant { ptr, ptr, i32, i32, ptr, i64 } { ptr getelementptr inbounds (i8, ptr @_ZTVN10__cxxabiv121__vmi_class_type_infoE, i64 16), ptr @_ZTS1B, i32 0, i32 1, ptr @_ZTI1A, i64 -6141 }, comdat, align 8
# | @_ZTVN10__cxxabiv121__vmi_class_type_infoE = external global [0 x ptr]
# | @_ZTS1B = linkonce_odr constant [3 x i8] c"1B\00", comdat, align 1
# | @_ZTI1A = linkonce_odr constant { ptr, ptr } { ptr getelementptr inbounds (i8, ptr @_ZTVN10__cxxabiv117__class_type_infoE, i64 16), ptr @_ZTS1A }, comdat, align 8
# | @_ZTVN10__cxxabiv117__class_type_infoE = external global [0 x ptr]
# | @_ZTS1A = linkonce_odr constant [3 x i8] c"1A\00", comdat, align 1
# | @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer
# | 
# | !llvm.ident = !{!0}
# | !llvm.errno.tbaa = !{!1}
# | 
# | !0 = !{!"clang version 24.0.0"}
# | !1 = !{!2, !3, i64 0}
# | !2 = !{!"__libc_errno", !3, i64 0}
# | !3 = !{!"int", !4, i64 0}
# | !4 = !{!"omnipotent char", !5, i64 0}
# | !5 = !{!"Simple C++ TBAA"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o -
# |  #0 0x000055b3791e315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055b3791e00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055b3791e389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f63de533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f63de58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f63de533a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f63de51b507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055b379178e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055b379178c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055b37915db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055b378e0d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055b378e0cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f63de51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f63de51d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f63de51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055b378e0ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c (3289 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3(ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 8 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 8 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, ptr %0, <vscale x 8 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), <vscale x 8 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @test_vloxseg3ei16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @test_vloxseg3ei16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @test_vloxseg3ei16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @test_vloxseg3ei16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, <vscale x 8 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 8 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %vm, ptr %vm
# | ...
# `---data was truncated (10240/11863) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005584507af15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005584507ac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005584507af89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f267dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f267dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f267dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f267dc31507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000558450744e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000558450744c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000558450729b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005584503d90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005584503d8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f267dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f267dc330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f267dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005584503d8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c (3290 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 1 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 1 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 1 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(<vscale x 8 x i8>, <vscale x 1 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 2 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 2 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 2 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(<vscale x 8 x i8>, <vscale x 2 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8mf2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 4 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 4 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 4 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(<vscale x 8 x i8>, <vscale x 4 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m1_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 8 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 8 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 8 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m2_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 16 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 16 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 16 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 16 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(<vscale x 8 x i8>, <vscale x 16 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m4_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 32 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 32 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 32 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 32 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(<vscale x 8 x i8>, <vscale x 32 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i8> @test_vredmin_vs_i8m8_i8m1_tu(<vscale x 8 x i8> %maskedoff, <vscale x 64 x i8> %vector, <vscale x 8 x i8> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 8 x i8>, align 1
# |   %vector.addr = alloca <vscale x 64 x i8>, align 1
# |   %scalar.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %maskedoff, ptr %maskedoff.addr, align 1
# |   store <vscale x 64 x i8> %vector, ptr %vector.addr, align 1
# |   store <vscale x 8 x i8> %scalar, ptr %scalar.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %maskedoff.addr, align 1
# |   %1 = load <vscale x 64 x i8>, ptr %vector.addr, align 1
# |   %2 = load <vscale x 8 x i8>, ptr %scalar.addr, align 1
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8> %0, <vscale x 64 x i8> %1, <vscale x 8 x i8> %2, i64 %3)
# |   ret <vscale x 8 x i8> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(<vscale x 8 x i8>, <vscale x 64 x i8>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i16> @test_vredmin_vs_i16mf4_i16m1_tu(<vscale x 4 x i16> %maskedoff, <vscale x 1 x i16> %vector, <vscale x 4 x i16> %scalar, i64 noundef %vl) #0 {
# | entry:
# |   %maskedoff.addr = alloca <vscale x 4 x i16>, align 2
# |   %vector.addr = alloca <vscale x 1 x i16>, align 2
# |   %scalar.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i16> %maskedoff, ptr %maskedoff.addr, align 2
# |   store <vscale x 1 x i16> %vector, ptr %vector.addr, align 2
# |   store <vscale x 4 x i16> %scalar, ptr %scalar.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i16>, ptr %maskedoff.addr, align 2
# |   %1 = load <vscale x 1 x i16>, ptr %vector.addr, align 2
# |   %2 = load <vscale x 4 x i16>, ptr %scalar.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3)
# |   ret <vscale x 4 x i16> %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willretu
# | ...
# `---data was truncated (10240/61937) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005606bcbc015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005606bcbbd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005606bcbc089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fb6b0b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fb6b0b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fb6b0b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fb6b0aed507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005606bcb55e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005606bcb55c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005606bcb3ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005606bc7ea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005606bc7e9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fb6b0aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fb6b0aef0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fb6b0aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005606bc7e9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c (3291 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1(<vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %0, i64 %1)
# |   ret <vscale x 1 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2(<vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %0, i64 %1)
# |   ret <vscale x 2 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4(<vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %0, i64 %1)
# |   ret <vscale x 4 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8(<vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %1 = load i64, ptr %vl.addr, align 8
# |   %2 = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %0, i64 %1)
# |   ret <vscale x 8 x i64> %2
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i64> @test_vzext_vf8_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %op1.addr = alloca <vscale x 1 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 1 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 1 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> poison, <vscale x 1 x i8> %1, <vscale x 1 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 1 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>, <vscale x 1 x i8>, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i64> @test_vzext_vf8_u64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %op1.addr = alloca <vscale x 2 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 2 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 2 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> poison, <vscale x 2 x i8> %1, <vscale x 2 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 2 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>, <vscale x 2 x i8>, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i64> @test_vzext_vf8_u64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 4 x i1>, align 1
# |   %op1.addr = alloca <vscale x 4 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 4 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 4 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> poison, <vscale x 4 x i8> %1, <vscale x 4 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 4 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i64> @test_vzext_vf8_u64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 8 x i1>, align 1
# |   %op1.addr = alloca <vscale x 8 x i8>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %mask, ptr %mask.addr, align 1
# |   store <vscale x 8 x i8> %op1, ptr %op1.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %mask.addr, align 1
# |   %1 = load <vscale x 8 x i8>, ptr %op1.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> poison, <vscale x 8 x i8> %1, <vscale x 8 x i1> %0, i64 %2, i64 3)
# |   ret <vscale x 8 x i64> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>, <vscale x 8 x i8>, <vscale x 8 x i1>, i64, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x0000563953f5515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x0000563953f520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x0000563953f5589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007ff1aa733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007ff1aa78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007ff1aa733a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007ff1aa71b507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000563953eeae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000563953eeac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x0000563953ecfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000563953b7f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000563953b7edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007ff1aa71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007ff1aa71d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007ff1aa71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000563953b7ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c (3292 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load i64, ptr %rs2.addr, align 8
# |   %2 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %vs3.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %2, ptr %0, i64 %1, i64 %3, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf4x3_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16mf2x3_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m1x3_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store i64 %rs2, ptr %rs2.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %vs3, ptr %vs3.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load i64, ptr %rs2.addr, align 8
# |   %3 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %vs3.addr, align 2
# |   %4 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr %1, i64 %2, <vscale x 4 x i1> %0, i64 %4, i64 4)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
# | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, <vscale x 4 x i1>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local void @test_vssseg3e16_v_bf16m2x3_m(<vscale x 8 x i1> %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %vs3, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 8 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca i64, align 8
# |   %vs3.addr = alloca target("risc
# | ...
# `---data was truncated (10240/11912) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005629040b215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005629040af0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005629040b289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f9b4c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f9b4c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f9b4c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f9b4c431507 abort ./stdlib/abort.c:85:3
# |  #7 0x0000562904047e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x0000562904047c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056290402cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x0000562903cdc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x0000562903cdbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f9b4c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f9b4c4330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f9b4c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x0000562903cdbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c (3293 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load i64, ptr %bstride.addr, align 8
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, i64 %1, i64 %2, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_f32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), i64, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_f32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 2 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), i64, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vlsseg5e32_v_i32mf2x5_m(<vscale x 1 x i1> %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 {
# | entry:
# |   %mask.addr = alloca <vscale x 1 x i1>, align 1
# |   %base.addr = alloca ptr, align 8
# |   %bstride.addr = alloca i64, align 8
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %mask, ptr %mask.addr, align 1
# |   store ptr %base, ptr %base.addr, align 8
# |   store i64 %bstride, ptr %bstride.addr, align 8
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %mask.addr, align 1
# |   %1 = load ptr, ptr %base.addr, align 8
# |   %2 = load i64, ptr %bstride.addr, align 8
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, i64 %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 5)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vlsseg5e32_v_i32m1x5_m(<vscale x 2 x i1> %mask, ptr noundef %
# | ...
# `---data was truncated (10240/14001) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000056417a89215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000056417a88f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000056417a89289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fda7de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fda7dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fda7de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fda7de31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000056417a827e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000056417a827c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000056417a80cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000056417a4bc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000056417a4bbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fda7de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fda7de330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fda7de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000056417a4bbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c (3294 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x half> @test_vfslide1down_vf_f16mf4(<vscale x 1 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half> poison, <vscale x 1 x half> %0, half %1, i64 %2)
# |   ret <vscale x 1 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16.i64(<vscale x 1 x half>, <vscale x 1 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x half> @test_vfslide1down_vf_f16mf2(<vscale x 2 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half> poison, <vscale x 2 x half> %0, half %1, i64 %2)
# |   ret <vscale x 2 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16.i64(<vscale x 2 x half>, <vscale x 2 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x half> @test_vfslide1down_vf_f16m1(<vscale x 4 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> %0, half %1, i64 %2)
# |   ret <vscale x 4 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16.i64(<vscale x 4 x half>, <vscale x 4 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x half> @test_vfslide1down_vf_f16m2(<vscale x 8 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half> poison, <vscale x 8 x half> %0, half %1, i64 %2)
# |   ret <vscale x 8 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16.i64(<vscale x 8 x half>, <vscale x 8 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x half> @test_vfslide1down_vf_f16m4(<vscale x 16 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 16 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half> poison, <vscale x 16 x half> %0, half %1, i64 %2)
# |   ret <vscale x 16 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16.i64(<vscale x 16 x half>, <vscale x 16 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x half> @test_vfslide1down_vf_f16m8(<vscale x 32 x half> %src, half noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 32 x half>, align 2
# |   %value.addr = alloca half, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x half> %src, ptr %src.addr, align 2
# |   store half %value, ptr %value.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x half>, ptr %src.addr, align 2
# |   %1 = load half, ptr %value.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half> poison, <vscale x 32 x half> %0, half %1, i64 %2)
# |   ret <vscale x 32 x half> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16.i64(<vscale x 32 x half>, <vscale x 32 x half>, half, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x float> @test_vfslide1down_vf_f32mf2(<vscale x 1 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 1 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float> poison, <vscale x 1 x float> %0, float %1, i64 %2)
# |   ret <vscale x 1 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32.i64(<vscale x 1 x float>, <vscale x 1 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x float> @test_vfslide1down_vf_f32m1(<vscale x 2 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 2 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> %0, float %1, i64 %2)
# |   ret <vscale x 2 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x float> @test_vfslide1down_vf_f32m2(<vscale x 4 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 4 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float> poison, <vscale x 4 x float> %0, float %1, i64 %2)
# |   ret <vscale x 4 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32.i64(<vscale x 4 x float>, <vscale x 4 x float>, float, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x float> @test_vfslide1down_vf_f32m4(<vscale x 8 x float> %src, float noundef %value, i64 noundef %vl) #0 {
# | entry:
# |   %src.addr = alloca <vscale x 8 x float>, align 4
# |   %value.addr = alloca float, align 4
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x float> %src, ptr %src.addr, align 4
# |   store float %value, ptr %value.addr, align 4
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x float>, ptr %src.addr, align 4
# |   %1 = load float, ptr %value.addr, align 4
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float> poison, <vscale x 8 x float> %0, float %1, i64 %2)
# |   ret <vscale x 8 x float> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32.i64(<vscale x 8 x float>, <vscale x 8 x float>, flo
# | ...
# `---data was truncated (10240/34773) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055bbfef1215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055bbfef0f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055bbfef1289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fbc6c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fbc6c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fbc6c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fbc6c031507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055bbfeea7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055bbfeea7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055bbfee8cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055bbfeb3c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055bbfeb3bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fbc6c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fbc6c0330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fbc6c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055bbfeb3bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c (3295 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh    -target-feature +zvfh -disable-O0-optnone     -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_i8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
# | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr captures(none), i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf8x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 1 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf4x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 2 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8mf2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 4 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m1x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %1, ptr %0, i64 %2, i64 3)
# |   ret void
# | }
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local void @test_vsseg3e8_v_u8m2x3(ptr noundef %base, target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, i64 noundef %vl) #0 {
# | entry:
# |   %base.addr = alloca ptr, align 8
# |   %v_tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 3), align 1
# |   %vl.addr = alloca i64, align 8
# |   store ptr %base, ptr %base.addr, align 8
# |   store target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %v_tuple, ptr %v_tuple.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %base.addr, align 8
# |   %1 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr %v_tuple.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   cal
# | ...
# `---data was truncated (10240/23487) (change limit with -D output_limit=N)
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x00005638b5d6515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x00005638b5d620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x00005638b5d6589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007efc51f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007efc51f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007efc51f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007efc51f1b507 abort ./stdlib/abort.c:85:3
# |  #7 0x00005638b5cfae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x00005638b5cfac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x00005638b5cdfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x00005638b598f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x00005638b598edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007efc51f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007efc51f1d0d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007efc51f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x00005638b598ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c (3296 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 64 x i1> @test_vmorn_mm_b1(<vscale x 64 x i1> %op1, <vscale x 64 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 64 x i1>, align 1
# |   %op2.addr = alloca <vscale x 64 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 64 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 64 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 64 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 64 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2)
# |   ret <vscale x 64 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 64 x i1> @llvm.riscv.vmorn.nxv64i1.i64(<vscale x 64 x i1>, <vscale x 64 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 32 x i1> @test_vmorn_mm_b2(<vscale x 32 x i1> %op1, <vscale x 32 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 32 x i1>, align 1
# |   %op2.addr = alloca <vscale x 32 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 32 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 32 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 32 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 32 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2)
# |   ret <vscale x 32 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 32 x i1> @llvm.riscv.vmorn.nxv32i1.i64(<vscale x 32 x i1>, <vscale x 32 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 16 x i1> @test_vmorn_mm_b4(<vscale x 16 x i1> %op1, <vscale x 16 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 16 x i1>, align 1
# |   %op2.addr = alloca <vscale x 16 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 16 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 16 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 16 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 16 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2)
# |   ret <vscale x 16 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 16 x i1> @llvm.riscv.vmorn.nxv16i1.i64(<vscale x 16 x i1>, <vscale x 16 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 8 x i1> @test_vmorn_mm_b8(<vscale x 8 x i1> %op1, <vscale x 8 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 8 x i1>, align 1
# |   %op2.addr = alloca <vscale x 8 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 8 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 8 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 8 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 8 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2)
# |   ret <vscale x 8 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 8 x i1> @llvm.riscv.vmorn.nxv8i1.i64(<vscale x 8 x i1>, <vscale x 8 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 4 x i1> @test_vmorn_mm_b16(<vscale x 4 x i1> %op1, <vscale x 4 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 4 x i1>, align 1
# |   %op2.addr = alloca <vscale x 4 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 4 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 4 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2)
# |   ret <vscale x 4 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 4 x i1> @llvm.riscv.vmorn.nxv4i1.i64(<vscale x 4 x i1>, <vscale x 4 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 2 x i1> @test_vmorn_mm_b32(<vscale x 2 x i1> %op1, <vscale x 2 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 2 x i1>, align 1
# |   %op2.addr = alloca <vscale x 2 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 2 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 2 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2)
# |   ret <vscale x 2 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 2 x i1> @llvm.riscv.vmorn.nxv2i1.i64(<vscale x 2 x i1>, <vscale x 2 x i1>, i64) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(2,1024)
# | define dso_local <vscale x 1 x i1> @test_vmorn_mm_b64(<vscale x 1 x i1> %op1, <vscale x 1 x i1> %op2, i64 noundef %vl) #0 {
# | entry:
# |   %op1.addr = alloca <vscale x 1 x i1>, align 1
# |   %op2.addr = alloca <vscale x 1 x i1>, align 1
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %op1, ptr %op1.addr, align 1
# |   store <vscale x 1 x i1> %op2, ptr %op2.addr, align 1
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %op1.addr, align 1
# |   %1 = load <vscale x 1 x i1>, ptr %op2.addr, align 1
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2)
# |   ret <vscale x 1 x i1> %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
# | declare <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1.i64(<vscale x 1 x i1>, <vscale x 1 x i1>, i64) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64d"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055cb622a315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055cb622a00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055cb622a389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007fd6a5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007fd6a56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007fd6a5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007fd6a5631507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055cb62238e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055cb62238c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055cb6221db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055cb61ecd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055cb61eccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007fd6a5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007fd6a56330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007fd6a56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055cb61ecccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.
FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c (3613 of 27911)
******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c' FAILED ********************
Exit Code: 2

Command Output (stdout):
--
# RUN: at line 3
/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x    -target-feature +zvfbfmin -disable-O0-optnone    -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg |    /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c -o -
# .---command stdout------------
# | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c'
# | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c"
# | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
# | target triple = "riscv64"
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %0, <vscale x 1 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %0, <vscale x 2 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5(ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load ptr, ptr %rs1.addr, align 8
# |   %1 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %2 = load i64, ptr %vl.addr, align 8
# |   %3 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %0, <vscale x 4 x i16> %1, i64 %2, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %3
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, i64, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @test_vloxseg5ei16_v_bf16mf4x5_m(<vscale x 1 x i1> %vm, ptr noundef %rs1, <vscale x 1 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 1 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 1 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 1 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 1 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 1 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 1 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) poison, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr captures(none), <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @test_vloxseg5ei16_v_bf16mf2x5_m(<vscale x 2 x i1> %vm, ptr noundef %rs1, <vscale x 2 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 2 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 2 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 2 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 2 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 2 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 2 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr captures(none), <vscale x 2 x i16>, <vscale x 2 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | ; Function Attrs: noinline nounwind vscale_range(1,1024)
# | define dso_local target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @test_vloxseg5ei16_v_bf16m1x5_m(<vscale x 4 x i1> %vm, ptr noundef %rs1, <vscale x 4 x i16> %rs2, i64 noundef %vl) #0 {
# | entry:
# |   %vm.addr = alloca <vscale x 4 x i1>, align 1
# |   %rs1.addr = alloca ptr, align 8
# |   %rs2.addr = alloca <vscale x 4 x i16>, align 2
# |   %vl.addr = alloca i64, align 8
# |   store <vscale x 4 x i1> %vm, ptr %vm.addr, align 1
# |   store ptr %rs1, ptr %rs1.addr, align 8
# |   store <vscale x 4 x i16> %rs2, ptr %rs2.addr, align 2
# |   store i64 %vl, ptr %vl.addr, align 8
# |   %0 = load <vscale x 4 x i1>, ptr %vm.addr, align 1
# |   %1 = load ptr, ptr %rs1.addr, align 8
# |   %2 = load <vscale x 4 x i16>, ptr %rs2.addr, align 2
# |   %3 = load i64, ptr %vl.addr, align 8
# |   %4 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) poison, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %0, i64 %3, i64 3, i64 4)
# |   ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %4
# | }
# | 
# | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
# | declare target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr captures(none), <vscale x 4 x i16>, <vscale x 4 x i1>, i64, i64 immarg, i64 immarg) #1
# | 
# | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" }
# | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
# | 
# | !llvm.module.flags = !{!0, !1, !3}
# | !llvm.ident = !{!4}
# | 
# | !0 = !{i32 1, !"target-abi", !"lp64f"}
# | !1 = !{i32 6, !"riscv-isa", !2}
# | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"}
# | !3 = !{i32 8, !"SmallDataLimit", i32 0}
# | !4 = !{!"clang version 24.0.0"}
# `-----------------------------
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# .---command stderr------------
# | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once!
# | LLVM ERROR: inconsistency in registered CommandLine options
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
# | Stack dump:
# | 0.	Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg
# |  #0 0x000055a48815815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b)
# |  #1 0x000055a4881550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5)
# |  #2 0x000055a48815889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
# |  #3 0x00007f0244a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70)
# |  #4 0x00007f0244aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76
# |  #5 0x00007f0244a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6
# |  #6 0x00007f0244a31507 abort ./stdlib/abort.c:85:3
# |  #7 0x000055a4880ede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d)
# |  #8 0x000055a4880edc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76)
# |  #9 0x000055a4880d2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29)
# | #10 0x000055a487d820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6)
# | #11 0x000055a487d81dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3)
# | #12 0x00007f0244a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3
# | #13 0x00007f0244a330d7 call_init ./csu/../csu/libc-start.c:128:20
# | #14 0x00007f0244a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5
# | #15 0x000055a487d81cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1)
# `-----------------------------
# error: command failed with exit status: -6
# executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
# .---command stderr------------
# | FileCheck error: '<stdin>' is empty.
# | FileCheck command line:  /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
# `-----------------------------
# error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90..
********************
Failed Tests (3297):
  Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c
  Clang :: CodeGen/2005-09-24-AsmUserPrefix.c
  Clang :: CodeGen/2008-07-17-no-emit-on-error.c
  Clang :: CodeGen/AArch64/atomic-hint-template.cpp
  Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c
  Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c
  Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c
  Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c
  Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c
  Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c
  Clang :: CodeGen/AArch64/fp8-cast.c
  Clang :: CodeGen/AArch64/fp8-extract.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
  Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c
  Clang :: CodeGen/AArch64/neon-2velem.c
  Clang :: CodeGen/AArch64/neon-3v.c
  Clang :: CodeGen/AArch64/neon-dot-product.c
  Clang :: CodeGen/AArch64/neon-extract.c
  Clang :: CodeGen/AArch64/neon-fma.c
  Clang :: CodeGen/AArch64/neon-fp16fml.c
  Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c
  Clang :: CodeGen/AArch64/neon-intrinsics.c
  Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c
  Clang :: CodeGen/AArch64/neon-misc-constrained.c
  Clang :: CodeGen/AArch64/neon-misc.c
  Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c
  Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c
  Clang :: CodeGen/AArch64/neon-shifts.c
  Clang :: CodeGen/AArch64/neon-tbl.c
  Clang :: CodeGen/AArch64/neon-vcmla.c
  Clang :: CodeGen/AArch64/neon-vcombine.c
  Clang :: CodeGen/AArch64/neon-vget-hilo.c
  Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c
  Clang :: CodeGen/AArch64/neon/add.c
  Clang :: CodeGen/AArch64/neon/bf16-getset.c
  Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c
  Clang :: CodeGen/AArch64/neon/f16-getset.c
  Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c
  Clang :: CodeGen/AArch64/neon/fullfp16.c
  Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c
  Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c
  Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c
  Clang :: CodeGen/AArch64/neon/fused-multiply.c
  Clang :: CodeGen/AArch64/neon/getset.c
  Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c
  Clang :: CodeGen/AArch64/neon/intrinsics.c
  Clang :: CodeGen/AArch64/neon/load.c
  Clang :: CodeGen/AArch64/neon/perm.c
  Clang :: CodeGen/AArch64/neon/rounding-v8.5.c
  Clang :: CodeGen/AArch64/neon/rounding.c
  Clang :: CodeGen/AArch64/neon/store.c
  Clang :: CodeGen/AArch64/neon/subtraction.c
  Clang :: CodeGen/AArch64/neon/vpaddl.c
  Clang :: CodeGen/AArch64/neon/widen.c
  Clang :: CodeGen/AArch64/poly128.c
  Clang :: CodeGen/AArch64/poly64.c
  Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
  Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c
  Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c
  Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c
  Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c
  Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c
  Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c
  Clang :: CodeGen/AArch64/sve-vector-arith-ops.c
  Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c
  Clang :: CodeGen/AArch64/sve-vector-compare-ops.c
  Clang :: CodeGen/AArch64/sve-vector-shift-ops.c
  Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c
  Clang :: CodeGen/AArch64/sve-vls-arith-ops.c
  Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c
  Clang :: CodeGen/AArch64/sve-vls-compare-ops.c
  Clang :: CodeGen/AArch64/sve-vls-shift-ops.c
  Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c
  Clang :: CodeGen/AArch64/sve/addv.c
  Clang :: CodeGen/AArch64/sve/andv.c
  Clang :: CodeGen/AArch64/sve/dup.c
  Clang :: CodeGen/AArch64/sve/eorv.c
  Clang :: CodeGen/AArch64/sve/len.c
  Clang :: CodeGen/AArch64/sve/maxnmv.c
  Clang :: CodeGen/AArch64/sve/maxv.c
  Clang :: CodeGen/AArch64/sve/minnmv.c
  Clang :: CodeGen/AArch64/sve/minv.c
  Clang :: CodeGen/AArch64/sve/nand.c
  Clang :: CodeGen/AArch64/sve/nor.c
  Clang :: CodeGen/AArch64/sve/orn.c
  Clang :: CodeGen/AArch64/sve/orv.c
  Clang :: CodeGen/AArch64/sve/pfalse.c
  Clang :: CodeGen/AArch64/sve/recpe.c
  Clang :: CodeGen/AArch64/sve/recps.c
  Clang :: CodeGen/AArch64/sve/rsqrte.c
  Clang :: CodeGen/AArch64/sve/rsqrts.c
  Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c
  Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c
  Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c
  Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c
  Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c
  Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c
  Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
  Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c
  Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c
  Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c
  Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c
  Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c
  Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c
  Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c
  Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c
  Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c
  Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c
  Clang :: CodeGen/RISCV/builtin-cpu-is.c
  Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c
  Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c
  Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c
  Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c
  Clang :: CodeGen/RISCV/riscv-xcvalu.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c
  Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c
  Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c
  Clang :: CodeGen/RISCV/rvp-intrinsics.c
  Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
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  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
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  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
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  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
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  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
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  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
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  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
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  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
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  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
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  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
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  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c
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  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
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  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
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  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c
  Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c
  Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c
  Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c
  Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c
  Clang :: CodeGen/SystemZ/zvector.c
  Clang :: CodeGen/WebAssembly/builtins-table-externref.c
  Clang :: CodeGen/WebAssembly/builtins-table-funcref.c
  Clang :: CodeGen/X86/avx-cmp-builtins.c
  Clang :: CodeGen/X86/avx-shuffle-builtins.c
  Clang :: CodeGen/X86/bfloat16-convert-half.c
  Clang :: CodeGen/X86/sse.c
  Clang :: CodeGen/aapcs-bitfield.c
  Clang :: CodeGen/arm-bf16-convert-intrinsics.c
  Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c
  Clang :: CodeGen/arm-bf16-params-returns.c
  Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c
  Clang :: CodeGen/arm-cde-gpr.c
  Clang :: CodeGen/arm-cde-reinterpret.c
  Clang :: CodeGen/arm-cde-vec.c
  Clang :: CodeGen/arm-cde-vfp.c
  Clang :: CodeGen/arm-crc32.c
  Clang :: CodeGen/arm-mfp8.c
  Clang :: CodeGen/arm-mve-intrinsics/absneg.c
  Clang :: CodeGen/arm-mve-intrinsics/admin.c
  Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c
  Clang :: CodeGen/arm-mve-intrinsics/compare.c
  Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp
  Clang :: CodeGen/arm-mve-intrinsics/dup.c
  Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c
  Clang :: CodeGen/arm-mve-intrinsics/idup.c
  Clang :: CodeGen/arm-mve-intrinsics/load-store.c
  Clang :: CodeGen/arm-mve-intrinsics/predicates.c
  Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c
  Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c
  Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c
  Clang :: CodeGen/arm-mve-intrinsics/ternary.c
  Clang :: CodeGen/arm-mve-intrinsics/vabavq.c
  Clang :: CodeGen/arm-mve-intrinsics/vabdq.c
  Clang :: CodeGen/arm-mve-intrinsics/vadc.c
  Clang :: CodeGen/arm-mve-intrinsics/vaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vaddv.c
  Clang :: CodeGen/arm-mve-intrinsics/vandq.c
  Clang :: CodeGen/arm-mve-intrinsics/vbicq.c
  Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c
  Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vclz.c
  Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c
  Clang :: CodeGen/arm-mve-intrinsics/vcvt.c
  Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c
  Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c
  Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c
  Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c
  Clang :: CodeGen/arm-mve-intrinsics/veorq.c
  Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c
  Clang :: CodeGen/arm-mve-intrinsics/vld24.c
  Clang :: CodeGen/arm-mve-intrinsics/vldr.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminq.c
  Clang :: CodeGen/arm-mve-intrinsics/vminvq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmldav.c
  Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c
  Clang :: CodeGen/arm-mve-intrinsics/vmovl.c
  Clang :: CodeGen/arm-mve-intrinsics/vmovn.c
  Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c
  Clang :: CodeGen/arm-mve-intrinsics/vmulq.c
  Clang :: CodeGen/arm-mve-intrinsics/vornq.c
  Clang :: CodeGen/arm-mve-intrinsics/vorrq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c
  Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c
  Clang :: CodeGen/arm-mve-intrinsics/vrev.c
  Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c
  Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c
  Clang :: CodeGen/arm-mve-intrinsics/vrnd.c
  Clang :: CodeGen/arm-mve-intrinsics/vshlc.c
  Clang :: CodeGen/arm-mve-intrinsics/vsubq.c
  Clang :: CodeGen/arm-neon-directed-rounding-constrained.c
  Clang :: CodeGen/arm-neon-directed-rounding.c
  Clang :: CodeGen/arm-neon-dot-product.c
  Clang :: CodeGen/arm-neon-endianness.c
  Clang :: CodeGen/arm-neon-fma.c
  Clang :: CodeGen/arm-neon-numeric-maxmin.c
  Clang :: CodeGen/arm-neon-shifts.c
  Clang :: CodeGen/arm-neon-vcadd.c
  Clang :: CodeGen/arm-neon-vcvtX.c
  Clang :: CodeGen/arm-neon-vget.c
  Clang :: CodeGen/arm-neon-vld.c
  Clang :: CodeGen/arm-neon-vst.c
  Clang :: CodeGen/arm-poly-add.c
  Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c
  Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c
  Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c
  Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c
  Clang :: CodeGen/arm-vector_type-params-returns.c
  Clang :: CodeGen/arm64-crc32.c
  Clang :: CodeGen/arm64-lanes.c
  Clang :: CodeGen/arm64_vcopy.c
  Clang :: CodeGen/arm64_vcreate.c
  Clang :: CodeGen/arm64_vdupq_n_f64.c
  Clang :: CodeGen/arm_acle.c
  Clang :: CodeGen/arm_acle_swp.c
  Clang :: CodeGen/arm_neon_intrinsics.c
  Clang :: CodeGen/attr-counted-by-issue200014.c
  Clang :: CodeGen/builtin-align.c
  Clang :: CodeGen/builtins-arm-exclusive.c
  Clang :: CodeGen/builtins-arm.c
  Clang :: CodeGen/builtins-arm64.c
  Clang :: CodeGen/builtins-loongarch.c
  Clang :: CodeGen/builtins-riscv.c
  Clang :: CodeGen/cx-complex-range-real.c
  Clang :: CodeGen/cx-complex-range.c
  Clang :: CodeGen/distributed-thin-lto/backend-skip.ll
  Clang :: CodeGen/distributed-thin-lto/basic.ll
  Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll
  Clang :: CodeGen/distributed-thin-lto/cfi.ll
  Clang :: CodeGen/distributed-thin-lto/newpm.ll
  Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll
  Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll
  Clang :: CodeGen/linker-diagnostic.ll
  Clang :: CodeGen/memcmp-inline-builtin-to-asm.c
  Clang :: CodeGen/mozilla-ms-inline-asm.c
  Clang :: CodeGen/packed-structure.c
  Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll
  Clang :: CodeGen/thinlto-funcattr-prop.ll
  Clang :: CodeGen/thinlto-multi-module.ll
  Clang :: CodeGen/thinlto-opaque-typed-mix.ll
  Clang :: CodeGen/thinlto_backend.ll
  Clang :: CodeGen/thinlto_backend_local_name_conflict.ll
  Clang :: CodeGen/thinlto_embed_bitcode.ll
  Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
  Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
  Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp
  Clang :: CodeGenCXX/attr-musttail.cpp
  Clang :: CodeGenCXX/ctor-globalopt.cpp
  Clang :: CodeGenCXX/inline-then-fold-variadics.cpp
  Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll
  Clang :: CodeGenCXX/virtual-base-ctor.cpp
  Clang :: CodeGenCoroutines/coro-gro4.cpp
  Clang :: CodeGenCoroutines/pr65054.cpp
  Clang :: CodeGenHIP/offload-pgo-sections.hip
  Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl
  Clang :: Modules/pr93497.cppm


Testing Time: 162.88s

Total Discovered Tests: 55927
  Skipped          :    37 (0.07%)
  Unsupported      :  1675 (2.99%)
  Passed           : 50889 (90.99%)
  Expectedly Failed:    29 (0.05%)
  Failed           :  3297 (5.90%)
FAILED: gen/clang/test/run-lit 
python3 bin/llvm-lit -sv ../../clang/test
ninja: build stopped: subcommand failed.
Command '['ninja', '-C', 'out/gn', 'check-clang']' returned non-zero exit status 1.